diff options
| author | Joris van Vossen <joris.van.vossen@sintecs.nl> | 2020-01-17 09:24:44 (GMT) |
|---|---|---|
| committer | Joris van Vossen <joris.van.vossen@sintecs.nl> | 2020-01-17 12:39:03 (GMT) |
| commit | 2d09eb46306dc029c7b25f3bdd1b705f9b92353c (patch) | |
| tree | 362e2605ddc6782719c3787e84e9833b876694a5 /board/scalys/simc-t10xx/simc-t10x0_m_nand_rcw.cfg | |
| parent | c9b89a4f8b11463e3bd8587a05ae0955e2e86c2a (diff) | |
| download | u-boot-fsl-qoriq-2d09eb46306dc029c7b25f3bdd1b705f9b92353c.tar.xz | |
Moved SERDES lane multiplexing configuration before PCIe initialization.
Clean-up of ddr related code and fixed a buffer overflow.
Made M speedgrade default and added support for P speedgrade with through Kconfig.
Diffstat (limited to 'board/scalys/simc-t10xx/simc-t10x0_m_nand_rcw.cfg')
| -rw-r--r-- | board/scalys/simc-t10xx/simc-t10x0_m_nand_rcw.cfg | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/board/scalys/simc-t10xx/simc-t10x0_m_nand_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_m_nand_rcw.cfg new file mode 100644 index 0000000..c10cc9a --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10x0_m_nand_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 + +0a0c000c 0c000000 00000000 00000000 +81000002 40000002 e8105000 21000000 +00000000 cafebabe 00000000 00030ffc +00000314 00005005 00000000 00000000 |