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author | vojo <joris.van.vossen@sintecs.nl> | 2017-08-23 13:51:00 (GMT) |
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committer | vojo <joris.van.vossen@sintecs.nl> | 2017-08-23 13:51:00 (GMT) |
commit | 0d48297646c426cdd206b0e530495ab7eb02acd3 (patch) | |
tree | 003db115fb07d125bade819a49da8b05b146d38b /board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg | |
parent | dd543f16bbaeb86c8131d2532791dcc2748c6e5f (diff) | |
download | u-boot-fsl-qoriq-0d48297646c426cdd206b0e530495ab7eb02acd3.tar.xz |
Upstream u-boot update and added QT1040-1GB device support
Diffstat (limited to 'board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg')
-rw-r--r-- | board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg new file mode 100644 index 0000000..ad31c5b --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg @@ -0,0 +1,43 @@ +#PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 (LAW 13) +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure IFC controller +# (IFC_CSPR1) +09124010 ff8000c3 +# IFC_CSOR_NAND +09124130 85084101 +# IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND +091241c0 181c080c +091241c4 3850141a +091241c8 03008028 +091241cc 28000000 +# Set IFC_CCR clkdiv to 2 (=/3) to get: +# (platform clock/2/3=83.3MHz) +0912444c 02008000 +#Flush PBL data (Wait 0xFFFFF cycles ) +091380c0 000fffff
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