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author | Evert Pap <evert.pap@sintecs.nl> | 2016-09-22 08:09:53 (GMT) |
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committer | vojo <joris.van.vossen@sintecs.nl> | 2017-08-23 08:07:14 (GMT) |
commit | 6525ac8b91220342e476cedd4bd7e71fc6542a47 (patch) | |
tree | dd6ea583eefdc2768790ee80d82ce0627d836406 /board/scalys/simc-t10xx/tlb.c | |
parent | 91259b783fb00422df6157b85317bf5035c72ed4 (diff) | |
download | u-boot-fsl-qoriq-6525ac8b91220342e476cedd4bd7e71fc6542a47.tar.xz |
Add secure boot support for simc-t1040
Diffstat (limited to 'board/scalys/simc-t10xx/tlb.c')
-rw-r--r-- | board/scalys/simc-t10xx/tlb.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/board/scalys/simc-t10xx/tlb.c b/board/scalys/simc-t10xx/tlb.c index 1890034..fa2dccb 100644 --- a/board/scalys/simc-t10xx/tlb.c +++ b/board/scalys/simc-t10xx/tlb.c @@ -31,7 +31,8 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. @@ -39,6 +40,18 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), + +#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot + * the physical address of the SRAM is at 0xbffc0000, + * and virtual address is 0xfffc0000 + */ + + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, + CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |