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author | vojo <joris.van.vossen@sintecs.nl> | 2017-09-12 09:08:00 (GMT) |
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committer | vojo <joris.van.vossen@sintecs.nl> | 2017-09-15 13:34:09 (GMT) |
commit | 12a11a405781bdb817091192f66b82c8fe35ae08 (patch) | |
tree | ffa1e70a87ae6399fb80ab84dc943d021f728dfc /board/scalys/simc-t2081/tlb.c | |
parent | 0d48297646c426cdd206b0e530495ab7eb02acd3 (diff) | |
download | u-boot-fsl-qoriq-12a11a405781bdb817091192f66b82c8fe35ae08.tar.xz |
T2081 initial support and minor fixes
Diffstat (limited to 'board/scalys/simc-t2081/tlb.c')
-rw-r--r-- | board/scalys/simc-t2081/tlb.c | 47 |
1 files changed, 31 insertions, 16 deletions
diff --git a/board/scalys/simc-t2081/tlb.c b/board/scalys/simc-t2081/tlb.c index c03282e..ddaa10e 100644 --- a/board/scalys/simc-t2081/tlb.c +++ b/board/scalys/simc-t2081/tlb.c @@ -39,7 +39,7 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_512K, 1), + 0, 0, BOOKE_PAGESZ_1M, 1), #elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD) /* * *I*G - L3SRAM. When L3 is used as 512K SRAM, in case of Secure Boot @@ -65,45 +65,60 @@ struct fsl_e_tlb_entry tlb_table[] = { /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_64M, 1), /* modified to simc-t1040 equivalent */ + 0, 2, BOOKE_PAGESZ_64M, 1), #ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_PCI - /* *I*G* - PCI */ + /* *I*G* - PCIe 1, 0x80000000 */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), + 0, 3, BOOKE_PAGESZ_512M, 1), + + /* *I*G* - PCIe 2, 0xa0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 3, 0xb0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 4, 0xc0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), -#endif + 0, 7, BOOKE_PAGESZ_256K, 1), - /* Bman/Qman */ + + /* Bman/Qman + */ #ifdef CONFIG_SYS_BMAN_MEM_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_16M, 1), + 0, 9, BOOKE_PAGESZ_16M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), + 0, 10, BOOKE_PAGESZ_16M, 1), #endif #ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_16M, 1), + 0, 11, BOOKE_PAGESZ_16M, 1), SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_16M, 1), + 0, 12, BOOKE_PAGESZ_16M, 1), #endif #endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_4M, 1), + 0, 13, BOOKE_PAGESZ_32M, 1), #endif #ifdef CONFIG_SYS_NAND_BASE /* @@ -113,17 +128,17 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_64K, 1), + 0, 16, BOOKE_PAGESZ_64K, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 12, BOOKE_PAGESZ_1G, 1), + 0, 19, BOOKE_PAGESZ_1G, 1), SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 13, BOOKE_PAGESZ_1G, 1) + 0, 20, BOOKE_PAGESZ_1G, 1) #endif }; |