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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-12-10 09:32:20 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-19 02:14:01 (GMT) |
| commit | cf04d0326bd1e24909cfe644c0c8676440a915b1 (patch) | |
| tree | b0363c4e98bc6eb2bfe4c5bf5c6ef76f40ccaf36 /board/ti/am43xx/board.h | |
| parent | 4892495e368da9462cd5c1c0d6498fe95b45192e (diff) | |
| download | u-boot-fsl-qoriq-cf04d0326bd1e24909cfe644c0c8676440a915b1.tar.xz | |
ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_CORE VDD_MPU
OPP50 OPP50
OPP50 OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz
Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/ti/am43xx/board.h')
| -rw-r--r-- | board/ti/am43xx/board.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 9268895..091162e 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -25,6 +25,9 @@ static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START; #define HDR_ETH_ALEN 6 #define HDR_NAME_LEN 8 +#define DEV_ATTR_MAX_OFFSET 5 +#define DEV_ATTR_MIN_OFFSET 0 + struct am43xx_board_id { unsigned int magic; char name[HDR_NAME_LEN]; @@ -46,4 +49,5 @@ static inline int board_is_gpevm(void) void enable_uart0_pin_mux(void); void enable_board_pin_mux(void); +void enable_i2c0_pin_mux(void); #endif |