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author | Trent Piepho <tpiepho@freescale.com> | 2008-12-03 23:16:34 (GMT) |
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committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-12-20 00:20:25 (GMT) |
commit | a5d212a263c58cc746481bf1fc878510533ce7d6 (patch) | |
tree | eb08c782227ec1399e96eb6dc082db2123262e41 /board/tqc/tqm85xx | |
parent | 58ec4866ed916c7e422f5107bb27b0822084728e (diff) | |
download | u-boot-fsl-qoriq-a5d212a263c58cc746481bf1fc878510533ce7d6.tar.xz |
mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'board/tqc/tqm85xx')
-rw-r--r-- | board/tqc/tqm85xx/tqm85xx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 73f1d01..cda8208 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -361,7 +361,7 @@ uint get_lbc_clock (void) { volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sys_info; - ulong clkdiv = lbc->lcrr & 0x0f; + ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; get_sys_info (&sys_info); |