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author | Joris van Vossen <joris.van.vossen@sintecs.nl> | 2020-01-17 09:24:44 (GMT) |
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committer | Joris van Vossen <joris.van.vossen@sintecs.nl> | 2020-01-17 12:39:03 (GMT) |
commit | 2d09eb46306dc029c7b25f3bdd1b705f9b92353c (patch) | |
tree | 362e2605ddc6782719c3787e84e9833b876694a5 /board | |
parent | c9b89a4f8b11463e3bd8587a05ae0955e2e86c2a (diff) | |
download | u-boot-fsl-qoriq-2d09eb46306dc029c7b25f3bdd1b705f9b92353c.tar.xz |
Moved SERDES lane multiplexing configuration before PCIe initialization.
Clean-up of ddr related code and fixed a buffer overflow.
Made M speedgrade default and added support for P speedgrade with through Kconfig.
Diffstat (limited to 'board')
17 files changed, 98 insertions, 57 deletions
diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig index a82d91d..4539288 100644 --- a/board/scalys/simc-t10xx/Kconfig +++ b/board/scalys/simc-t10xx/Kconfig @@ -21,3 +21,31 @@ config SYS_CONFIG_NAME default "QT1040-1GB" endif + +if (TARGET_SIMC_TXXXX && (ARCH_T1040 || ARCH_T1020)) + +choice + prompt "T10X0 speed grade" + default T10X0_M_SPEEDGRADE + +config T10X0_M_SPEEDGRADE + bool + prompt "M" + help + Select T10X0 with speed grade M (1200MHz) + +config T10X0_P_SPEEDGRADE + bool + prompt "P" + help + Select T10X0 with speed grade P (1400MHz) + +config T10X0_W_SPEEDGRADE + bool + prompt "W" + help + Select T10X0 with speed grade W (1500MHz) + +endchoice + +endif diff --git a/board/scalys/simc-t10xx/ddr.c b/board/scalys/simc-t10xx/ddr.c index 7fed0d2..8328872 100644 --- a/board/scalys/simc-t10xx/ddr.c +++ b/board/scalys/simc-t10xx/ddr.c @@ -94,13 +94,13 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int controller_number, unsigned int dimm_number) { - const char dimm_model[] = "Soldered-down discrete DDR3"; + const char dimm_model[] = "Soldered DDR3L"; if (((controller_number == 0) && (dimm_number == 0)) || ((controller_number == 1) && (dimm_number == 0))) { memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + memcpy(pdimm->mpart, dimm_model, sizeof(pdimm->mpart) - 1); } return 0; diff --git a/board/scalys/simc-t10xx/ddr_QT1040-1GB.c b/board/scalys/simc-t10xx/ddr_QT1040-1GB.c index e4fdcf6..8a4ebbe 100644 --- a/board/scalys/simc-t10xx/ddr_QT1040-1GB.c +++ b/board/scalys/simc-t10xx/ddr_QT1040-1GB.c @@ -1,5 +1,5 @@ /* - * Copyright 2017 Scalys B.V. + * Copyright 2020 Scalys B.V. * opensource@scalys.com * * SPDX-License-Identifier: GPL-2.0+ @@ -106,56 +106,23 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int controller_number, unsigned int dimm_number) { - const char dimm_model[] = "Soldered-down discrete DDR3"; + const char dimm_model[] = "Soldered DDR3L"; if (((controller_number == 0) && (dimm_number == 0)) || ((controller_number == 1) && (dimm_number == 0))) { memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + memcpy(pdimm->mpart, dimm_model, sizeof(pdimm->mpart) - 1); } return 0; } -int test123(void){ - { - volatile int waitforme = 0; - - while (waitforme) { - asm volatile ("nop"); - } - } - return 0; -} - - int dram_init(void) { phys_size_t dram_size; #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) - uint32_t regval; - - /* Remove reset of DDR using GPIO pin. We do this manually since - * we have not yet access to the DM gpio at this time */ - /* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ - -#define CONFIG_SYS_MPC85XX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000) -#define DDR_RST_N (12) -/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ -/* #define DDR_RST_N MPC85XX_GPIO_NR(2, 12) */ - - /* Set output */ - regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8); - regval |= (0x80000000 >> 12); - out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval); - - /* Set direction to acivate gpio pin */ - regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR); - regval |= (0x80000000 >> 12); - out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval); - dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; @@ -163,9 +130,7 @@ int dram_init(void) /* DDR has been initialised by SPL loader */ dram_size = fsl_ddr_sdram_size(); #endif - - test123(); - + gd->ram_size = dram_size; return 0; diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c index 12accc0..6c0a15f 100644 --- a/board/scalys/simc-t10xx/dragonfruit.c +++ b/board/scalys/simc-t10xx/dragonfruit.c @@ -1,5 +1,5 @@ /* - * Copyright 2017 Scalys B.V. + * Copyright 2020 Scalys B.V. * opensource@scalys.com * * SPDX-License-Identifier: GPL-2.0+ @@ -150,8 +150,8 @@ int scalys_carrier_setup_muxing(int serdes_config) printf("Serdes lane configuration:\n"); if ((mux_config & 1) != 0) { gpio_direction_output(MUX_SER0_1_SEL, 1); - printf("A: SFP slot 0 (T2081 only)\n"); - printf("B: SFP slot 1 (T2081 only)\n"); + printf("A: SFP+ slot 0 (T2081 only)\n"); + printf("B: SFP+ slot 1 (T2081 only)\n"); } else { gpio_direction_output(MUX_SER0_1_SEL, 0); printf("A: PCIe slot 1 on lane 0\n"); diff --git a/board/scalys/simc-t10xx/pci.c b/board/scalys/simc-t10xx/pci.c index 9a02f90..8adcc4b 100644 --- a/board/scalys/simc-t10xx/pci.c +++ b/board/scalys/simc-t10xx/pci.c @@ -1,5 +1,5 @@ /* - * Copyright 2017 Scalys B.V. + * Copyright 2020 Scalys B.V. * opensource@scalys.com * * Copyright 2013 Freescale Semiconductor, Inc. @@ -14,9 +14,13 @@ #include <libfdt.h> #include <fdt_support.h> #include <asm/fsl_serdes.h> +#include "dragonfruit.h" void pci_init_board(void) { + int serdes_config; + uint32_t boot_source; + ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000; uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008; @@ -24,14 +28,16 @@ void pci_init_board(void) uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; uint32_t regval; - /*debug("%s\n", __FUNCTION__);*/ - - /*TODO, when present pins are available on the board, use them to enable only active slots*/ + + /* SERDES configuration is determined boot time through the RCW config. + * It is located in the fourth RCW word (bit 128-135 of the RCW). */ + serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24); + /* Configure SERDES lane multiplexing on Dragonfruit carrier */ + scalys_carrier_setup_muxing(serdes_config); #if 0 /* Dragonfruit Carrier board 1.x */ - /* * IRQ[0-3] : PCIe present detect signals * IRQ[0] : SLOT1_PRSNT2_N : XXX @@ -57,7 +63,7 @@ void pci_init_board(void) out_be32(gpio1_gpdir, regval); #else - /* Dragonfruit Carrier board 2.x */ + /* Dragonfruit Carrier board 2.x/3.x */ /* * PCIe present detect signals: * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N diff --git a/board/scalys/simc-t10xx/simc-t10x0_m_nand_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_m_nand_rcw.cfg new file mode 100644 index 0000000..c10cc9a --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10x0_m_nand_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 + +0a0c000c 0c000000 00000000 00000000 +81000002 40000002 e8105000 21000000 +00000000 cafebabe 00000000 00030ffc +00000314 00005005 00000000 00000000 diff --git a/board/scalys/simc-t10xx/simc-t10x0_m_nand_secure_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_m_nand_secure_rcw.cfg new file mode 100644 index 0000000..5e14ebf --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10x0_m_nand_secure_rcw.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +0a0C000C 0C000000 00000000 00000000 +# HOLDOFF E8705000 +# core 0 enabled E8305000 +# PBL disabled F8505000 +# PBL enabled E8705000 + +#Holdoff enabled, PBL enabled No secure boot E8505000 +#Holdoff enabled, PBL enabled with secure boot E8705000 +81000002 40000002 e8305000 21000000 +00000000 cafebabe 00000000 00030ffc +00000314 00005005 00000000 00000000 diff --git a/board/scalys/simc-t10xx/simc-t10x0_m_nor_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_m_nor_rcw.cfg new file mode 100644 index 0000000..a9476f5 --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10x0_m_nor_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +0a0c000c 0c000000 00000000 00000000 +81000002 40000002 e8023000 21000000 +00000000 cafebabe 00000000 00030ffc +00000314 00005005 00000000 00000000 diff --git a/board/scalys/simc-t10xx/simc-t10x0_m_sdhc_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_m_sdhc_rcw.cfg new file mode 100644 index 0000000..0cdb9ea --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10x0_m_sdhc_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +0a0c000c 0c000000 00000000 00000000 +81000002 40000002 68105000 21000000 +00000000 cafebabe 00000000 00030ffc +00000314 00005005 00000000 00000000 diff --git a/board/scalys/simc-t10xx/simc-t10x0_m_spi_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_m_spi_rcw.cfg new file mode 100644 index 0000000..5b35bb1 --- /dev/null +++ b/board/scalys/simc-t10xx/simc-t10x0_m_spi_rcw.cfg @@ -0,0 +1,9 @@ +#PBL preamble and RCW header +AA55AA55 010E0100 +# +0a0c000c 0c000000 00000000 00000000 +81000002 40000002 58105000 21000000 +00000000 cafebabe 00000000 00030ffc +00000314 00005005 00000000 00000000 + +#58505000 / 58105000 diff --git a/board/scalys/simc-t10xx/simc-t10x0_nand_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_p_nand_rcw.cfg index ccb3509..ccb3509 100644 --- a/board/scalys/simc-t10xx/simc-t10x0_nand_rcw.cfg +++ b/board/scalys/simc-t10xx/simc-t10x0_p_nand_rcw.cfg diff --git a/board/scalys/simc-t10xx/simc-t10x0_nand_secure_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_p_nand_secure_rcw.cfg index 6f0ec4d..6f0ec4d 100644 --- a/board/scalys/simc-t10xx/simc-t10x0_nand_secure_rcw.cfg +++ b/board/scalys/simc-t10xx/simc-t10x0_p_nand_secure_rcw.cfg diff --git a/board/scalys/simc-t10xx/simc-t10x0_nor_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_p_nor_rcw.cfg index a63c1f2..a63c1f2 100644 --- a/board/scalys/simc-t10xx/simc-t10x0_nor_rcw.cfg +++ b/board/scalys/simc-t10xx/simc-t10x0_p_nor_rcw.cfg diff --git a/board/scalys/simc-t10xx/simc-t10x0_sdhc_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_p_sdhc_rcw.cfg index 61236ed..61236ed 100644 --- a/board/scalys/simc-t10xx/simc-t10x0_sdhc_rcw.cfg +++ b/board/scalys/simc-t10xx/simc-t10x0_p_sdhc_rcw.cfg diff --git a/board/scalys/simc-t10xx/simc-t10x0_spi_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_p_spi_rcw.cfg index dba4882..dba4882 100644 --- a/board/scalys/simc-t10xx/simc-t10x0_spi_rcw.cfg +++ b/board/scalys/simc-t10xx/simc-t10x0_p_spi_rcw.cfg diff --git a/board/scalys/simc-t10xx/simc-t10xx.c b/board/scalys/simc-t10xx/simc-t10xx.c index 2f9b8d3..e567579 100644 --- a/board/scalys/simc-t10xx/simc-t10xx.c +++ b/board/scalys/simc-t10xx/simc-t10xx.c @@ -34,6 +34,8 @@ int checkboard(void) { #ifdef CONFIG_TARGET_QT1040_1GB printf("Board: QT1040-1GB\n" ); +#elif defined(CONFIG_TARGET_QT1040_4GB) + printf("Board: QT1040-4GB\n" ); #else printf("Board: simc-t10xx\n" ); #endif @@ -43,8 +45,6 @@ int checkboard(void) int misc_init_r(void) { const void* bcd_dtc_blob; - int serdes_config; - ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int ret; debug("t10xx: misc_init_r\n"); @@ -61,10 +61,7 @@ int misc_init_r(void) gpio_direction_output(MODULE_LED_RED, 0); gpio_direction_output(MODULE_LED_GREEN, 1); - /* SERDES configuration is determined boot time through the RCW config. - * It is located in the fourth RCW word (bit 128-135 of the RCW). */ - serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24); - scalys_carrier_setup_muxing(serdes_config); + /* Configuration of SERDES lane is done in pci_init_board() of pci.c */ bcd_dtc_blob = get_boardinfo_eeprom(); if (bcd_dtc_blob != NULL) { @@ -149,5 +146,5 @@ void board_detail(void) void board_reset(void) { - printf("U-boot reset command not implemented.\n"); + printf("Resetting now\n"); } diff --git a/board/scalys/simc-t10xx/spl.c b/board/scalys/simc-t10xx/spl.c index cfb6e04..07e8393 100644 --- a/board/scalys/simc-t10xx/spl.c +++ b/board/scalys/simc-t10xx/spl.c @@ -107,6 +107,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; gd->env_addr = (ulong)(CONFIG_ENV_ADDR); gd->env_valid = 1; |