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| author | Michal Simek <michal.simek@xilinx.com> | 2017-07-12 08:32:18 (GMT) |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-08-02 07:11:52 (GMT) |
| commit | 90a35db410ae5b6123ebdb2f6233a1f9ce8d0412 (patch) | |
| tree | ccb813a9350fcb071abe0a7b2c442c1685110847 /board | |
| parent | 926870478d1fd5e8cf6a38716c9cf1ae845435e1 (diff) | |
| download | u-boot-fsl-qoriq-90a35db410ae5b6123ebdb2f6233a1f9ce8d0412.tar.xz | |
arm64: zynqmp: Do not setup time if already setup
Newer psu_init_gpl.c/h contain clock setup. Detect if
reference clock is active. If yes, skip timer setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/xilinx/zynqmp/zynqmp.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index ecdae5e..a67473f 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -155,7 +155,10 @@ int board_early_init_r(void) { u32 val; - if (current_el() == 3) { + val = readl(&crlapb_base->timestamp_ref_ctrl); + val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + + if (current_el() == 3 && !val) { val = readl(&crlapb_base->timestamp_ref_ctrl); val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; writel(val, &crlapb_base->timestamp_ref_ctrl); |