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authorCooper Jr., Franklin <fcooper@ti.com>2017-06-16 22:25:20 (GMT)
committerTom Rini <trini@konsulko.com>2017-07-10 18:25:57 (GMT)
commita76a6f3e0434b68de30fbdf2825dea8060d066fd (patch)
tree5f0ee6afaacd5263203ebfbbb5eef9f62f1266af /board
parentf8b4a2d7e219abfd22cf93de043f4102052e3a9d (diff)
downloadu-boot-fsl-qoriq-a76a6f3e0434b68de30fbdf2825dea8060d066fd.tar.xz
ARM: k2g: Program DDR PHY MR2 register with the default value
K2G GP doesn't require the MR2 register to be programed since the default is good enough. However, newer K2G boards do need to change this register value. Therefore, instead of not writing this register if ran on a K2G board just program the value to be written to match the default/reset value. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board')
-rw-r--r--board/ti/ks2_evm/ddr3_k2g.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index 344961d..aeb7da6 100644
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -27,7 +27,7 @@ struct ddr3_phy_config ddr3phy_800_2g = {
.dtpr2 = 0x50022A00ul,
.mr0 = 0x00001430ul,
.mr1 = 0x00000006ul,
- .mr2 = 0x00000018ul,
+ .mr2 = 0x00000000ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F03D09ul,
.zq0cr1 = 0x0001005Dul,