Merge branch 'master' of git://git.denx.de/u-boot-arm

24 files changed, 903 insertions, 541 deletions

diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index 0725989..6492d41 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -61,9 +61,8 @@ int board_mmc_init(bd_t *bd)
 	pin_mux_mmc();
 
 	debug("board_mmc_init: init eMMC\n");
-	/* init dev 0, eMMC chip, with 4-bit bus */
-	/* The board has an 8-bit bus, but 8-bit doesn't work yet */
-	tegra_mmc_init(0, 4, -1, -1);
+	/* init dev 0, eMMC chip, with 8-bit bus */
+	tegra_mmc_init(0, 8, -1, -1);
 
 	debug("board_mmc_init: init SD slot\n");
 	/* init dev 3, SD slot, with 4-bit bus */
diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts
index db79e77..4450674 100644
--- a/board/compulab/dts/tegra20-trimslice.dts
+++ b/board/compulab/dts/tegra20-trimslice.dts
@@ -8,6 +8,7 @@
 
 	aliases {
 		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5000000";
 	};
 
 	memory {
@@ -48,7 +49,7 @@
 	};
 
 	usb@c5000000 {
-		status = "disabled";
+		nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
 	};
 
 	usb@c5004000 {
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
index 9ef66fd..8f4dd09 100644
--- a/board/compulab/trimslice/trimslice.c
+++ b/board/compulab/trimslice/trimslice.c
@@ -34,6 +34,14 @@
 #include <mmc.h>
 #endif
 
+void pin_mux_usb(void)
+{
+	/*
+	 * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
+	 * in the current device tree.
+	 */
+	pinmux_tristate_disable(PINGRP_UAC);
+}
 
 void pin_mux_spi(void)
 {
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index 4a8352f..d73e27e 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -19,12 +19,71 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/imx25-pinmux.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc34704.h>
+
+#define FEC_RESET_B		IMX_GPIO_NR(2, 3)
+#define FEC_ENABLE_B		IMX_GPIO_NR(4, 8)
+#define CARD_DETECT		IMX_GPIO_NR(2, 1)
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{IMX_MMC_SDHC1_BASE},
+};
+#endif
+
+static void mx25pdk_fec_init(void)
+{
+	struct iomuxc_mux_ctl *muxctl;
+	struct iomuxc_pad_ctl *padctl;
+	u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+	u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+
+	/* FEC pin init is generic */
+	mx25_fec_init_pins();
+
+	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+	/*
+	 * Set up FEC_RESET_B and FEC_ENABLE_B
+	 *
+	 * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
+	 * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
+	 */
+	writel(gpio_mux_mode, &muxctl->pad_d12);
+	writel(gpio_mux_mode, &muxctl->pad_a17);
+
+	writel(0x0, &padctl->pad_d12);
+	writel(0x0, &padctl->pad_a17);
+
+	/* Assert RESET and ENABLE low */
+	gpio_direction_output(FEC_RESET_B, 0);
+	gpio_direction_output(FEC_ENABLE_B, 0);
+
+	udelay(10);
+
+	/* Deassert RESET and ENABLE */
+	gpio_set_value(FEC_RESET_B, 1);
+	gpio_set_value(FEC_ENABLE_B, 1);
+
+	/* Setup I2C pins so that PMIC can turn on PHY supply */
+	writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
+	writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
+	writel(0x1E8, &padctl->pad_i2c1_clk);
+	writel(0x1E8, &padctl->pad_i2c1_dat);
+}
+
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
@@ -48,6 +107,68 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	struct pmic *p;
+	int ret;
+
+	mx25pdk_fec_init();
+
+	ret = pmic_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("FSL_PMIC");
+	if (!p)
+		return -ENODEV;
+
+	/* Turn on Ethernet PHY supply */
+	pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct iomuxc_mux_ctl *muxctl;
+	struct iomuxc_pad_ctl *padctl;
+	u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+
+	/*
+	 * Set up the Card Detect pin.
+	 *
+	 * SD1_GPIO_CD: gpio2_1 is ALT 5 mode of pin A15
+	 *
+	 */
+	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+
+	writel(gpio_mux_mode, &muxctl->pad_a15);
+	writel(0x0, &padctl->pad_a15);
+
+	gpio_direction_input(CARD_DETECT);
+	return !gpio_get_value(CARD_DETECT);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	struct iomuxc_mux_ctl *muxctl;
+	u32 sdhc1_mux_mode = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+
+	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+	writel(sdhc1_mux_mode, &muxctl->pad_sd1_cmd);
+	writel(sdhc1_mux_mode, &muxctl->pad_sd1_clk);
+	writel(sdhc1_mux_mode, &muxctl->pad_sd1_data0);
+	writel(sdhc1_mux_mode, &muxctl->pad_sd1_data1);
+	writel(sdhc1_mux_mode, &muxctl->pad_sd1_data2);
+	writel(sdhc1_mux_mode, &muxctl->pad_sd1_data3);
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
 int checkboard(void)
 {
 	puts("Board: MX25PDK\n");
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 29ad0e6..5267729 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -65,6 +65,8 @@ SECTIONS
 
 	. = ALIGN(4);
 
+	__image_copy_end = .;
+
 	.rel.dyn : {
 		__rel_dyn_start = .;
 		*(.rel*)
diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S
index 75bb958..da8b6f3 100644
--- a/board/freescale/mx35pdk/lowlevel_init.S
+++ b/board/freescale/mx35pdk/lowlevel_init.S
@@ -94,6 +94,10 @@
 	orr r1, r1, #0x00000C00
 	orr r1, r1, #0x00000003
 	str r1, [r0, #CLKCTL_CGR1]
+
+	ldr r1, [r0, #CLKCTL_CGR2]
+	orr r1, r1, #0x00C00000
+	str r1, [r0, #CLKCTL_CGR2]
 .endm
 
 .macro setup_sdram
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index c835b0e..2aa000f 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -98,6 +98,26 @@ static void setup_iomux_spi(void)
 	mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
 }
 
+static void setup_iomux_usbotg(void)
+{
+	int in_pad, out_pad;
+
+	/* Set up pins for USBOTG. */
+	mxc_request_iomux(MX35_PIN_USBOTG_PWR,
+			  MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_USBOTG_OC,
+			  MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+	in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+		PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+	out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+		PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+	mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+	mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
 static void setup_iomux_fec(void)
 {
 	int pad;
@@ -189,6 +209,7 @@ int board_early_init_f(void)
 	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 
 	setup_iomux_i2c();
+	setup_iomux_usbotg();
 	setup_iomux_fec();
 	setup_iomux_spi();
 
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index 81c511c..2c8cb7a 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -374,7 +374,7 @@ static int power_init(void)
 		if (retval)
 			return retval;
 
-		p = pmic_get("DIALOG_PMIC");
+		p = pmic_get("FSL_PMIC");
 		if (!p)
 			return -ENODEV;
 
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 2c7cd0d..76ec687 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -26,10 +26,12 @@
 #include <linux/compiler.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/display.h>
 #include <asm/arch/emc.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/pmu.h>
+#include <asm/arch/pwm.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch/usb.h>
 #include <asm/arch-tegra/board.h>
@@ -119,6 +121,13 @@ int board_init(void)
 	pin_mux_spi();
 	spi_init();
 #endif
+#ifdef CONFIG_PWM_TEGRA
+	if (pwm_init(gd->fdt_blob))
+		debug("%s: Failed to init pwm\n", __func__);
+#endif
+#ifdef CONFIG_LCD
+	tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
 	/* boot param addr */
 	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 
@@ -144,6 +153,9 @@ int board_init(void)
 	pin_mux_usb();
 	board_usb_init(gd->fdt_blob);
 #endif
+#ifdef CONFIG_LCD
+	tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
 
 #ifdef CONFIG_TEGRA_NAND
 	pin_mux_nand();
@@ -174,7 +186,19 @@ int board_early_init_f(void)
 	/* Initialize periph GPIOs */
 	gpio_early_init();
 	gpio_early_init_uart();
+#ifdef CONFIG_LCD
+	tegra_lcd_early_init(gd->fdt_blob);
+#endif
 
 	return 0;
 }
 #endif	/* EARLY_INIT */
+
+int board_late_init(void)
+{
+#ifdef CONFIG_LCD
+	/* Make sure we finish initing the LCD */
+	tegra_lcd_check_next_stage(gd->fdt_blob, 1);
+#endif
+	return 0;
+}
diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
index 25a63a0..dd98ca4 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -163,4 +163,37 @@
 			compatible = "hynix,hy27uf4g2b", "nand-flash";
 		};
 	};
+
+	host1x {
+		status = "okay";
+		dc@54200000 {
+			status = "okay";
+			rgb {
+				status = "okay";
+				nvidia,panel = <&lcd_panel>;
+			};
+		};
+	};
+
+	lcd_panel: panel {
+		/* Seaboard has 1366x768 */
+		clock = <70600000>;
+		xres = <1366>;
+		yres = <768>;
+		left-margin = <58>;
+		right-margin = <58>;
+		hsync-len = <58>;
+		lower-margin = <4>;
+		upper-margin = <4>;
+		vsync-len = <4>;
+		hsync-active-high;
+		nvidia,bits-per-pixel = <16>;
+		nvidia,pwm = <&pwm 2 0>;
+		nvidia,backlight-enable-gpios = <&gpio 28 0>;	/* PD4 */
+		nvidia,lvds-shutdown-gpios = <&gpio 10 0>;	/* PB2 */
+		nvidia,backlight-vdd-gpios = <&gpio 176 0>;	/* PW0 */
+		nvidia,panel-vdd-gpios = <&gpio 22 0>;		/* PC6 */
+		nvidia,panel-timings = <400 4 203 17 15>;
+	};
+
 };
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index c7590ac..93430ed 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -64,9 +64,8 @@ int board_mmc_init(bd_t *bd)
 	pin_mux_mmc();
 
 	debug("board_mmc_init: init SD slot J26\n");
-	/* init dev 0, SD slot J26, with 4-bit bus */
-	/* The board has an 8-bit bus, but 8-bit doesn't work yet */
-	tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+	/* init dev 0, SD slot J26, with 8-bit bus */
+	tegra_mmc_init(0, 8, GPIO_PI6, GPIO_PH2);
 
 	debug("board_mmc_init: init SD slot J5\n");
 	/* init dev 2, SD slot J5, with 4-bit bus */
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index c412c07..3e33da0 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -71,9 +71,8 @@ int board_mmc_init(bd_t *bd)
 	pin_mux_mmc();
 
 	debug("board_mmc_init: init eMMC\n");
-	/* init dev 0, eMMC chip, with 4-bit bus */
-	/* The board has an 8-bit bus, but 8-bit doesn't work yet */
-	tegra_mmc_init(0, 4, -1, -1);
+	/* init dev 0, eMMC chip, with 8-bit bus */
+	tegra_mmc_init(0, 8, -1, -1);
 
 	debug("board_mmc_init: init SD slot\n");
 	/* init dev 1, SD slot, with 4-bit bus */
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 1474fa8..47c6a5a 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -36,7 +36,7 @@ COBJS	+= smdk5250.o
 endif
 
 ifdef CONFIG_SPL_BUILD
-COBJS	+= mmc_boot.o
+COBJS	+= spl_boot.o
 endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index a5816e4..9c926d6 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -24,11 +24,13 @@
 #include <asm/io.h>
 #include <i2c.h>
 #include <netdev.h>
+#include <spi.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/sromc.h>
+#include <power/pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -63,6 +65,9 @@ static int smc9115_pre_init(void)
 int board_init(void)
 {
 	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#ifdef CONFIG_EXYNOS_SPI
+	spi_init();
+#endif
 	return 0;
 }
 
@@ -79,6 +84,16 @@ int dram_init(void)
 	return 0;
 }
 
+#if defined(CONFIG_POWER)
+int power_init_board(void)
+{
+	if (pmic_init(I2C_PMIC))
+		return -1;
+	else
+		return 0;
+}
+#endif
+
 void dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
diff --git a/board/samsung/smdk5250/mmc_boot.c b/board/samsung/smdk5250/spl_boot.c
index 449a919..d8f3c1e 100644
--- a/board/samsung/smdk5250/mmc_boot.c
+++ b/board/samsung/smdk5250/spl_boot.c
@@ -23,6 +23,16 @@
 #include<common.h>
 #include<config.h>
 
+enum boot_mode {
+	BOOT_MODE_MMC = 4,
+	BOOT_MODE_SERIAL = 20,
+	/* Boot based on Operating Mode pin settings */
+	BOOT_MODE_OM = 32,
+	BOOT_MODE_USB,	/* Boot using USB download */
+};
+
+	typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst);
+
 /*
 * Copy U-boot from mmc to RAM:
 * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
@@ -30,9 +40,26 @@
 */
 void copy_uboot_to_ram(void)
 {
-	u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+	spi_copy_func_t spi_copy;
+	enum boot_mode bootmode;
+	u32 (*copy_bl2)(u32, u32, u32);
+
+	bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
 
-	copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
+	switch (bootmode) {
+	case BOOT_MODE_SERIAL:
+		spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR;
+		spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
+						CONFIG_SYS_TEXT_BASE);
+		break;
+	case BOOT_MODE_MMC:
+		copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+		copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
+						CONFIG_SYS_TEXT_BASE);
+		break;
+	default:
+		break;
+	}
 }
 
 void board_init_f(unsigned long bootflag)
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index e540190..4724029 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -29,6 +29,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/mipi_dsim.h>
@@ -361,7 +362,9 @@ int power_init_board(void)
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
-		get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+		get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
+		get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
+		get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
 
 	return 0;
 }
@@ -372,6 +375,10 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
 }
 
 static unsigned int get_hw_revision(void)
@@ -419,54 +426,22 @@ int board_mmc_init(bd_t *bis)
 {
 	struct exynos4_gpio_part2 *gpio =
 		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
-	int i, err;
+	int err;
 
 	/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 	s5p_gpio_direction_output(&gpio->k0, 2, 1);
 	s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 
 	/*
-	 * eMMC GPIO:
-	 * SDR 8-bit@48MHz at MMC0
-	 * GPK0[0]	SD_0_CLK(2)
-	 * GPK0[1]	SD_0_CMD(2)
-	 * GPK0[2]	SD_0_CDn	-> Not used
-	 * GPK0[3:6]	SD_0_DATA[0:3](2)
-	 * GPK1[3:6]	SD_0_DATA[0:3](3)
-	 *
-	 * DDR 4-bit@26MHz at MMC4
-	 * GPK0[0]	SD_4_CLK(3)
-	 * GPK0[1]	SD_4_CMD(3)
-	 * GPK0[2]	SD_4_CDn	-> Not used
-	 * GPK0[3:6]	SD_4_DATA[0:3](3)
-	 * GPK1[3:6]	SD_4_DATA[4:7](4)
-	 */
-	for (i = 0; i < 7; i++) {
-		if (i == 2)
-			continue;
-		/* GPK0[0:6] special function 2 */
-		s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
-		/* GPK0[0:6] pull disable */
-		s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
-		/* GPK0[0:6] drv 4x */
-		s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
-	}
-
-	for (i = 3; i < 7; i++) {
-		/* GPK1[3:6] special function 3 */
-		s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
-		/* GPK1[3:6] pull disable */
-		s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
-		/* GPK1[3:6] drv 4x */
-		s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
-	}
-
-	/*
 	 * MMC device init
 	 * mmc0	 : eMMC (8-bit buswidth)
 	 * mmc2	 : SD card (4-bit buswidth)
 	 */
-	err = s5p_mmc_init(0, 8);
+	err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+	if (err)
+		debug("SDMMC0 not configured\n");
+	else
+		err = s5p_mmc_init(0, 8);
 
 	/* T-flash detect */
 	s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
@@ -477,24 +452,11 @@ int board_mmc_init(bd_t *bis)
 	 * GPX3[4] T-flash detect pin
 	 */
 	if (!s5p_gpio_get_value(&gpio->x3, 4)) {
-		/*
-		 * SD card GPIO:
-		 * GPK2[0]	SD_2_CLK(2)
-		 * GPK2[1]	SD_2_CMD(2)
-		 * GPK2[2]	SD_2_CDn	-> Not used
-		 * GPK2[3:6]	SD_2_DATA[0:3](2)
-		 */
-		for (i = 0; i < 7; i++) {
-			if (i == 2)
-				continue;
-			/* GPK2[0:6] special function 2 */
-			s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
-			/* GPK2[0:6] pull disable */
-			s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
-			/* GPK2[0:6] drv 4x */
-			s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
-		}
-		err = s5p_mmc_init(2, 4);
+		err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+		if (err)
+			debug("SDMMC2 not configured\n");
+		else
+			err = s5p_mmc_init(2, 4);
 	}
 
 	return err;
@@ -629,6 +591,10 @@ static void board_power_init(void)
 	writel(0, (unsigned int)&pwr->lcd1_configuration);
 	writel(0, (unsigned int)&pwr->gps_configuration);
 	writel(0, (unsigned int)&pwr->gps_alive_configuration);
+
+	/* It is necessary to power down core 1 */
+	/* to successfully boot CPU1 in kernel */
+	writel(0, (unsigned int)&pwr->arm_core1_configuration);
 }
 
 static void board_uart_init(void)
diff --git a/board/samsung/universal_c210/Makefile b/board/samsung/universal_c210/Makefile
index bfec08f..587cc1b 100644
--- a/board/samsung/universal_c210/Makefile
+++ b/board/samsung/universal_c210/Makefile
@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS-y	:= universal.o onenand.o
-SOBJS	:= lowlevel_init.o
 
 SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S
deleted file mode 100644
index dc7f69e..0000000
--- a/board/samsung/universal_c210/lowlevel_init.S
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * Lowlevel setup for universal board based on EXYNOS4210
- *
- * Copyright (C) 2010 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has GPIO part1 base 0x11400000
- * r6 has GPIO part2 base 0x11000000
- */
-
-	.globl lowlevel_init
-lowlevel_init:
-	mov	r11, lr
-
-	/* r5 has always zero */
-	mov	r5, #0
-
-	ldr	r7, =EXYNOS4_GPIO_PART1_BASE
-	ldr	r6, =EXYNOS4_GPIO_PART2_BASE
-
-	/* System Timer */
-	ldr	r0, =EXYNOS4_SYSTIMER_BASE
-	ldr	r1, =0x5000
-	str	r1, [r0, #0x0]
-	ldr	r1, =0xffffffff
-	str	r1, [r0, #0x8]
-	ldr	r1, =0x49
-	str	r1, [r0, #0x4]
-
-	/* PMIC manual reset */
-	/* nPOWER: XEINT_23: GPX2[7] */
-	add	r0, r6, #0xC40			@ EXYNOS4_GPIO_X2_OFFSET
-	ldr	r1, [r0, #0x0]
-	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
-	orr	r1, r1, #(0x1 << 28)		@ Output
-	str	r1, [r0, #0x0]
-
-	ldr	r1, [r0, #0x4]
-	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
-	str	r1, [r0, #0x4]
-
-	/* init system clock */
-	bl	system_clock_init
-
-	/* Disable Watchdog */
-	ldr	r0, =EXYNOS4_WATCHDOG_BASE		@0x10060000
-	str	r5, [r0]
-
-	/* UART */
-	bl	uart_asm_init
-
-	/* PMU init */
-	bl	system_power_init
-
-	bl	tzpc_init
-
-	mov	lr, r11
-	mov	pc, lr
-	nop
-	nop
-	nop
-
-/*
- * uart_asm_init: Initialize UART's pins
- */
-uart_asm_init:
-	/*
-	 * setup UART0-UART4 GPIOs (part1)
-	 * GPA1CON[3] = I2C_3_SCL (3)
-	 * GPA1CON[2] = I2C_3_SDA (3)
-	 */
-	mov	r0, r7
-	ldr	r1, =0x22222222
-	str	r1, [r0, #0x00]			@ EXYNOS4_GPIO_A0_OFFSET
-	ldr	r1, =0x00223322
-	str	r1, [r0, #0x20]			@ EXYNOS4_GPIO_A1_OFFSET
-
-	/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
-	add	r0, r6, #0x1A0			@ EXYNOS4_GPIO_Y4_OFFSET
-	ldr	r1, [r0, #0x0]
-	bic	r1, r1, #(0xf << 28)		@ 28 = 7 * 4-bit
-	orr	r1, r1, #(0x1 << 28)
-	str	r1, [r0, #0x0]
-
-	ldr	r1, [r0, #0x8]
-	bic	r1, r1, #(0x3 << 14)		@ 14 = 7 * 2-bit
-	orr	r1, r1, #(0x3 << 14)		@ Pull-up enabled
-	str	r1, [r0, #0x8]
-
-	ldr	r1, [r0, #0x4]
-	orr	r1, r1, #(1 << 7)		@ 7 = 7 * 1-bit
-	str	r1, [r0, #0x4]
-
-	mov	pc, lr
-	nop
-	nop
-	nop
-
-system_clock_init:
-	ldr	r0, =EXYNOS4_CLOCK_BASE
-
-	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
-	ldr	r1, =0x0101
-	ldr	r2, =0x14200			@ CLK_SRC_CPU
-	str	r1, [r0, r2]
-
-	/* wait ?us */
-	mov	r1, #0x10000
-1:	subs	r1, r1, #1
-	bne	1b
-
-	/*
-	 * CLK_SRC_TOP0
-	 * MUX_ONENAND_SEL[28]	0: DOUT133, 1: DOUT166
-	 * MUX_VPLL_SEL[8]	0: FINPLL,  1: FOUTVPLL
-	 * MUX_EPLL_SEL[4]	0: FINPLL,  1: FOUTEPLL
-	 */
-	ldr	r1, =0x10000110
-	ldr	r2, =0x0C210			@ CLK_SRC_TOP
-	str	r1, [r0, r2]
-
-	/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
-	ldr	r1, =0x0066666
-	ldr	r2, =0x0C240			@ CLK_SRC_FSYS
-	str	r1, [r0, r2]
-	/* UART[0:5], PWM: SCLKMPLL(6) */
-	ldr	r1, =0x6666666
-	ldr	r2, =0x0C250			@ CLK_SRC_PERIL0_OFFSET
-	str	r1, [r0, r2]
-
-	/* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
-	ldr	r1, =0x0133730
-	ldr	r2, =0x14500			@ CLK_DIV_CPU0
-	str	r1, [r0, r2]
-	/* CPU1: COPY, HPM */
-	ldr	r1, =0x03
-	ldr	r2, =0x14504			@ CLK_DIV_CPU1
-	str	r1, [r0, r2]
-	/* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
-	ldr	r1, =0x13111113
-	ldr	r2, =0x10500			@ CLK_DIV_DMC0
-	str	r1, [r0, r2]
-	/* DMC1: PWI, DVSEM, DPM */
-	ldr	r1, =0x01010100
-	ldr	r2, =0x10504			@ CLK_DIV_DMC1
-	str	r1, [r0, r2]
-	/* LEFTBUS: GDL, GPL */
-	ldr	r1, =0x13
-	ldr	r2, =0x04500			@ CLK_DIV_LEFTBUS
-	str	r1, [r0, r2]
-	/* RIGHHTBUS: GDR, GPR */
-	ldr	r1, =0x13
-	ldr	r2, =0x08500			@ CLK_DIV_RIGHTBUS
-	str	r1, [r0, r2]
-	/*
-	 * CLK_DIV_TOP
-	 * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
-	 * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
-	 */
-	ldr	r1, =0x00005473
-	ldr	r2, =0x0C510			@ CLK_DIV_TOP
-	str	r1, [r0, r2]
-	/* MMC[0:1] */
-	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =0x0C544			@ CLK_DIV_FSYS1
-	str	r1, [r0, r2]
-	/* MMC[2:3] */
-	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =0x0C548			@ CLK_DIV_FSYS2
-	str	r1, [r0, r2]
-	/* MMC4 */
-	ldr	r1, =0x000f			/* 800(MPLL) / (15 + 1) */
-	ldr	r2, =0x0C54C			@ CLK_DIV_FSYS3
-	str	r1, [r0, r2]
-	/* UART[0:5] */
-	ldr	r1, =0x774777
-	ldr	r2, =0x0C550			@ CLK_DIV_PERIL0
-	str	r1, [r0, r2]
-	/* SLIMBUS: ???, PWM */
-	ldr	r1, =0x8
-	ldr	r2, =0x0C55C			@ CLK_DIV_PERIL3
-	str	r1, [r0, r2]
-
-	/* PLL Setting */
-	ldr	r1, =0x1C20
-	ldr	r2, =0x14000			@ APLL_LOCK
-	str	r1, [r0, r2]
-	ldr	r2, =0x14008			@ MPLL_LOCK
-	str	r1, [r0, r2]
-	ldr	r2, =0x0C010			@ EPLL_LOCK
-	str	r1, [r0, r2]
-	ldr	r2, =0x0C020			@ VPLL_LOCK
-	str	r1, [r0, r2]
-
-	/* APLL */
-	ldr	r1, =0x8000001c
-	ldr	r2, =0x14104			@ APLL_CON1
-	str	r1, [r0, r2]
-	ldr	r1, =0x80c80601			@ 800MHz
-	ldr	r2, =0x14100			@ APLL_CON0
-	str	r1, [r0, r2]
-	/* MPLL */
-	ldr	r1, =0x8000001C
-	ldr	r2, =0x1410C			@ MPLL_CON1
-	str	r1, [r0, r2]
-	ldr	r1, =0x80c80601			@ 800MHz
-	ldr	r2, =0x14108			@ MPLL_CON0
-	str	r1, [r0, r2]
-	/* EPLL */
-	ldr	r1, =0x0
-	ldr	r2, =0x0C114			@ EPLL_CON1
-	str	r1, [r0, r2]
-	ldr	r1, =0x80300302			@ 96MHz
-	ldr	r2, =0x0C110			@ EPLL_CON0
-	str	r1, [r0, r2]
-	/* VPLL */
-	ldr	r1, =0x11000400
-	ldr	r2, =0x0C124			@ VPLL_CON1
-	str	r1, [r0, r2]
-	ldr	r1, =0x80350302			@ 108MHz
-	ldr	r2, =0x0C120			@ VPLL_CON0
-	str	r1, [r0, r2]
-
-	/*
-	 * SMMUJPEG[11], JPEG[6], CSIS1[5]		: 0111 1001
-	 * Turn off all
-	 */
-	ldr	r1, =0xFFF80000
-	ldr	r2, =0x0C920			@ CLK_GATE_IP_CAM
-	str	r1, [r0, r2]
-
-	/* Turn off all */
-	ldr	r1, =0xFFFFFFC0
-	ldr	r2, =0x0C924			@ CLK_GATE_IP_VP
-	str	r1, [r0, r2]
-
-	/* Turn off all */
-	ldr	r1, =0xFFFFFFE0
-	ldr	r2, =0x0C928			@ CLK_GATE_IP_MFC
-	str	r1, [r0, r2]
-
-	/* Turn off all */
-	ldr	r1, =0xFFFFFFFC
-	ldr	r2, =0x0C92C			@ CLK_GATE_IP_G3D
-	str	r1, [r0, r2]
-
-	/* Turn off all */
-	ldr	r1, =0xFFFFFC00
-	ldr	r2, =0x0C930			@ CLK_GATE_IP_IMAGE
-	str	r1, [r0, r2]
-
-	/* DSIM0[3], MDNIE0[2], MIE0[1]			: 0001 */
-	ldr	r1, =0xFFFFFFF1
-	ldr	r2, =0x0C934			@ CLK_GATE_IP_LCD0
-	str	r1, [r0, r2]
-
-	/* Turn off all */
-	ldr	r1, =0xFFFFFFC0
-	ldr	r2, =0x0C938			@ CLK_GATE_IP_LCD1
-	str	r1, [r0, r2]
-
-	/*
-	 * SMMUPCIE[18], NFCON[16]			: 1111 1010
-	 * PCIE[14],  SATA[10], SDMMC43[9:8]		: 1011 1000
-	 * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2]	: 1010 0011
-	 */
-	ldr	r1, =0xFFFAB8A3
-	ldr	r2, =0x0C940			@ CLK_GATE_IP_FSYS
-	str	r1, [r0, r2]
-
-	/* Turn off all */
-	ldr	r1, =0xFFFFFFFC
-	ldr	r2, =0x0C94C			@ CLK_GATE_IP_GPS
-	str	r1, [r0, r2]
-
-	/*
-	 * AC97[27], SPDIF[26], SLIMBUS[25]		: 1111 0001
-	 * I2C2[8]					: 1111 1110
-	 */
-	ldr	r1, =0xF1FFFEFF
-	ldr	r2, =0x0C950			@ CLK_GATE_IP_PERIL
-	str	r1, [r0, r2]
-
-	/*
-	 * KEYIF[16]					: 1111 1110
-	 */
-	ldr	r1, =0xFFFEFFFF
-	ldr	r2, =0x0C960			@ CLK_GATE_IP_PERIR
-	str	r1, [r0, r2]
-
-	/* LCD1[5], G3D[3], MFC[2], TV[1]		: 1101 0001 */
-	ldr	r1, =0xFFFFFFD1
-	ldr	r2, =0x0C970			@ CLK_GATE_BLOCK
-	str	r1, [r0, r2]
-	mov	pc, lr
-	nop
-	nop
-	nop
-
-system_power_init:
-	ldr	r0, =EXYNOS4_POWER_BASE		@ 0x10020000
-
-	ldr	r2, =0x330C			@ PS_HOLD_CONTROL
-	ldr	r1, [r0, r2]
-	orr	r1, r1, #(0x3 << 8)		@ Data High, Output En
-	str	r1, [r0, r2]
-
-	/* Power Down */
-	add	r2, r0, #0x3000
-	str	r5, [r2, #0xC20]		@ TV_CONFIGURATION
-	str	r5, [r2, #0xC40]		@ MFC_CONFIGURATION
-	str	r5, [r2, #0xC60]		@ G3D_CONFIGURATION
-	str	r5, [r2, #0xCA0]		@ LCD1_CONFIGURATION
-	str	r5, [r2, #0xCE0]		@ GPS_CONFIGURATION
-
-	mov	pc, lr
-	nop
-	nop
-	nop
-
-tzpc_init:
-	ldr	r0, =0x10110000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	ldr	r0, =0x10120000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	ldr	r0, =0x10130000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	ldr	r0, =0x10140000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	ldr	r0, =0x10150000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	mov	pc, lr
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 36a0472..e742707 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -23,10 +23,17 @@
  */
 
 #include <common.h>
+#include <spi.h>
+#include <lcd.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/adc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/watchdog.h>
+#include <libtizen.h>
+#include <ld9040.h>
 #include <power/pmic.h>
 #include <usb/s3c_udc.h>
 #include <asm/arch/cpu.h>
@@ -48,21 +55,7 @@ static int get_hwrev(void)
 	return board_rev & 0xFF;
 }
 
-static void check_hw_revision(void);
-
-int board_init(void)
-{
-	gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
-	gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
-	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	check_hw_revision();
-	printf("HW Revision:\t0x%x\n", board_rev);
-
-	return 0;
-}
+static void init_pmic_lcd(void);
 
 int power_init_board(void)
 {
@@ -72,6 +65,8 @@ int power_init_board(void)
 	if (ret)
 		return ret;
 
+	init_pmic_lcd();
+
 	return 0;
 }
 
@@ -186,7 +181,7 @@ int checkboard(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	int i, err;
+	int err;
 
 	switch (get_hwrev()) {
 	case 0:
@@ -209,75 +204,30 @@ int board_mmc_init(bd_t *bis)
 	}
 
 	/*
-	 * eMMC GPIO:
-	 * SDR 8-bit@48MHz at MMC0
-	 * GPK0[0]	SD_0_CLK(2)
-	 * GPK0[1]	SD_0_CMD(2)
-	 * GPK0[2]	SD_0_CDn	-> Not used
-	 * GPK0[3:6]	SD_0_DATA[0:3](2)
-	 * GPK1[3:6]	SD_0_DATA[0:3](3)
-	 *
-	 * DDR 4-bit@26MHz at MMC4
-	 * GPK0[0]	SD_4_CLK(3)
-	 * GPK0[1]	SD_4_CMD(3)
-	 * GPK0[2]	SD_4_CDn	-> Not used
-	 * GPK0[3:6]	SD_4_DATA[0:3](3)
-	 * GPK1[3:6]	SD_4_DATA[4:7](4)
+	 * MMC device init
+	 * mmc0	 : eMMC (8-bit buswidth)
+	 * mmc2	 : SD card (4-bit buswidth)
 	 */
-	for (i = 0; i < 7; i++) {
-		if (i == 2)
-			continue;
-		/* GPK0[0:6] special function 2 */
-		s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2);
-		/* GPK0[0:6] pull disable */
-		s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
-		/* GPK0[0:6] drv 4x */
-		s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
-	}
-
-	for (i = 3; i < 7; i++) {
-		/* GPK1[3:6] special function 3 */
-		s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3);
-		/* GPK1[3:6] pull disable */
-		s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
-		/* GPK1[3:6] drv 4x */
-		s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
-	}
+	err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+	if (err)
+		debug("SDMMC0 not configured\n");
+	else
+		err = s5p_mmc_init(0, 8);
 
 	/* T-flash detect */
 	s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
 	s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
 
 	/*
-	 * MMC device init
-	 * mmc0	 : eMMC (8-bit buswidth)
-	 * mmc2	 : SD card (4-bit buswidth)
-	 */
-	err = s5p_mmc_init(0, 8);
-
-	/*
 	 * Check the T-flash  detect pin
 	 * GPX3[4] T-flash detect pin
 	 */
 	if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
-		/*
-		 * SD card GPIO:
-		 * GPK2[0]	SD_2_CLK(2)
-		 * GPK2[1]	SD_2_CMD(2)
-		 * GPK2[2]	SD_2_CDn	-> Not used
-		 * GPK2[3:6]	SD_2_DATA[0:3](2)
-		 */
-		for (i = 0; i < 7; i++) {
-			if (i == 2)
-				continue;
-			/* GPK2[0:6] special function 2 */
-			s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2);
-			/* GPK2[0:6] pull disable */
-			s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
-			/* GPK2[0:6] drv 4x */
-			s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
-		}
-		err = s5p_mmc_init(2, 4);
+		err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+		if (err)
+			debug("SDMMC2 not configured\n");
+		else
+			err = s5p_mmc_init(2, 4);
 	}
 
 	return err;
@@ -331,3 +281,242 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
 	.usb_flags = PHY0_SLEEP,
 };
 #endif
+
+int board_early_init_f(void)
+{
+	wdt_stop();
+
+	return 0;
+}
+
+#ifdef CONFIG_SOFT_SPI
+static void soft_spi_init(void)
+{
+	gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
+		CONFIG_SOFT_SPI_MODE & SPI_CPOL);
+	gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
+	gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO);
+	gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS,
+		!(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+		!(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+	SPI_SCL(1);
+	gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+		CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+		!(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+int  spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void universal_spi_scl(int bit)
+{
+	gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit);
+}
+
+void universal_spi_sda(int bit)
+{
+	gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit);
+}
+
+int universal_spi_read(void)
+{
+	return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO);
+}
+#endif
+
+static void init_pmic_lcd(void)
+{
+	unsigned char val;
+	int ret = 0;
+
+	struct pmic *p = pmic_get("MAX8998_PMIC");
+
+	if (!p)
+		return;
+
+	if (pmic_probe(p))
+		return;
+
+	/* LDO7 1.8V */
+	val = 0x02; /* (1800 - 1600) / 100; */
+	ret |= pmic_reg_write(p,  MAX8998_REG_LDO7, val);
+
+	/* LDO17 3.0V */
+	val = 0xe; /* (3000 - 1600) / 100; */
+	ret |= pmic_reg_write(p,  MAX8998_REG_LDO17, val);
+
+	/* Disable unneeded regulators */
+	/*
+	 * ONOFF1
+	 * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
+	 * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
+	 */
+	val = 0xB9;
+	ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF1, val);
+
+	/* ONOFF2
+	 * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
+	 * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
+	 */
+	val = 0x50;
+	ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF2, val);
+
+	/* ONOFF3
+	 * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
+	 * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
+	 */
+	val = 0x00;
+	ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF3, val);
+
+	if (ret)
+		puts("LCD pmic initialisation error!\n");
+}
+
+static void lcd_cfg_gpio(void)
+{
+	unsigned int i, f3_end = 4;
+
+	for (i = 0; i < 8; i++) {
+		/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
+		s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
+		s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
+		s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+		/* pull-up/down disable */
+		s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
+		s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+
+		/* drive strength to max (24bit) */
+		s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
+		s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+		s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
+		s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
+		s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
+		s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+	}
+
+	for (i = 0; i < f3_end; i++) {
+		/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
+		s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+		/* pull-up/down disable */
+		s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+		/* drive strength to max (24bit) */
+		s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
+		s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+	}
+
+	/* gpio pad configuration for LCD reset. */
+	s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+
+	spi_init();
+}
+
+static void reset_lcd(void)
+{
+	s5p_gpio_set_value(&gpio2->y4, 5, 1);
+	udelay(10000);
+	s5p_gpio_set_value(&gpio2->y4, 5, 0);
+	udelay(10000);
+	s5p_gpio_set_value(&gpio2->y4, 5, 1);
+	udelay(100);
+}
+
+static void lcd_power_on(void)
+{
+	struct pmic *p = pmic_get("MAX8998_PMIC");
+
+	if (!p)
+		return;
+
+	if (pmic_probe(p))
+		return;
+
+	pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
+	pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
+}
+
+vidinfo_t panel_info = {
+	.vl_freq	= 60,
+	.vl_col		= 480,
+	.vl_row		= 800,
+	.vl_width	= 480,
+	.vl_height	= 800,
+	.vl_clkp	= CONFIG_SYS_HIGH,
+	.vl_hsp		= CONFIG_SYS_HIGH,
+	.vl_vsp		= CONFIG_SYS_HIGH,
+	.vl_dp		= CONFIG_SYS_HIGH,
+
+	.vl_bpix	= 5,	/* Bits per pixel */
+
+	/* LD9040 LCD Panel */
+	.vl_hspw	= 2,
+	.vl_hbpd	= 16,
+	.vl_hfpd	= 16,
+
+	.vl_vspw	= 2,
+	.vl_vbpd	= 8,
+	.vl_vfpd	= 8,
+	.vl_cmd_allow_len = 0xf,
+
+	.win_id		= 0,
+	.cfg_gpio	= lcd_cfg_gpio,
+	.backlight_on	= NULL,
+	.lcd_power_on	= lcd_power_on,
+	.reset_lcd	= reset_lcd,
+	.dual_lcd_enabled = 0,
+
+	.init_delay	= 0,
+	.power_on_delay = 10000,
+	.reset_delay	= 10000,
+	.interface_mode = FIMD_RGB_INTERFACE,
+	.mipi_enabled	= 0,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+	vid->logo_on	= 1;
+	vid->resolution	= HD_RESOLUTION;
+	vid->rgb_mode	= MODE_RGB_P;
+
+#ifdef CONFIG_TIZEN
+	get_tizen_logo_info(vid);
+#endif
+
+	/* for LD9040. */
+	vid->pclk_name = 1;	/* MPLL */
+	vid->sclk_div = 1;
+
+	vid->cfg_ldo = ld9040_cfg_ldo;
+	vid->enable_ldo = ld9040_enable_ldo;
+
+	setenv("lcdinfo", "lcd=ld9040");
+}
+
+int board_init(void)
+{
+	gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+	gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
+
+	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#ifdef CONFIG_SOFT_SPI
+	soft_spi_init();
+#endif
+	check_hw_revision();
+	printf("HW Revision:\t0x%x\n", board_rev);
+
+	return 0;
+}
diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c
index fe5589d..4f37c59 100644
--- a/board/syteco/zmx25/zmx25.c
+++ b/board/syteco/zmx25/zmx25.c
@@ -33,6 +33,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/imx25-pinmux.h>
+#include <asm/arch/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/woodburn/Makefile b/board/woodburn/Makefile
new file mode 100644
index 0000000..b60163f
--- /dev/null
+++ b/board/woodburn/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= woodburn.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/woodburn/imximage.cfg b/board/woodburn/imximage.cfg
new file mode 100644
index 0000000..b4cc8ec
--- /dev/null
+++ b/board/woodburn/imximage.cfg
@@ -0,0 +1,4 @@
+BOOT_FROM      sd
+
+# DDR2 init
+DATA 4 0xB8001010 0x00000304
diff --git a/board/woodburn/lowlevel_init.S b/board/woodburn/lowlevel_init.S
new file mode 100644
index 0000000..57fb1b1
--- /dev/null
+++ b/board/woodburn/lowlevel_init.S
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+	core_init
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	mov pc, lr
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
new file mode 100644
index 0000000..d74f360
--- /dev/null
+++ b/board/woodburn/woodburn.c
@@ -0,0 +1,264 @@
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * Based on flea3.c and mx35pdk.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+#include <spl.h>
+
+#define CCM_CCMR_CONFIG		0x003F4208
+
+#define ESDCTL_DDR2_CONFIG	0x007FFC3F
+
+/* For MMC */
+#define GPIO_MMC_CD	7
+#define GPIO_MMC_WP	8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+		PHYS_SDRAM_1_SIZE);
+
+	return 0;
+}
+
+static void board_setup_sdram(void)
+{
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+	/* Initialize with default values both CSD0/1 */
+	writel(0x2000, &esdc->esdctl0);
+	writel(0x2000, &esdc->esdctl1);
+
+	mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+		 13, 10, 2, 0x8080);
+}
+
+static void setup_iomux_fec(void)
+{
+	/* setup pins for FEC */
+	mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+}
+
+int woodburn_init(void)
+{
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	/* initialize PLL and clock configuration */
+	writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+	/* Set-up RAM */
+	board_setup_sdram();
+
+	/* enable clocks */
+	writel(readl(&ccm->cgr0) |
+		MXC_CCM_CGR0_EMI_MASK |
+		MXC_CCM_CGR0_EDIO_MASK |
+		MXC_CCM_CGR0_EPIT1_MASK,
+		&ccm->cgr0);
+
+	writel(readl(&ccm->cgr1) |
+		MXC_CCM_CGR1_FEC_MASK |
+		MXC_CCM_CGR1_GPIO1_MASK |
+		MXC_CCM_CGR1_GPIO2_MASK |
+		MXC_CCM_CGR1_GPIO3_MASK |
+		MXC_CCM_CGR1_I2C1_MASK |
+		MXC_CCM_CGR1_I2C2_MASK |
+		MXC_CCM_CGR1_I2C3_MASK,
+		&ccm->cgr1);
+
+	/* Set-up NAND */
+	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+	/* Set pinmux for the required peripherals */
+	setup_iomux_fec();
+
+	/* setup GPIO1_4 FEC_ENABLE signal */
+	mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
+	gpio_direction_output(4, 1);
+	mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
+	gpio_direction_output(9, 1);
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void board_init_f(ulong dummy)
+{
+	/* Set the stack pointer. */
+	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+	/* Initialize MUX and SDRAM */
+	woodburn_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end__ - __bss_start);
+
+	/* Set global data pointer. */
+	gd = &gdata;
+
+	preloader_console_init();
+	timer_init();
+
+	board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+}
+
+#endif
+
+
+/* Booting from NOR in external mode */
+int board_early_init_f(void)
+{
+	return woodburn_init();
+}
+
+
+int board_init(void)
+{
+	struct pmic *p;
+	u32 val;
+	int ret;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	ret = pmic_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("FSL_PMIC");
+
+	/*
+	 * Set switchers in Auto in NORMAL mode & STANDBY mode
+	 * Setup the switcher mode for SW1 & SW2
+	 */
+	pmic_reg_read(p, REG_SW_4, &val);
+	val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+		(SWMODE_MASK << SWMODE2_SHIFT)));
+	val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+	/* Set SWILIMB */
+	val |= (1 << 22);
+	pmic_reg_write(p, REG_SW_4, val);
+
+	/* Setup the switcher mode for SW3 & SW4 */
+	pmic_reg_read(p, REG_SW_5, &val);
+	val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+		(SWMODE_MASK << SWMODE3_SHIFT));
+	val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+		(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+	pmic_reg_write(p, REG_SW_5, val);
+
+	/* Set VGEN1 to 3.15V */
+	pmic_reg_read(p, REG_SETTING_0, &val);
+	val &= ~(VGEN1_MASK);
+	val |= VGEN1_3_15;
+	pmic_reg_write(p, REG_SETTING_0, val);
+
+	pmic_reg_read(p, REG_MODE_0, &val);
+	val |= VGEN1EN;
+	pmic_reg_write(p, REG_MODE_0, val);
+	udelay(2000);
+
+	return 0;
+}
+
+#if defined(CONFIG_FSL_ESDHC)
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
+
+int board_mmc_init(bd_t *bis)
+{
+	/* configure pins for SDHC1 only */
+	mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+
+	/* MMC Card Detect on GPIO1_7 */
+	mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
+	mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
+	gpio_direction_input(GPIO_MMC_CD);
+
+	mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
+	mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
+	gpio_direction_output(GPIO_MMC_WP, 0);
+
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return !gpio_get_value(GPIO_MMC_CD);
+}
+#endif
+
+u32 get_board_rev(void)
+{
+	int rev = 0;
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}