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| author | Chris Zankel <chris@zankel.net> | 2016-08-10 15:36:43 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-08-15 22:46:38 (GMT) |
| commit | de5e5cea022ab44006ff1edf45a39f0943fb9dff (patch) | |
| tree | 8dbaf0260ec277035ecb514d8437bd4cd05de70e /common/image.c | |
| parent | f225d39d30935c3d27271bee676ef554fa9b0f3c (diff) | |
| download | u-boot-fsl-qoriq-de5e5cea022ab44006ff1edf45a39f0943fb9dff.tar.xz | |
xtensa: add support for the xtensa processor architecture [1/2]
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Cadence.
This is the first part of the basic architecture port with changes to
common files. The 'arch/xtensa' directory, and boards and additional
drivers will be in separate commits.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'common/image.c')
| -rw-r--r-- | common/image.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/common/image.c b/common/image.c index af155b2..7ad04ca 100644 --- a/common/image.c +++ b/common/image.c @@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_ARM64, "arm64", "AArch64", }, { IH_ARCH_ARC, "arc", "ARC", }, { IH_ARCH_X86_64, "x86_64", "AMD x86_64", }, + { IH_ARCH_XTENSA, "xtensa", "Xtensa", }, { -1, "", "", }, }; |