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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2017-07-03 10:37:11 (GMT)
committerYork Sun <york.sun@nxp.com>2017-08-09 16:57:32 (GMT)
commitbf7aecce04f0b29126b870c6d1e926bd26a681e8 (patch)
treea695a2c27318a57c342f3683b92e4fbdf01854db /configs/gwventana_nand_defconfig
parent263536a693b3c3260f88b5e47a1d3e4962d66ba7 (diff)
downloadu-boot-fsl-qoriq-bf7aecce04f0b29126b870c6d1e926bd26a681e8.tar.xz
armv8/fsl-lsch2: correct the config description of DSPI clock divider
It is derived from Platform clock instead of Platform PLL frequency. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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