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author | Kumar Gala <galak@kernel.crashing.org> | 2008-04-29 15:27:08 (GMT) |
---|---|---|
committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-04-29 16:44:29 (GMT) |
commit | 45239cf4152109caa925145ccd433529902df887 (patch) | |
tree | cbeedce4c8e289bf2da8f6a4afa3677f57578ccd /cpu/mpc85xx | |
parent | ef7d30b14394e4c4a153118f5845760cadada02a (diff) | |
download | u-boot-fsl-qoriq-45239cf4152109caa925145ccd433529902df887.tar.xz |
85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs
All the 85xx and 86xx UM describe the register as timing_cfg_3
not as ext_refrec.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx')
-rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 435458a..e3a8249 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -610,8 +610,8 @@ spd_sdram(void) /* * Sneak in some Extended Refresh Recovery. */ - ddr->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); + ddr->timing_cfg_3 = (trfc_high << 16); + debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); ddr->timing_cfg_1 = (0 |