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authorStefan Roese <sr@denx.de>2007-11-18 13:44:44 (GMT)
committerStefan Roese <sr@denx.de>2007-11-18 13:44:44 (GMT)
commit653811a3c2b35856bf12e196dcc8c4694e28e420 (patch)
treeb140527dddce7f3d90e76168e8a69c880e799177 /cpu/ppc4xx
parent9ea61b57968554eaf0f474ec7e088b17d367f474 (diff)
downloadu-boot-fsl-qoriq-653811a3c2b35856bf12e196dcc8c4694e28e420.tar.xz
ppc4xx: Correct 405EX PCIe UTL register mapping
Map 4k mem space for UTL registers for each port. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
-rw-r--r--cpu/ppc4xx/4xx_pcie.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index cafd933..3af9862 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -412,14 +412,14 @@ static void ppc4xx_setup_utl(u32 port)
case 0:
mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xfffffc01); /* 4k region, valid */
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */
mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
break;
case 1:
mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xfffffc01); /* 4k region, valid */
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */
mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
break;
@@ -554,7 +554,7 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
#endif /* CONFIG_405EX */
int ppc4xx_init_pcie_port_hw(int port, int rootport)
- __attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
+__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw")));
/*
* We map PCI Express configuration access into the 512MB regions