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author | Wolfgang Denk <wd@denx.de> | 2009-04-05 21:04:30 (GMT) |
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committer | Wolfgang Denk <wd@denx.de> | 2009-04-05 21:04:30 (GMT) |
commit | 712ac6a1a6909a58d6549fb220cc921a7e9f9979 (patch) | |
tree | 7391a68d2b81d9a9096e170b97bbfe0ed81c2c7f /cpu | |
parent | 23e4af49e066a53cd3e3659b68ef90572d88de84 (diff) | |
parent | c6fadb9c73a6a3e0c7f20696e978304a593a8d2d (diff) | |
download | u-boot-fsl-qoriq-712ac6a1a6909a58d6549fb220cc921a7e9f9979.tar.xz |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/arm1136/cpu.c | 90 | ||||
-rw-r--r-- | cpu/arm1176/cpu.c | 103 | ||||
-rw-r--r-- | cpu/arm1176/s3c64xx/cpu_init.S | 7 | ||||
-rw-r--r-- | cpu/arm720t/cpu.c | 120 | ||||
-rw-r--r-- | cpu/arm920t/cpu.c | 124 | ||||
-rw-r--r-- | cpu/arm925t/cpu.c | 96 | ||||
-rw-r--r-- | cpu/arm926ejs/cpu.c | 125 | ||||
-rw-r--r-- | cpu/arm946es/cpu.c | 101 | ||||
-rw-r--r-- | cpu/arm_cortexa8/cpu.c | 82 | ||||
-rw-r--r-- | cpu/arm_cortexa8/omap3/board.c | 2 | ||||
-rw-r--r-- | cpu/arm_intcm/cpu.c | 25 | ||||
-rw-r--r-- | cpu/ixp/cpu.c | 83 | ||||
-rw-r--r-- | cpu/lh7a40x/cpu.c | 121 | ||||
-rw-r--r-- | cpu/pxa/cpu.c | 81 | ||||
-rw-r--r-- | cpu/s3c44b0/cpu.c | 9 | ||||
-rw-r--r-- | cpu/sa1100/cpu.c | 81 |
16 files changed, 108 insertions, 1142 deletions
diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c index 0486163..e03a765 100644 --- a/cpu/arm1136/cpu.c +++ b/cpu/arm1136/cpu.c @@ -33,55 +33,13 @@ #include <common.h> #include <command.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ +static void cache_flush(void); int cpu_init (void) { @@ -104,8 +62,6 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); #ifdef CONFIG_LCD @@ -119,44 +75,18 @@ int cleanup_before_linux (void) #endif /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ - asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ - return(0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return(0); -} - -void icache_enable (void) -{ - ulong reg; + cache_flush(); - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); + return 0; } -void icache_disable (void) +static void cache_flush(void) { - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} + unsigned long i = 0; -int icache_status (void) -{ - return(read_p15_c1 () & C1_IC) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */ } diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index 1e94f7d..bfa4378 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -34,55 +34,10 @@ #include <common.h> #include <command.h> #include <s3c6400.h> +#include <asm/system.h> static void cache_flush (void); -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1(); -} - -static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++) - __asm__ __volatile__("nop\n"); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1 << 0) /* mmu off/on */ -#define C1_ALIGN (1 << 1) /* alignment faults off/on */ -#define C1_DC (1 << 2) /* dcache off/on */ -#define C1_WB (1 << 3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1 << 7) /* big endian off/on */ -#define C1_SYS_PROT (1 << 8) /* system protection */ -#define C1_ROM_PROT (1 << 9) /* ROM protection */ -#define C1_IC (1 << 12) /* icache off/on */ -#define C1_HIGH_VECTORS (1 << 13) /* location of vectors: low/high */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - int cpu_init (void) { return 0; @@ -102,6 +57,7 @@ int cleanup_before_linux (void) /* turn off I/D-cache */ icache_disable(); dcache_disable(); + /* flush I/D-cache */ cache_flush(); return 0; @@ -123,61 +79,6 @@ void reset_cpu (ulong ignored) /*NOTREACHED*/ } -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return 0; -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} - -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_DC); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_DC); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_DC) != 0; -} - /* flush I/D-cache */ static void cache_flush (void) { diff --git a/cpu/arm1176/s3c64xx/cpu_init.S b/cpu/arm1176/s3c64xx/cpu_init.S index 08bda99..32bb467 100644 --- a/cpu/arm1176/s3c64xx/cpu_init.S +++ b/cpu/arm1176/s3c64xx/cpu_init.S @@ -28,13 +28,6 @@ .globl mem_ctrl_asm_init mem_ctrl_asm_init: - /* Memory subsystem address 0x7e00f120 */ - ldr r0, =ELFIN_MEM_SYS_CFG - - /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */ - mov r1, #0xd - str r1, [r0] - /* DMC1 base address 0x7e001000 */ ldr r0, =ELFIN_DMC1_BASE diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 8166982..6c40903 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -34,6 +34,11 @@ #include <command.h> #include <clps7111.h> #include <asm/hardware.h> +#include <asm/system.h> + +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) +static void cache_flush(void); +#endif int cpu_init (void) { @@ -58,17 +63,14 @@ int cleanup_before_linux (void) */ #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - unsigned long i; - disable_interrupts (); /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable(); /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + cache_flush(); #ifdef CONFIG_ARM7_REVD /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; @@ -84,109 +86,13 @@ int cleanup_before_linux (void) return 0; } -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -/* - * Instruction and Data cache enable and disable functions - * - */ - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1(void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - /* printf("p15/c1 is = %08lx\n", value); */ - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1(unsigned long value) -{ - /* printf("write %08lx to p15/c1\n", value); */ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1(); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_IDC (1<<2) /* icache and/or dcache off/on */ -#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_IDC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IDC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IDC) != 0; -} - -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_IDC); -} - -void dcache_disable (void) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IDC); -} + unsigned long i = 0; -int dcache_status (void) -{ - return (read_p15_c1 () & C1_IDC) != 0; + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific cache setup for IntegratorAP/CM720T as yet */ diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c index 1b9cde6..87c1adc 100644 --- a/cpu/arm920t/cpu.c +++ b/cpu/arm920t/cpu.c @@ -32,62 +32,13 @@ #include <common.h> #include <command.h> #include <arm920t.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM920T Technical reference Manual */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ - -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - +static void cache_flush(void); int cpu_init (void) { @@ -110,76 +61,21 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); + cache_flush(); - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} - -#ifdef USE_920T_MMU -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_DC); + return 0; } -void dcache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; + unsigned long i = 0; - reg = read_p15_c1 (); - cp_delay (); - reg &= ~C1_DC; - write_p15_c1 (reg); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_DC) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } -#endif diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c index b9f0931..cf6a489 100644 --- a/cpu/arm925t/cpu.c +++ b/cpu/arm925t/cpu.c @@ -32,62 +32,13 @@ #include <common.h> #include <command.h> #include <arm925t.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ +static void cache_flush(void); int cpu_init (void) { @@ -110,48 +61,23 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - return (0); -} + cache_flush(); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); + return 0; } -void icache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; + unsigned long i = 0; - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index 48a2c0b..6307e33 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -32,62 +32,13 @@ #include <common.h> #include <command.h> #include <arm926ejs.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM926EJ-S Technical Reference Manual */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ - -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - +static void cache_flush(void); int cpu_init (void) { @@ -110,76 +61,22 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); - /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - - return (0); -} + cache_flush(); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -/* cache_bit must be either C1_IC or C1_DC */ -static void cache_enable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = read_p15_c1(); /* get control reg. */ - cp_delay(); - write_p15_c1(reg | cache_bit); -} - -/* cache_bit must be either C1_IC or C1_DC */ -static void cache_disable(uint32_t cache_bit) -{ - uint32_t reg; - - reg = read_p15_c1(); - cp_delay(); - write_p15_c1(reg & ~cache_bit); -} - -void icache_enable(void) -{ - cache_enable(C1_IC); -} - -void icache_disable(void) -{ - cache_disable(C1_IC); -} - -int icache_status(void) -{ - return (read_p15_c1() & C1_IC) != 0; -} - -void dcache_enable(void) -{ - cache_enable(C1_DC); + return 0; } -void dcache_disable(void) +/* flush I/D-cache */ +static void cache_flush (void) { - cache_disable(C1_DC); -} + unsigned long i = 0; -int dcache_status(void) -{ - return (read_p15_c1() & C1_DC) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c index 44c589a..ef7995d 100644 --- a/cpu/arm946es/cpu.c +++ b/cpu/arm946es/cpu.c @@ -32,62 +32,13 @@ #include <common.h> #include <command.h> #include <arm946es.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM946E-S Technical Reference Manual */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ - -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ - +static void cache_flush(void); int cpu_init (void) { @@ -110,8 +61,6 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); /* ARM926E-S needs the protection unit enabled for the icache to have @@ -119,47 +68,19 @@ int cleanup_before_linux (void) * should turn off the protection unit as well.... */ /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); - return (0); -} + cache_flush(); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - extern void reset_cpu (ulong addr); - - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} -/* ARM926E-S needs the protection unit enabled for this to have any effect - - left for possible later use */ -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); + return 0; } -void icache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} + unsigned long i = 0; -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i)); } diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index ad2085b..5e7b935 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -34,6 +34,7 @@ #include <common.h> #include <command.h> #include <asm/arch/sys_proto.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; @@ -45,46 +46,6 @@ void l2cache_disable(void); static void cache_flush(void); -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1(void) -{ - unsigned long value; - - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\ - @ read control reg\n":"=r"(value) - ::"memory"); - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1(unsigned long value) -{ - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\ - @ write it back\n"::"r"(value) - : "memory"); - - read_p15_c1(); -} - -static void cp_delay(void) -{ - /* Many OMAP regs need at least 2 nops */ - asm("nop"); - asm("nop"); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_WB (1<<3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - int cpu_init(void) { /* @@ -134,42 +95,6 @@ int cleanup_before_linux(void) return 0; } -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts(); - reset_cpu(0); - - /* NOTREACHED */ - return 0; -} - -void icache_enable(void) -{ - ulong reg; - - reg = read_p15_c1(); /* get control reg. */ - cp_delay(); - write_p15_c1(reg | C1_IC); -} - -void icache_disable(void) -{ - ulong reg; - - reg = read_p15_c1(); - cp_delay(); - write_p15_c1(reg & ~C1_IC); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_DC); -} - void l2cache_enable() { unsigned long i; @@ -229,11 +154,6 @@ void l2cache_disable() } } -int icache_status(void) -{ - return (read_p15_c1() & C1_IC) != 0; -} - static void cache_flush(void) { asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 7bb3e28..15ea936 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -331,7 +331,7 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; usage: - printf ("Usage: nandecc %s\n", cmdtp->help); + printf ("Usage: nandecc %s\n", cmdtp->usage); return 1; } diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c index ccf7fd5..1636ffb 100644 --- a/cpu/arm_intcm/cpu.c +++ b/cpu/arm_intcm/cpu.c @@ -66,28 +66,3 @@ int cleanup_before_linux (void) return (0); } - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - extern void reset_cpu (ulong addr); - - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -/* May not be cahed processor on the CM - do nothing */ -void icache_enable (void) -{ -} - -void icache_disable (void) -{ -} - -/* return "disabled" */ -int icache_status (void) -{ - return 0; -} diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c index fd545b5..42c62f6 100644 --- a/cpu/ixp/cpu.c +++ b/cpu/ixp/cpu.c @@ -34,6 +34,7 @@ #include <command.h> #include <netdev.h> #include <asm/arch/ixp425.h> +#include <asm/system.h> ulong loops_per_jiffy; @@ -41,6 +42,8 @@ ulong loops_per_jiffy; DECLARE_GLOBAL_DATA_PTR; #endif +static void cache_flush(void); + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { @@ -98,92 +101,26 @@ int cleanup_before_linux (void) * just disable everything that can disturb booting linux */ - unsigned long i; - disable_interrupts (); /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable(); /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); - - return (0); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf ("resetting ...\n"); - - udelay (50000); /* wait 50 ms */ - disable_interrupts (); - reset_cpu (0); + cache_flush(); - /*NOTREACHED*/ - return (0); -} - -/* taken from blob */ -void icache_enable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* set i-cache */ - i |= 0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + return 0; } -void icache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* clear i-cache */ - i &= ~0x1000; + unsigned long i = 0; - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush i-cache */ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } -int icache_status (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* return bit */ - return (i & 0x1000); -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} - /* FIXME */ /* void pci_init(void) diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c index 8ff3a36..93ebd13 100644 --- a/cpu/lh7a40x/cpu.c +++ b/cpu/lh7a40x/cpu.c @@ -32,61 +32,13 @@ #include <common.h> #include <command.h> #include <arm920t.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - -#ifdef MMU_DEBUG - printf ("p15/c1 is = %08lx\n", value); -#endif - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ -#ifdef MMU_DEBUG - printf ("write %08lx to p15/c1\n", value); -#endif - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1 (); -} - -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1<<0) /* mmu off/on */ -#define C1_ALIGN (1<<1) /* alignment faults off/on */ -#define C1_DC (1<<2) /* dcache off/on */ -#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ -#define C1_SYS_PROT (1<<8) /* system protection */ -#define C1_ROM_PROT (1<<9) /* ROM protection */ -#define C1_IC (1<<12) /* icache off/on */ -#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ +static void cache_flush(void); int cpu_init (void) { @@ -109,75 +61,22 @@ int cleanup_before_linux (void) * we turn off caches etc ... */ - unsigned long i; - disable_interrupts (); /* turn off I/D-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(C1_DC | C1_IC); - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable(); /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); - return (0); -} + cache_flush(); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return (0); -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} - -#ifdef USE_920T_MMU -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_DC); + return 0; } -void dcache_disable (void) +/* flush I/D-cache */ +static void cache_flush (void) { - ulong reg; + unsigned long i = 0; - reg = read_p15_c1 (); - cp_delay (); - reg &= ~C1_DC; - write_p15_c1 (reg); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_DC) != 0; + asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } -#endif diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c index e84cb5b..3a1be57 100644 --- a/cpu/pxa/cpu.c +++ b/cpu/pxa/cpu.c @@ -33,11 +33,14 @@ #include <common.h> #include <command.h> #include <asm/arch/pxa-regs.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif +static void cache_flush(void); + int cpu_init (void) { /* @@ -59,92 +62,26 @@ int cleanup_before_linux (void) * just disable everything that can disturb booting linux */ - unsigned long i; - disable_interrupts (); /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable(); /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + cache_flush(); return (0); } -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +/* flush I/D-cache */ +static void cache_flush (void) { - printf ("resetting ...\n"); - - udelay (50000); /* wait 50 ms */ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} - -/* taken from blob */ -void icache_enable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* set i-cache */ - i |= 0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void icache_disable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + unsigned long i = 0; - /* clear i-cache */ - i &= ~0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush i-cache */ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } -int icache_status (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* return bit */ - return (i & 0x1000); -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} - #ifndef CONFIG_CPU_MONAHANS void set_GPIO_mode(int gpio_mode) { diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c index e4cdb82..7ef4a1f 100644 --- a/cpu/s3c44b0/cpu.c +++ b/cpu/s3c44b0/cpu.c @@ -72,12 +72,3 @@ void reset_cpu (ulong addr) /*NOP*/ } } - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c index bb4e5a1..ed1a6f7 100644 --- a/cpu/sa1100/cpu.c +++ b/cpu/sa1100/cpu.c @@ -32,11 +32,14 @@ #include <common.h> #include <command.h> +#include <asm/system.h> #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; #endif +static void cache_flush(void); + int cpu_init (void) { /* @@ -58,88 +61,22 @@ int cleanup_before_linux (void) * just disable everything that can disturb booting linux */ - unsigned long i; - disable_interrupts (); /* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + icache_disable(); + dcache_disable(); /* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + cache_flush(); return (0); } -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +/* flush I/D-cache */ +static void cache_flush (void) { - printf ("resetting ...\n"); - - udelay (50000); /* wait 50 ms */ - disable_interrupts (); - reset_cpu (0); - - /*NOTREACHED*/ - return (0); -} - -/* taken from blob */ -void icache_enable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* set i-cache */ - i |= 0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); -} - -void icache_disable (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + unsigned long i = 0; - /* clear i-cache */ - i &= ~0x1000; - - /* write back to control register */ - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); - - /* flush i-cache */ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); } - -int icache_status (void) -{ - register u32 i; - - /* read control register */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - - /* return bit */ - return (i & 0x1000); -} - -/* we will never enable dcache, because we have to setup MMU first */ -void dcache_enable (void) -{ - return; -} - -void dcache_disable (void) -{ - return; -} - -int dcache_status (void) -{ - return 0; /* always off */ -} |