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authorwdenk <wdenk>2005-05-09 10:17:32 (GMT)
committerwdenk <wdenk>2005-05-09 10:17:32 (GMT)
commited16fefcbaf99a67a7dd7639898dbc896c70cb1b (patch)
tree588d9a44a35df45e937c09c8f8bd603f4c43efbe /cpu
parent931da93e0fced277c058c0c989d30bd1f6d10742 (diff)
downloadu-boot-fsl-qoriq-ed16fefcbaf99a67a7dd7639898dbc896c70cb1b.tar.xz
On LWMON we must use the watchdog to reset the board as the CPU
genereated HRESET pulse is too short to reset the external circuitry.
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc8xx/cpu.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c
index 5f92a37..4a32986 100644
--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@@ -463,6 +463,8 @@ void upmconfig (uint upm, uint * table, uint size)
/* ------------------------------------------------------------------------- */
+#ifndef CONFIG_LWMON
+
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong msr, addr;
@@ -497,6 +499,32 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
+#else /* CONFIG_LWMON */
+
+/*
+ * On the LWMON board, the MCLR reset input of the PIC's on the board
+ * uses a 47K/1n RC combination which has a 47us time constant. The
+ * low signal on the HRESET pin of the CPU is only 512 clocks = 8 us
+ * and thus too short to reset the external hardware. So we use the
+ * watchdog to reset the board.
+ */
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ /* prevent triggering the watchdog */
+ disable_interrupts ();
+
+ /* make sure the watchdog is running */
+ reset_8xx_watchdog ((immap_t *) CFG_IMMR);
+
+ /* wait for watchdog reset */
+ while (1) {};
+
+ /* NOTREACHED */
+ return 1;
+}
+
+#endif /* CONFIG_LWMON */
+
/* ------------------------------------------------------------------------- */
/*
@@ -558,6 +586,9 @@ void watchdog_reset (void)
if (re_enable)
enable_interrupts ();
}
+#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
void reset_8xx_watchdog (volatile immap_t * immr)
{