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| author | Grzegorz Bernacki <gjb@semihalf.com> | 2007-09-07 16:20:23 (GMT) |
|---|---|---|
| committer | Rafal Jaworowski <raj@semihalf.com> | 2007-09-07 16:20:23 (GMT) |
| commit | 7f1913938984ef6c6a46cb53e003719196d9c5de (patch) | |
| tree | 127789e73caeb3464c9941c1f96440031b1e3f6c /doc/README.nand-boot-ppc440 | |
| parent | 15ee4734e4e08003d73d9ead3ca80e2a0672e427 (diff) | |
| download | u-boot-fsl-qoriq-7f1913938984ef6c6a46cb53e003719196d9c5de.tar.xz | |
[PPC440SPe] Improve PCIe configuration space access
- correct configuration space mapping
- correct bus numbering
- better access to config space
Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
first device on the first bus. We now allow to configure up to 16 buses;
also, scanning for devices behind the PCIe-PCIe bridge is supported, so
peripheral devices farther in hierarchy can be identified.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Diffstat (limited to 'doc/README.nand-boot-ppc440')
0 files changed, 0 insertions, 0 deletions