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authorYork Sun <yorksun@freescale.com>2014-08-21 23:13:22 (GMT)
committerYork Sun <yorksun@freescale.com>2014-09-25 15:36:18 (GMT)
commitbb5783224b9b12eecf406761f82e3de2a2ca9dae (patch)
tree5ac9b5958714c356191ecf2a7a2cd03d76cd6aac /drivers/ddr/fsl/options.c
parentd9c68b1444acb383684636eb856fd7e4cec04129 (diff)
downloadu-boot-fsl-qoriq-bb5783224b9b12eecf406761f82e3de2a2ca9dae.tar.xz
driver/ddr/fsl: Fix tXP and tCKE
The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/options.c')
-rw-r--r--drivers/ddr/fsl/options.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 31cc2bf..6d098d1 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -777,10 +777,6 @@ unsigned int populate_memctl_options(int all_dimms_registered,
*/
popts->bstopre = 0x100;
- /* Minimum CKE pulse width -- tCKE(MIN) */
- popts->tcke_clock_pulse_width_ps
- = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
-
/*
* Window for four activates -- tFAW
*