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author | Lokesh Vutla <lokeshvutla@ti.com> | 2016-05-23 08:01:19 (GMT) |
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committer | Tom Rini <trini@konsulko.com> | 2016-05-27 19:47:57 (GMT) |
commit | 9b77b19178446393fce2e74554815c17454f8da8 (patch) | |
tree | 72bf8dd28d739040e0829f59617dad0a6149c127 /drivers/net | |
parent | 87c2f76f3fae11bf559996505e23b37d03f4c5dc (diff) | |
download | u-boot-fsl-qoriq-9b77b19178446393fce2e74554815c17454f8da8.tar.xz |
ARM: OMAP4+: Fix DPLL programming sequence
All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'drivers/net')
0 files changed, 0 insertions, 0 deletions