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authorStefan Roese <sr@denx.de>2017-03-10 05:07:45 (GMT)
committerStefan Roese <sr@denx.de>2017-03-29 05:44:32 (GMT)
commitfb64072934a5a4d0e8b89d2e9fd64c5e12d5c2ea (patch)
tree8be8abdb547a9d422a20320c334c435b59c5629b /drivers/net
parent3e3cbb4967f0bff734aba20ca501bd391d858d77 (diff)
downloadu-boot-fsl-qoriq-fb64072934a5a4d0e8b89d2e9fd64c5e12d5c2ea.tar.xz
net: mvpp2: Configure SMI PHY address needed for PHY polling
On PPv2.2 we enable PHY polling, so we also need to configure the PHY address in the specific PHY address rgisters. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/mvpp2.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 36e209e..dc9fbb9 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5329,6 +5329,14 @@ static void mvpp2_stop(struct udevice *dev)
mvpp2_cleanup_txqs(port);
}
+static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
+{
+ writel(port->phyaddr, port->priv->iface_base +
+ MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
+
+ return 0;
+}
+
static int mvpp2_base_probe(struct udevice *dev)
{
struct mvpp2 *priv = dev_get_priv(dev);
@@ -5467,6 +5475,9 @@ static int mvpp2_probe(struct udevice *dev)
port->base = priv->iface_base + MVPP22_PORT_BASE +
port->gop_id * MVPP22_PORT_OFFSET;
+ /* Set phy address of the port */
+ mvpp22_smi_phy_addr_cfg(port);
+
/* GoP Init */
gop_port_init(port);
}