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authorSimon Glass <sjg@chromium.org>2015-06-07 14:50:40 (GMT)
committerSimon Glass <sjg@chromium.org>2015-07-15 00:03:17 (GMT)
commitaec241dfb45e7763716c1cbc98942cb01a3a77fd (patch)
tree1dccf1997219cdcd4bc565751ac5142113d235d3 /drivers/pci/pci-uclass.c
parentcdb6babec6422ad4b89e447b1b468f625deaea79 (diff)
downloadu-boot-fsl-qoriq-aec241dfb45e7763716c1cbc98942cb01a3a77fd.tar.xz
dm: pci: Use the correct hose when configuring devices
Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pci/pci-uclass.c')
-rw-r--r--drivers/pci/pci-uclass.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index de87505..41d19cb 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -296,6 +296,7 @@ int pci_auto_config_devices(struct udevice *bus)
!ret && dev;
ret = device_find_next_child(&dev)) {
struct pci_child_platdata *pplat;
+ struct pci_controller *ctlr_hose;
pplat = dev_get_parent_platdata(dev);
unsigned int max_bus;
@@ -303,7 +304,10 @@ int pci_auto_config_devices(struct udevice *bus)
bdf = PCI_ADD_BUS(bus->seq, pplat->devfn);
debug("%s: device %s\n", __func__, dev->name);
- max_bus = pciauto_config_device(hose, bdf);
+
+ /* The root controller has the region information */
+ ctlr_hose = hose->ctlr->uclass_priv;
+ max_bus = pciauto_config_device(ctlr_hose, bdf);
sub_bus = max(sub_bus, max_bus);
}
debug("%s: done\n", __func__);