diff options
| author | Dani Krishna Mohan <krishna.md@samsung.com> | 2013-09-11 11:08:46 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-09-24 13:10:33 (GMT) |
| commit | d981d80d743623d50e10de77dfe013263aa0c866 (patch) | |
| tree | a9067d2c9269a1d81d021125ee9b1d34f29bf044 /drivers/sound/wm8994_registers.h | |
| parent | d7884e047d08447dfd1374e9fa2fdf7ab36e56f5 (diff) | |
| download | u-boot-fsl-qoriq-d981d80d743623d50e10de77dfe013263aa0c866.tar.xz | |
Sound: WM8994: Support I2S0 channel
This patch modifies the WM8994 codec to support I2S0 channel
in codec slave mode
Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
Diffstat (limited to 'drivers/sound/wm8994_registers.h')
| -rw-r--r-- | drivers/sound/wm8994_registers.h | 39 |
1 files changed, 35 insertions, 4 deletions
diff --git a/drivers/sound/wm8994_registers.h b/drivers/sound/wm8994_registers.h index 1e987c2..0aba2fd 100644 --- a/drivers/sound/wm8994_registers.h +++ b/drivers/sound/wm8994_registers.h @@ -13,6 +13,7 @@ #define WM8994_SOFTWARE_RESET 0x00 #define WM8994_POWER_MANAGEMENT_1 0x01 #define WM8994_POWER_MANAGEMENT_2 0x02 +#define WM8994_POWER_MANAGEMENT_4 0x04 #define WM8994_POWER_MANAGEMENT_5 0x05 #define WM8994_LEFT_OUTPUT_VOLUME 0x1C #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D @@ -38,6 +39,7 @@ #define WM8994_AIF2_CONTROL_2 0x311 #define WM8994_AIF2_MASTER_SLAVE 0x312 #define WM8994_AIF2_BCLK 0x313 +#define WM8994_AIF1_DAC_FILTERS_1 0x420 #define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 #define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503 #define WM8994_AIF2_DAC_FILTERS_1 0x520 @@ -45,6 +47,7 @@ #define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 #define WM8994_DAC1_LEFT_VOLUME 0x610 #define WM8994_DAC1_RIGHT_VOLUME 0x611 +#define WM8994_GPIO_1 0x700 #define WM8994_GPIO_3 0x702 #define WM8994_GPIO_4 0x703 #define WM8994_GPIO_5 0x704 @@ -82,6 +85,20 @@ /* OPCLK_ENA */ #define WM8994_OPCLK_ENA 0x0800 +#define WM8994_TSHUT_ENA 0x4000 +#define WM8994_MIXINL_ENA 0x0200 +#define WM8994_MIXINR_ENA 0x0100 +#define WM8994_IN2L_ENA 0x0080 +#define WM8994_IN2R_ENA 0x0020 + +/* + * R5 (0x04) - Power Management (4) + */ +#define WM8994_ADCL_ENA 0x0001 +#define WM8994_ADCR_ENA 0x0002 +#define WM8994_AIF1ADC1R_ENA 0x0100 +#define WM8994_AIF1ADC1L_ENA 0x0200 + /* * R5 (0x05) - Power Management (5) */ @@ -91,6 +108,12 @@ /* AIF2DACR_ENA */ #define WM8994_AIF2DACR_ENA 0x1000 #define WM8994_AIF2DACR_ENA_MASK 0x1000 +/* AIF1DACL_ENA */ +#define WM8994_AIF1DACL_ENA 0x0200 +#define WM8994_AIF1DACL_ENA_MASK 0x0200 +/* AIF1DACR_ENA */ +#define WM8994_AIF1DACR_ENA 0x0100 +#define WM8994_AIF1DACR_ENA_MASK 0x0100 /* DAC1L_ENA */ #define WM8994_DAC1L_ENA 0x0002 #define WM8994_DAC1L_ENA_MASK 0x0002 @@ -170,6 +193,9 @@ /* * R520 (0x208) - Clocking (1) */ +/* AIF1DSPCLK_ENA */ +#define WM8994_AIF1DSPCLK_ENA 0x0008 +#define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF2DSPCLK_ENA */ #define WM8994_AIF2DSPCLK_ENA 0x0004 #define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 @@ -254,6 +280,8 @@ /* AIF2DACL_TO_DAC1L */ #define WM8994_AIF2DACL_TO_DAC1L 0x0004 #define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 +/* AIF1DAC1L_TO_DAC1L */ +#define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 /* * R1538 (0x602) - DAC1 Right Mixer Routing @@ -261,6 +289,8 @@ /* AIF2DACR_TO_DAC1R */ #define WM8994_AIF2DACR_TO_DAC1R 0x0004 #define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 +/* AIF1DAC1R_TO_DAC1R */ +#define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 /* * R1552 (0x610) - DAC1 Left Volume @@ -285,11 +315,12 @@ * GPIO */ /* OUTPUT PIN */ -#define WM8994_GPIO_DIR_OUTPUT 0x8000 +#define WM8994_GPIO_DIR_OUTPUT 0x8000 /* GPIO PIN MASK */ -#define WM8994_GPIO_DIR_MASK 0xFFE0 +#define WM8994_GPIO_DIR_MASK 0xFFE0 /* I2S CLK */ -#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0000 +#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0001 +#define WM8994_GPIO_INPUT_DEBOUNCE 0x0100 /* GPn FN */ -#define WM8994_GPIO_FUNCTION_MASK 0x001F +#define WM8994_GPIO_FUNCTION_MASK 0x001F #endif |