diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2014-02-28 07:12:25 (GMT) |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2014-08-11 15:31:41 (GMT) |
| commit | e66866c542e492c42f04cfc2e59317203b7cd6ea (patch) | |
| tree | 7b9f9ab94172bb0eb046029f7b4bd821ba0f0f91 /drivers/video/ipu_regs.h | |
| parent | 3c5fabd13993172e6c29500cc78de8ef7c1abbc0 (diff) | |
| download | u-boot-fsl-qoriq-e66866c542e492c42f04cfc2e59317203b7cd6ea.tar.xz | |
video: ipu_disp: wait for DP SF end irq when disabling sync BG flows
Instead of waiting for DC triple buffer to be cleared, this patch
changes to wait for a relevant DP sync flow end interrupt to come
when disabling sync BG flows. In this way, we align the implement
to the freescale internal IPUv3 driver. After applying this patch,
an uboot hang up issue at the arch_preboot_os() stage, where we
disable a relevant ipu display channel, is not observed any more on
some MX6DL platforms.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'drivers/video/ipu_regs.h')
| -rw-r--r-- | drivers/video/ipu_regs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index 21e9c99..c2c134a 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -313,9 +313,12 @@ struct ipu_dmfc { #define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \ IPU_STAT_REG_BASE)) +#define IPU_INT_STAT(n) (&IPU_STAT->int_stat[(n) - 1]) #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32]) #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32]) #define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32]) +#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32)) +#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F)) #define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1]) |