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author | Tom Rini <trini@konsulko.com> | 2017-04-08 13:28:02 (GMT) |
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committer | Tom Rini <trini@konsulko.com> | 2017-04-08 13:28:02 (GMT) |
commit | 089795090a627f4216c5f21eaf436ba1672cf02e (patch) | |
tree | 386074cdee0ea3fe02cc6ee8228c5adb8d7e7ea7 /drivers | |
parent | b09ece0836e0267b86f37defec267aa3806cb03a (diff) | |
parent | f7d4d9e52cdcff2a8fcdc80b567a41f48b61951c (diff) | |
download | u-boot-fsl-qoriq-089795090a627f4216c5f21eaf436ba1672cf02e.tar.xz |
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mtd/nand/Kconfig | 19 | ||||
-rw-r--r-- | drivers/mtd/nand/sunxi_nand_spl.c | 7 | ||||
-rw-r--r-- | drivers/mtd/ubi/Kconfig | 1 | ||||
-rw-r--r-- | drivers/net/sun8i_emac.c | 86 |
4 files changed, 103 insertions, 10 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index a2ea9b1..a7b76f4 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -67,12 +67,29 @@ config NAND_SUNXI bool "Support for NAND on Allwinner SoCs" depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I select SYS_NAND_SELF_INIT + select SYS_NAND_U_BOOT_LOCATIONS ---help--- Enable support for NAND. This option enables the standard and SPL drivers. The SPL driver only supports reading from the NAND using DMA transfers. +if NAND_SUNXI + +config NAND_SUNXI_SPL_ECC_STRENGTH + int "Allwinner NAND SPL ECC Strength" + default 64 + +config NAND_SUNXI_SPL_ECC_SIZE + int "Allwinner NAND SPL ECC Step Size" + default 1024 + +config NAND_SUNXI_SPL_USABLE_PAGE_SIZE + int "Allwinner NAND SPL Usable Page Size" + default 1024 + +endif + config NAND_ARASAN bool "Configure Arasan Nand" help @@ -127,7 +144,7 @@ config SYS_NAND_U_BOOT_LOCATIONS config SYS_NAND_U_BOOT_OFFS hex "Location in NAND to read U-Boot from" - default 0x8000 if NAND_SUNXI + default 0x800000 if NAND_SUNXI depends on SYS_NAND_U_BOOT_LOCATIONS help Set the offset from the start of the nand where u-boot should be diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 1ef7366..eed4472 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -245,7 +245,7 @@ static int nand_read_page(const struct nfc_config *conf, u32 offs, { dma_addr_t dst = (dma_addr_t)dest; int nsectors = len / conf->ecc_size; - u16 rand_seed; + u16 rand_seed = 0; u32 val; int page; @@ -258,8 +258,9 @@ static int nand_read_page(const struct nfc_config *conf, u32 offs, /* clear ecc status */ writel(0, SUNXI_NFC_BASE + NFC_ECC_ST); - /* Choose correct seed */ - rand_seed = random_seed[page % conf->nseeds]; + /* Choose correct seed if randomized */ + if (conf->randomize) + rand_seed = random_seed[page % conf->nseeds]; writel((rand_seed << 16) | (conf->ecc_strength << 12) | (conf->randomize ? NFC_ECC_RANDOM_EN : 0) | diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index 0c82395..cb9ba78 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -3,6 +3,7 @@ menu "UBI support" config MTD_UBI bool "Enable UBI - Unsorted block images" select CRC32 + select RBTREE if ARCH_SUNXI help UBI is a software layer above MTD layer which admits of LVM-like logical volumes on top of MTD devices, hides some complexities of diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index abdfada..a3dbe28 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -21,6 +21,9 @@ #include <malloc.h> #include <miiphy.h> #include <net.h> +#ifdef CONFIG_DM_GPIO +#include <asm-generic/gpio.h> +#endif #define MDIO_CMD_MII_BUSY BIT(0) #define MDIO_CMD_MII_WRITE BIT(1) @@ -128,11 +131,22 @@ struct emac_eth_dev { phys_addr_t sysctl_reg; struct phy_device *phydev; struct mii_dev *bus; +#ifdef CONFIG_DM_GPIO + struct gpio_desc reset_gpio; +#endif +}; + + +struct sun8i_eth_pdata { + struct eth_pdata eth_pdata; + u32 reset_delays[3]; }; + static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { - struct emac_eth_dev *priv = bus->priv; + struct udevice *dev = bus->priv; + struct emac_eth_dev *priv = dev_get_priv(dev); ulong start; u32 miiaddr = 0; int timeout = CONFIG_MDIO_TIMEOUT; @@ -164,7 +178,8 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val) { - struct emac_eth_dev *priv = bus->priv; + struct udevice *dev = bus->priv; + struct emac_eth_dev *priv = dev_get_priv(dev); ulong start; u32 miiaddr = 0; int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; @@ -604,7 +619,41 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); } -static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv) +#if defined(CONFIG_DM_GPIO) +static int sun8i_mdio_reset(struct mii_dev *bus) +{ + struct udevice *dev = bus->priv; + struct emac_eth_dev *priv = dev_get_priv(dev); + struct sun8i_eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + if (!dm_gpio_is_valid(&priv->reset_gpio)) + return 0; + + /* reset the phy */ + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) + return ret; + + udelay(pdata->reset_delays[0]); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) + return ret; + + udelay(pdata->reset_delays[1]); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) + return ret; + + udelay(pdata->reset_delays[2]); + + return 0; +} +#endif + +static int sun8i_mdio_init(const char *name, struct udevice *priv) { struct mii_dev *bus = mdio_alloc(); @@ -617,6 +666,9 @@ static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv) bus->write = sun8i_mdio_write; snprintf(bus->name, sizeof(bus->name), name); bus->priv = (void *)priv; +#if defined(CONFIG_DM_GPIO) + bus->reset = sun8i_mdio_reset; +#endif return mdio_register(bus); } @@ -696,7 +748,7 @@ static int sun8i_emac_eth_probe(struct udevice *dev) sun8i_emac_board_setup(priv); sun8i_emac_set_syscon(priv); - sun8i_mdio_init(dev->name, priv); + sun8i_mdio_init(dev->name, dev); priv->bus = miiphy_get_dev_by_name(dev->name); return sun8i_phy_init(priv, dev); @@ -713,11 +765,16 @@ static const struct eth_ops sun8i_emac_eth_ops = { static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_platdata(dev); + struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); + struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; struct emac_eth_dev *priv = dev_get_priv(dev); const char *phy_mode; int node = dev_of_offset(dev); int offset = 0; +#ifdef CONFIG_DM_GPIO + int reset_flags = GPIOD_IS_OUT; + int ret = 0; +#endif pdata->iobase = dev_get_addr_name(dev, "emac"); priv->sysctl_reg = dev_get_addr_name(dev, "syscon"); @@ -762,6 +819,23 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) if (!priv->use_internal_phy) parse_phy_pins(dev); +#ifdef CONFIG_DM_GPIO + if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, + "snps,reset-active-low")) + reset_flags |= GPIOD_ACTIVE_LOW; + + ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, + &priv->reset_gpio, reset_flags); + + if (ret == 0) { + ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "snps,reset-delays-us", + sun8i_pdata->reset_delays, 3); + } else if (ret == -ENOENT) { + ret = 0; + } +#endif + return 0; } @@ -782,6 +856,6 @@ U_BOOT_DRIVER(eth_sun8i_emac) = { .probe = sun8i_emac_eth_probe, .ops = &sun8i_emac_eth_ops, .priv_auto_alloc_size = sizeof(struct emac_eth_dev), - .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; |