diff options
| author | Peng Fan <peng.fan@nxp.com> | 2017-06-12 09:50:53 (GMT) |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2017-07-12 07:44:22 (GMT) |
| commit | 32a9179f3adf6b36d85601ff6eba251dc6d207f9 (patch) | |
| tree | b4b4be9b325eefea3498811a499be97bd34dfd7c /drivers | |
| parent | 15a91651bffa1892eec04dc10b02e24a123203ef (diff) | |
| download | u-boot-fsl-qoriq-32a9179f3adf6b36d85601ff6eba251dc6d207f9.tar.xz | |
mmc: fsl_esdhc: introduce vs18_enable for 1.8V fix I/O
When using eMMC with 1.8V I/O, the VSELECT bit need to be set in
the USDHC controller when init.
This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg
structure and priv data, so each controller can have different
settings.
We could not use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT, it has problem
that it will apply to all USDHC controllers and it only set the 1.8V
at init phase. So if user does not select to the eMMC device,
the voltage on the I/O pins are not correct.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 73748c5..74a0017 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -92,6 +92,7 @@ struct fsl_esdhc { * @dev: pointer for the device * @non_removable: 0: removable; 1: non-removable * @wp_enable: 1: enable checking wp; 0: no check + * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V * @cd_gpio: gpio for card detection * @wp_gpio: gpio for write protection */ @@ -104,6 +105,7 @@ struct fsl_esdhc_priv { struct udevice *dev; int non_removable; int wp_enable; + int vs18_enable; #ifdef CONFIG_DM_GPIO struct gpio_desc cd_gpio; struct gpio_desc wp_gpio; @@ -674,6 +676,9 @@ static int esdhc_init(struct mmc *mmc) esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); #endif + if (priv->vs18_enable) + esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); + return 0; } @@ -746,6 +751,9 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); #endif + if (priv->vs18_enable) + esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); + writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); memset(&priv->cfg, 0, sizeof(priv->cfg)); @@ -831,6 +839,7 @@ static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, priv->bus_width = cfg->max_bus_width; priv->sdhc_clk = cfg->sdhc_clk; priv->wp_enable = cfg->wp_enable; + priv->vs18_enable = cfg->vs18_enable; return 0; }; |