Merge branch 'master' of http://git.denx.de/u-boot-sunxi

9 files changed, 118 insertions, 17 deletions

diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c
index bd2ac89..ec00827 100644
--- a/drivers/gpio/axp_gpio.c
+++ b/drivers/gpio/axp_gpio.c
@@ -59,10 +59,11 @@ static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
 	u8 reg;
 
 	switch (pin) {
-#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
+#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+	/* Only available on later PMICs */
 	case SUNXI_GPIO_AXP0_VBUS_ENABLE:
-		ret = pmic_bus_clrbits(AXP221_MISC_CTRL,
-				       AXP221_MISC_CTRL_N_VBUSEN_FUNC);
+		ret = pmic_bus_clrbits(AXP_MISC_CTRL,
+				       AXP_MISC_CTRL_N_VBUSEN_FUNC);
 		if (ret)
 			return ret;
 
@@ -90,10 +91,11 @@ static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
 		mask = AXP_POWER_STATUS_VBUS_PRESENT;
 		break;
 #endif
-#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
+#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+	/* Only available on later PMICs */
 	case SUNXI_GPIO_AXP0_VBUS_ENABLE:
-		ret = pmic_bus_read(AXP221_VBUS_IPSOUT, &val);
-		mask = AXP221_VBUS_IPSOUT_DRIVEBUS;
+		ret = pmic_bus_read(AXP_VBUS_IPSOUT, &val);
+		mask = AXP_VBUS_IPSOUT_DRIVEBUS;
 		break;
 #endif
 	default:
@@ -115,14 +117,15 @@ static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val)
 	u8 reg;
 
 	switch (pin) {
-#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
+#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+	/* Only available on later PMICs */
 	case SUNXI_GPIO_AXP0_VBUS_ENABLE:
 		if (val)
-			return pmic_bus_setbits(AXP221_VBUS_IPSOUT,
-						AXP221_VBUS_IPSOUT_DRIVEBUS);
+			return pmic_bus_setbits(AXP_VBUS_IPSOUT,
+						AXP_VBUS_IPSOUT_DRIVEBUS);
 		else
-			return pmic_bus_clrbits(AXP221_VBUS_IPSOUT,
-						AXP221_VBUS_IPSOUT_DRIVEBUS);
+			return pmic_bus_clrbits(AXP_VBUS_IPSOUT,
+						AXP_VBUS_IPSOUT_DRIVEBUS);
 #endif
 	default:
 		reg = axp_get_gpio_ctrl_reg(pin);
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 7b33094..ce2dc4a 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -339,7 +339,7 @@ static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 
 	if (data) {
-		if ((u32) data->dest & 0x3) {
+		if ((u32)(long)data->dest & 0x3) {
 			error = -1;
 			goto out;
 		}
@@ -480,6 +480,10 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	cfg->host_caps = MMC_MODE_4BIT;
+#ifdef CONFIG_MACH_SUN50I
+	if (sdc_no == 2)
+		cfg->host_caps = MMC_MODE_8BIT;
+#endif
 	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 2a229b8..e0008fd 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -13,6 +13,27 @@ config PHYLIB
 	help
 	  Enable Ethernet PHY (physical media interface) support.
 
+config RTL8211X_PHY_FORCE_MASTER
+	bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
+	depends on PHYLIB
+	help
+	  Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
+	  This can work around link stability and data corruption issues on gigabit
+	  links which can occur in slave mode on certain PHYs, e.g. on the
+	  RTL8211C(L).
+
+	  Please note that two directly connected devices (i.e. via crossover cable)
+	  will not be able to establish a link between each other if they both force
+	  master mode. Multiple devices forcing master mode when connected by a
+	  network switch do not pose a problem as the switch configures its affected
+	  ports into slave mode.
+
+	  This option only affects gigabit links. If you must establish a direct
+	  connection between two devices which both force master mode, try forcing
+	  the link speed to 100MBit/s.
+
+	  If unsure, say N.
+
 menuconfig NETDEVICES
 	bool "Network device support"
 	depends on NET
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 259a87f..359ec50 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -12,6 +12,10 @@
 
 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
 
+/* RTL8211x 1000BASE-T Control Register */
+#define MIIM_RTL8211x_CTRL1000T_MSCE (1 << 12);
+#define MIIM_RTL8211X_CTRL1000T_MASTER (1 << 11);
+
 /* RTL8211x PHY Status Register */
 #define MIIM_RTL8211x_PHY_STATUS       0x11
 #define MIIM_RTL8211x_PHYSTAT_SPEED    0xc000
@@ -53,7 +57,14 @@ static int rtl8211x_config(struct phy_device *phydev)
 	 */
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
 		  MIIM_RTL8211x_PHY_INTR_DIS);
-
+#ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
+	unsigned int reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
+	/* force manual master/slave configuration */
+	reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
+	/* force master mode */
+	reg |= MIIM_RTL8211X_CTRL1000T_MASTER;
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
+#endif
 	/* read interrupt status just to clear it */
 	phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
 
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index adc6455..3c41bca 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -10,7 +10,7 @@ choice
 	default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
 	default AXP818_POWER if MACH_SUN8I_A83T
-	default SUNXI_NO_PMIC if MACH_SUN8I_H3
+	default SUNXI_NO_PMIC if MACH_SUN8I_H3 || MACH_SUN50I
 
 config SUNXI_NO_PMIC
 	boolean "board without a pmic"
@@ -118,13 +118,12 @@ config AXP_DCDC4_VOLT
 config AXP_DCDC5_VOLT
 	int "axp pmic dcdc5 voltage"
 	depends on AXP221_POWER || AXP818_POWER
-	default 1800 if AXP818_POWER
 	default 1500 if MACH_SUN6I || MACH_SUN8I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
 	disable dcdc5.
 	On A23 / A31 / A33 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V,
-	1.8V for A83T.
+	1.35V if DDR3L is used.
 
 config AXP_ALDO1_VOLT
 	int "axp pmic (a)ldo1 voltage"
@@ -239,6 +238,33 @@ config AXP_ELDO3_VOLT
 	1.2V for the SSD2828 chip (converter of parallel LCD interface
 	into MIPI DSI).
 
+config AXP_FLDO1_VOLT
+	int "axp pmic fldo1 voltage"
+	depends on AXP818_POWER
+	default 0 if MACH_SUN8I_A83T
+	---help---
+	Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to
+	disable fldo1.
+	On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is
+	used.
+
+config AXP_FLDO2_VOLT
+	int "axp pmic eldo2 voltage"
+	depends on AXP818_POWER
+	default 900 if MACH_SUN8I_A83T
+	---help---
+	Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to
+	disable fldo2.
+	On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V.
+
+config AXP_FLDO3_VOLT
+	int "axp pmic fldo3 voltage"
+	depends on AXP818_POWER
+	default 0
+	---help---
+	Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to
+	disable fldo3.
+
 config SY8106A_VOUT1_VOLT
 	int "SY8106A pmic VOUT1 voltage"
 	depends on SY8106A_POWER
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index e885d02..3ac05ff 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -191,6 +191,40 @@ int axp_set_eldo(int eldo_num, unsigned int mvolt)
 				AXP818_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
 }
 
+int axp_set_fldo(int fldo_num, unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (fldo_num < 1 || fldo_num > 3)
+		return -EINVAL;
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP818_OUTPUT_CTRL3,
+				AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1));
+
+	if (fldo_num < 3) {
+		cfg = axp818_mvolt_to_cfg(mvolt, 700, 1450, 50);
+		ret = pmic_bus_write(AXP818_FLDO1_CTRL + (fldo_num - 1), cfg);
+	} else {
+		/*
+		 * Special case for FLDO3, which is DCDC5 / 2 or FLDOIN / 2
+		 * Since FLDOIN is unknown, test against DCDC5.
+		 */
+		if (mvolt * 2 == CONFIG_AXP_DCDC5_VOLT)
+			ret = pmic_bus_clrbits(AXP818_FLDO2_3_CTRL,
+					       AXP818_FLDO2_3_CTRL_FLDO3_VOL);
+		else
+			ret = pmic_bus_setbits(AXP818_FLDO2_3_CTRL,
+					       AXP818_FLDO2_3_CTRL_FLDO3_VOL);
+	}
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP818_OUTPUT_CTRL3,
+				AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1));
+}
+
 int axp_init(void)
 {
 	u8 axp_chip_id;
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 677a5d3..d5eb492 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -91,6 +91,7 @@ static const struct udevice_id ehci_usb_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-ehci", },
 	{ .compatible = "allwinner,sun7i-a20-ehci", },
 	{ .compatible = "allwinner,sun8i-a23-ehci", },
+	{ .compatible = "allwinner,sun8i-a83t-ehci", },
 	{ .compatible = "allwinner,sun8i-h3-ehci",  },
 	{ .compatible = "allwinner,sun9i-a80-ehci", },
 	{ }
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index d4fb95a..6f3f4ce 100644
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -94,6 +94,7 @@ static const struct udevice_id ohci_usb_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-ohci", },
 	{ .compatible = "allwinner,sun7i-a20-ohci", },
 	{ .compatible = "allwinner,sun8i-a23-ohci", },
+	{ .compatible = "allwinner,sun8i-a83t-ohci", },
 	{ .compatible = "allwinner,sun8i-h3-ohci",  },
 	{ .compatible = "allwinner,sun9i-a80-ohci", },
 	{ }
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h
index 4dc9abb..0f18dd7 100644
--- a/drivers/usb/musb-new/musb_regs.h
+++ b/drivers/usb/musb-new/musb_regs.h
@@ -434,7 +434,7 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
 
 static inline u8 musb_read_configdata(void __iomem *mbase)
 {
-#ifdef CONFIG_MACH_SUN8I_A33
+#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T
 	/* <Sigh> allwinner saves a reg, and we need to hardcode this */
 	return 0xde;
 #else