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authorBenoît Thébaudeau <benoit@wsystem.com>2017-05-03 09:59:06 (GMT)
committerStefano Babic <sbabic@denx.de>2017-05-31 08:14:41 (GMT)
commit747778cf69468daa1f35abb932e17032ddfe9c1a (patch)
tree941e43aba76e6868955a8a57d4186cbf077f758d /drivers
parent3e3aab3379d99f4c955ecca4992ad33ae70e71e4 (diff)
downloadu-boot-fsl-qoriq-747778cf69468daa1f35abb932e17032ddfe9c1a.tar.xz
mx25pdk: Set the eSDHC PER clock to 48 MHz
The maximum SD clock frequency in High Speed mode is 50 MHz. This change makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1) instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2). Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
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