diff options
author | Wolfgang Denk <wd@denx.de> | 2011-07-30 13:33:49 (GMT) |
---|---|---|
committer | Wolfgang Denk <wd@denx.de> | 2011-08-01 13:19:40 (GMT) |
commit | e6a857da746d5d7d450e59c0f86664c6b279b1c2 (patch) | |
tree | d95cae5bc677061c4313f7405545e837d67b02ee /drivers | |
parent | f6c019c45440c61734a6ea02d27895820fbba31e (diff) | |
download | u-boot-fsl-qoriq-e6a857da746d5d7d450e59c0f86664c6b279b1c2.tar.xz |
fpga: constify to fix build warning
Fix compiler warning:
cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer type
Adding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andre Schwarz <andre.schwarz@matrix-vision.de>
Cc: Murray Jensen <Murray.Jensen@csiro.au>
Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/fpga/ACEX1K.c | 14 | ||||
-rw-r--r-- | drivers/fpga/altera.c | 4 | ||||
-rw-r--r-- | drivers/fpga/cyclon2.c | 12 | ||||
-rw-r--r-- | drivers/fpga/fpga.c | 8 | ||||
-rw-r--r-- | drivers/fpga/spartan2.c | 24 | ||||
-rw-r--r-- | drivers/fpga/spartan3.c | 24 | ||||
-rw-r--r-- | drivers/fpga/virtex2.c | 20 | ||||
-rw-r--r-- | drivers/fpga/xilinx.c | 4 |
8 files changed, 55 insertions, 55 deletions
diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 06b4247..4703fc1 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -48,13 +48,13 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ #endif -static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize ); -static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); -/* static int ACEX1K_ps_info( Altera_desc *desc ); */ +static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize); +static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); +/* static int ACEX1K_ps_info(Altera_desc *desc); */ /* ------------------------------------------------------------------------- */ /* ACEX1K Generic Implementation */ -int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) +int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -74,7 +74,7 @@ int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize) +int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -103,7 +103,7 @@ int ACEX1K_info( Altera_desc *desc ) /* ------------------------------------------------------------------------- */ /* ACEX1K Passive Serial Generic Implementation */ -static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) +static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns; @@ -256,7 +256,7 @@ static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize) +static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 103d81c..f087d01 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -45,7 +45,7 @@ static int altera_validate (Altera_desc * desc, const char *fn); /* ------------------------------------------------------------------------- */ -int altera_load( Altera_desc *desc, void *buf, size_t bsize ) +int altera_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -85,7 +85,7 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize ) return ret_val; } -int altera_dump( Altera_desc *desc, void *buf, size_t bsize ) +int altera_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 567099e..26494a3 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -47,13 +47,13 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ #endif -static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize ); -static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); +static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); +static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); /* static int CYC2_ps_info( Altera_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* CYCLON2 Generic Implementation */ -int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) +int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -83,7 +83,7 @@ int CYC2_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize) +int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -110,7 +110,7 @@ int CYC2_info( Altera_desc *desc ) /* ------------------------------------------------------------------------- */ /* CYCLON2 Passive Serial Generic Implementation */ -static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) +static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; @@ -210,7 +210,7 @@ static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) return ret_val; } -static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize) +static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index a669039..26d2443 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -52,7 +52,7 @@ static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; /* Local static functions */ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum ); -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf, +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf, size_t bsize, char *fn ); static int fpga_dev_info( int devnum ); @@ -94,7 +94,7 @@ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_ge /* fpga_validate * generic parameter checking code */ -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate( int devnum, void *buf, +static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf, size_t bsize, char *fn ) { fpga_desc * desc = fpga_get_desc( devnum ); @@ -212,7 +212,7 @@ int fpga_add( fpga_type devtype, void *desc ) /* * Generic multiplexing code */ -int fpga_load( int devnum, void *buf, size_t bsize ) +int fpga_load(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); @@ -252,7 +252,7 @@ int fpga_load( int devnum, void *buf, size_t bsize ) /* fpga_dump * generic multiplexing code */ -int fpga_dump( int devnum, void *buf, size_t bsize ) +int fpga_dump(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index cd16a9c..4bc7070 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -48,17 +48,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan2_sp_info( Xilinx_desc *desc ); */ +static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan2_sp_info(Xilinx_desc *desc ); */ -static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan2_ss_info( Xilinx_desc *desc ); */ +static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan2_ss_info(Xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -81,7 +81,7 @@ int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -113,7 +113,7 @@ int Spartan2_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; @@ -265,7 +265,7 @@ static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; @@ -313,7 +313,7 @@ static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; @@ -456,7 +456,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 1dd6f26..9207391 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -53,17 +53,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan3_sp_info( Xilinx_desc *desc ); */ +static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan3_sp_info(Xilinx_desc *desc ); */ -static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); -static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); -/* static int Spartan3_ss_info( Xilinx_desc *desc ); */ +static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int Spartan3_ss_info(Xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -86,7 +86,7 @@ int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -118,7 +118,7 @@ int Spartan3_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; @@ -272,7 +272,7 @@ static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; @@ -320,7 +320,7 @@ static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; @@ -475,7 +475,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index d1b4d15..b26d231 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -101,13 +101,13 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize); -static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize); +static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize); -static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize); +static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) +int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -129,7 +129,7 @@ int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int Virtex2_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -170,7 +170,7 @@ int Virtex2_info (Xilinx_desc * desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; @@ -369,7 +369,7 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; @@ -421,13 +421,13 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) +static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 08dfdec..4072cb4 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -48,7 +48,7 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn); /* ------------------------------------------------------------------------- */ -int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) +int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -95,7 +95,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) +int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ |