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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-09-13 16:06:10 (GMT) |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-09-16 16:29:44 (GMT) |
| commit | f6bbec3d5c12457e2ce207f662e65e7da70254ce (patch) | |
| tree | 674e72034147ad69e92804357a1974b9ce3b899b /dts | |
| parent | ef70eb54aab8466b3989e83623b5ca4db78b7b2a (diff) | |
| download | u-boot-fsl-qoriq-f6bbec3d5c12457e2ce207f662e65e7da70254ce.tar.xz | |
ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21
Unfortunately, this SoC needs per-board adjustment between clock
and address/command lines. This flag will be passed to the DRAM
init function and used for compensating the difference of DRAM
timing parameters.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'dts')
0 files changed, 0 insertions, 0 deletions