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authorEvert Pap <evert.pap@sintecs.nl>2016-09-14 11:10:56 (GMT)
committerEvert Pap <evert.pap@sintecs.nl>2016-09-14 11:10:56 (GMT)
commit67e39eed5d590a9d29e2cb747b5eaa79a0f11a69 (patch)
tree40422948d7909f8306f4425adca0d838ba81976b /include/configs/exynos-common.h
parent6d249763300432a786ee03cdbb09dd3b065c5189 (diff)
parentab01ef5fa617444fd95543ee04ea53ccda273269 (diff)
downloadu-boot-fsl-qoriq-67e39eed5d590a9d29e2cb747b5eaa79a0f11a69.tar.xz
Merge branch 'master' into scalys
Diffstat (limited to 'include/configs/exynos-common.h')
-rw-r--r--include/configs/exynos-common.h8
1 files changed, 1 insertions, 7 deletions
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 852829c..38298a2 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -16,7 +16,6 @@
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <linux/sizes.h>
-
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@@ -27,10 +26,10 @@
#define CONFIG_USE_ARCH_MEMSET
/* Keep L2 Cache Disabled */
-#define CONFIG_CMD_CACHE
/* input clock of PLL: 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ 24000000
+#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
@@ -52,16 +51,11 @@
#define CONFIG_EXYNOS_DWMMC
#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
/* PWM */
#define CONFIG_PWM
/* Command definition*/
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_FAT_WRITE
-#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_PART
#define CONFIG_PARTITION_UUIDS