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| author | Tom Rini <trini@ti.com> | 2013-08-20 12:53:52 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-28 15:44:59 (GMT) |
| commit | 078aa4f1310f88aaf9727fc5eb0b493d4fe232a9 (patch) | |
| tree | c53060d9c386bf2faa2e0c651b6d7fe7cf3a9b32 /include/configs | |
| parent | 78c392f143260a5ea2a4cb1051eae13611858036 (diff) | |
| download | u-boot-fsl-qoriq-078aa4f1310f88aaf9727fc5eb0b493d4fe232a9.tar.xz | |
TI:omap5: Clarify comments about SPL and DDR timings in common config
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/omap5_common.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 0345c57..98ba559 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -28,9 +28,12 @@ /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE +/* + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. + */ #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -/* Defines for SDRAM init */ #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS @@ -127,7 +130,13 @@ "fi" -/* Defines for SPL */ +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 + * (dra7xx is larger, but we do not need to be larger at this time). We + * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and + * print some information. + */ #define CONFIG_SPL_TEXT_BASE 0x40300000 #define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT |