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| author | Anthony Felice <tony.felice@timesys.com> | 2014-09-06 17:47:06 (GMT) |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-10-07 11:08:31 (GMT) |
| commit | c19a8bc5711ec63e905ef91f045a1489f0aa3cb0 (patch) | |
| tree | a29aaf854053be0d81157e8ee1dc106cc9956b8d /include/configs | |
| parent | 1454ba8e56d88a8b95ac8050cde2c07c651cd0ae (diff) | |
| download | u-boot-fsl-qoriq-c19a8bc5711ec63e905ef91f045a1489f0aa3cb0.tar.xz | |
vf610twr: Tune DDR initialization settings
Removed settings in unsupported register fields. They didn’t
do anything, and in most cases, were not documented in the
reference manual.
Changed register settings to comply with JEDEC required values.
Changed timing parameters because they included full clock
periods that were doing nothing.
Signed-off-by: Anthony Felice <tony.felice@timesys.com>
[rebased on v2014.10-rc2]
Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'include/configs')
0 files changed, 0 insertions, 0 deletions