diff options
| author | John Rigby <jrigby@freescale.com> | 2008-08-28 19:17:07 (GMT) |
|---|---|---|
| committer | John Rigby <jrigby@freescale.com> | 2008-08-28 19:36:43 (GMT) |
| commit | 8a490422bed685c9491274ec997f62061d88620b (patch) | |
| tree | d5d8b3471cacd352bf419431c619b742f5aa8589 /include/mpc512x.h | |
| parent | 33aa4eac66b71c797bbc13b3afe432a2132947d4 (diff) | |
| download | u-boot-fsl-qoriq-8a490422bed685c9491274ec997f62061d88620b.tar.xz | |
ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon
MPC5121 rev 2 silicon has a new register for controlling how long
CS is asserted after deassertion of ALE in multiplexed mode.
The default is to assert CS together with ALE. The alternative
is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.
The default is wrong for the NOR flash and CPLD on the ADS5121.
This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
it does so conditionally based on silicon rev 2.0 or greater.
Signed-off-by: Martha J Marx <mmarx@silicontkx.com>
Signed-off-by: John Rigby <jrigby@freescale.com>
Diffstat (limited to 'include/mpc512x.h')
| -rw-r--r-- | include/mpc512x.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/mpc512x.h b/include/mpc512x.h index a76b1ca..cb418d1 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -58,6 +58,7 @@ #define CS5_CONFIG 0x00014 #define CS6_CONFIG 0x00018 #define CS7_CONFIG 0x0001C +#define CS_ALE_TIMING_CONFIG 0x00034 #define CS_CTRL 0x00020 #define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ |