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authorAlexey Brodkin <Alexey.Brodkin@synopsys.com>2013-09-25 15:27:48 (GMT)
committerJoe Hershberger <joe.hershberger@ni.com>2013-11-22 22:50:55 (GMT)
commited102be70f762afc39bda165ba57ea84dc9be39e (patch)
tree1056dc7f0270deb8db3283264267a486b768ed0e /include/net.h
parent227ad7b2b6fab024fff6f60613b0e90c9e3a6724 (diff)
downloadu-boot-fsl-qoriq-ed102be70f762afc39bda165ba57ea84dc9be39e.tar.xz
net: designware: Fix alignment of buffer descriptors
It's important that buffer descriptors are aligned in accordance to GMAC data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes) for every bus width type. If buffer descriptor is improperly aligned GMAC discards lower bits of provided address and as a result reads from improper location that doesn't match expected fields. Commit ef76025a99247cdb8f927a2c9f15400678dfb599 "net: Multiple updates/enhancements to designware.c" introduced another structure member "link_printed" right before buffer descriptors while "padding" member was left untouched. This together with alignment of structure itself to 16-byte boundary forces buffer descriptoprs always to be 4-byte aligned that causes driver complete disfunction if GMAC bus width is 64 or 128-bit. Proposed change makes sure all buffer descriptors are 16-byte (128-bit) aligned. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Patch: 277902
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