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| author | Akshay Bhat <akshay.bhat@timesys.com> | 2016-04-12 22:13:58 (GMT) |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-04-19 14:05:13 (GMT) |
| commit | 494d43ec35ff3d27926ed9d668e0df4b7e6ae6d3 (patch) | |
| tree | e1462a832210defa82bfad1e6bfaea86a7c2eb74 /include | |
| parent | de708da0e87f39d99f902a5434702d6ba0f4c5e0 (diff) | |
| download | u-boot-fsl-qoriq-494d43ec35ff3d27926ed9d668e0df4b7e6ae6d3.tar.xz | |
board: ge: bx50v3: Setup LDB_DI_CLK source
To generate accurate pixel clocks required by the displays we need to
set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since
PLL5 is disabled on reset, we need to enable PLL5.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions