powerpc, 5xx: remove support for 5xx

There was for long time no activity in the 5xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 5xx,
so remove it.

Signed-off-by: Heiko Schocher <hs@denx.de>

5 files changed, 1 insertions, 437 deletions

diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index a779713..0c1bdc7 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -41,8 +41,7 @@ typedef struct bd_info {
 	unsigned long	bi_dsp_freq; /* dsp core frequency */
 	unsigned long	bi_ddr_freq; /* ddr frequency */
 #endif
-#if defined(CONFIG_5xx) \
-	|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
 #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
deleted file mode 100644
index 1f26ac4..0000000
--- a/include/configs/PATI.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * (C) Copyright 2003
- * Denis Peter d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * File:		PATI.h
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-
-#define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
-#define CONFIG_PATI		1		/* ...On a PATI board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
-
-/* Serial Console Configuration */
-#define	CONFIG_5xx_CONS_SCI1
-#undef	CONFIG_5xx_CONS_SCI2
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_REGINFO
-
-#define CONFIG_BOOTCOMMAND	""	/* autoboot command			*/
-
-#define CONFIG_BOOTARGS		""		/* */
-
-#define CONFIG_WATCHDOG				/* turn on platform specific watchdog	*/
-
-#define CONFIG_LOADS_ECHO	1		/* Echo on for serial download */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_PREBOOT
-
-#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
-#else
-#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#endif
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16	       /* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00010000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x00A00000	/* 10 MB in SRAM			*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
-
-/***********************************************************************
- * Last Stage Init
- ***********************************************************************/
-#define CONFIG_LAST_STAGE_INIT
-
-/*
- * Low Level Configuration Settings
- */
-
-/*
- * Internal Memory Mapped (This is not the IMMR content)
- */
-#define CONFIG_SYS_IMMR		0x01C00000		/* Physical start adress of internal memory map */
-
-/*
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
-#define	CONFIG_SYS_INIT_RAM_SIZE	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
-#define	CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_IMMR + 0x03fa000)	/* Physical start adress of inital stack */
-/*
- * Start addresses for the final memory configuration
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define	CONFIG_SYS_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
-#define CONFIG_SYS_FLASH_BASE		0xffC00000	/* External flash */
-#define PCI_BASE		0x03000000	/* PCI Base (CS2) */
-#define PCI_CONFIG_BASE		0x04000000	/* PCI & PLD  (CS3) */
-#define PLD_CONFIG_BASE		0x04001000	/* PLD  (CS3) */
-
-#define	CONFIG_SYS_MONITOR_BASE	0xFFF00000
-/* CONFIG_SYS_FLASH_BASE	*/ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file.	*/
-						/* This adress is given to the linker with -Ttext to	*/
-						/* locate the text section at this adress.		*/
-#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 192 kB for Monitor				*/
-#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()				*/
-
-#define CONFIG_SYS_RESET_ADDRESS	(PLD_CONFIG_BASE + 0x10)	 /* Adress which causes reset */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- *-----------------------------------------------------------------------
- *
- */
-
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_FLASH_SHOW_PROGRESS	45
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	128
-
-#define	CONFIG_ENV_IS_IN_EEPROM
-#ifdef	CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_OFFSET		0
-#define CONFIG_ENV_SIZE		2048
-#endif
-
-#undef  CONFIG_ENV_IS_IN_FLASH
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-#define	CONFIG_ENV_SIZE		0x00002000		/* Set whole sector as env		*/
-#define CONFIG_ENV_OFFSET		((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)		/* Environment starts at this adress	*/
-#endif
-
-#define CONFIG_SPI		1
-#define CONFIG_SYS_SPI_CS_USED	0x09 /* CS0 and CS3 are used */
-#define CONFIG_SYS_SPI_CS_BASE	0x08 /* CS3 is active low */
-#define CONFIG_SYS_SPI_CS_ACT	0x00 /* CS3 is active low */
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * SW Watchdog freeze
- */
-#undef CONFIG_WATCHDOG
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-			 SYPCR_SWP)
-#endif	/* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK	SCCR_EBDF00
-#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
-			 SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration
- *-----------------------------------------------------------------------
- * Data show cycle
- */
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle	*/
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register
- *-----------------------------------------------------------------------
- * Set all bits to 40 Mhz
- *
- */
-#define CONFIG_SYS_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
-
-#define CONFIG_SYS_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
-
-/*-----------------------------------------------------------------------
- * UMCR - UIMB Module Configuration Register
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
-
-/*-----------------------------------------------------------------------
- * ICTRL - I-Bus Support Control Register
- */
-#define CONFIG_SYS_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
-
-/*-----------------------------------------------------------------------
- * USIU - Memory Controller Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
-#define CONFIG_SYS_OR0_PRELIM		(0xffc00000) /* SCY is not used if external TA is set */
-/* SDRAM */
-#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
-#define CONFIG_SYS_OR1_PRELIM		(OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
-/* PCI */
-#define CONFIG_SYS_BR2_PRELIM		(PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
-#define CONFIG_SYS_OR2_PRELIM		(OR_ADDR_MK_FF)
-/* config registers: */
-#define CONFIG_SYS_BR3_PRELIM		(PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
-#define CONFIG_SYS_OR3_PRELIM		(0xffff0000)
-
-#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* We don't realign the flash	*/
-
-/*-----------------------------------------------------------------------
- * DER - Timer Decrementer
- *-----------------------------------------------------------------------
- * Initialise to zero
- */
-#define CONFIG_SYS_DER			0x00000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/mpc5xx.h b/include/mpc5xx.h
deleted file mode 100644
index 6c170dc..0000000
--- a/include/mpc5xx.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * File:		mpc5xx.h
- *
- * Discription:		mpc5xx specific definitions
- *
- */
-
-#ifndef __MPC5XX_H__
-#define __MPC5XX_H__
-
-
-/*-----------------------------------------------------------------------
- * Exception offsets (PowerPC standard)
- */
-#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
-#define _START_OFFSET		EXC_OFF_SYS_RESET
-
-/*-----------------------------------------------------------------------
- * ISB bit in IMMR to set internal memory map
- */
-
-#define CONFIG_SYS_ISB			((CONFIG_SYS_IMMR / 0x00400000) << 1)
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control Register
- */
-#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count	*/
-#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing			*/
-#define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
-#define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
-#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
-#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select	*/
-#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale		*/
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration Register
- */
-#define SIUMCR_EARB	0x80000000	/* External Arbitration			*/
-#define SIUMCR_EARP0	0x00000000	/* External Arbi. Request priority 0	*/
-#define SIUMCR_EARP1	0x10000000	/* External Arbi. Request priority 1	*/
-#define SIUMCR_EARP2	0x20000000	/* External Arbi. Request priority 2	*/
-#define SIUMCR_EARP3	0x30000000	/* External Arbi. Request priority 3	*/
-#define SIUMCR_EARP4	0x40000000	/* External Arbi. Request priority 4	*/
-#define SIUMCR_EARP5	0x50000000	/* External Arbi. Request priority 5	*/
-#define SIUMCR_EARP6	0x60000000	/* External Arbi. Request priority 6	*/
-#define SIUMCR_EARP7	0x70000000	/* External Arbi. Request priority 7	*/
-#define SIUMCR_DSHW	0x00800000	/* Data Showcycles			*/
-#define SIUMCR_DBGC00	0x00000000	/* Debug pins configuration		*/
-#define SIUMCR_DBGC01	0x00200000	/* - " -				*/
-#define SIUMCR_DBGC10	0x00400000	/* - " -				*/
-#define SIUMCR_DBGC11	0x00600000	/* - " -				*/
-#define SIUMCR_DBPC00	0x00000000	/* Debug Port pins Config.		*/
-#define SIUMCR_DBPC01	0x00080000	/* - " -				*/
-#define SIUMCR_DBPC10	0x00100000	/* - " -				*/
-#define SIUMCR_DBPC11	0x00180000	/* - " -				*/
-#define SIUMCR_GPC00	0x00000000	/* General Pins Config			*/
-#define SIUMCR_GPC01	0x00020000	/* General Pins Config			*/
-#define SIUMCR_GPC10	0x00040000	/* General Pins Config			*/
-#define SIUMCR_GPC11	0x00060000	/* General Pins Config			*/
-#define SIUMCR_DLK	0x00010000	/* Debug Register Lock			*/
-#define SIUMCR_SC00	0x00000000	/* Multi Chip 32 bit			*/
-#define SIUMCR_SC01	0x00004000	/* Muilt Chip 16 bit			*/
-#define SIUMCR_SC10	0x00004000	/* Single adress show			*/
-#define SIUMCR_SC11	0x00006000	/* Single adress			*/
-#define SIUMCR_RCTX	0x00001000	/* Data Parity pins Config.		*/
-#define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
-#define SIUMCR_MLRC01	0x00000400	/* - " -				*/
-#define SIUMCR_MLRC10	0x00000800	/* - " -				*/
-#define SIUMCR_MLRC11	0x00000c00	/* - " -				*/
-#define SIUMCR_MTSC	0x00000100	/* Memory transfer			*/
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control Register
- */
-#define TBSCR_REFA	((ushort)0x0080)	/* Reference Interrupt Status A	*/
-#define TBSCR_REFB	((ushort)0x0040)	/* Reference Interrupt Status B */
-#define TBSCR_TBF	((ushort)0x0002)	/* Time Base stops while FREEZE */
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control Register
- */
-#define PISCR_PITF	((ushort)0x0002)	/* PIT stops when FREEZE	*/
-#define PISCR_PS	0x0080			/* Periodic Interrupt Status	*/
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register
- */
-#define PLPRCR_MF_MSK	0xfff00000	/* MF mask				*/
-#define PLPRCR_DIVF_MSK	0x0000001f	/* DIVF mask				*/
-#define PLPRCR_CSRC_MSK 0x00000400	/* CSRC mask				*/
-#define PLPRCR_MF_SHIFT 0x00000014	/* Multiplication factor shift value	*/
-#define PLPRCR_DIVF_0   0x00000000	/* Division factor 0			*/
-#define PLPRCR_MF_9     0x00900000	/* Mulitipliaction factor 9		*/
-#define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
-#define PLPRCR_TMIST	0x00001000	/* Timers Interrupt Status		*/
-#define PLPRCR_CSR	0x00000080	/* CheskStop Reset value		*/
-#define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit		*/
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register
- */
-#define SCCR_DFNL_MSK	0x00000070	/* DFNL mask				*/
-#define SCCR_DFNH_MSK	0x00000007	/* DFNH mask				*/
-#define SCCR_DFNL_SHIFT 0x0000004	/* DFNL shift value			*/
-#define SCCR_RTSEL	0x00100000	/* RTC circuit input source select	*/
-#define SCCR_EBDF00	0x00000000	/* Division factor 1. CLKOUT is GCLK2   */
-#define SCCR_EBDF11	0x00060000	/* reserved				*/
-#define SCCR_TBS	0x02000000	/* Time Base Source			*/
-#define SCCR_RTDIV	0x01000000	/* RTC Clock Divide			*/
-#define SCCR_COM00	0x00000000	/* full strength CLKOUT output buffer	*/
-#define SCCR_COM01	0x20000000	/* half strength CLKOUT output buffer	*/
-#define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
-#define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
-
-/*-----------------------------------------------------------------------
- * MC - Memory Controller
- */
-#define BR_V		0x00000001	/* Bank valid				*/
-#define BR_BI		0x00000002	/* Burst inhibit			*/
-#define BR_PS_8		0x00000400	/* 8 bit port size			*/
-#define BR_PS_16	0x00000800	/* 16 bit port size			*/
-#define BR_PS_32	0x00000000	/* 32 bit port size			*/
-#define BR_LBDIR	0x00000008	/* Late burst data in progess		*/
-#define BR_SETA		0x00000004	/* External Data Acknowledge		*/
-#define OR_SCY_3	0x00000030	/* 3 clock cycles wait states		*/
-#define OR_SCY_1	0x00000000	/* 1 clock cycle wait state		*/
-#define OR_SCY_8	0x00000080	/* 8 clock cycles wait states		*/
-#define OR_TRLX		0x00000001	/* Timing relaxed			*/
-#define OR_BSCY		0x00000060	/* Burst beats length in clocks		*/
-#define OR_ACS_10	0x00000600	/* Adress to chip-select setup		*/
-#define OR_CSNT		0x00000800	/* Chip-select negotation time		*/
-#define OR_ETHR		0x00000100	/* Extended hold time on read		*/
-#define OR_ADDR_MK_FF	0xFF000000
-#define OR_ADDR_MK_FFFF	0xFFFF0000
-
-/*-----------------------------------------------------------------------
- * UMCR - UIMB Module Configuration Register
- */
-#define UMCR_FSPEED	0x00000000	/* Full speed. Opposit of UMCR_HSPEED	*/
-#define UMCR_HSPEED	0x10000000	/* Half speed				*/
-
-/*-----------------------------------------------------------------------
- * ICTRL - I-Bus Support Control Register
- */
-#define ICTRL_ISCT_SER_7 0x00000007	/* All indirect change of flow		*/
-
-
-#define NR_IRQS		0		/* Place this later in a separate file */
-
-/*-----------------------------------------------------------------------
- * SCI - Serial communication interface
- */
-
-#define SCI_TDRE	0x0100		/* Transmit data register empty		*/
-#define SCI_TE		0x0008		/* Transmitter enabled			*/
-#define SCI_RE		0x0004		/* Receiver enabled			*/
-#define SCI_RDRF	0x0040		/* Receive data register full		*/
-#define SCI_PE		0x0400		/* Parity enable			*/
-#define SCI_SCXBR_MK	0x1fff		/* Baudrate mask			*/
-#define SCI_SCXDR_MK	0x00ff		/* Data register mask			*/
-#define SCI_M_11	0x0200		/* Frame size is 11 bit			*/
-#define SCI_M_10	0x0000		/* Frame size is 10 bit			*/
-#define SCI_PORT_1	((int)1)	/* Place this later somewhere better	*/
-#define SCI_PORT_2	((int)2)
-
-#endif	/* __MPC5XX_H__ */
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 53141b1..5a0fda2 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -81,18 +81,6 @@
 #define	r30	30
 #define	r31	31
 
-
-#if  defined(CONFIG_5xx)
-/* Some special purpose registers */
-#define DER	149		/* Debug Enable Register		*/
-#define COUNTA	150		/* Breakpoint Counter			*/
-#define COUNTB	151		/* Breakpoint Counter			*/
-#define LCTRL1	156		/* Load/Store Support			*/
-#define LCTRL2	157		/* Load/Store Support			*/
-#define ICTRL	158		/* I-Bus Support Control Register	*/
-#define EID	81
-#endif	/* CONFIG_5xx */
-
 #if defined(CONFIG_MPC5xxx)
 
 #define HID0_ICE_BITPOS	16
diff --git a/include/watchdog.h b/include/watchdog.h
index 0055a83..20ac59a 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -72,11 +72,6 @@ int init_func_watchdog_reset(void);
  * Prototypes from $(CPU)/cpu.c.
  */
 
-/* MPC 5xx */
-#if defined(CONFIG_5xx) && !defined(__ASSEMBLY__)
-	void reset_5xx_watchdog(volatile immap_t *immr);
-#endif
-
 /* MPC 5xxx */
 #if defined(CONFIG_MPC5xxx) && !defined(__ASSEMBLY__)
 	void reset_5xxx_watchdog(void);