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| author | Shaohui Xie <Shaohui.Xie@nxp.com> | 2016-01-28 07:38:15 (GMT) |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-03-21 19:42:10 (GMT) |
| commit | abc7d0f75c078524f713cb2d4b4efe1b1a122c60 (patch) | |
| tree | 93b1b221776309ecda58810f5ba0e2093ecc51f6 /include | |
| parent | 2b690b9837b4bb6d3598e4259581e399d078bff8 (diff) | |
| download | u-boot-fsl-qoriq-abc7d0f75c078524f713cb2d4b4efe1b1a122c60.tar.xz | |
armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/ls2080ardb.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index b2c0181..14635b7 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -355,6 +355,7 @@ unsigned long get_board_sys_clk(void); #define AQ_PHY_ADDR2 0x01 #define AQ_PHY_ADDR3 0x02 #define AQ_PHY_ADDR4 0x03 +#define AQR405_IRQ_MASK 0x36 #define CONFIG_MII #define CONFIG_ETHPRIME "DPNI1" |