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author | Boschung, Rainer <Rainer.Boschung@keymile.com> | 2014-06-03 07:05:13 (GMT) |
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committer | York Sun <yorksun@freescale.com> | 2014-08-01 21:18:07 (GMT) |
commit | 60b295672d61fe79e6af3d9e4f3e8bd23bf3b4ad (patch) | |
tree | 3ec0fd58ef11a66a91fc9006999eab7333150904 /lib/vsprintf.c | |
parent | 3345d18d5baad05807ecac36bc4125dbc74d288f (diff) | |
download | u-boot-fsl-qoriq-60b295672d61fe79e6af3d9e4f3e8bd23bf3b4ad.tar.xz |
powerpc: macros for e500mc timer regs added
For e500mc cores the watchdog timer period has to be set by means of a
6bit value, that defines the bit of the timebase counter used to signal
a watchdog timer exception on its 0 to 1 transition.
The macro used to set the watchdog period TCR_WP, was redefined for e500mc
to support 6 WP setting.
The parameter (x) given to the macro specifies the prescaling factor of
the time base clock (fTB):
watchdog_period = 1/fTB * 2^x
Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'lib/vsprintf.c')
0 files changed, 0 insertions, 0 deletions