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| author | Michal Simek <michal.simek@xilinx.com> | 2017-02-14 16:40:21 (GMT) |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-08-02 07:11:51 (GMT) |
| commit | 0b180d02a30191478ec8088661049e19930253f7 (patch) | |
| tree | f43f64b13e373fef33bf6558be02171fb27c31e8 /test/dm/regmap.c | |
| parent | 6364a5d4bd55beeedc11171419acd0bdff17a599 (diff) | |
| download | u-boot-fsl-qoriq-0b180d02a30191478ec8088661049e19930253f7.tar.xz | |
arm: zynq: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
Diffstat (limited to 'test/dm/regmap.c')
0 files changed, 0 insertions, 0 deletions