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authorPhil Edworthy <PHIL.EDWORTHY@renesas.com>2016-11-29 12:58:33 (GMT)
committerJagan Teki <jagan@amarulasolutions.com>2016-12-15 15:57:27 (GMT)
commit22e63ff3a23d189187d96dbcec50e94233027b3a (patch)
tree9534e2b608fbe4987f92c30ea29ff6e8503e8a69 /tools/ifdtool.h
parent3c5695321929d3c3d1936cb8a7773566af0886b5 (diff)
downloadu-boot-fsl-qoriq-22e63ff3a23d189187d96dbcec50e94233027b3a.tar.xz
spi: cadence_qspi: Fix CS timings
The Cadence QSPI controller has specified overheads for the various CS times that are in addition to those programmed in to the Device Delay register. The overheads are different for the delays. In addition, the existing code does not handle the case when the delay is less than a SCLK period. This change accurately calculates the additional delays in Ref clocks. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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