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-rw-r--r--README6
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/liodn.c4
-rw-r--r--arch/powerpc/cpu/mpc8xxx/fdt.c4
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h1
-rw-r--r--include/fsl_sec.h16
7 files changed, 29 insertions, 6 deletions
diff --git a/README b/README
index 46def00..19abe20 100644
--- a/README
+++ b/README
@@ -544,6 +544,12 @@ The following options need to be configured:
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory.
+ CONFIG_SYS_FSL_SEC_BE
+ Defines the SEC controller register space as Big Endian
+
+ CONFIG_SYS_FSL_SEC_LE
+ Defines the SEC controller register space as Little Endian
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 5bfab70..bf9fbbf 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -803,7 +803,7 @@ int cpu_init_r(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
#define MCFGR_AXIPIPE 0x000000f0
if (IS_SVR_REV(svr, 1, 0))
- clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
+ sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 3222e26..d4c3d9d 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -714,7 +714,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ccsr_sec_t __iomem *sec;
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
- fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms));
+ fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 19e130e..7a2d4be 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -66,12 +66,12 @@ static void setup_sec_liodn_base(void)
return;
/* QILCR[QSLOM] */
- out_be32(&sec->qilcr_ms, 0x3ff<<16);
+ sec_out32(&sec->qilcr_ms, 0x3ff<<16);
base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) |
liodn_bases[FSL_HW_PORTAL_SEC].id[1];
- out_be32(&sec->qilcr_ls, base);
+ sec_out32(&sec->qilcr_ls, base);
}
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 4cec5e1..c6b4d95 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -287,8 +287,8 @@ static u8 caam_get_era(void)
};
ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
- u32 secvid_ms = in_be32(&sec->secvid_ms);
- u32 ccbvid = in_be32(&sec->ccbvid);
+ u32 secvid_ms = sec_in32(&sec->secvid_ms);
+ u32 ccbvid = sec_in32(&sec->ccbvid);
u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
SEC_SECVID_MS_IPID_SHIFT;
u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 712f2ef..4c1774f 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -24,6 +24,7 @@
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_SEC_BE
/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index b31999f..a11f58d 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -11,6 +11,22 @@
#include <common.h>
#include <asm/io.h>
+#ifdef CONFIG_SYS_FSL_SEC_LE
+#define sec_in32(a) in_le32(a)
+#define sec_out32(a, v) out_le32(a, v)
+#define sec_in16(a) in_le16(a)
+#define sec_clrbits32 clrbits_le32
+#define sec_setbits32 setbits_le32
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+#define sec_in32(a) in_be32(a)
+#define sec_out32(a, v) out_be32(a, v)
+#define sec_in16(a) in_be16(a)
+#define sec_clrbits32 clrbits_be32
+#define sec_setbits32 setbits_be32
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+
/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
typedef struct ccsr_sec {