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-rw-r--r--drivers/ddr/altera/sequencer.c8
-rw-r--r--drivers/ddr/altera/sequencer.h45
2 files changed, 4 insertions, 49 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index dd72566..f6414e0 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -966,8 +966,8 @@ static void rw_mgr_mem_initialize(void)
* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
* b = 6A
*/
- rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
- SEQ_TINIT_CNTR2_VAL,
+ rw_mgr_mem_init_load_regs(TINIT_CNTR0_VAL, TINIT_CNTR1_VAL,
+ TINIT_CNTR2_VAL,
rwcfg->init_reset_0_cke_0);
/* Indicate that memory is stable. */
@@ -987,8 +987,8 @@ static void rw_mgr_mem_initialize(void)
* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
* b = FF
*/
- rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
- SEQ_TRESET_CNTR2_VAL,
+ rw_mgr_mem_init_load_regs(TRESET_CNTR0_VAL, TRESET_CNTR1_VAL,
+ TRESET_CNTR2_VAL,
rwcfg->init_reset_1_cke_0);
/* Bring up clock enable. */
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index a80f227..839a374 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -122,51 +122,6 @@
#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
-/* Init and Reset delay constants - Only use if defined by sequencer_defines.h,
- * otherwise, revert to defaults
- * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 =
- * 200.75us @ 266MHz
- */
-#ifdef TINIT_CNTR0_VAL
-#define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
-#else
-#define SEQ_TINIT_CNTR0_VAL 0
-#endif
-
-#ifdef TINIT_CNTR1_VAL
-#define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
-#else
-#define SEQ_TINIT_CNTR1_VAL 202
-#endif
-
-#ifdef TINIT_CNTR2_VAL
-#define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
-#else
-#define SEQ_TINIT_CNTR2_VAL 131
-#endif
-
-
-/* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 =
- * 500.86us @ 266MHz
- */
-#ifdef TRESET_CNTR0_VAL
-#define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
-#else
-#define SEQ_TRESET_CNTR0_VAL 2
-#endif
-
-#ifdef TRESET_CNTR1_VAL
-#define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
-#else
-#define SEQ_TRESET_CNTR1_VAL 252
-#endif
-
-#ifdef TRESET_CNTR2_VAL
-#define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
-#else
-#define SEQ_TRESET_CNTR2_VAL 131
-#endif
-
struct socfpga_sdr_rw_load_manager {
u32 load_cntr0;
u32 load_cntr1;