diff options
92 files changed, 2281 insertions, 1432 deletions
@@ -8,7 +8,7 @@ VERSION = 2014 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else @@ -2756,6 +2756,12 @@ CBFS (Coreboot Filesystem) support Define this option to use the Bank addr/Extended addr support on SPI flashes which has size > 16Mbytes. + CONFIG_SF_DUAL_FLASH Dual flash memories + + Define this option to use dual flash support where two flash + memories can be connected with a given cs line. + currently Xilinx Zynq qspi support these type of connections. + - SystemACE Support: CONFIG_SYSTEMACE diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 329c7a7..cfa4209 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -109,5 +109,5 @@ endif ifdef CONFIG_ARM64 OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn else -OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn +OBJCFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn endif diff --git a/arch/arm/cpu/armv7/exynos/config.mk b/arch/arm/cpu/armv7/exynos/config.mk new file mode 100644 index 0000000..ee0d2da --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/config.mk @@ -0,0 +1,7 @@ +# +# Copyright (C) Albert ARIBAUD <albert.u.boot@aribaud.net> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +SPL_OBJCFLAGS += -j .machine_param diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 69e3053..f1aea05 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -24,7 +24,7 @@ ENTRY(lowlevel_init) #ifdef CONFIG_SPL_BUILD ldr r9, =gdata #else - sub sp, #GD_SIZE + sub sp, sp, #GD_SIZE bic sp, sp, #7 mov r9, sp #endif diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fcc4f35..5617a41 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> @@ -123,7 +124,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) return 0; } - return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> + return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> ANATOP_PFD_FRAC_SHIFT(pfd_num)); } @@ -322,7 +323,7 @@ static u32 get_mmdc_ch0_clk(void) #endif #ifdef CONFIG_FEC_MXC -int enable_fec_anatop_clock(void) +int enable_fec_anatop_clock(enum enet_freq freq) { u32 reg = 0; s32 timeout = 100000; @@ -330,7 +331,13 @@ int enable_fec_anatop_clock(void) struct anatop_regs __iomem *anatop = (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + if (freq < ENET_25MHz || freq > ENET_125MHz) + return -EINVAL; + reg = readl(&anatop->pll_enet); + reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; + reg |= freq; + if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 009a644..0208cba 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -19,8 +19,6 @@ #include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> -#define VDDPU_MASK (0x1f << 9) - enum ldo_reg { LDO_ARM, LDO_SOC, @@ -179,50 +177,11 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } -static void imx_set_vddpu_power_down(void) -{ - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR; - - u32 reg; - - /* - * Disable the brown out detection since we are going to be - * disabling the LDO. - */ - reg = readl(&anatop->ana_misc2); - reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN; - writel(reg, &anatop->ana_misc2); - - /* need to power down xPU in GPC before turning off PU LDO */ - reg = readl(&gpc->gpu_ctrl); - writel(reg | 0x1, &gpc->gpu_ctrl); - - reg = readl(&gpc->ctrl); - writel(reg | 0x1, &gpc->ctrl); - while (readl(&gpc->ctrl) & 0x1) - ; - - /* Mask the ANATOP brown out interrupt in the GPC. */ - reg = readl(&gpc->imr4); - reg |= 0x80000000; - writel(reg, &gpc->imr4); - - /* disable VDDPU */ - writel(VDDPU_MASK, &anatop->reg_core_clr); - - /* Clear the BO interrupt in the ANATOP. */ - reg = readl(&anatop->ana_misc1); - reg |= 0x80000000; - writel(reg, &anatop->ana_misc1); -} - int arch_cpu_init(void) { init_aips(); imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ - imx_set_vddpu_power_down(); #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk index d8d263d..f2befbe 100644 --- a/arch/arm/cpu/pxa/config.mk +++ b/arch/arm/cpu/pxa/config.mk @@ -14,3 +14,16 @@ PLATFORM_CPPFLAGS += -mcpu=xscale # ======================================================================== PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) + +# +# !WARNING! +# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from +# really small OneNAND memories where the mmap'd window is only 1KiB big. The +# .text.0 contains only the bare minimum needed to load the real SPL into SRAM. +# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd, +# they are not discarded. +# + +#ifdef CONFIG_SPL_BUILD +OBJCFLAGS += -j .text.0 -j .text.1 +#endif diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 9463a33..4da5d24 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -92,8 +92,6 @@ SECTIONS } .dynsym _end : { *(.dynsym) } - .hash : { *(.hash) } - .got.plt : { *(.got.plt) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } .dynamic : { *(.dynamic*) } @@ -101,4 +99,5 @@ SECTIONS .interp : { *(.interp*) } .gnu : { *(.gnu*) } .ARM.exidx : { *(.ARM.exidx*) } + .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) } } diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h index d79f25c..d2d70bd 100644 --- a/arch/arm/include/asm/arch-exynos/ehci.h +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -29,6 +29,20 @@ #define EHCICTRL_ENAINCR8 (1 << 27) #define EHCICTRL_ENAINCR16 (1 << 26) +#define HSIC_CTRL_REFCLKSEL (0x2) +#define HSIC_CTRL_REFCLKSEL_MASK (0x3) +#define HSIC_CTRL_REFCLKSEL_SHIFT (23) + +#define HSIC_CTRL_REFCLKDIV_12 (0x24) +#define HSIC_CTRL_REFCLKDIV_MASK (0x7f) +#define HSIC_CTRL_REFCLKDIV_SHIFT (16) + +#define HSIC_CTRL_SIDDQ (0x1 << 6) +#define HSIC_CTRL_FORCESLEEP (0x1 << 5) +#define HSIC_CTRL_FORCESUSPEND (0x1 << 4) +#define HSIC_CTRL_UTMISWRST (0x1 << 2) +#define HSIC_CTRL_PHYSWRST (0x1 << 0) + /* Register map for PHY control */ struct exynos_usb_phy { unsigned int usbphyctrl0; diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 93f29a7..e31ba0a 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -42,6 +42,13 @@ enum mxc_clock { MXC_I2C_CLK, }; +enum enet_freq { + ENET_25MHz, + ENET_50MHz, + ENET_100MHz, + ENET_125MHz, +}; + u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); @@ -50,5 +57,5 @@ void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_ipu_clock(void); -int enable_fec_anatop_clock(void); +int enable_fec_anatop_clock(enum enet_freq freq); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index aede126..7202073 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -890,5 +890,4 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) -#define ANADIG_ANA_MISC2_REG1_BO_EN (1 << 13) #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index fb0c4c7..f2ad6e9 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -245,6 +245,10 @@ struct src { u32 gpr10; }; +/* GPR1 bitfields */ +#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 +#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) + /* GPR3 bitfields */ #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET) @@ -659,28 +663,5 @@ struct wdog_regs { u16 wmcr; /* Miscellaneous Control */ }; -struct gpc_regs { - u32 ctrl; /* 0x000 */ - u32 pgr; /* 0x004 */ - u32 imr1; /* 0x008 */ - u32 imr2; /* 0x00c */ - u32 imr3; /* 0x010 */ - u32 imr4; /* 0x014 */ - u32 isr1; /* 0x018 */ - u32 isr2; /* 0x01c */ - u32 isr3; /* 0x020 */ - u32 isr4; /* 0x024 */ - u32 reserved1[0x86]; - u32 gpu_ctrl; /* 0x260 */ - u32 gpu_pupscr; /* 0x264 */ - u32 gpu_pdnscr; /* 0x268 */ - u32 gpu_sr; /* 0x26c */ - u32 reserved2[0xc]; - u32 cpu_ctrl; /* 0x2a0 */ - u32 cpu_pupscr; /* 0x2a4 */ - u32 cpu_pdnscr; /* 0x2a8 */ - u32 cpu_sr; /* 0x2ac */ -}; - #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h index 42d65d3..d9ea71f 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7790.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h @@ -19,6 +19,7 @@ #define DBSC3_1_BASE 0xE67A0000 #define TMU_BASE 0xE61E0000 #define GPIO5_BASE 0xE6055000 +#define SH_QSPI_BASE 0xE6B10000 #define S3C_BASE 0xE6784000 #define S3C_INT_BASE 0xE6784A00 diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h index 2afda0a..ff30180 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7791.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h @@ -19,6 +19,7 @@ #define DBSC3_1_BASE 0xE67A0000 #define TMU_BASE 0xE61E0000 #define GPIO5_BASE 0xE6055000 +#define SH_QSPI_BASE 0xE6B10000 #define S3C_BASE 0xE6784000 #define S3C_INT_BASE 0xE6784A00 diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index ac54b93..dfc2de9 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -67,7 +67,7 @@ ENTRY(_main) ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - sub sp, #GD_SIZE /* allocate one GD above SP */ + sub sp, sp, #GD_SIZE /* allocate one GD above SP */ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ mov r9, sp /* GD is above SP */ mov r0, #0 diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c index 5c5b1b9..aa126d7 100644 --- a/board/altera/nios2-generic/nios2-generic.c +++ b/board/altera/nios2-generic/nios2-generic.c @@ -8,7 +8,9 @@ #include <common.h> #include <netdev.h> +#if defined(CONFIG_CFI_FLASH_MTD) #include <mtd/cfi_flash.h> +#endif #include <asm/io.h> #include <asm/gpio.h> diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c index 6db4488..84a7b84 100644 --- a/board/barco/titanium/titanium.c +++ b/board/barco/titanium/titanium.c @@ -264,15 +264,9 @@ int board_phy_config(struct phy_device *phydev) int board_eth_init(bd_t *bis) { - int ret; - setup_iomux_enet(); - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); - - return ret; + return cpu_eth_init(bis); } int board_early_init_f(void) diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index e063407..6c51f3a 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -186,13 +186,10 @@ int fecmxc_mii_postcall(int phy) int board_eth_init(bd_t *bis) { struct eth_device *dev; - int ret; + int ret = cpu_eth_init(bis); - ret = cpu_eth_init(bis); - if (ret) { - printf("FEC MXC: %s:failed\n", __func__); + if (ret) return ret; - } dev = eth_get_dev_by_name("FEC"); if (!dev) { diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index fc75eae..928dadf 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -192,15 +192,9 @@ int board_phy_config(struct phy_device *phydev) int board_eth_init(bd_t *bis) { - int ret; - setup_iomux_enet(); - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); - - return ret; + return cpu_eth_init(bis); } #define BOARD_REV_B 0x200 diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 2ffc3b8..12d8c56 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -453,15 +453,9 @@ int overwrite_console(void) int board_eth_init(bd_t *bis) { - int ret; - setup_iomux_enet(); - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); - - return ret; + return cpu_eth_init(bis); } int board_early_init_f(void) diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 643fdac..c496254 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -106,17 +106,9 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_FEC_MXC int board_eth_init(bd_t *bis) { - int ret; - setup_iomux_fec(); - ret = cpu_eth_init(bis); - if (ret) { - printf("FEC MXC: %s:failed\n", __func__); - return ret; - } - - return 0; + return cpu_eth_init(bis); } static int setup_fec(void) @@ -128,7 +120,7 @@ static int setup_fec(void) /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - ret = enable_fec_anatop_clock(); + ret = enable_fec_anatop_clock(ENET_50MHz); if (ret) return ret; diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile deleted file mode 100644 index f367107..0000000 --- a/board/friendlyarm/mini2440/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2012 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mini2440.o diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c deleted file mode 100644 index 59ed054..0000000 --- a/board/friendlyarm/mini2440/mini2440.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2009 - * Michel Pollet <buserror@gmail.com> - * - * (C) Copyright 2012 - * Gabriel Huau <contact@huau-gabriel.fr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/s3c2440.h> -#include <asm/arch/iomux.h> -#include <asm/arch/gpio.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <netdev.h> -#include "mini2440.h" - -DECLARE_GLOBAL_DATA_PTR; - -static inline void pll_delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b" : "=r" (loops) : "0" (loops)); -} - -int board_early_init_f(void) -{ - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); - - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */ - clk_power->clkdivn = CLKDIVN_VAL; - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - /* some delay between MPLL and UPLL */ - pll_delay(100); - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - pll_delay(10000); - - return 0; -} - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* IOMUX Port H : UART Configuration */ - gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 | - IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2; - - gpio_direction_output(GPH8, 0); - gpio_direction_output(GPH9, 0); - gpio_direction_output(GPH10, 0); - - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; - - return 0; -} - -int dram_init(void) -{ - struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl(); - - /* - * Configuring bus width and timing - * Initialize clocks for each bank 0..5 - * Bank 3 and 4 are used for DM9000 - */ - writel(BANK_CONF, &memctl->bwscon); - writel(B0_CONF, &memctl->bankcon[0]); - writel(B1_CONF, &memctl->bankcon[1]); - writel(B2_CONF, &memctl->bankcon[2]); - writel(B3_CONF, &memctl->bankcon[3]); - writel(B4_CONF, &memctl->bankcon[4]); - writel(B5_CONF, &memctl->bankcon[5]); - - /* Bank 6 and 7 are used for DRAM */ - writel(SDRAM_64MB, &memctl->bankcon[6]); - writel(SDRAM_64MB, &memctl->bankcon[7]); - - writel(MEM_TIMING, &memctl->refresh); - writel(BANKSIZE_CONF, &memctl->banksize); - writel(B6_MRSR, &memctl->mrsrb6); - writel(B7_MRSR, &memctl->mrsrb7); - - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_SIZE); - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_DRIVER_DM9000 - return dm9000_initialize(bis); -#else - return 0; -#endif -} diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h deleted file mode 100644 index db386ea..0000000 --- a/board/friendlyarm/mini2440/mini2440.h +++ /dev/null @@ -1,144 +0,0 @@ -#ifndef __MINI2440_BOARD_CONF_H__ -#define __MINI2440_BOARD_CONF_H__ - -/* PLL Parameters */ -#define CLKDIVN_VAL 7 -#define M_MDIV 0x7f -#define M_PDIV 0x2 -#define M_SDIV 0x1 - -#define U_M_MDIV 0x38 -#define U_M_PDIV 0x2 -#define U_M_SDIV 0x2 - -/* BWSCON */ -#define DW8 0x0 -#define DW16 0x1 -#define DW32 0x2 -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -#define B1_BWSCON (DW32) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* - * Bank Configuration - */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x0 /* 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* 0clk */ -#define B0_PMC 0x0 /* normal */ - -#define B1_Tacs 0x0 -#define B1_Tcos 0x0 -#define B1_Tacc 0x7 -#define B1_Tcoh 0x0 -#define B1_Tah 0x0 -#define B1_Tacp 0x0 -#define B1_PMC 0x0 - -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 - -#define B3_Tacs 0x0 -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 -#define B3_Tcoh 0x1 /* 1clk */ -#define B3_Tah 0x3 /* 4clk */ -#define B3_Tacp 0x0 -#define B3_PMC 0x0 - -#define B4_Tacs 0x0 -#define B4_Tcos 0x3 -#define B4_Tacc 0x7 -#define B4_Tcoh 0x1 -#define B4_Tah 0x3 -#define B4_Tacp 0x0 -#define B4_PMC 0x0 - -#define B5_Tacs 0x0 -#define B5_Tcos 0x0 -#define B5_Tacc 0x7 -#define B5_Tcoh 0x0 -#define B5_Tah 0x0 -#define B5_Tacp 0x0 -#define B5_PMC 0x0 - -/* - * SDRAM Configuration - */ -#define SDRAM_MT 0x3 /* SDRAM */ -#define SDRAM_Trcd 0x0 /* 2clk */ -#define SDRAM_SCAN_9 0x1 /* 9bit */ -#define SDRAM_SCAN_10 0x2 /* 10bit */ - -#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9)) - -/* - * Refresh Parameter - */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x1 /* 3clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x0 /* unused */ -#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */ - -/* - * MRSR Parameter - */ -#define BL 0x0 -#define BT 0x0 -#define CL 0x3 /* 3 clocks */ -#define TM 0x0 -#define WBL 0x0 - -/* - * BankSize Parameter - */ -#define BK76MAP 0x2 /* 128MB/128MB */ -#define SCLK_EN 0x1 /* SCLK active */ -#define SCKE_EN 0x1 /* SDRAM power down mode enable */ -#define BURST_EN 0x1 /* Burst enable */ - -/* - * Register values - */ -#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \ - (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \ - (B7_BWSCON<<28))) - -#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \ - (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC)) -#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \ - (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC)) -#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \ - (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC)) -#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \ - (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC)) -#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \ - (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC)) -#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \ - (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC)) - -#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \ - (Trc<<18) + (Tchr<<16) + REFCNT - -#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7) -#define B6_MRSR (CL<<4) -#define B7_MRSR (CL<<4) - -#endif diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile deleted file mode 100644 index 6dfd18e..0000000 --- a/board/mx1ads/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# board/mx1ads/Makefile -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (c) Copyright 2004 -# Techware Information Technology, Inc. -# http://www.techware.com.tw/ -# -# Ming-Len Wu <minglen_wu@techware.com.tw> -# -# SPDX-License-Identifier: GPL-2.0+ - -obj-y := mx1ads.o syncflash.o -obj-y += lowlevel_init.o diff --git a/board/mx1ads/lowlevel_init.S b/board/mx1ads/lowlevel_init.S deleted file mode 100644 index d1e472a..0000000 --- a/board/mx1ads/lowlevel_init.S +++ /dev/null @@ -1,68 +0,0 @@ -/* - * board/mx1ads/lowlevel_init.S - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu <minglen_wu@techware.com.tw> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> - -#define SDCTL0 0x221000 -#define SDCTL1 0x221004 - - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -.globl lowlevel_init -lowlevel_init: -/* memory controller init */ - - ldr r1, =SDCTL0 - -/* Set Precharge Command */ - - ldr r3, =0x92120200 -/* ldr r3, =0x92120251 -*/ - str r3, [r1] - -/* Issue Precharge All Commad */ - ldr r3, =0x8200000 - ldr r2, [r3] - -/* Set AutoRefresh Command */ - ldr r3, =0xA2120200 - str r3, [r1] - -/* Issue AutoRefresh Command */ - ldr r3, =0x8000000 - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - ldr r2, [r3] - -/* Set Mode Register */ - ldr r3, =0xB2120200 - str r3, [r1] - -/* Issue Mode Register Command */ - ldr r3, =0x08111800 /* Mode Register Value */ - ldr r2, [r3] - -/* Set Normal Mode */ - ldr r3, =0x82124200 - str r3, [r1] - -/* everything is fine now */ - mov pc, lr diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c deleted file mode 100644 index 4266048..0000000 --- a/board/mx1ads/mx1ads.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * board/mx1ads/mx1ads.c - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu <minglen_wu@techware.com.tw> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -/*#include <mc9328.h>*/ -#include <asm/arch/imx-regs.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -#if 0 - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -#endif - -/* - * Miscellaneous platform dependent initialisations - */ - -void SetAsynchMode (void) -{ - __asm__ ("mrc p15,0,r0,c1,c0,0 \n" - "mov r2, #0xC0000000 \n" - "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n"); -} - -static u32 mc9328sid; - -int board_early_init_f(void) -{ - mc9328sid = SIDR; - - GPCR = 0x000003AB; /* I/O pad driving strength */ - - /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ -/* MX1_CS1L = 0x11110601; */ - - MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ - -/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and - * BCLK divider to 2 (i.e. BCLK to 48 MHz) - */ - CSCR = 0xAF000403; - - CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ - CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ - -/* setup cs4 for cs8900 ethernet */ - - CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ - CS4L = 0x00001501; - - GIUS (0) &= 0xFF3FFFFF; - GPR (0) &= 0xFF3FFFFF; - - readl(0x1500000C); - readl(0x1500000C); - - SetAsynchMode (); - - icache_enable (); - dcache_enable (); - -/* set PERCLKs */ - PCDR = 0x00000055; /* set PERCLKS */ - -/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes - * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place - * all sources selected as normal interrupt - */ - -/* MX1_INTTYPEH = 0; - MX1_INTTYPEL = 0; -*/ - return 0; -} - -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; - - gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ - - return 0; -} - -int board_late_init (void) -{ - - setenv ("stdout", "serial"); - setenv ("stderr", "serial"); - - switch (mc9328sid) { - case 0x0005901d: - printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n", - mc9328sid); - break; - case 0x04d4c01d: - printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n", - mc9328sid); - break; - case 0x00d4c01d: - printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n", - mc9328sid); - break; - - default: - printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n", - mc9328sid); - break; - } - return 0; -} - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c deleted file mode 100644 index 5d68533..0000000 --- a/board/mx1ads/syncflash.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * board/mx1ads/syncflash.c - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu <minglen_wu@techware.com.tw> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -/*#include <mc9328.h>*/ -#include <asm/arch/imx-regs.h> - -typedef unsigned long * p_u32; - -/* 4Mx16x2 IAM=0 CSD1 */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Following Setting is for CSD1 */ -#define SFCTL 0x00221004 -#define reg_SFCTL __REG(SFCTL) - -#define SYNCFLASH_A10 (0x00100000) - -#define CMD_NORMAL (0x81020300) /* Normal Mode */ -#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ -#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ -#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ -#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ -#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) - -#define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ - -/* LCR Command */ -#define LCR_READSTATUS (0x0001C000) /* 0x70 */ -#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ -#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ -#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ -#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ - -/* Get Status register */ -u32 SF_SR(void) { - u32 tmp; - - reg_SFCTL = CMD_PROGRAM; - tmp = __REG(CONFIG_SYS_FLASH_BASE); - - reg_SFCTL = CMD_NORMAL; - - reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ - __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR); - - return tmp; -} - -/* check if SyncFlash is ready */ -u8 SF_Ready(void) { - u32 tmp; - - tmp = SF_SR(); - - if ((tmp & 0x00800000) && (tmp & 0x001C0000)) { - printf ("SyncFlash Error code %08x\n",tmp); - }; - - if ((tmp & 0x00000080) && (tmp & 0x0000001C)) { - printf ("SyncFlash Error code %08x\n",tmp); - }; - - if (tmp == 0x00800080) /* Test Bit 7 of SR */ - return 1; - else - return 0; -} - -/* Issue the precharge all command */ -void SF_PrechargeAll(void) { - - /* Set Precharge Command */ - reg_SFCTL = CMD_PREC; - /* Issue Precharge All Command */ - __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); -} - -/* set SyncFlash to normal mode */ -void SF_Normal(void) { - - SF_PrechargeAll(); - - reg_SFCTL = CMD_NORMAL; -} - -/* Erase SyncFlash */ -void SF_Erase(u32 RowAddress) { - - reg_SFCTL = CMD_NORMAL; - __REG(RowAddress); - - reg_SFCTL = CMD_PREC; - __REG(RowAddress); - - reg_SFCTL = CMD_LCR; /* Set LCR mode */ - __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ - - reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ - __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ - - while(!SF_Ready()); -} - -void SF_NvmodeErase(void) { - SF_PrechargeAll(); - - reg_SFCTL = CMD_LCR; /* Set to LCR mode */ - __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ - - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ - - while(!SF_Ready()); -} - -void SF_NvmodeWrite(void) { - SF_PrechargeAll(); - - reg_SFCTL = CMD_LCR; /* Set to LCR mode */ - __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ - - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ -} - -/****************************************************************************************/ - -ulong flash_init(void) { - int i, j; - -/* Turn on CSD1 for negating RESETSF of SyncFLash */ - - reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ - udelay(200); - - reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ - __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ - - SF_Normal(); - - i = 0; - - flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; - - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000; - } - - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); - - return FLASH_BANK_SIZE; -} - -void flash_print_info (flash_info_t *info) { - - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (FLASH_MAN_MT & FLASH_VENDMASK): - printf("Micron: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (FLASH_MT28S4M16LC & FLASH_TYPEMASK): - printf("2x FLASH_MT28S4M16LC (16MB Total)\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - break; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses: "); - - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) - printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*-----------------------------------------------------------------------*/ - -int flash_erase (flash_info_t *info, int s_first, int s_last) { - int iflag, cflag, prot, sect; - int rc = ERR_OK; - -/* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) - return ERR_INVAL; - - if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf("protected!\n"); - return ERR_PROTECTED; - } -/* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status(); - icache_disable(); - iflag = disable_interrupts(); - -/* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc(); sect++) { - - printf("Erasing sector %2d ... ", sect); - -/* arm simple, non interrupt dependent timer */ - - get_timer(0); - - SF_NvmodeErase(); - SF_NvmodeWrite(); - - SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect)); - SF_Normal(); - - printf("ok.\n"); - } - - if (ctrlc()) - printf("User Interrupt!\n"); - - if (iflag) - enable_interrupts(); - - if (cflag) - icache_enable(); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { - int i; - - for(i = 0; i < cnt; i += 4) { - - SF_PrechargeAll(); - - reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */ - __REG(addr + i) = __REG((u32)src + i); - - while(!SF_Ready()); - } - - SF_Normal(); - - return ERR_OK; -} diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 89f5c91..32d3b58 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -253,6 +253,12 @@ int board_early_init_f(void) return 0; } +void arch_preboot_os(void) +{ + /* Disable TMU0 */ + mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); +} + /* LSI pin pull-up control */ #define PUPR5 0xe6060114 #define PUPR5_ETH 0x3FFC0000 diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index cdd5b32..ad5289a 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -254,6 +254,12 @@ int board_early_init_f(void) return 0; } +void arch_preboot_os(void) +{ + /* Disable TMU0 */ + mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); +} + DECLARE_GLOBAL_DATA_PTR; int board_init(void) { diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index 052fecd..9efc355 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -5,12 +5,33 @@ */ #include <common.h> +#include <usb.h> #include <asm/arch/pinmux.h> #include <asm/arch/dwmmc.h> +#include <asm/arch/gpio.h> #include <asm/arch/power.h> DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_USB_EHCI_EXYNOS +int board_usb_init(int index, enum usb_init_type init) +{ + struct exynos5_gpio_part1 *gpio = (struct exynos5_gpio_part1 *) + samsung_get_base_gpio_part1(); + + /* Configure gpios for usb 3503 hub: + * disconnect, toggle reset and connect + */ + s5p_gpio_direction_output(&gpio->d1, 7, 0); + s5p_gpio_direction_output(&gpio->x3, 5, 0); + + s5p_gpio_direction_output(&gpio->x3, 5, 1); + s5p_gpio_direction_output(&gpio->d1, 7, 1); + + return 0; +} +#endif + int board_init(void) { gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); diff --git a/board/solidrun/hummingboard/Makefile b/board/solidrun/hummingboard/Makefile new file mode 100644 index 0000000..042a2f0 --- /dev/null +++ b/board/solidrun/hummingboard/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2013 Freescale Semiconductor, Inc. +# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com> +# Copyright (C) 2013, Jon Nettleton <jon.nettleton@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := hummingboard.o diff --git a/board/solidrun/hummingboard/README b/board/solidrun/hummingboard/README new file mode 100644 index 0000000..cfd62d4 --- /dev/null +++ b/board/solidrun/hummingboard/README @@ -0,0 +1,40 @@ +U-Boot for SolidRun Hummingboard +-------------------------------- + +This file contains information for the port of U-Boot to the Hummingboard. + +For more details about Hummingboard, please refer to: +http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware + +(Carrier-One was the previous name of Hummingboard). + +Building U-boot for Hummingboard +-------------------------------- + +To build U-Boot for the Hummingboard Solo version: + +$ make hummingboard_solo_config +$ make + +Flashing U-boot into the SD card +-------------------------------- + +- After the 'make' command completes, the generated 'u-boot.imx' binary must be +flashed into the SD card: + +$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=1k seek=1; sync + +(Note - the SD card node may vary, so adjust this as needed). + +Also, a more detailed explanation on how to format the SD card is available +at doc/README.imximage. + +- Insert the micro SD card into the slot located in the bottom of the board + +- Connect a 3.3V USB to serial converter cable to the host PC. The MX6 UART +signals are available in the 26 pin connector as shown at: +http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware +(Check for "26 pin header layout"). + +- Power up the board via USB cable (CON201) and U-boot messages will appear in +the serial console. diff --git a/board/solidrun/hummingboard/hummingboard.c b/board/solidrun/hummingboard/hummingboard.c new file mode 100644 index 0000000..8b309b4 --- /dev/null +++ b/board/solidrun/hummingboard/hummingboard.c @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>. + * + * Authors: Fabio Estevam <fabio.estevam@freescale.com> + Jon Nettleton <jon.nettleton@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/io.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define USDHC_PAD_GPIO_CTRL (PAD_CTL_PUS_22K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ETH_PHY_RESET IMX_GPIO_NR(4, 15) + +int dram_init(void) +{ + gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(USDHC_PAD_GPIO_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + { USDHC2_BASE_ADDR }, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* SD card is the boot medium, so always present */ +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8035 reset */ + MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + /* AR8035 interrupt */ + MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* GPIO16 -> AR8035 25MHz */ + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + gpio_direction_output(ETH_PHY_RESET, 0); + mdelay(2); + gpio_set_value(ETH_PHY_RESET, 1); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct iomuxc_base_regs *const iomuxc_regs = + (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + + int ret = enable_fec_anatop_clock(ENET_25MHz); + if (ret) + return ret; + + /* set gpr1[ENET_CLK_SEL] */ + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + setup_iomux_enet(); + + ret = cpu_eth_init(bis); + if (ret) + printf("FEC MXC: %s:failed\n", __func__); + + return ret; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Hummingboard\n"); + + return 0; +} diff --git a/board/solidrun/hummingboard/solo.cfg b/board/solidrun/hummingboard/solo.cfg new file mode 100644 index 0000000..28dd750 --- /dev/null +++ b/board/solidrun/hummingboard/solo.cfg @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch/mx6-ddr.h" +#include "asm/arch/iomux.h" +#include "asm/arch/crm_regs.h" + +#include "../mx6-microsom/ddr-800mhz-32bit-setup.cfg" +#include "../mx6-microsom/800mhz_2x128mx16.cfg" +#include "../mx6-microsom/clocks.cfg" diff --git a/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg b/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg new file mode 100644 index 0000000..40747ab --- /dev/null +++ b/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* ZQ Calibrations */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 +DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003 +/* write leveling */ +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057 +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052 +/* + * DQS gating, read delay, write delay calibration values + * based on calibration compare of 0x00ffff00 + */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230 +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440 +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034 +/* read data bit delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +/* Complete calibration by forced measurement */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 + +/* + * MMDC init: + * in DDR3, 32-bit mode, only MMDC0 is initiated: + */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d +DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040 + +DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63 + +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db +DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 +/* CS0_END - 0x2fffffff, 512M */ +DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 + +/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */ +DATA 4, 0x021b0400, 0x11420000 + +/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */ +DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 + +/* + * Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C + * MR2 + */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032 +/* MR3 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +/* MR1 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 +/* MR0 */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 +/* ZQ calibration */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +/* final DDR setup */ +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/board/solidrun/mx6-microsom/clocks.cfg b/board/solidrun/mx6-microsom/clocks.cfg new file mode 100644 index 0000000..1288811 --- /dev/null +++ b/board/solidrun/mx6-microsom/clocks.cfg @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x007F007F +DATA 4, MX6_IOMUXC_GPR7, 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4, CCM_CCOSR, 0x000000fb diff --git a/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg new file mode 100644 index 0000000..f92fc19 --- /dev/null +++ b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits x16/x32 + */ +/* DDR IO TYPE */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* Clock */ +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028 +/* Address */ +DATA 4, MX6_IOM_DRAM_CAS, 0x00000010 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000010 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010 +/* Control */ +DATA 4, MX6_IOM_DRAM_RESET, 0x00000010 +DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010 + +/* + * Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS, + * CMOS mode saves power, but have less timing margin in case of DDR + * timing issue on your board you can try DDR_MODE: [= 0x00020000] + */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 + +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000 + +/* + * DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS, + * CMOS mode saves power, but have less timing margin in case of DDR + * timing issue on your board you can try DDR_MODE: [= 0x00020000] + */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 + +DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 +DATA 4, MX6_IOM_GRP_B4DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B5DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B6DS, 0x00000000 +DATA 4, MX6_IOM_GRP_B7DS, 0x00000000 + +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 +DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000 +DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000 diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 02d107c..b6fdde4 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -20,6 +20,7 @@ SECTIONS .text.0 : { arch/arm/cpu/pxa/start.o (.text*) + arch/arm/lib/built-in.o (.text*) board/vpac270/built-in.o (.text*) drivers/mtd/onenand/built-in.o (.text*) } diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 0043bc6..72e9bb2 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -257,15 +257,9 @@ static void setup_display(void) int board_eth_init(bd_t *bis) { - int ret; - setup_iomux_enet(); - ret = cpu_eth_init(bis); - if (ret) - printf("FEC MXC: %s:failed\n", __func__); - - return ret; + return cpu_eth_init(bis); } int board_early_init_f(void) @@ -65,11 +65,9 @@ Active arm arm920t at91 BuS eb_cpux9k2 Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de> Active arm arm920t at91 eukrea cpuat91 cpuat91 cpuat91 Eric Benard <eric@eukrea.com> Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com> -Active arm arm920t imx - - mx1ads - - Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de> Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com> Active arm arm920t ks8695 - - cm41xx - - -Active arm arm920t s3c24x0 friendlyarm mini2440 mini2440 - Gabriel Huau <contact@huau-gabriel.fr> Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller@elsoft.ch> Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller@elsoft.ch> Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org> @@ -311,6 +309,7 @@ Active arm armv7 mx6 freescale mx6sabresd Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr@denx.de> +Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com> Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com> Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com> Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com> diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 3f57659..a59ee95 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -82,6 +82,9 @@ static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); static void fixup_silent_linux(void); #endif +static int do_bootm_standalone(int flag, int argc, char * const argv[], + bootm_headers_t *images); + static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[], bootm_headers_t *images, ulong *os_data, ulong *os_len); @@ -139,6 +142,7 @@ static boot_os_fn do_bootm_integrity; #endif static boot_os_fn *boot_os[] = { + [IH_OS_U_BOOT] = do_bootm_standalone, #ifdef CONFIG_BOOTM_LINUX [IH_OS_LINUX] = do_bootm_linux, #endif @@ -499,17 +503,18 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, return 0; } -static int bootm_start_standalone(int argc, char * const argv[]) +static int do_bootm_standalone(int flag, int argc, char * const argv[], + bootm_headers_t *images) { char *s; int (*appl)(int, char * const []); /* Don't start if "autostart" is set to "no" */ if (((s = getenv("autostart")) != NULL) && (strcmp(s, "no") == 0)) { - setenv_hex("filesize", images.os.image_len); + setenv_hex("filesize", images->os.image_len); return 0; } - appl = (int (*)(int, char * const []))(ulong)ntohl(images.ep); + appl = (int (*)(int, char * const []))(ulong)ntohl(images->ep); (*appl)(argc, argv); return 0; } @@ -535,14 +540,12 @@ static cmd_tbl_t cmd_bootm_sub[] = { static int boot_selected_os(int argc, char * const argv[], int state, bootm_headers_t *images, boot_os_fn *boot_fn) { - if (images->os.type == IH_TYPE_STANDALONE) { - /* This may return when 'autostart' is 'no' */ - bootm_start_standalone(argc, argv); - return 0; - } arch_preboot_os(); boot_fn(state, argc, argv, images); - if (state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */ + + /* Stand-alone may return when 'autostart' is 'no' */ + if (images->os.type == IH_TYPE_STANDALONE || + state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */ return 0; bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED); #ifdef DEBUG diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 3994b06..b4ceb71 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -358,7 +358,8 @@ static void show_time(struct test_info *test, int stage) int bps; /* Bits per second */ speed = (long long)test->bytes * 1000; - do_div(speed, test->time_ms[stage] * 1024); + if (test->time_ms[stage]) + do_div(speed, test->time_ms[stage] * 1024); bps = speed * 8; printf("%d %s: %d ticks, %d KiB/s %d.%03d Mbps\n", stage, @@ -446,11 +447,13 @@ static int do_spi_flash_test(int argc, char * const argv[]) { unsigned long offset; unsigned long len; - uint8_t *buf = (uint8_t *)CONFIG_SYS_TEXT_BASE; + uint8_t *buf, *from; char *endp; uint8_t *vbuf; int ret; + if (argc < 3) + return -1; offset = simple_strtoul(argv[1], &endp, 16); if (*argv[1] == 0 || *endp != 0) return -1; @@ -460,17 +463,18 @@ static int do_spi_flash_test(int argc, char * const argv[]) vbuf = malloc(len); if (!vbuf) { - printf("Cannot allocate memory\n"); + printf("Cannot allocate memory (%lu bytes)\n", len); return 1; } buf = malloc(len); if (!buf) { free(vbuf); - printf("Cannot allocate memory\n"); + printf("Cannot allocate memory (%lu bytes)\n", len); return 1; } - memcpy(buf, (char *)CONFIG_SYS_TEXT_BASE, len); + from = map_sysmem(CONFIG_SYS_TEXT_BASE, 0); + memcpy(buf, from, len); ret = spi_flash_test(flash, buf, len, offset, vbuf); free(vbuf); free(buf); diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c index 99487f4..5f557d5 100644 --- a/common/cmd_usb_mass_storage.c +++ b/common/cmd_usb_mass_storage.c @@ -42,6 +42,30 @@ int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, g_dnl_register("ums"); + /* Timeout unit: seconds */ + int cable_ready_timeout = UMS_CABLE_READY_TIMEOUT; + + if (!usb_cable_connected()) { + puts("Please connect USB cable.\n"); + + while (!usb_cable_connected()) { + if (ctrlc()) { + puts("\rCTRL+C - Operation aborted.\n"); + goto exit; + } + if (!cable_ready_timeout) { + puts("\rUSB cable not detected.\n" \ + "Command exit.\n"); + goto exit; + } + + printf("\rAuto exit in: %.2d s.", cable_ready_timeout); + mdelay(1000); + cable_ready_timeout--; + } + puts("\r\n"); + } + while (1) { usb_gadget_handle_interrupts(); diff --git a/common/command.c b/common/command.c index 625571d..597ab4c 100644 --- a/common/command.c +++ b/common/command.c @@ -184,10 +184,10 @@ static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv /* output full list of commands */ for (; cmdtp != cmdend; cmdtp++) { if (n_found >= maxv - 2) { - cmdv[n_found] = "..."; + cmdv[n_found++] = "..."; break; } - cmdv[n_found] = cmdtp->name; + cmdv[n_found++] = cmdtp->name; } cmdv[n_found] = NULL; return n_found; diff --git a/common/env_callback.c b/common/env_callback.c index 34bb58e..d03fa03 100644 --- a/common/env_callback.c +++ b/common/env_callback.c @@ -35,6 +35,9 @@ static struct env_clbk_tbl *find_env_callback(const char *name) return NULL; } +static int first_call = 1; +static const char *callback_list; + /* * Look for a possible callback for a newly added variable * This is called specifically when the variable did not exist in the hash @@ -43,11 +46,15 @@ static struct env_clbk_tbl *find_env_callback(const char *name) void env_callback_init(ENTRY *var_entry) { const char *var_name = var_entry->key; - const char *callback_list = getenv(ENV_CALLBACK_VAR); char callback_name[256] = ""; struct env_clbk_tbl *clbkp; int ret = 1; + if (first_call) { + callback_list = getenv(ENV_CALLBACK_VAR); + first_call = 0; + } + /* look in the ".callbacks" var for a reference to this variable */ if (callback_list != NULL) ret = env_attr_lookup(callback_list, var_name, callback_name); diff --git a/common/env_flags.c b/common/env_flags.c index e9b72e6..985f92e 100644 --- a/common/env_flags.c +++ b/common/env_flags.c @@ -395,6 +395,9 @@ static int env_parse_flags_to_bin(const char *flags) return binflags; } +static int first_call = 1; +static const char *flags_list; + /* * Look for possible flags for a newly added variable * This is called specifically when the variable did not exist in the hash @@ -403,10 +406,13 @@ static int env_parse_flags_to_bin(const char *flags) void env_flags_init(ENTRY *var_entry) { const char *var_name = var_entry->key; - const char *flags_list = getenv(ENV_FLAGS_VAR); char flags[ENV_FLAGS_ATTR_MAX_LEN + 1] = ""; int ret = 1; + if (first_call) { + flags_list = getenv(ENV_FLAGS_VAR); + first_call = 0; + } /* look in the ".flags" and static for a reference to this variable */ ret = env_flags_lookup(flags_list, var_name, flags); diff --git a/common/image.c b/common/image.c index 4145354..ae95c3f 100644 --- a/common/image.c +++ b/common/image.c @@ -96,9 +96,9 @@ static const table_entry_t uimage_os[] = { { IH_OS_PLAN9, "plan9", "Plan 9", }, { IH_OS_RTEMS, "rtems", "RTEMS", }, { IH_OS_U_BOOT, "u-boot", "U-Boot", }, + { IH_OS_VXWORKS, "vxworks", "VxWorks", }, #if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC) { IH_OS_QNX, "qnx", "QNX", }, - { IH_OS_VXWORKS, "vxworks", "VxWorks", }, #endif #if defined(CONFIG_INTEGRITY) || defined(USE_HOSTCC) { IH_OS_INTEGRITY,"integrity", "INTEGRITY", }, diff --git a/doc/README.mini2440 b/doc/README.mini2440 deleted file mode 100644 index 311ca52..0000000 --- a/doc/README.mini2440 +++ /dev/null @@ -1,28 +0,0 @@ -U-Boot for FriendlyARM Mini2440 (s3c2440) - -This file contains information for the port of U-Boot to FriendlyARM -mini2440 - -All information about the board can be found on : -http://www.friendlyarm.net/products/mini2440 - -To build u-boot : ./MAKEALL mini2440 - -Overview : --------- -FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440 -ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9 -systems. It's a low cost board. - -Boot Methods : ------------- -Mini2440 can boot from NOR or NAND. - -Build : ------ -./MAKEALL mini2440 - -or - -make mini2440_config -make diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 604de0c..2aed855 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,8 +11,10 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -omap730p2 arm arm926ejs - 2013-11-11 -pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger <wg@grandegger.com> +mx1ads arm arm920t - 2014-01-13 +mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr> +omap730p2 arm arm926ejs 79c5c08d 2013-11-11 +pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg@grandegger.com> pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de> scpu arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de> omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com> diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash new file mode 100644 index 0000000..6c88d65 --- /dev/null +++ b/doc/SPI/README.dual-flash @@ -0,0 +1,92 @@ +SPI/QSPI Dual flash connection modes: +===================================== + +This describes how SPI/QSPI flash memories are connected to a given +controller in a single chip select line. + +Current spi_flash framework supports, single flash memory connected +to a given controller with single chip select line, but there are some +hw logics(ex: xilinx zynq qspi) that describes two/dual memories are +connected with a single chip select line from a controller. + +"dual_flash" from include/spi.h describes these types of connection mode + +Possible connections: +-------------------- +SF_SINGLE_FLASH: + - single spi flash memory connected with single chip select line. + + +------------+ CS +---------------+ + | |----------------------->| | + | Controller | I0[3:0] | Flash memory | + | SPI/QSPI |<======================>| (SPI/QSPI) | + | | CLK | | + | |----------------------->| | + +------------+ +---------------+ + +SF_DUAL_STACKED_FLASH: + - dual spi/qspi flash memories are connected with a single chipselect + line and these two memories are operating stacked fasion with shared buses. + - xilinx zynq qspi controller has implemented this feature [1] + + +------------+ CS +---------------+ + | |---------------------->| | + | | I0[3:0] | Upper Flash | + | | +=========>| memory | + | | | CLK | (SPI/QSPI) | + | | | +---->| | + | Controller | CS | | +---------------+ + | SPI/QSPI |------------|----|---->| | + | | I0[3:0] | | | Lower Flash | + | |<===========+====|====>| memory | + | | CLK | | (SPI/QSPI) | + | |-----------------+---->| | + +------------+ +---------------+ + + - two memory flash devices should has same hw part attributes (like size, + vendor..etc) + - Configurations: + on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG + Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory + Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory + - Operation: + accessing memories serially like one after another. + by default, if U_PAGE is unset lower memory should accessible, + once user wants to access upper memory need to set U_PAGE. + +SPI_FLASH_CONN_DUALPARALLEL: + - dual spi/qspi flash memories are connected with a single chipselect + line and these two memories are operating parallel with separate buses. + - xilinx zynq qspi controller has implemented this feature [1] + + +-------------+ CS +---------------+ + | |---------------------->| | + | | I0[3:0] | Upper Flash | + | |<=====================>| memory | + | | CLK | (SPI/QSPI) | + | |---------------------->| | + | Controller | CS +---------------+ + | SPI/QSPI |---------------------->| | + | | I0[3:0] | Lower Flash | + | |<=====================>| memory | + | | CLK | (SPI/QSPI) | + | |---------------------->| | + +-------------+ +---------------+ + + - two memory flash devices should has same hw part attributes (like size, + vendor..etc) + - Configurations: + Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register. + - Operation: + Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory + and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory. + +Note: Technically there is only one CS line from the controller, but +zynq qspi controller has an internal hw logic to enable additional CS +when controller is configured for dual memories. + +[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf + +-- +Jagannadha Sutradharudu Teki <jaganna@xilinx.com> +05-01-2014. diff --git a/doc/SPI/README.ftssp010_spi_test b/doc/SPI/README.ftssp010_spi_test new file mode 100644 index 0000000..1d86f36 --- /dev/null +++ b/doc/SPI/README.ftssp010_spi_test @@ -0,0 +1,41 @@ +SPI Flash test on Faraday A369 EVB: +================================== + +U-Boot 2014.01-rc2-g3444b6f (Dec 20 2013 - 10:58:40) + +CPU: FA626TE 528 MHz +AHB: 132 MHz +APB: 66 MHz +I2C: ready +DRAM: 256 MiB +MMU: on +NAND: 512 MiB +MMC: ftsdc010: 0 +*** Warning - bad CRC, using default environment + +In: serial +Out: serial +Err: serial +Net: FTGMAC100#0 +Hit any key to stop autoboot: 0 +=> sf probe 0:0 +SF: Detected MX25L1605D with page size 256 Bytes, erase size 64 KiB, total 2 MiB +=> sf read 0x10800000 0 0x400 +SF: 1024 bytes @ 0x0 Read: OK +=> md 0x10800000 +10800000: ea000013 e59ff014 e59ff014 e59ff014 ................ +10800010: e59ff014 e59ff014 e59ff014 e59ff014 ................ +10800020: 1ff7b0c0 1ff7b120 1ff7b180 1ff7b1e0 .... ........... +10800030: 1ff7b240 1ff7b2a0 1ff7b300 deadbeef @............... +10800040: 10800000 0002c1f0 0007409c 00032048 .........@..H .. +10800050: 1fd6af40 e10f0000 e3c0001f e38000d3 @............... +10800060: e129f000 eb000001 eb000223 e12fff1e ..).....#...../. +10800070: e3a00000 ee070f1e ee080f17 ee070f15 ................ +10800080: ee070f9a ee110f10 e3c00c03 e3c00087 ................ +10800090: e3c00a02 e3800002 e3800a01 ee010f10 ................ +108000a0: e1a0c00e eb007a68 e1a0e00c e1a0f00e ....hz.......... +108000b0: e1a00000 e1a00000 e1a00000 e1a00000 ................ +108000c0: e51fd078 e58de000 e14fe000 e58de004 x.........O..... +108000d0: e3a0d013 e169f00d e1a0e00f e1b0f00e ......i......... +108000e0: e24dd048 e88d1fff e51f20a0 e892000c H.M...... ...... +108000f0: e28d0048 e28d5034 e1a0100e e885000f H...4P.......... diff --git a/doc/SPI/status.txt b/doc/SPI/status.txt index 62c3c85..13889f5 100644 --- a/doc/SPI/status.txt +++ b/doc/SPI/status.txt @@ -11,6 +11,11 @@ SPI FLASH (drivers/mtd/spi): - Bank Address Register (Accessing flashes > 16Mbytes in 3-byte addressing) - Added memory_mapped support for read operations. - Common probe support for all supported flash vendors except, ramtron. +- Extended read commands support(dual read, dual IO read) +- Quad Page Program support. +- Quad Read support(quad fast read, quad IO read) +- Dual flash connection topology support(accessing two spi flash memories with single cs) +- Banking support on dual flash connection topology. SPI DRIVERS (drivers/spi): - @@ -18,14 +23,10 @@ SPI DRIVERS (drivers/spi): TODO: - Runtime detection of spi_flash params, SFDP(if possible) - Add support for multibus build/accessing. -- Extended read commands support(dual read, dual IO read) -- Quad Page Program support. -- Quad Read support(quad fast read, quad IO read) -- Dual flash connection topology support(accessing two spi flash memories with single cs) -- Banking support on dual flash connection topology. - Need proper cleanups on spi_flash and drivers. -- Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> 18-09-2013. 07-10-2013. +08-01-2014. diff --git a/doc/uImage.FIT/howto.txt b/doc/uImage.FIT/howto.txt index 59e21e9..526be55 100644 --- a/doc/uImage.FIT/howto.txt +++ b/doc/uImage.FIT/howto.txt @@ -20,8 +20,8 @@ www.jdl.com for its latest version. mkimage (together with dtc) takes as input an image source file, which describes the contents of the image and defines its various properties used during booting. By convention, image source file has the ".its" extension, also, the details of its format are given in -doc/source_file_format.txt. The actual data that is to be included in the -uImage (kernel, ramdisk, etc.) is specified in the image source file in the +doc/uImage.FIT/source_file_format.txt. The actual data that is to be included in +the uImage (kernel, ramdisk, etc.) is specified in the image source file in the form of paths to appropriate data files. The outcome of the image creation process is a binary file (by convention with the ".itb" extension) that contains all the referenced data (kernel, ramdisk, etc.) and other information @@ -39,7 +39,7 @@ Here's a graphical overview of the image creation and booting process: image source file mkimage + dtc transfer to target + ---------------> image file --------------------> bootm -image data files(s) +image data file(s) Example 1 -- old-style (non-FDT) kernel booting diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 160b2d0..9ed6f65 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -159,7 +159,7 @@ the '/images' node should have the following layout: - description : Textual description of the component sub-image - type : Name of component sub-image type, supported types are: "standalone", "kernel", "ramdisk", "firmware", "script", "filesystem", - "fdt". + "flat_dt". - data : Path to the external file which contains this node's binary data. - compression : Compression used by included data. Supported compressions are "gzip" and "bzip2". If no compression is used compression property diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4cec5aa..4cec5aa 100755..100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 790d538..389c4de 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -933,6 +933,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) mtd = &nand_info[nand_curr_device]; nand = mtd->priv; nand->options |= NAND_OWN_BUFFERS; + nand->options &= ~NAND_SUBPAGE_READ; /* Setup the ecc configurations again */ if (hardware) { if (eccstrength == 1) { diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 26483a2..9e18fb4 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -10,8 +10,8 @@ obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o endif -obj-$(CONFIG_CMD_SF) += sf.o -obj-$(CONFIG_SPI_FLASH) += sf_probe.o sf_ops.o +obj-$(CONFIG_CMD_SF) += sf.o +obj-$(CONFIG_SPI_FLASH) += sf_params.o sf_probe.o sf_ops.o obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c index d5e175c..664e860 100644 --- a/drivers/mtd/spi/sf.c +++ b/drivers/mtd/spi/sf.c @@ -18,6 +18,10 @@ static int spi_flash_read_write(struct spi_slave *spi, unsigned long flags = SPI_XFER_BEGIN; int ret; +#ifdef CONFIG_SF_DUAL_FLASH + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; +#endif if (data_len == 0) flags |= SPI_XFER_END; diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index d291746..6bcd522 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -10,12 +10,15 @@ #ifndef _SF_INTERNAL_H_ #define _SF_INTERNAL_H_ +#define SPI_FLASH_3B_ADDR_LEN 3 +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000 -/* SECT flags */ -#define SECT_4K (1 << 1) -#define SECT_32K (1 << 2) -#define E_FSR (1 << 3) +/* CFI Manufacture ID's */ +#define SPI_FLASH_CFI_MFR_SPANSION 0x01 +#define SPI_FLASH_CFI_MFR_STMICRO 0x20 +#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 +#define SPI_FLASH_CFI_MFR_WINBOND 0xef /* Erase commands */ #define CMD_ERASE_4K 0x20 @@ -28,6 +31,7 @@ #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 +#define CMD_QUAD_PAGE_PROGRAM 0x32 #define CMD_READ_STATUS1 0x35 #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_CONFIG 0x35 @@ -36,6 +40,10 @@ /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 #define CMD_READ_ARRAY_FAST 0x0b +#define CMD_READ_DUAL_OUTPUT_FAST 0x3b +#define CMD_READ_DUAL_IO_FAST 0xbb +#define CMD_READ_QUAD_OUTPUT_FAST 0x6b +#define CMD_READ_QUAD_IO_FAST 0xeb #define CMD_READ_ID 0x9f /* Bank addr access commands */ @@ -47,8 +55,10 @@ #endif /* Common status */ -#define STATUS_WIP 0x01 -#define STATUS_PEC 0x80 +#define STATUS_WIP (1 << 0) +#define STATUS_QEB_WINSPAN (1 << 1) +#define STATUS_QEB_MXIC (1 << 6) +#define STATUS_PEC (1 << 7) /* Flash timeout values */ #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) @@ -86,11 +96,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, /* Flash erase(sectors) operation, support all possible erase commands */ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); +/* Read the status register */ +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); + /* Program the status register */ -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr); +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); + +/* Read the config register */ +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); -/* Set quad enbale bit */ -int spi_flash_set_qeb(struct spi_flash *flash); +/* Program the config register */ +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc); /* Enable writing on the SPI flash */ static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index e316a69..1f1bb36 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <malloc.h> #include <spi.h> #include <spi_flash.h> #include <watchdog.h> @@ -23,13 +24,28 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } -int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) +int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs) +{ + int ret; + u8 cmd; + + cmd = CMD_READ_STATUS; + ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); + if (ret < 0) { + debug("SF: fail to read status register\n"); + return ret; + } + + return 0; +} + +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws) { u8 cmd; int ret; cmd = CMD_WRITE_STATUS; - ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1); + ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1); if (ret < 0) { debug("SF: fail to write status register\n"); return ret; @@ -38,6 +54,44 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) return 0; } +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc) +{ + int ret; + u8 cmd; + + cmd = CMD_READ_CONFIG; + ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); + if (ret < 0) { + debug("SF: fail to read config register\n"); + return ret; + } + + return 0; +} + +int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) +{ + u8 data[2]; + u8 cmd; + int ret; + + ret = spi_flash_cmd_read_status(flash, &data[0]); + if (ret < 0) + return ret; + + cmd = CMD_WRITE_STATUS; + data[1] = wc; + ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); + if (ret) { + debug("SF: fail to write config register\n"); + return ret; + } + + return 0; +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) { @@ -65,7 +119,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) u8 bank_sel; int ret; - bank_sel = offset / SPI_FLASH_16MB_BOUN; + bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); if (ret) { @@ -73,7 +127,29 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset) return ret; } - return 0; + return bank_sel; +} +#endif + +#ifdef CONFIG_SF_DUAL_FLASH +static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr) +{ + switch (flash->dual_flash) { + case SF_DUAL_STACKED_FLASH: + if (*addr >= (flash->size >> 1)) { + *addr -= flash->size >> 1; + flash->spi->flags |= SPI_XFER_U_PAGE; + } else { + flash->spi->flags &= ~SPI_XFER_U_PAGE; + } + break; + case SF_DUAL_PARALLEL_FLASH: + *addr >>= flash->shift; + break; + default: + debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); + break; + } } #endif @@ -81,6 +157,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) { struct spi_slave *spi = flash->spi; unsigned long timebase; + unsigned long flags = SPI_XFER_BEGIN; int ret; u8 status; u8 check_status = 0x0; @@ -92,7 +169,11 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) check_status = poll_bit; } - ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); +#ifdef CONFIG_SF_DUAL_FLASH + if (spi->flags & SPI_XFER_U_PAGE) + flags |= SPI_XFER_U_PAGE; +#endif + ret = spi_xfer(spi, 8, &cmd, NULL, flags); if (ret) { debug("SF: fail to read %s status register\n", cmd == CMD_READ_STATUS ? "read" : "flag"); @@ -165,8 +246,8 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { - u32 erase_size; - u8 cmd[4]; + u32 erase_size, erase_addr; + u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1; erase_size = flash->erase_size; @@ -177,15 +258,21 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) cmd[0] = flash->erase_cmd; while (len) { + erase_addr = offset; + +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &erase_addr); +#endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_bank(flash, offset); + ret = spi_flash_bank(flash, erase_addr); if (ret < 0) return ret; #endif - spi_flash_addr(offset, cmd); + spi_flash_addr(erase_addr, cmd); debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], - cmd[2], cmd[3], offset); + cmd[2], cmd[3], erase_addr); ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); if (ret < 0) { @@ -204,16 +291,23 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { unsigned long byte_addr, page_size; + u32 write_addr; size_t chunk_len, actual; - u8 cmd[4]; + u8 cmd[SPI_FLASH_CMD_LEN]; int ret = -1; page_size = flash->page_size; - cmd[0] = CMD_PAGE_PROGRAM; + cmd[0] = flash->write_cmd; for (actual = 0; actual < len; actual += chunk_len) { + write_addr = offset; + +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &write_addr); +#endif #ifdef CONFIG_SPI_FLASH_BAR - ret = spi_flash_bank(flash, offset); + ret = spi_flash_bank(flash, write_addr); if (ret < 0) return ret; #endif @@ -223,9 +317,9 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, if (flash->spi->max_write_size) chunk_len = min(chunk_len, flash->spi->max_write_size); - spi_flash_addr(offset, cmd); + spi_flash_addr(write_addr, cmd); - debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", + debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_write_common(flash, cmd, sizeof(cmd), @@ -267,8 +361,9 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data) { - u8 cmd[5], bank_sel = 0; - u32 remain_len, read_len; + u8 *cmd, cmdsz; + u32 remain_len, read_len, read_addr; + int bank_sel = 0; int ret = -1; /* Handle memory-mapped SPI */ @@ -285,29 +380,33 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return 0; } - cmd[0] = CMD_READ_ARRAY_FAST; - cmd[4] = 0x00; + cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; + cmd = malloc(cmdsz); + memset(cmd, 0, cmdsz); + cmd[0] = flash->read_cmd; while (len) { -#ifdef CONFIG_SPI_FLASH_BAR - bank_sel = offset / SPI_FLASH_16MB_BOUN; + read_addr = offset; - ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); - if (ret) { - debug("SF: fail to set bank%d\n", bank_sel); +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash > SF_SINGLE_FLASH) + spi_flash_dual_flash(flash, &read_addr); +#endif +#ifdef CONFIG_SPI_FLASH_BAR + bank_sel = spi_flash_bank(flash, read_addr); + if (bank_sel < 0) return ret; - } #endif - remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset; + remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * + (bank_sel + 1)) - offset; if (len < remain_len) read_len = len; else read_len = remain_len; - spi_flash_addr(offset, cmd); + spi_flash_addr(read_addr, cmd); - ret = spi_flash_read_common(flash, cmd, sizeof(cmd), - data, read_len); + ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); if (ret < 0) { debug("SF: read failed\n"); break; diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c new file mode 100644 index 0000000..daf8fe7 --- /dev/null +++ b/drivers/mtd/spi/sf_params.c @@ -0,0 +1,130 @@ +/* + * SPI flash Params table + * + * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi_flash.h> + +#include "sf_internal.h" + +/* SPI/QSPI flash device params structure */ +const struct spi_flash_params spi_flash_params_table[] = { +#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ + {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K}, + {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K}, + {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K}, + {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K}, + {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K}, + {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K}, + {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K}, +#endif +#ifdef CONFIG_SPI_FLASH_EON /* EON */ + {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0}, + {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0}, + {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0}, +#endif +#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ + {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K}, +#endif +#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ + {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0}, + {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0}, + {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0}, + {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0}, + {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0}, + {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0}, + {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP}, + {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP}, + {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, +#endif +#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ + {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0}, + {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0}, + {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0}, + {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0}, + {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP}, + {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, + {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP}, + {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP}, + {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, + {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, RD_FULL, WR_QPP}, + {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP}, +#endif +#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ + {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0}, + {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0}, + {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0}, + {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0}, + {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0}, + {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0}, + {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0}, + {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0}, + {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP}, + {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, + {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, + {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, +#endif +#ifdef CONFIG_SPI_FLASH_SST /* SST */ + {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP}, + {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP}, + {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP}, + {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP}, + {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP}, + {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP}, + {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP}, + {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP}, + {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP}, +#endif +#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ + {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0}, + {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0}, + {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0}, + {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K}, + {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K}, + {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K}, + {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K}, + {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, + {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, +#endif + /* + * Note: + * Below paired flash devices has similar spi_flash params. + * (S25FL129P_64K, S25FL128S_64K) + * (W25Q80BL, W25Q80BV) + * (W25Q16CL, W25Q16DV) + * (W25Q32BV, W25Q32FV_SPI) + * (W25Q64CV, W25Q64FV_SPI) + * (W25Q128BV, W25Q128FV_SPI) + * (W25Q32DW, W25Q32FV_QPI) + * (W25Q64DW, W25Q64FV_QPI) + * (W25Q128FW, W25Q128FV_QPI) + */ +}; diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index b863a98..bc3cf6c 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -19,154 +19,93 @@ DECLARE_GLOBAL_DATA_PTR; -/** - * struct spi_flash_params - SPI/QSPI flash device params structure - * - * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) - * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) - * @ext_jedec: Device ext_jedec ID - * @sector_size: Sector size of this device - * @nr_sectors: No.of sectors on this device - * @flags: Importent param, for flash specific behaviour - */ -struct spi_flash_params { - const char *name; - u32 jedec; - u16 ext_jedec; - u32 sector_size; - u32 nr_sectors; - u16 flags; +/* Read commands array */ +static u8 spi_read_cmds_array[] = { + CMD_READ_ARRAY_SLOW, + CMD_READ_DUAL_OUTPUT_FAST, + CMD_READ_DUAL_IO_FAST, + CMD_READ_QUAD_OUTPUT_FAST, + CMD_READ_QUAD_IO_FAST, }; -static const struct spi_flash_params spi_flash_params_table[] = { -#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ - {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K}, - {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K}, - {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K}, - {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K}, - {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K}, - {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K}, - {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K}, - {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, SECT_4K}, -#endif -#ifdef CONFIG_SPI_FLASH_EON /* EON */ - {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0}, - {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K}, - {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0}, - {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0}, -#endif -#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ - {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K}, - {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K}, -#endif -#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ - {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0}, - {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0}, - {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0}, - {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0}, - {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0}, - {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0}, - {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0}, - {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0}, - {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0}, - {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0}, +#ifdef CONFIG_SPI_FLASH_MACRONIX +static int spi_flash_set_qeb_mxic(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = spi_flash_cmd_read_status(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_MXIC) { + debug("SF: mxic: QEB is already set\n"); + } else { + ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC); + if (ret < 0) + return ret; + } + + return ret; +} #endif -#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ - {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0}, - {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0}, - {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0}, - {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0}, - {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0}, - {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0}, - {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0}, - {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0}, - {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0}, - {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, 0}, - {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, 0}, - {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0}, - {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0}, + +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) +static int spi_flash_set_qeb_winspan(struct spi_flash *flash) +{ + u8 qeb_status; + int ret; + + ret = spi_flash_cmd_read_config(flash, &qeb_status); + if (ret < 0) + return ret; + + if (qeb_status & STATUS_QEB_WINSPAN) { + debug("SF: winspan: QEB is already set\n"); + } else { + ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN); + if (ret < 0) + return ret; + } + + return ret; +} #endif -#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0}, - {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0}, - {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0}, - {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0}, - {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0}, - {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0}, - {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0}, - {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0}, - {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, SECT_4K}, - {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, SECT_4K}, - {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, SECT_4K}, - {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, SECT_4K}, - {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, SECT_4K}, - {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, SECT_4K}, - {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, SECT_4K}, - {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, SECT_4K}, - {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K}, - {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, E_FSR | SECT_4K}, - {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K}, - {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, E_FSR | SECT_4K}, + +static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) +{ + switch (idcode0) { +#ifdef CONFIG_SPI_FLASH_MACRONIX + case SPI_FLASH_CFI_MFR_MACRONIX: + return spi_flash_set_qeb_mxic(flash); #endif -#ifdef CONFIG_SPI_FLASH_SST /* SST */ - {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WP}, - {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WP}, - {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WP}, - {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WP}, - {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K}, - {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WP}, - {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WP}, - {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WP}, - {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WP}, - {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WP}, +#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) + case SPI_FLASH_CFI_MFR_SPANSION: + case SPI_FLASH_CFI_MFR_WINBOND: + return spi_flash_set_qeb_winspan(flash); #endif -#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ - {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0}, - {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0}, - {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0}, - {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K}, - {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K}, - {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K}, - {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K}, - {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, SECT_4K}, - {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, SECT_4K}, - {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, SECT_4K}, - {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, SECT_4K}, - {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, SECT_4K}, - {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, SECT_4K}, - {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, SECT_4K}, - {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, SECT_4K}, - {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, SECT_4K}, - {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, SECT_4K}, - {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, SECT_4K}, +#ifdef CONFIG_SPI_FLASH_STMICRO + case SPI_FLASH_CFI_MFR_STMICRO: + debug("SF: QEB is volatile for %02x flash\n", idcode0); + return 0; #endif - /* - * Note: - * Below paired flash devices has similar spi_flash params. - * (S25FL129P_64K, S25FL128S_64K) - * (W25Q80BL, W25Q80BV) - * (W25Q16CL, W25Q16DV) - * (W25Q32BV, W25Q32FV_SPI) - * (W25Q64CV, W25Q64FV_SPI) - * (W25Q128BV, W25Q128FV_SPI) - * (W25Q32DW, W25Q32FV_QPI) - * (W25Q64DW, W25Q64FV_QPI) - * (W25Q128FW, W25Q128FV_QPI) - */ -}; + default: + printf("SF: Need set QEB func for %02x flash\n", idcode0); + return -1; + } +} static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, u8 *idcode) { const struct spi_flash_params *params; struct spi_flash *flash; - int i; + u8 cmd; u16 jedec = idcode[1] << 8 | idcode[2]; u16 ext_jedec = idcode[3] << 8 | idcode[4]; - /* Get the flash id (jedec = manuf_id + dev_id, ext_jedec) */ - for (i = 0; i < ARRAY_SIZE(spi_flash_params_table); i++) { - params = &spi_flash_params_table[i]; + params = spi_flash_params_table; + for (; params->name != NULL; params++) { if ((params->jedec >> 16) == idcode[0]) { if ((params->jedec & 0xFFFF) == jedec) { if (params->ext_jedec == 0) @@ -177,7 +116,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, } } - if (i == ARRAY_SIZE(spi_flash_params_table)) { + if (!params->name) { printf("SF: Unsupported flash IDs: "); printf("manuf %02x, jedec %04x, ext_jedec %04x\n", idcode[0], jedec, ext_jedec); @@ -195,6 +134,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->spi = spi; flash->name = params->name; flash->memory_map = spi->memory_map; + flash->dual_flash = flash->spi->option; /* Assign spi_flash ops */ flash->write = spi_flash_cmd_write_ops; @@ -206,23 +146,74 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash->read = spi_flash_cmd_read_ops; /* Compute the flash size */ - flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256; - flash->sector_size = params->sector_size; - flash->size = flash->sector_size * params->nr_sectors; + flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; + flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift; + flash->sector_size = params->sector_size << flash->shift; + flash->size = flash->sector_size * params->nr_sectors << flash->shift; +#ifdef CONFIG_SF_DUAL_FLASH + if (flash->dual_flash & SF_DUAL_STACKED_FLASH) + flash->size <<= 1; +#endif /* Compute erase sector and command */ if (params->flags & SECT_4K) { flash->erase_cmd = CMD_ERASE_4K; - flash->erase_size = 4096; + flash->erase_size = 4096 << flash->shift; } else if (params->flags & SECT_32K) { flash->erase_cmd = CMD_ERASE_32K; - flash->erase_size = 32768; + flash->erase_size = 32768 << flash->shift; } else { flash->erase_cmd = CMD_ERASE_64K; flash->erase_size = flash->sector_size; } - /* Poll cmd seclection */ + /* Look for the fastest read cmd */ + cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx); + if (cmd) { + cmd = spi_read_cmds_array[cmd - 1]; + flash->read_cmd = cmd; + } else { + /* Go for default supported read cmd */ + flash->read_cmd = CMD_READ_ARRAY_FAST; + } + + /* Not require to look for fastest only two write cmds yet */ + if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP) + flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; + else + /* Go for default supported write cmd */ + flash->write_cmd = CMD_PAGE_PROGRAM; + + /* Set the quad enable bit - only for quad commands */ + if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || + (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || + (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { + if (spi_flash_set_qeb(flash, idcode[0])) { + debug("SF: Fail to set QEB for %02x\n", idcode[0]); + return NULL; + } + } + + /* Read dummy_byte: dummy byte is determined based on the + * dummy cycles of a particular command. + * Fast commands - dummy_byte = dummy_cycles/8 + * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 + * For I/O commands except cmd[0] everything goes on no.of lines + * based on particular command but incase of fast commands except + * data all go on single line irrespective of command. + */ + switch (flash->read_cmd) { + case CMD_READ_QUAD_IO_FAST: + flash->dummy_byte = 2; + break; + case CMD_READ_ARRAY_SLOW: + flash->dummy_byte = 0; + break; + default: + flash->dummy_byte = 1; + } + + /* Poll cmd selection */ flash->poll_cmd = CMD_READ_STATUS; #ifdef CONFIG_SPI_FLASH_STMICRO if (params->flags & E_FSR) @@ -339,7 +330,10 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi) puts("\n"); #endif #ifndef CONFIG_SPI_FLASH_BAR - if (flash->size > SPI_FLASH_16MB_BOUN) { + if (((flash->dual_flash == SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN)) || + ((flash->dual_flash > SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN << 1))) { puts("SF: Warning - Only lower 16MiB accessible,"); puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); } diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index b20b4df..32c2ab9 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -50,7 +50,7 @@ static struct phy_driver AR8021_driver = { static struct phy_driver AR8031_driver = { .name = "AR8031/AR8033", .uid = 0x4dd074, - .mask = 0x4fffff, + .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, .config = ar8021_config, .startup = genphy_startup, @@ -60,7 +60,7 @@ static struct phy_driver AR8031_driver = { static struct phy_driver AR8035_driver = { .name = "AR8035", .uid = 0x4dd072, - .mask = 0x4fffff, + .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, .config = ar8035_config, .startup = genphy_startup, diff --git a/drivers/power/fuel_gauge/fg_max17042.c b/drivers/power/fuel_gauge/fg_max17042.c index c285747..154ca6a 100644 --- a/drivers/power/fuel_gauge/fg_max17042.c +++ b/drivers/power/fuel_gauge/fg_max17042.c @@ -20,21 +20,30 @@ static int fg_write_regs(struct pmic *p, u8 addr, u16 *data, int num) int ret = 0; int i; - for (i = 0; i < num; i++, addr++) - ret |= pmic_reg_write(p, addr, *(data + i)); + for (i = 0; i < num; i++, addr++) { + ret = pmic_reg_write(p, addr, *(data + i)); + if (ret) + return ret; + } - return ret; + return 0; } static int fg_read_regs(struct pmic *p, u8 addr, u16 *data, int num) { + unsigned int dat; int ret = 0; int i; - for (i = 0; i < num; i++, addr++) - ret |= pmic_reg_read(p, addr, (u32 *) (data + i)); + for (i = 0; i < num; i++, addr++) { + ret = pmic_reg_read(p, addr, &dat); + if (ret) + return ret; - return ret; + *(data + i) = (u16)dat; + } + + return 0; } static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data) @@ -57,9 +66,13 @@ static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data) static void por_fuelgauge_init(struct pmic *p) { u16 r_data0[16], r_data1[16], r_data2[16]; - u32 rewrite_count = 5, i = 0; - unsigned int val; - int ret = 0; + u32 rewrite_count = 5; + u32 check_count; + u32 lock_count; + u32 i = 0; + u32 val; + s32 ret = 0; + char *status_msg; /* Delay 500 ms */ mdelay(500); @@ -67,29 +80,55 @@ static void por_fuelgauge_init(struct pmic *p) pmic_reg_write(p, MAX17042_CONFIG, 0x2310); rewrite_model: + check_count = 5; + lock_count = 5; + + if (!rewrite_count--) { + status_msg = "init failed!"; + goto error; + } + /* Unlock Model Access */ pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_UNLOCK1); pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_UNLOCK2); /* Write/Read/Verify the Custom Model */ - ret |= fg_write_regs(p, MAX17042_MODEL1, cell_character0, + ret = fg_write_regs(p, MAX17042_MODEL1, cell_character0, ARRAY_SIZE(cell_character0)); - ret |= fg_write_regs(p, MAX17042_MODEL2, cell_character1, + if (ret) + goto rewrite_model; + + ret = fg_write_regs(p, MAX17042_MODEL2, cell_character1, ARRAY_SIZE(cell_character1)); - ret |= fg_write_regs(p, MAX17042_MODEL3, cell_character2, + if (ret) + goto rewrite_model; + + ret = fg_write_regs(p, MAX17042_MODEL3, cell_character2, ARRAY_SIZE(cell_character2)); + if (ret) + goto rewrite_model; - if (ret) { - printf("%s: Cell parameters write failed!\n", __func__); - return; +check_model: + if (!check_count--) { + if (rewrite_count) + goto rewrite_model; + else + status_msg = "check failed!"; + + goto error; } - ret |= fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); - ret |= fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); - ret |= fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); + ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); + if (ret) + goto check_model; + + ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); + if (ret) + goto check_model; + ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); if (ret) - printf("%s: Cell parameters read failed!\n", __func__); + goto check_model; for (i = 0; i < 16; i++) { if ((cell_character0[i] != r_data0[i]) @@ -98,29 +137,37 @@ rewrite_model: goto rewrite_model; } +lock_model: + if (!lock_count--) { + if (rewrite_count) + goto rewrite_model; + else + status_msg = "lock failed!"; + + goto error; + } + /* Lock model access */ pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_LOCK1); pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_LOCK2); /* Verify the model access is locked */ - ret |= fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); - ret |= fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); - ret |= fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); + ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); + if (ret) + goto lock_model; - if (ret) { - printf("%s: Cell parameters read failed!\n", __func__); - return; - } + ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); + if (ret) + goto lock_model; + + ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); + if (ret) + goto lock_model; for (i = 0; i < ARRAY_SIZE(r_data0); i++) { /* Check if model locked */ - if (r_data0[i] || r_data1[i] || r_data2[i]) { - /* Rewrite model data - prevent from endless loop */ - if (rewrite_count--) { - puts("FG - Lock model access failed!\n"); - goto rewrite_model; - } - } + if (r_data0[i] || r_data1[i] || r_data2[i]) + goto lock_model; } /* Write Custom Parameters */ @@ -137,6 +184,11 @@ rewrite_model: /* Delay at least 350 ms */ mdelay(350); + + status_msg = "OK!"; +error: + debug("%s: model init status: %s\n", p->name, status_msg); + return; } static int power_update_battery(struct pmic *p, struct pmic *bat) @@ -178,7 +230,7 @@ static int power_check_battery(struct pmic *p, struct pmic *bat) ret |= pmic_reg_read(p, MAX17042_STATUS, &val); debug("fg status: 0x%x\n", val); - if (val == MAX17042_POR) + if (val & MAX17042_POR) por_fuelgauge_init(p); ret |= pmic_reg_read(p, MAX17042_VERSION, &val); diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d5a7143..81b6af6 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_CF_SPI) += cf_spi.o obj-$(CONFIG_CF_QSPI) += cf_qspi.o obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o +obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c new file mode 100644 index 0000000..aa3b5a0 --- /dev/null +++ b/drivers/spi/ftssp010_spi.c @@ -0,0 +1,508 @@ +/* + * (C) Copyright 2013 + * Faraday Technology Corporation. <http://www.faraday-tech.com/tw/> + * Kuo-Jung Su <dantesu@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/compat.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> + +#ifndef CONFIG_FTSSP010_BASE_LIST +#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE } +#endif + +#ifndef CONFIG_FTSSP010_GPIO_BASE +#define CONFIG_FTSSP010_GPIO_BASE 0 +#endif + +#ifndef CONFIG_FTSSP010_GPIO_LIST +#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE } +#endif + +#ifndef CONFIG_FTSSP010_CLOCK +#define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP"); +#endif + +#ifndef CONFIG_FTSSP010_TIMEOUT +#define CONFIG_FTSSP010_TIMEOUT 100 +#endif + +/* FTSSP010 chip registers */ +struct ftssp010_regs { + uint32_t cr[3];/* control register */ + uint32_t sr; /* status register */ + uint32_t icr; /* interrupt control register */ + uint32_t isr; /* interrupt status register */ + uint32_t dr; /* data register */ + uint32_t rsvd[17]; + uint32_t revr; /* revision register */ + uint32_t fear; /* feature register */ +}; + +/* Control Register 0 */ +#define CR0_FFMT_MASK (7 << 12) +#define CR0_FFMT_SSP (0 << 12) +#define CR0_FFMT_SPI (1 << 12) +#define CR0_FFMT_MICROWIRE (2 << 12) +#define CR0_FFMT_I2S (3 << 12) +#define CR0_FFMT_AC97 (4 << 12) +#define CR0_FLASH (1 << 11) +#define CR0_FSDIST(x) (((x) & 0x03) << 8) +#define CR0_LOOP (1 << 7) /* loopback mode */ +#define CR0_LSB (1 << 6) /* LSB */ +#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */ +#define CR0_FSJUSTIFY (1 << 4) +#define CR0_OPM_SLAVE (0 << 2) +#define CR0_OPM_MASTER (3 << 2) +#define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */ +#define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */ +#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */ +#define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */ +#define CR0_SCLKPO (1 << 1) /* clock polarity */ +#define CR0_SCLKPH (1 << 0) /* clock phase */ + +/* Control Register 1 */ +#define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */ +#define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */ +#define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */ + +/* Control Register 2 */ +#define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */ +#define CR2_FS (1 << 9) /* CS/FS signal level */ +#define CR2_TXEN (1 << 8) /* tx enable */ +#define CR2_RXEN (1 << 7) /* rx enable */ +#define CR2_RESET (1 << 6) /* chip reset */ +#define CR2_TXFC (1 << 3) /* tx fifo Clear */ +#define CR2_RXFC (1 << 2) /* rx fifo Clear */ +#define CR2_TXDOE (1 << 1) /* tx data output enable */ +#define CR2_EN (1 << 0) /* chip enable */ + +/* Status Register */ +#define SR_RFF (1 << 0) /* rx fifo full */ +#define SR_TFNF (1 << 1) /* tx fifo not full */ +#define SR_BUSY (1 << 2) /* chip busy */ +#define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */ +#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */ + +/* Feature Register */ +#define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */ +#define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */ +#define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */ +#define FEAR_AC97 (1 << 24) +#define FEAR_I2S (1 << 25) +#define FEAR_SPI_MWR (1 << 26) +#define FEAR_SSP (1 << 27) +#define FEAR_SPDIF (1 << 28) + +/* FTGPIO010 chip registers */ +struct ftgpio010_regs { + uint32_t out; /* 0x00: Data Output */ + uint32_t in; /* 0x04: Data Input */ + uint32_t dir; /* 0x08: Direction */ + uint32_t bypass; /* 0x0c: Bypass */ + uint32_t set; /* 0x10: Data Set */ + uint32_t clr; /* 0x14: Data Clear */ + uint32_t pull_up; /* 0x18: Pull-Up Enabled */ + uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */ +}; + +struct ftssp010_gpio { + struct ftgpio010_regs *regs; + uint32_t pin; +}; + +struct ftssp010_spi { + struct spi_slave slave; + struct ftssp010_gpio gpio; + struct ftssp010_regs *regs; + uint32_t fifo; + uint32_t mode; + uint32_t div; + uint32_t clk; + uint32_t speed; + uint32_t revision; +}; + +static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ftssp010_spi, slave); +} + +static int get_spi_chip(int bus, struct ftssp010_spi *chip) +{ + uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST; + + if (bus >= ARRAY_SIZE(base) || !base[bus]) + return -1; + + chip->regs = (struct ftssp010_regs *)base[bus]; + + chip->revision = readl(&chip->regs->revr); + + fear = readl(&chip->regs->fear); + chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear)); + + return 0; +} + +static int get_spi_gpio(int bus, struct ftssp010_gpio *chip) +{ + uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST; + + if (bus >= ARRAY_SIZE(base) || !base[bus]) + return -1; + + chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000); + chip->pin = base[bus] & 0x1f; + + /* make it an output pin */ + setbits_le32(&chip->regs->dir, 1 << chip->pin); + + return 0; +} + +static int ftssp010_wait(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + int ret = -1; + ulong t; + + /* wait until device idle */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (readl(®s->sr) & SR_BUSY) + continue; + ret = 0; + break; + } + + if (ret) + puts("ftspi010: busy timeout\n"); + + return ret; +} + +static int ftssp010_wait_tx(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + int ret = -1; + ulong t; + + /* wait until tx fifo not full */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (!(readl(®s->sr) & SR_TFNF)) + continue; + ret = 0; + break; + } + + if (ret) + puts("ftssp010: tx timeout\n"); + + return ret; +} + +static int ftssp010_wait_rx(struct ftssp010_spi *chip) +{ + struct ftssp010_regs *regs = chip->regs; + int ret = -1; + ulong t; + + /* wait until rx fifo not empty */ + for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { + if (!SR_RFVE(readl(®s->sr))) + continue; + ret = 0; + break; + } + + if (ret) + puts("ftssp010: rx timeout\n"); + + return ret; +} + +static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip, + const void *tx_buf, void *rx_buf, int len, uint flags) +{ + struct ftssp010_regs *regs = chip->regs; + const uint8_t *txb = tx_buf; + uint8_t *rxb = rx_buf; + + while (len > 0) { + int i, depth = min(chip->fifo >> 2, len); + uint32_t xmsk = 0; + + if (tx_buf) { + for (i = 0; i < depth; ++i) { + ftssp010_wait_tx(chip); + writel(*txb++, ®s->dr); + } + xmsk |= CR2_TXEN | CR2_TXDOE; + if ((readl(®s->cr[2]) & xmsk) != xmsk) + setbits_le32(®s->cr[2], xmsk); + } + if (rx_buf) { + xmsk |= CR2_RXEN; + if ((readl(®s->cr[2]) & xmsk) != xmsk) + setbits_le32(®s->cr[2], xmsk); + for (i = 0; i < depth; ++i) { + ftssp010_wait_rx(chip); + *rxb++ = (uint8_t)readl(®s->dr); + } + } + + len -= depth; + } + + return 0; +} + +static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip, + const void *tx_buf, void *rx_buf, int len, uint flags) +{ + struct ftssp010_regs *regs = chip->regs; + const uint8_t *txb = tx_buf; + uint8_t *rxb = rx_buf; + + while (len > 0) { + int i, depth = min(chip->fifo >> 2, len); + uint32_t tmp; + + for (i = 0; i < depth; ++i) { + ftssp010_wait_tx(chip); + writel(txb ? (*txb++) : 0, ®s->dr); + } + for (i = 0; i < depth; ++i) { + ftssp010_wait_rx(chip); + tmp = readl(®s->dr); + if (rxb) + *rxb++ = (uint8_t)tmp; + } + + len -= depth; + } + + return 0; +} + +static void ftssp010_cs_set(struct ftssp010_spi *chip, int high) +{ + struct ftssp010_regs *regs = chip->regs; + struct ftssp010_gpio *gpio = &chip->gpio; + uint32_t mask; + + /* cs pull high/low */ + if (chip->revision >= 0x11900) { + mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0); + writel(mask, ®s->cr[2]); + } else if (gpio->regs) { + mask = 1 << gpio->pin; + if (high) + writel(mask, &gpio->regs->set); + else + writel(mask, &gpio->regs->clr); + } + + /* extra delay for signal propagation */ + udelay_masked(1); +} + +/* + * Determine if a SPI chipselect is valid. + * This function is provided by the board if the low-level SPI driver + * needs it to determine if a given chipselect is actually valid. + * + * Returns: 1 if bus:cs identifies a valid chip on this board, 0 + * otherwise. + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + struct ftssp010_spi chip; + + if (get_spi_chip(bus, &chip)) + return 0; + + if (!cs) + return 1; + else if ((cs < 4) && (chip.revision >= 0x11900)) + return 1; + + return 0; +} + +/* + * Activate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should activate the chip select + * to the device identified by "slave". + */ +void spi_cs_activate(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + /* cs pull */ + if (chip->mode & SPI_CS_HIGH) + ftssp010_cs_set(chip, 1); + else + ftssp010_cs_set(chip, 0); + + /* chip enable + fifo clear */ + setbits_le32(®s->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC); +} + +/* + * Deactivate a SPI chipselect. + * This function is provided by the board code when using a driver + * that can't control its chipselects automatically (e.g. + * common/soft_spi.c). When called, it should deactivate the chip + * select to the device identified by "slave". + */ +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + + /* wait until chip idle */ + ftssp010_wait(chip); + + /* cs pull */ + if (chip->mode & SPI_CS_HIGH) + ftssp010_cs_set(chip, 0); + else + ftssp010_cs_set(chip, 1); +} + +void spi_init(void) +{ + /* nothing to do */ +} + +struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) +{ + struct ftssp010_spi *chip; + + if (mode & SPI_3WIRE) { + puts("ftssp010: can't do 3-wire\n"); + return NULL; + } + + if (mode & SPI_SLAVE) { + puts("ftssp010: can't do slave mode\n"); + return NULL; + } + + if (mode & SPI_PREAMBLE) { + puts("ftssp010: can't skip preamble bytes\n"); + return NULL; + } + + if (!spi_cs_is_valid(bus, cs)) { + puts("ftssp010: invalid (bus, cs)\n"); + return NULL; + } + + chip = spi_alloc_slave(struct ftssp010_spi, bus, cs); + if (!chip) + return NULL; + + if (get_spi_chip(bus, chip)) + goto free_out; + + if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) { + puts("ftssp010: Before revision 1.19.0, its clock & cs are\n" + "controlled by tx engine which is not synced with rx engine,\n" + "so the clock & cs might be shutdown before rx engine\n" + "finishs its jobs.\n" + "If possible, please add a dedicated gpio for it.\n"); + } + + chip->mode = mode; + chip->clk = CONFIG_FTSSP010_CLOCK; + chip->div = 2; + if (max_hz) { + while (chip->div < 0xffff) { + if ((chip->clk / (2 * chip->div)) <= max_hz) + break; + chip->div += 1; + } + } + chip->speed = chip->clk / (2 * chip->div); + + return &chip->slave; + +free_out: + free(chip); + return NULL; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + writel(CR1_SDL(8) | CR1_DIV(chip->div), ®s->cr[1]); + + if (chip->revision >= 0x11900) { + writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH, + ®s->cr[0]); + writel(CR2_TXFC | CR2_RXFC, + ®s->cr[2]); + } else { + writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO, + ®s->cr[0]); + writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE, + ®s->cr[2]); + } + + if (chip->mode & SPI_LOOP) + setbits_le32(®s->cr[0], CR0_LOOP); + + if (chip->mode & SPI_CPOL) + setbits_le32(®s->cr[0], CR0_SCLKPO); + + if (chip->mode & SPI_CPHA) + setbits_le32(®s->cr[0], CR0_SCLKPH); + + spi_cs_deactivate(slave); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + struct ftssp010_regs *regs = chip->regs; + + writel(0, ®s->cr[2]); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct ftssp010_spi *chip = to_ftssp010_spi(slave); + uint32_t len = bitlen >> 3; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + if (chip->revision >= 0x11900) + ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags); + else + ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags); + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c index edeb42d..77ede6b 100644 --- a/drivers/spi/sh_qspi.c +++ b/drivers/spi/sh_qspi.c @@ -10,6 +10,7 @@ #include <common.h> #include <malloc.h> #include <spi.h> +#include <asm/arch/rmobile.h> #include <asm/io.h> /* SH QSPI register bit masks <REG>_<BIT> */ @@ -170,7 +171,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } - ss->regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE; + ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE; /* Init SH QSPI */ sh_qspi_init(ss); diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c index 744afe3..7ca5e36 100644 --- a/drivers/spi/sh_spi.c +++ b/drivers/spi/sh_spi.c @@ -151,7 +151,6 @@ static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, { int i, cur_len, ret = 0; int remain = (int)len; - unsigned long tmp; if (len >= SH_SPI_FIFO_SIZE) sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); @@ -183,9 +182,7 @@ static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, } if (flags & SPI_XFER_END) { - tmp = sh_spi_read(&ss->regs->cr1); - tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); - sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1); sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); udelay(100); write_fifo_empty_wait(ss); @@ -198,16 +195,13 @@ static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data, unsigned int len, unsigned long flags) { int i; - unsigned long tmp; if (len > SH_SPI_MAX_BYTE) sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3); else sh_spi_write(len, &ss->regs->cr3); - tmp = sh_spi_read(&ss->regs->cr1); - tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); - sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1); sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); for (i = 0; i < len; i++) { diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c index 6e19db1..3acf6a1 100644 --- a/drivers/usb/gadget/fotg210.c +++ b/drivers/usb/gadget/fotg210.c @@ -245,6 +245,7 @@ static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req) if (ep->id == 0) { /* Wait until cx/ep0 fifo empty */ fotg210_cxwait(chip, CXFIFO_CXFIFOE); + udelay(1); writel(DMAFIFO_CX, ®s->dma_fifo); } else { /* Wait until epx fifo empty */ @@ -847,6 +848,13 @@ int usb_gadget_handle_interrupts(void) /* CX interrupts */ if (gisr & GISR_GRP0) { st = readl(®s->gisr0); + /* + * Write 1 and then 0 works for both W1C & RW. + * + * HW v1.11.0+: It's a W1C register (write 1 clear) + * HW v1.10.0-: It's a R/W register (write 0 clear) + */ + writel(st & GISR0_CXABORT, ®s->gisr0); writel(0, ®s->gisr0); if (st & GISR0_CXERR) @@ -873,6 +881,13 @@ int usb_gadget_handle_interrupts(void) /* Device Status Interrupts */ if (gisr & GISR_GRP2) { st = readl(®s->gisr2); + /* + * Write 1 and then 0 works for both W1C & RW. + * + * HW v1.11.0+: It's a W1C register (write 1 clear) + * HW v1.10.0-: It's a R/W register (write 0 clear) + */ + writel(st, ®s->gisr2); writel(0, ®s->gisr2); if (st & GISR2_RESET) diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 66b4de0..9356878 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -88,6 +88,8 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) /* Setup the EHCI host controller. */ static void setup_usb_phy(struct exynos_usb_phy *usb) { + u32 hsic_ctrl; + set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); @@ -112,6 +114,32 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST); + + /* HSIC Phy Setting */ + hsic_ctrl = (HSIC_CTRL_FORCESUSPEND | + HSIC_CTRL_FORCESLEEP | + HSIC_CTRL_SIDDQ); + + clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl); + + hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK) + << HSIC_CTRL_REFCLKDIV_SHIFT) + | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK) + << HSIC_CTRL_REFCLKSEL_SHIFT) + | HSIC_CTRL_UTMISWRST); + + setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); + + udelay(10); + + clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST | + HSIC_CTRL_UTMISWRST); + + clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST | + HSIC_CTRL_UTMISWRST); + udelay(20); /* EHCI Ctrl setting */ @@ -125,6 +153,8 @@ static void setup_usb_phy(struct exynos_usb_phy *usb) /* Reset the EHCI host controller. */ static void reset_usb_phy(struct exynos_usb_phy *usb) { + u32 hsic_ctrl; + /* HOST_PHY reset */ setbits_le32(&usb->usbphyctrl0, HOST_CTRL0_PHYSWRST | @@ -133,6 +163,15 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); + /* HSIC Phy reset */ + hsic_ctrl = (HSIC_CTRL_FORCESUSPEND | + HSIC_CTRL_FORCESLEEP | + HSIC_CTRL_SIDDQ | + HSIC_CTRL_PHYSWRST); + + setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); + setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); + set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); } @@ -164,6 +203,8 @@ int ehci_hcd_init(int index, enum usb_init_type init, setup_usb_phy(ctx->usb); + board_usb_init(index, init); + *hccr = ctx->hcd; *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index 73e57ea..21e9c99 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -171,7 +171,7 @@ struct ipu_cm { u32 gpr; u32 reserved0[26]; u32 ch_db_mode_sel[2]; - u32 reserved1[16]; + u32 reserved1[4]; u32 alt_ch_db_mode_sel[2]; u32 reserved2[2]; u32 ch_trb_mode_sel[2]; @@ -188,7 +188,7 @@ struct ipu_idmac { u32 sub_addr[5]; u32 bndm_en[2]; u32 sc_cord[2]; - u32 reserved[45]; + u32 reserved[44]; u32 ch_busy[2]; }; diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 7e367f3..9584d82 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -117,6 +117,10 @@ #define CONFIG_USB_EHCI_EXYNOS #define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + /* MMC SPL */ #define CONFIG_EXYNOS_SPL #define CONFIG_SPL diff --git a/include/configs/hummingboard.h b/include/configs/hummingboard.h new file mode 100644 index 0000000..4055af5 --- /dev/null +++ b/include/configs/hummingboard.h @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> + * + * Configuration settings for the SolidRun Hummingboard. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> +#include <asm/sizes.h> + +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_MACH_TYPE 4773 + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_I2C + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_MEMTEST +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Ethernet Configuration */ +#define CONFIG_FEC_MXC +#ifdef CONFIG_FEC_MXC +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +#if defined(CONFIG_MX6S) +#define CONFIG_DEFAULT_FDT_FILE "imx6dl-hummingboard.dtb" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttymxc0\0" \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x18000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "update_sd_firmware_filename=u-boot.imx\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 1024 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H * */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index f8cca5b..cc3c7a8 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -31,7 +31,16 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ + +#if defined(CONFIG_SYS_USE_BOOT_NORFLASH) #define CONFIG_CMD_FLASH +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#else +/* SPI flash boot is default. */ +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS @@ -101,7 +110,7 @@ #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ -#define CONFIG_SYS_TEXT_BASE 0x00000000 +#if defined(CONFIG_SYS_USE_BOOT_NORFLASH) #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_FLASH_CFI_DRIVER @@ -117,13 +126,28 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT 3000 #define CONFIG_SYS_FLASH_LOCK_TOUT 3000 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 - /* ENV setting */ #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SECT_SIZE (256 * 1024) #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ CONFIG_SYS_MONITOR_LEN) + +#else /* CONFIG_SYS_USE_BOOT_NORFLASH */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SPI +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_SPANSION +/* ENV setting */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_ADDR 0xC0000 + +#endif /* CONFIG_SYS_USE_BOOT_NORFLASH */ + +/* Common ENV setting */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SECT_SIZE (256 * 1024) #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) diff --git a/include/configs/lager.h b/include/configs/lager.h index 8932825..b6c1954 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -34,7 +34,15 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_FLASH + +#if defined(CONFIG_SYS_USE_BOOT_NORFLASH) +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#else +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SYS_TEXT_BASE 0xE8080000 +#endif #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS @@ -104,8 +112,8 @@ #define CONFIG_SYS_GBL_DATA_SIZE (256) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) +#if defined(CONFIG_SYS_USE_BOOT_NORFLASH) /* USE NOR FLASH */ -#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_FLASH_CFI_DRIVER @@ -124,10 +132,27 @@ /* ENV setting */ #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SECT_SIZE (256 * 1024) #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ CONFIG_SYS_MONITOR_LEN) + +#else /* CONFIG_SYS_USE_BOOT_NORFLASH */ + +/* USE SPI */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SYS_NO_FLASH + +/* ENV setting */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_ADDR 0xC0000 +#endif + +/* Common ENV setting */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SECT_SIZE (256 * 1024) #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h deleted file mode 100644 index 12667c5..0000000 --- a/include/configs/mx1ads.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * include/configs/mx1ads.h - * - * (c) Copyright 2004 - * Techware Information Technology, Inc. - * http://www.techware.com.tw/ - * - * Ming-Len Wu <minglen_wu@techware.com.tw> - * - * This is the Configuration setting for Motorola MX1ADS board - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */ -#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */ - -/* - * Select serial console configuration - */ -#define CONFIG_IMX_SERIAL -#define CONFIG_IMX_SERIAL1 /* internal uart 1 */ -/* #define _CONFIG_UART2 */ /* internal uart 2 */ -/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */ - -#define CONFIG_BOARD_LATE_INIT -#define USE_920T_MMU 1 - -#if 0 -#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ -#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ -#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ -#endif - -/* - * Size of malloc() pool - */ - -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * CS8900 Ethernet drivers - */ -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x15000300 -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -/* - * select serial console configuration - */ - -/* #define CONFIG_UART1 */ -/* #define CONFIG_UART2 1 */ - -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_ELF - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M" -#define CONFIG_BOOTFILE "mx1ads" -#define CONFIG_BOOTCOMMAND "tftp; bootm" - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#endif - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_HUSH_PARSER 1 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "MX1ADS$ " /* Monitor Command Prompt */ -#else -#define CONFIG_SYS_PROMPT "MX1ADS=> " /* Monitor Command Prompt */ -#endif - -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x09000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */ -#define CONFIG_SYS_HZ 3686400 -#define CONFIG_SYS_CPUSPEED 0x141 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ -#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_TEXT_BASE 0x10000000 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ -#define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYNCFLASH 1 -#define PHYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_SECT (16) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x00ff8000) - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x100000 - -/*----------------------------------------------------------------------- - * Enable passing ATAGS - */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 - -#define CONFIG_SYS_CLK_FREQ 16780000 -#define CONFIG_SYSPLL_CLK_FREQ 16000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 21c848f..5ee7fa5 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -95,6 +95,28 @@ #define CONFIG_LOADADDR 0x12000000 #define CONFIG_SYS_TEXT_BASE 0x17800000 +#ifdef CONFIG_SUPPORT_EMMC_BOOT +#define EMMC_ENV \ + "emmcdev=2\0" \ + "update_emmc_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "if mmc dev ${emmcdev} && " \ + "mmc open ${emmcdev} 1; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "mmc close ${emmcdev} 1; " \ + "fi; " \ + "fi\0" +#else +#define EMMC_ENV "" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "uimage=uImage\0" \ @@ -121,6 +143,7 @@ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ "fi; " \ "fi\0" \ + EMMC_ENV \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 3229bc7..4919f53 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -23,6 +23,8 @@ #endif #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + #include "mx6sabre_common.h" #define CONFIG_SYS_FSL_USDHC_NUM 3 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 7abad08..b29f78c 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -11,6 +11,7 @@ #include <asm/arch/imx-regs.h> #include <asm/sizes.h> +#include "mx6_common.h" #define CONFIG_MX6 #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 1b566c0..c58bc91 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -241,6 +241,8 @@ "setenv fdtfile omap3-beagle.dtb; fi; " \ "if test $beaglerev = Cx; then " \ "setenv fdtfile omap3-beagle.dtb; fi; " \ + "if test $beaglerev = C4; then " \ + "setenv fdtfile omap3-beagle.dtb; fi; " \ "if test $beaglerev = xMAB; then " \ "setenv fdtfile omap3-beagle-xm.dtb; fi; " \ "if test $beaglerev = xMC; then " \ diff --git a/include/configs/trats.h b/include/configs/trats.h index 6cd15c2..fdd8b46 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -27,6 +27,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 @@ -143,7 +144,10 @@ "u-boot mmc 80 400;" \ "uImage ext4 0 2;" \ "exynos4210-trats.dtb ext4 0 2;" \ - ""PARTS_ROOT" part 0 5\0" + ""PARTS_BOOT" part 0 2;" \ + ""PARTS_ROOT" part 0 5;" \ + ""PARTS_DATA" part 0 6;" \ + ""PARTS_UMS" part 0 7\0" #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_CONSOLE_INFO_QUIET diff --git a/include/configs/trats2.h b/include/configs/trats2.h index c9ce828..83633b0 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -30,6 +30,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF #define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE 0x10502000 @@ -114,6 +115,7 @@ /* USB Composite download gadget - g_dnl */ #define CONFIG_USBDOWNLOAD_GADGET #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_DFU_FUNCTION #define CONFIG_DFU_MMC @@ -173,7 +175,10 @@ "u-boot mmc 80 800;" \ "uImage ext4 0 2;" \ "exynos4412-trats2.dtb ext4 0 2;" \ - ""PARTS_ROOT" part 0 5\0" + ""PARTS_BOOT" part 0 2;" \ + ""PARTS_ROOT" part 0 5;" \ + ""PARTS_DATA" part 0 6;" \ + ""PARTS_UMS" part 0 7\0" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootk=" \ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index ce5f384..e851702 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -102,9 +102,9 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) -/* SMSC9115 Ethernet from SMSC9118 family */ -#define CONFIG_SMC9111 1 -#define CONFIG_SMC9111_BASE (0x1a000000) +/* SMSC91C111 Ethernet Configuration */ +#define CONFIG_SMC91111 1 +#define CONFIG_SMC91111_BASE (0x01A000000) /* PL011 Serial Configuration */ #define CONFIG_PL011_SERIAL diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 71a89b6..c6d4763 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -286,7 +286,7 @@ /* * Memory settings */ -#define CONFIG_SYS_MSC0_VAL 0x3ffc95fa +#define CONFIG_SYS_MSC0_VAL 0x3ffc95f9 #define CONFIG_SYS_MSC1_VAL 0x02ccf974 #define CONFIG_SYS_MSC2_VAL 0x00000000 #ifdef CONFIG_RAM_256M diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index ae8480d..3488472 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -108,7 +108,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ - "uimage=uImage\0" \ + "image=zImage\0" \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ "fdt_high=0xffffffff\0" \ @@ -140,22 +140,22 @@ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -167,19 +167,19 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ - "${get_cmd} ${uimage}; " \ + "${get_cmd} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ - "bootm; " \ + "bootz; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi; " \ "else " \ - "bootm; " \ + "bootz; " \ "fi;\0" #define CONFIG_BOOTCOMMAND \ @@ -187,7 +187,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ diff --git a/include/spi.h b/include/spi.h index aba7922..ffd6647 100644 --- a/include/spi.h +++ b/include/spi.h @@ -30,6 +30,24 @@ #define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ #define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) +#define SPI_XFER_U_PAGE (1 << 5) + +/* SPI TX operation modes */ +#define SPI_OPM_TX_QPP 1 << 0 + +/* SPI RX operation modes */ +#define SPI_OPM_RX_AS 1 << 0 +#define SPI_OPM_RX_DOUT 1 << 1 +#define SPI_OPM_RX_DIO 1 << 2 +#define SPI_OPM_RX_QOF 1 << 3 +#define SPI_OPM_RX_QIOF 1 << 4 +#define SPI_OPM_RX_EXTN SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \ + SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \ + SPI_OPM_RX_QIOF + +/* SPI bus connection options */ +#define SPI_CONN_DUAL_SHARED 1 << 0 +#define SPI_CONN_DUAL_SEPARATED 1 << 1 /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec @@ -43,17 +61,25 @@ * * @bus: ID of the bus that the slave is attached to. * @cs: ID of the chip select connected to the slave. + * @op_mode_rx: SPI RX operation mode. + * @op_mode_tx: SPI TX operation mode. * @wordlen: Size of SPI word in number of bits * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. * @memory_map: Address of read-only SPI flash access. + * @option: Varies SPI bus options - separate, shared bus. + * @flags: Indication of SPI flags. */ struct spi_slave { unsigned int bus; unsigned int cs; + u8 op_mode_rx; + u8 op_mode_tx; unsigned int wordlen; unsigned int max_write_size; void *memory_map; + u8 option; + u8 flags; }; /** diff --git a/include/spi_flash.h b/include/spi_flash.h index afc3a58..f79f0ea 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -19,11 +19,60 @@ #include <linux/types.h> #include <linux/compiler.h> +/* sf param flags */ +#define SECT_4K 1 << 1 +#define SECT_32K 1 << 2 +#define E_FSR 1 << 3 +#define WR_QPP 1 << 4 + +/* Enum list - Full read commands */ +enum spi_read_cmds { + ARRAY_SLOW = 1 << 0, + DUAL_OUTPUT_FAST = 1 << 1, + DUAL_IO_FAST = 1 << 2, + QUAD_OUTPUT_FAST = 1 << 3, + QUAD_IO_FAST = 1 << 4, +}; +#define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST +#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST + +/* Dual SPI flash memories */ +enum spi_dual_flash { + SF_SINGLE_FLASH = 0, + SF_DUAL_STACKED_FLASH = 1 << 0, + SF_DUAL_PARALLEL_FLASH = 1 << 1, +}; + +/** + * struct spi_flash_params - SPI/QSPI flash device params structure + * + * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) + * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) + * @ext_jedec: Device ext_jedec ID + * @sector_size: Sector size of this device + * @nr_sectors: No.of sectors on this device + * @e_rd_cmd: Enum list for read commands + * @flags: Importent param, for flash specific behaviour + */ +struct spi_flash_params { + const char *name; + u32 jedec; + u16 ext_jedec; + u32 sector_size; + u32 nr_sectors; + u8 e_rd_cmd; + u16 flags; +}; + +extern const struct spi_flash_params spi_flash_params_table[]; + /** * struct spi_flash - SPI flash structure * * @spi: SPI slave * @name: Name of SPI flash + * @dual_flash: Indicates dual flash memories - dual stacked, parallel + * @shift: Flash shift useful in dual parallel * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size @@ -33,6 +82,9 @@ * @bank_curr: Current flash bank * @poll_cmd: Poll cmd - for flash erase/program * @erase_cmd: Erase cmd 4K, 32K, 64K + * @read_cmd: Read cmd - Array Fast, Extn read and quad read. + * @write_cmd: Write cmd - page and quad program. + * @dummy_byte: Dummy cycles for read operation. * @memory_map: Address of read-only SPI flash access * @read: Flash read ops: Read len bytes at offset into buf * Supported cmds: Fast Array Read @@ -45,6 +97,8 @@ struct spi_flash { struct spi_slave *spi; const char *name; + u8 dual_flash; + u8 shift; u32 size; u32 page_size; @@ -57,6 +111,9 @@ struct spi_flash { #endif u8 poll_cmd; u8 erase_cmd; + u8 read_cmd; + u8 write_cmd; + u8 dummy_byte; void *memory_map; int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h index 9df3adc..058dcf1 100644 --- a/include/usb_mass_storage.h +++ b/include/usb_mass_storage.h @@ -20,6 +20,9 @@ #define UMS_NUM_SECTORS 0 #endif +/* Wait at maximum 60 seconds for cable connection */ +#define UMS_CABLE_READY_TIMEOUT 60 + struct ums { int (*read_sector)(struct ums *ums_dev, ulong start, lbaint_t blkcnt, void *buf); diff --git a/lib/lzma/LzmaTools.c b/lib/lzma/LzmaTools.c index 0aec2f9..90d31cd 100644 --- a/lib/lzma/LzmaTools.c +++ b/lib/lzma/LzmaTools.c @@ -102,7 +102,7 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize, return SZ_ERROR_OUTPUT_EOF; /* Decompress */ - outProcessed = *uncompressedSize; + outProcessed = outSizeFull; WATCHDOG_RESET(); @@ -111,6 +111,9 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize, inStream + LZMA_DATA_OFFSET, &compressedSize, inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc); *uncompressedSize = outProcessed; + + debug("LZMA: Uncompresed ................ 0x%zx\n", outProcessed); + if (res != SZ_OK) { return res; } diff --git a/spl/Makefile b/spl/Makefile index 003956e..5e5472d 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -165,7 +165,7 @@ $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin endif $(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN) - $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@ + $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O binary $< $@ GEN_UBOOT = \ cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $(__START) \ |