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-rw-r--r--CHANGELOG14
-rw-r--r--common/cmd_ace.c5
-rw-r--r--common/cmd_ide.c2
-rw-r--r--common/miiphyutil.c5
-rw-r--r--cpu/mpc8260/traps.c2
-rw-r--r--include/configs/OCOTEA.h1
-rw-r--r--include/configs/XPEDITE1K.h1
7 files changed, 23 insertions, 7 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 52e81e5..632cbb5 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,20 @@
Changes for U-Boot 1.0.2:
======================================================================
+* Patch by Stephen Williams, 19 March 2004
+ Increase speed of sector reads from SystemACE,
+ shorten poll timeout and remove a useless reset
+
+* Patch by Tolunay Orkun, 19 Mar 2004:
+ Make GigE PHY 1000Mbps Speed/Duplex detection conditional
+ (CONFIG_PHY_GIGE)
+
+* Patch by Brad Kemp, 18 Mar 2004:
+ prevent machine checks during a PCI scan
+
+* Patch by Pierre Aubert, 18 Mar 2004:
+ Fix string cleaning in IDE identification
+
* Patch by Pierre Aubert, 18 Mar 2004:
- Unify video mode handling for Chips & Technologies 69000 Video
chip and Silicon Motion SMI 712/710/810 Video chip
diff --git a/common/cmd_ace.c b/common/cmd_ace.c
index b6f8604..3512a15 100644
--- a/common/cmd_ace.c
+++ b/common/cmd_ace.c
@@ -190,16 +190,13 @@ static unsigned long systemace_read(int dev,
/* Write sector count | ReadMemCardData. */
ace_writew((trans&0xff) | 0x0300, 0x14);
- /* CONTROLREG = CFGRESET|LOCKREQ */
- ace_writew(0x0082, 0x18);
-
retry = trans * 16;
while (retry > 0) {
int idx;
/* Wait for buffer to become ready. */
while (! (ace_readw(0x04) & 0x0020)) {
- udelay(1000);
+ udelay(100);
}
/* Read 16 words of 2bytes from the sector buffer. */
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index 3bed194..842a2fd 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -1417,7 +1417,7 @@ static void ident_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
unsigned char *end, *last;
last = dst;
- end = src + len;
+ end = src + len - 1;
/* reserve space for '\0' */
if (len < 2)
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index f6436cf..919de3e 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -135,6 +135,7 @@ int miiphy_speed (unsigned char addr)
{
unsigned short reg;
+#if defined(CONFIG_PHY_GIGE)
if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
printf ("PHY 1000BT Status read failed\n");
} else {
@@ -144,6 +145,7 @@ int miiphy_speed (unsigned char addr)
}
}
}
+#endif /* CONFIG_PHY_GIGE */
if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
puts ("PHY speed1 read failed, assuming 10bT\n");
@@ -165,7 +167,7 @@ int miiphy_duplex (unsigned char addr)
{
unsigned short reg;
-
+#if defined(CONFIG_PHY_GIGE)
if (miiphy_read (addr, PHY_1000BTSR, &reg)) {
printf ("PHY 1000BT Status read failed\n");
} else {
@@ -178,6 +180,7 @@ int miiphy_duplex (unsigned char addr)
}
}
}
+#endif /* CONFIG_PHY_GIGE */
if (miiphy_read (addr, PHY_ANLPAR, &reg)) {
puts ("PHY duplex read failed, assuming half duplex\n");
diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c
index 715ef60..0c39e43 100644
--- a/cpu/mpc8260/traps.c
+++ b/cpu/mpc8260/traps.c
@@ -140,7 +140,7 @@ MachineCheckException(struct pt_regs *regs)
dump_pci();
#endif
/* clear the error in the error status register */
- if(immap->im_pci.pci_esr && cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) {
+ if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) {
immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP);
return;
}
diff --git a/include/configs/OCOTEA.h b/include/configs/OCOTEA.h
index dea8953..74e5acd 100644
--- a/include/configs/OCOTEA.h
+++ b/include/configs/OCOTEA.h
@@ -150,6 +150,7 @@
#define CONFIG_PHY2_ADDR 0x10
#define CONFIG_PHY3_ADDR 0x18
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.1.2.3
#define CONFIG_ETHADDR 00:04:AC:E3:28:8A
diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
index 4a19541..3cc4ff4 100644
--- a/include/configs/XPEDITE1K.h
+++ b/include/configs/XPEDITE1K.h
@@ -174,6 +174,7 @@ extern void out32(unsigned int, unsigned long);
#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
#define CONFIG_NET_MULTI 1
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \