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-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc58
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c6
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/config.h1
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/cpu.h4
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/soc.h4
-rw-r--r--board/freescale/ls2080a/MAINTAINERS2
-rw-r--r--board/freescale/ls2080aqds/MAINTAINERS2
-rw-r--r--board/freescale/ls2080aqds/README12
-rw-r--r--board/freescale/ls2080ardb/MAINTAINERS2
-rw-r--r--board/freescale/ls2080ardb/README8
10 files changed, 84 insertions, 15 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
index f7b949a..c7496c0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -4,6 +4,7 @@ SoC overview
2. LS2080A
3. LS1012A
4. LS1046A
+ 5. LS2088A
LS1043A
---------
@@ -169,3 +170,60 @@ The LS1046A SoC includes the following function and features:
- Two DUARTs
- Integrated flash controller (IFC) supporting NAND and NOR flash
- QorIQ platform's trust architecture 2.1
+
+LS2088A
+--------
+The LS2088A integrated multicore processor combines eight ARM Cortex-A72
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2088A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A72 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+ the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+ - Packet parsing, classification, and distribution (WRIOP)
+ - Queue and Hardware buffer management for scheduling, packet sequencing, and
+ congestion management, buffer allocation and de-allocation (QBMan)
+ - Cryptography acceleration (SEC) at up to 10 Gbps
+ - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+ - Decompression/compression acceleration (DCE) at up to 20 Gbps
+ - Accelerated I/O processing (AIOP) at up to 20 Gbps
+ - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+ - Up to eight 10 Gbps Ethernet MACs
+ - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 3.0) controllers
+ - Two high-speed USB 3.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (eSDXC/eMMC)
+ - Serial peripheral interface (SPI) controller
+ - Quad Serial Peripheral Interface (QSPI) Controller
+ - Four I2C controllers
+ - Two DUARTs
+ - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+ capabilities
+
+LS2088A SoC has 3 more similar SoC personalities
+1)LS2048A, few difference w.r.t. LS2088A:
+ a) Four 64-bit ARM v8 Cortex-A72 CPUs
+
+2)LS2084A, few difference w.r.t. LS2088A:
+ a) No AIOP
+ b) No 32-bit DDR3 SDRAM memory
+ c) 5 * 1/10G + 5 *1G WRIOP
+ d) No L2 switch
+
+3)LS2044A, few difference w.r.t. LS2084A:
+ a) Four 64-bit ARM v8 Cortex-A72 CPUs
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 5a4dd39..6c42387 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -31,8 +31,10 @@ bool soc_has_dp_ddr(void)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
- /* LS2085A has DP_DDR */
- if (SVR_SOC_VER(svr) == SVR_LS2085A)
+ /* LS2085A, LS2088A, LS2048A has DP_DDR */
+ if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
+ (SVR_SOC_VER(svr) == SVR_LS2088A) ||
+ (SVR_SOC_VER(svr) == SVR_LS2048A))
return true;
return false;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 4201e0f..6c3ba49 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -25,6 +25,7 @@
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
+#define CONFIG_FSL_TZASC_400
#endif
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index e2d96a1..a97be5c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -11,6 +11,10 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+ CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
+ CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
+ CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
+ CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 3ccacb9..78363b6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -50,6 +50,10 @@ struct cpu_type {
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100
#define SVR_LS2040A 0x870130
+#define SVR_LS2088A 0x870900
+#define SVR_LS2084A 0x870910
+#define SVR_LS2048A 0x870920
+#define SVR_LS2044A 0x870930
#define SVR_DEV_LS2080A 0x8701
diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
index c8dac99..de137ef 100644
--- a/board/freescale/ls2080a/MAINTAINERS
+++ b/board/freescale/ls2080a/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: York Sun <york.sun@nxp.com>
+M: York Sun <york.sun@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/ls2080a/
F: include/configs/ls2080a_emu.h
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 8f78b67..79877d7 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/ls2080aqds/
F: board/freescale/ls2080a/ls2080aqds.c
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index f288750..2808bd5 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -2,14 +2,14 @@ Overview
--------
The LS2080A Development System (QDS) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS2080A
-Layerscape Architecture processor. The LS2080AQDS provides validation and
-SW development platform for the Freescale LS2080A processor series, with
-a complete debugging environment.
+and LS2088A Layerscape Architecture processor. The LS2080AQDS provides
+validation and SW development platform for the Freescale LS2080A, LS2088A
+processor series, with a complete debugging environment.
-LS2080A SoC Overview
+LS2080A, LS2088A SoC Overview
--------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
-SoC overview.
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2088A SoC overview.
LS2080AQDS board Overview
-----------------------
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index a20c003..759a146 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/ls2080ardb/
F: board/freescale/ls2080a/ls2080ardb.c
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index b1613ba..0c9c574 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -1,13 +1,13 @@
Overview
--------
The LS2080A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2080A
+evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
Layerscape Architecture processor.
-LS2080A SoC Overview
+LS2080A, LS2088A SoC Overview
--------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
-SoC overview.
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2088A SoC overview.
LS2080ARDB board Overview
-----------------------
generated by cgit v0.10.2 at 2024-07-12 19:29:39 (GMT)