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-rw-r--r--CHANGELOG8
-rw-r--r--cpu/arm920t/imx/interrupts.c19
-rw-r--r--cpu/arm920t/s3c24x0/interrupts.c27
-rw-r--r--cpu/arm920t/start.S36
-rw-r--r--include/asm-arm/arch-imx/imx-regs.h6
5 files changed, 60 insertions, 36 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 39f102f..7d21583 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,14 @@
Changes for U-Boot 1.1.3:
======================================================================
+* Patch by Steven Scholz, 05 Apr 2005:
+ Use i.MX watchdog timer for reset_cpu()
+
+* Patch by Steven Scholz, 05 Apr 2005:
+ Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
+ subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
+ (now in interupts.c)
+
* Add support for MPC8220 based "sorcery" board.
* Add support for TQM8560 board.
diff --git a/cpu/arm920t/imx/interrupts.c b/cpu/arm920t/imx/interrupts.c
index 2f2e754..03ce06d 100644
--- a/cpu/arm920t/imx/interrupts.c
+++ b/cpu/arm920t/imx/interrupts.c
@@ -117,4 +117,23 @@ ulong get_tbclk (void)
return tbclk;
}
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+ /* Disable watchdog and set Time-Out field to 0 */
+ WCR = 0x00000000;
+
+ /* Write Service Sequence */
+ WSR = 0x00005555;
+ WSR = 0x0000AAAA;
+
+ /* Enable watchdog */
+ WCR = 0x00000001;
+
+ while (1);
+ /*NOTREACHED*/
+}
+
#endif /* defined (CONFIG_IMX) */
diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c
index 868621f..ba835f3 100644
--- a/cpu/arm920t/s3c24x0/interrupts.c
+++ b/cpu/arm920t/s3c24x0/interrupts.c
@@ -185,4 +185,31 @@ ulong get_tbclk (void)
return tbclk;
}
+/*
+ * reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+ S3C24X0_WATCHDOG * const watchdog;
+
+#ifdef CONFIG_TRAB
+ disable_vfd();
+#endif
+
+ watchdog = S3C24X0_GetBase_WATCHDOG();
+
+ /* Disable watchdog */
+ watchdog->WTCON = 0x0000;
+
+ /* Initialize watchdog timer count register */
+ watchdog->WTCNT = 0x0001;
+
+ /* Enable watchdog timer; assert reset at timer timeout */
+ watchdog->WTCON = 0x0021;
+
+ while(1); /* loop forever and wait for reset to happen */
+
+ /*NOTREACHED*/
+}
+
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index afe654b..74a97d5 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -433,39 +433,3 @@ fiq:
bl do_fiq
#endif
-
- .align 5
-.globl reset_cpu
-reset_cpu:
-#ifdef CONFIG_S3C2400
- bl disable_interrupts
-# ifdef CONFIG_TRAB
- bl disable_vfd
-# endif
- ldr r1, _rWTCON
- ldr r2, _rWTCNT
- /* Disable watchdog */
- mov r3, #0x0000
- str r3, [r1]
- /* Initialize watchdog timer count register */
- mov r3, #0x0001
- str r3, [r2]
- /* Enable watchdog timer; assert reset at timer timeout */
- mov r3, #0x0021
- str r3, [r1]
-_loop_forever:
- b _loop_forever
-_rWTCON:
- .word 0x15300000
-_rWTCNT:
- .word 0x15300008
-#else /* ! CONFIG_S3C2400 */
- mov ip, #0
- mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
- mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
- mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
- bic ip, ip, #0x000f @ ............wcam
- bic ip, ip, #0x2100 @ ..v....s........
- mcr p15, 0, ip, c1, c0, 0 @ ctrl register
- mov pc, r0
-#endif /* CONFIG_S3C2400 */
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index 1486b74..318de22 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -52,6 +52,12 @@
#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
+/* Watchdog Registers*/
+
+#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
+#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
+#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */
+
/* SYSCTRL Registers */
#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */