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-rw-r--r--cpu/mpc83xx/cpu_init.c261
-rw-r--r--include/configs/MPC8313ERDB.h3
-rw-r--r--include/configs/MPC8315ERDB.h3
-rw-r--r--include/configs/MPC8323ERDB.h3
-rw-r--r--include/configs/MPC832XEMDS.h3
-rw-r--r--include/configs/MPC8349EMDS.h3
-rw-r--r--include/configs/MPC8349ITX.h3
-rw-r--r--include/configs/MPC8360EMDS.h3
-rw-r--r--include/configs/MPC8360ERDK.h3
-rw-r--r--include/configs/MPC837XEMDS.h3
-rw-r--r--include/configs/MPC837XERDB.h3
-rw-r--r--include/configs/MVBLM7.h3
-rw-r--r--include/configs/SIMPC8313.h4
-rw-r--r--include/configs/TQM834x.h3
-rw-r--r--include/configs/kmeter1.h4
-rw-r--r--include/configs/sbc8349.h3
-rw-r--r--include/configs/vme8349.h3
17 files changed, 188 insertions, 123 deletions
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 5c930d3..031e8d5 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -23,8 +23,8 @@
#include <common.h>
#include <mpc83xx.h>
#include <ioports.h>
-#ifdef CONFIG_USB_EHCI_FSL
#include <asm/io.h>
+#ifdef CONFIG_USB_EHCI_FSL
#include <usb/ehci-fsl.h>
#endif
@@ -63,149 +63,163 @@ static void config_qe_ioports(void)
*/
void cpu_init_f (volatile immap_t * im)
{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
- /* Clear initial global data */
- memset ((void *) gd, 0, sizeof (gd_t));
-
- /* system performance tweaking */
-
-#ifdef CONFIG_SYS_ACR_PIPE_DEP
- /* Arbiter pipeline depth */
- im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ __be32 acr_mask =
+#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
+ (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_ACR_RPTCNT
- /* Arbiter repeat count */
- im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
+#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
+ (ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
#endif
-
+ 0;
+ __be32 acr_val =
+#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
+ (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
+ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
+#endif
+ 0;
+ __be32 spcr_mask =
+#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
+ (SPCR_OPT << SPCR_OPT_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
+ (SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
+ (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
+ (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
+#endif
+ 0;
+ __be32 spcr_val =
#ifdef CONFIG_SYS_SPCR_OPT
- /* Optimize transactions between CSB and other devices */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
- (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
+ (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SPCR_TSECEP
- /* all eTSEC's Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
- (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
+#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
+ (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SPCR_TSEC1EP
- /* TSEC1 Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
- (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
+#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
+ (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SPCR_TSEC2EP
- /* TSEC2 Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
- (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
+#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
+ (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_ENCCM
- /* Encryption clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
- (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT);
+ 0;
+ __be32 sccr_mask =
+#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
+ (SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_PCICM
- /* PCI & DMA clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
- (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
+ (SCCR_PCICM << SCCR_PCICM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_TSECCM
- /* all TSEC's clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
- (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
+ (SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC1CM
- /* TSEC1 clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
- (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+ (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC2CM
- /* TSEC2 clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
- (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+ (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC1ON
- /* TSEC1 clock switch */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
- (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
+#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
+ (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC2ON
- /* TSEC2 clock switch */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
- (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
+#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
+ (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_USBMPHCM
- /* USB MPH clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
- (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
+ (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_USBDRCM
- /* USB DR clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
- (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+ (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_SATACM
- /* SATA controller clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
- (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+ (SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#endif
+ 0;
+ __be32 sccr_val =
+#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
+ (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
#endif
+#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
+ (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
+ (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+ (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+ (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
+ (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
+ (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
+ (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+ (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+ (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#endif
+ 0;
+
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+ /* Clear initial global data */
+ memset ((void *) gd, 0, sizeof (gd_t));
+
+ /* system performance tweaking */
+ clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
+
+ clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
+
+ clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
/* RSR - Reset Status Register - clear all status (4.6.1.3) */
- gd->reset_status = im->reset.rsr;
- im->reset.rsr = ~(RSR_RES);
+ gd->reset_status = __raw_readl(&im->reset.rsr);
+ __raw_writel(~(RSR_RES), &im->reset.rsr);
/* AER - Arbiter Event Register - store status */
- gd->arbiter_event_attributes = im->arbiter.aeatr;
- gd->arbiter_event_address = im->arbiter.aeadr;
+ gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
+ gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
/*
* RMR - Reset Mode Register
* contains checkstop reset enable (4.6.1.4)
*/
- im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
-
- /* LCRR - Clock Ratio Register (10.3.1.16) */
- im->lbus.lcrr = CONFIG_SYS_LCRR;
+ __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
- /* Enable Time Base & Decrimenter ( so we will have udelay() )*/
- im->sysconf.spcr |= SPCR_TBEN;
+ /* Enable Time Base & Decrementer ( so we will have udelay() )*/
+ setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
/* System General Purpose Register */
#ifdef CONFIG_SYS_SICRH
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
- im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH;
+ __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
+ &im->sysconf.sicrh);
#else
- im->sysconf.sicrh = CONFIG_SYS_SICRH;
+ __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
#endif
#endif
#ifdef CONFIG_SYS_SICRL
- im->sysconf.sicrl = CONFIG_SYS_SICRL;
+ __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
#endif
- /* DDR control driver register */
-#ifdef CONFIG_SYS_DDRCDR
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
+#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
+ __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#endif
- /* Output buffer impedance register */
-#ifdef CONFIG_SYS_OBIR
- im->sysconf.obir = CONFIG_SYS_OBIR;
+#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
+ __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
#endif
#ifdef CONFIG_QE
@@ -308,7 +322,7 @@ void cpu_init_f (volatile immap_t * im)
/* Wait for clock to stabilize */
do {
- temp = in_be32(&ehci->control);
+ temp = __raw_readl(&ehci->control);
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
@@ -317,8 +331,41 @@ void cpu_init_f (volatile immap_t * im)
int cpu_init_r (void)
{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
#ifdef CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
+#endif
+ __be32 lcrr_mask =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+ LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
+ LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+ LCRR_CLKDIV |
+#endif
+ 0;
+ __be32 lcrr_val =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+ CONFIG_SYS_LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC
+ CONFIG_SYS_LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+ CONFIG_SYS_LCRR_CLKDIV |
+#endif
+ 0;
+
+ /* LCRR - Clock Ratio Register (10.3.1.16)
+ * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
+ */
+ clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
+ __raw_readl(&im->lbus.lcrr);
+ isync();
+
+#ifdef CONFIG_QE
qe_init(qe_base);
qe_reset();
#endif
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 76b7894..5927e76 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -216,7 +216,8 @@
/*
* Local Bus LCRR and LBCR regs
*/
-#define CONFIG_SYS_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4
+#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \
| (0xFF << LBCR_BMT_SHIFT) \
| 0xF ) /* 0x0004ff0f */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 84cc9fa..8eaff5d 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -182,7 +182,8 @@
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00040000
/*
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index c40d3d3..356586c 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -170,7 +170,8 @@
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index f16616c..f17f9c7 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -159,7 +159,8 @@
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 9b2d25a..6361c45 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -206,7 +206,8 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 3b4e344..eaa59fd 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -317,7 +317,8 @@ boards, we say we have two, but don't display a message if we find only one. */
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 62cf13b..8520155 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -185,7 +185,8 @@
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index cb0535c..6cee78a 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -177,7 +177,8 @@
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index a190a50..abeb6a2 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -220,7 +220,8 @@
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 89fafe7..7ef92f7 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -243,7 +243,8 @@
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 9835567..f8b016f 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -137,7 +137,8 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
/* LB sdram refresh timer, about 6us */
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 866ff17..f68d834 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -111,7 +111,9 @@
/*
* Local Bus LCRR and LBCR regs
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
| (0xFF << LBCR_BMT_SHIFT) \
| 0xF ) /* 0x0004ff0f */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index da08b7c..4c909e6 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -52,7 +52,8 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
/* board pre init: do not call, nothing to do */
#undef CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 79d8638..bec08da 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -170,7 +170,9 @@
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
/*
* Init Local Bus Memory Controller:
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 6f574ca..bf7cf82 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -197,7 +197,8 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 5304ec9..d0690fe 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -178,7 +178,8 @@
* External Local Bus rate is
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR 0x00000000
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */