diff options
125 files changed, 5044 insertions, 595 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 644ec02..132fa69 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-fennec.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ + rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ rk3288-tinker.dtb \ diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi index 4f44217..ca1d5ac 100644 --- a/arch/arm/dts/rk3036.dtsi +++ b/arch/arm/dts/rk3036.dtsi @@ -244,7 +244,7 @@ emmc: dwmmc@1021c000 { compatible = "rockchip,rk3288-dw-mshc"; clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; + max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts new file mode 100644 index 0000000..ccdac1c --- /dev/null +++ b/arch/arm/dts/rk3229-evb.dts @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; + +#include "rk322x.dtsi" + +/ { + model = "Rockchip RK3229 Evaluation board"; + compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; + + chosen { + stdout-path = &uart2; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + ext_gmac: ext_gmac { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc_phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&dmc { + rockchip,sdram-channel = /bits/ 8 <1 10 3 2 1 0 15 15>; + rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3 + 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4 + 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1 + 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4 + 0x0 0x924>; + rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>; + rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15 + 0 300 3 0 120>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&emmc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi new file mode 100644 index 0000000..7237da4 --- /dev/null +++ b/arch/arm/dts/rk322x.dtsi @@ -0,0 +1,710 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3228-cru.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + resets = <&cru SRST_CORE0>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + resets = <&cru SRST_CORE1>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + resets = <&cru SRST_CORE2>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + resets = <&cru SRST_CORE3>; + }; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@110f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x110f0000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + bus_intmem@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x9000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x9000>; + smp-sram@0 { + compatible = "rockchip,rk322x-smp-sram"; + reg = <0x00 0x10>; + }; + ddr_sram: ddr-sram@1000 { + compatible = "rockchip,rk322x-ddr-sram"; + reg = <0x1000 0x8000>; + }; + }; + + i2s1: i2s1@100b0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100b0000 0x4000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; + dmas = <&pdma 14>, <&pdma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + status = "disabled"; + }; + + i2s0: i2s0@100c0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100c0000 0x4000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; + dmas = <&pdma 11>, <&pdma 12>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s2: i2s2@100e0000 { + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; + reg = <0x100e0000 0x4000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; + dmas = <&pdma 0>, <&pdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + grf: syscon@11000000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3228-grf", "syscon"; + reg = <0x11000000 0x1000>; + }; + + uart0: serial@11010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11010000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@11020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11020000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@11030000 { + compatible = "snps,dw-apb-uart"; + reg = <0x11030000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + i2c0: i2c@11050000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11050000 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + i2c1: i2c@11060000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11060000 0x1000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c2: i2c@11070000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11070000 0x1000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + i2c3: i2c@11080000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11080000 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + pwm0: pwm@110b0000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0000 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + status = "disabled"; + }; + + pwm1: pwm@110b0010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0010 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + status = "disabled"; + }; + + pwm2: pwm@110b0020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0020 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + status = "disabled"; + }; + + pwm3: pwm@110b0030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x110b0030 0x10>; + #pwm-cells = <2>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + status = "disabled"; + }; + + timer: timer@110c0000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x110c0000 0x20>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xin24m>, <&cru PCLK_TIMER>; + clock-names = "timer", "pclk"; + }; + + cru: clock-controller@110e0000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3228-cru"; + reg = <0x110e0000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@11150000 { + compatible = "rockchip,rk3228-tsadc"; + reg = <0x11150000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + #thermal-sensor-cells = <0>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + + emmc: dwmmc@30020000 { + compatible = "rockchip,rk3288-dw-mshc"; + reg = <0x30020000 0x4000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <37500000>; + max-frequency = <37500000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + bus-width = <8>; + default-sample-phase = <158>; + num-slots = <1>; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + gmac: ethernet@30200000 { + compatible = "rockchip,rk3228-gmac"; + reg = <0x30200000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, + <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + resets = <&cru SRST_GMAC>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x2000>, + <0x32014000 0x2000>, + <0x32016000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3228-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@11110000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11110000 0x100>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@11120000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11120000 0x100>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@11130000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11130000 0x100>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@11140000 { + compatible = "rockchip,gpio-bank"; + reg = <0x11140000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, + <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, + <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>; + }; + + phy_pins: phy-pins { + rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>, + <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, + <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, + <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, + <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, + <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, + <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart2_cts: uart2-cts { + rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart2_rts: uart2-rts { + rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; + + dmc: dmc@11200000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3228-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,msch = <&service_msch>; + reg = <0x11200000 0x3fc + 0x12000000 0x400>; + rockchip,sram = <&ddr_sram>; + }; + + service_msch: syscon@31090000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3228-msch", "syscon"; + reg = <0x31090000 0x2000>; + }; +}; diff --git a/arch/arm/dts/rk3288-phycore-rdk.dts b/arch/arm/dts/rk3288-phycore-rdk.dts new file mode 100644 index 0000000..f2bb7b5 --- /dev/null +++ b/arch/arm/dts/rk3288-phycore-rdk.dts @@ -0,0 +1,294 @@ +/* + * Device tree file for Phytec PCM-947 carrier board + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "rk3288-phycore-som.dtsi" + +/ { + model = "Phytec RK3288 PCM-947"; + compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; + + config { + u-boot,dm-pre-reloc; + u-boot,boot0 = &emmc; + }; + + user_buttons: user-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&user_button_pins>; + + button@0 { + label = "home"; + linux,code = <KEY_HOME>; + gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + button@1 { + label = "menu"; + linux,code = <KEY_MENU>; + gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + }; + + vcc_host0_5v: usb-host0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host0_vbus_drv>; + regulator-name = "vcc_host0_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_in_otg_out>; + }; + + vcc_host1_5v: usb-host1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host1_vbus_drv>; + regulator-name = "vcc_host1_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_in_otg_out>; + }; + + vcc_otg_5v: usb-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_in_otg_out>; + }; +}; + +&dmc { + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>; +}; + +&gmac { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + touchscreen@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + }; + + adc@64 { + compatible = "maxim,max1037"; + reg = <0x64>; + }; + + i2c_rtc: rtc@68 { + compatible = "rv4162"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_rtc_int>; + interrupt-parent = <&gpio5>; + interrupts = <10 0>; + }; +}; + +&i2c3 { + status = "okay"; + + i2c_eeprom_cb: eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + u-boot,dm-pre-reloc; + + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + buttons { + user_button_pins: user-button-pins { + /* button 1 */ + rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_pull_up>, + /* button 2 */ + <8 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rv4162 { + i2c_rtc_int: i2c-rtc-int { + rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on pcm-947 board so bump up to 12 mA. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + ts_irq_pin: ts-irq-pin { + rockchip,pins = <5 15 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host0_vbus_drv: host0-vbus-drv { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host1_vbus_drv: host1-vbus-drv { + rockchip,pins = <2 0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vdd_io_sd>; + vqmmc-supply = <&vdd_io_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; + +&uart2 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi new file mode 100644 index 0000000..fd463f4 --- /dev/null +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -0,0 +1,506 @@ +/* + * Device tree file for Phytec phyCORE-RK3288 SoM + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/net/ti-dp83867.h> +#include "rk3288.dtsi" + +/ { + model = "Phytec RK3288 phyCORE"; + compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288"; + + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory { + device_type = "memory"; + reg = <0 0x8000000>; + }; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &rk818; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + io_domains: io_domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + + status = "okay"; + sdcard-supply = <&vdd_io_sd>; + flash0-supply = <&vdd_emmc_io>; + flash1-supply = <&vdd_misc_1v8>; + gpio1830-supply = <&vdd_3v3_io>; + gpio30-supply = <&vdd_3v3_io>; + bb-supply = <&vdd_3v3_io>; + dvp-supply = <&vdd_3v3_io>; + lcdc-supply = <&vdd_3v3_io>; + wifi-supply = <&vdd_3v3_io>; + audio-supply = <&vdd_3v3_io>; + }; + + leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led>; + + user { + label = "green_led"; + gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "keep"; + }; + }; + + vdd_emmc_io: vdd-emmc-io { + compatible = "regulator-fixed"; + regulator-name = "vdd_emmc_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_3v3_io>; + }; + + vdd_in_otg_out: vdd-in-otg-out { + compatible = "regulator-fixed"; + regulator-name = "vdd_in_otg_out"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_misc_1v8: vdd-misc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_misc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; + operating-points = < + /* KHz uV */ + 1800000 1400000 + 1608000 1350000 + 1512000 1300000 + 1416000 1200000 + 1200000 1100000 + 1008000 1050000 + 816000 1000000 + 696000 950000 + 600000 900000 + 408000 900000 + 312000 900000 + 216000 900000 + 126000 900000 + >; +}; + +&emmc { + status = "okay"; + u-boot,dm-pre-reloc; + + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vdd_3v3_io>; + vqmmc-supply = <&vdd_emmc_io>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins &phy_rst &phy_int>; + phy-handle = <&phy0>; + phy-supply = <&vdd_eth_2v5>; + phy-mode = "rgmii-id"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + tx_delay = <0x0>; + rx_delay = <0x0>; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + enet-phy-lane-no-swap; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; +}; + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + clock-frequency = <400000>; + + rk818: pmic@1c { + status = "okay"; + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + + vcc1-supply = <&vdd_sys>; + vcc2-supply = <&vdd_sys>; + vcc3-supply = <&vdd_sys>; + vcc4-supply = <&vdd_sys>; + boost-supply = <&vdd_in_otg_out>; + vcc6-supply = <&vdd_sys>; + vcc7-supply = <&vdd_misc_1v8>; + vcc8-supply = <&vdd_misc_1v8>; + vcc9-supply = <&vdd_3v3_io>; + vddio-supply = <&vdd_3v3_io>; + + regulators { + u-boot,dm-pre-reloc; + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_3v3_io: DCDC_REG4 { + regulator-name = "vdd_3v3_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_sys: DCDC_BOOST { + regulator-name = "vdd_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + /* vcc9 */ + vdd_sd: SWITCH_REG { + regulator-name = "vdd_sd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* vcc6 */ + vdd_eth_2v5: LDO_REG2 { + regulator-name = "vdd_eth_2v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2500000>; + }; + }; + + /* vcc7 */ + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + /* vcc8 */ + vdd_1v8_lcd_ldo: LDO_REG4 { + regulator-name = "vdd_1v8_lcd_ldo"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* vcc8 */ + vdd_1v0_lcd: LDO_REG6 { + regulator-name = "vdd_1v0_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + /* vcc7 */ + vdd_1v8_ldo: LDO_REG7 { + regulator-name = "vdd_1v8_ldo"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* vcc9 */ + vdd_io_sd: LDO_REG9 { + regulator-name = "vdd_io_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + }; + }; + + /* M24C32-D */ + i2c_eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + vdd_cpu: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1430000>; + regulator-ramp-delay = <8000>; + vin-supply = <&vdd_sys>; + }; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + emmc { + /* + * We run eMMC at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + emmc_clk: emmc-clk { + rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 1 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 2 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 3 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 4 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 5 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 6 RK_FUNC_2 &pcfg_pull_none_12ma>, + <3 7 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <4 2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + leds { + user_led: user-led { + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* Pin for switching state between sleep and non-sleep state */ + pmic_sleep: pmic-sleep { + rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8_ldo>; +}; + +&spi2 { + status = "okay"; + + serial_flash: flash@0 { + compatible = "micron,n25q128a13", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + }; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 64aa07d..da51878 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -167,7 +167,7 @@ sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; @@ -179,7 +179,7 @@ sdio0: dwmmc@ff0d0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; @@ -191,7 +191,7 @@ sdio1: dwmmc@ff0e0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; @@ -203,7 +203,7 @@ emmc: dwmmc@ff0f0000 { compatible = "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index b807bc5..8a14c65 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -14,6 +14,32 @@ chosen { stdout-path = &uart2; }; + + vcc3v3_sdmmc: sdmmc-pwren { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_otg: vcc5v0-otg-drv { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc5v0_otg"; + gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host_xhci: vcc5v0-host-xhci-drv { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc5v0_host_xhci"; + gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; }; &uart2 { @@ -52,7 +78,12 @@ status = "okay"; }; +&usb20_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + &usb_host0_xhci { - rockchip,vbus-gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + vbus-supply = <&vcc5v0_host_xhci>; status = "okay"; }; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index f18cfc2..35e02f5 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -184,6 +184,7 @@ }; grf: syscon@ff100000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; reg = <0x0 0xff100000 0x0 0x1000>; #address-cells = <1>; @@ -350,6 +351,12 @@ status = "disabled"; }; + dmc: dmc@ff400000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3328-dmc", "syscon"; + reg = <0x0 0xff400000 0x0 0x1000>; + }; + cru: clock-controller@ff440000 { compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; reg = <0x0 0xff440000 0x0 0x1000>; @@ -415,7 +422,7 @@ sdmmc: rksdmmc@ff500000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff500000 0x0 0x4000>; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; @@ -426,7 +433,7 @@ sdio: dwmmc@ff510000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff510000 0x0 0x4000>; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; @@ -438,7 +445,7 @@ emmc: rksdmmc@ff520000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff520000 0x0 0x4000>; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; @@ -460,10 +467,20 @@ status = "disabled"; }; + usb20_otg: usb@ff580000 { + compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff580000 0x0 0x40000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + hnp-srp-disable; + dr_mode = "otg"; + status = "disabled"; + }; + sdmmc_ext: rksdmmc@ff5f0000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff5f0000 0x0 0x4000>; - clock-freq-min-max = <400000 150000000>; + max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index 025dc32..9daf765 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -546,6 +546,12 @@ status = "disabled"; }; + dmc: dmc@ff610000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-dmc", "syscon"; + reg = <0x0 0xff610000 0x0 0x1000>; + }; + i2c0: i2c@ff650000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff650000 0x0 0x1000>; @@ -641,6 +647,7 @@ }; pmugrf: syscon@ff738000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-pmugrf", "syscon"; reg = <0x0 0xff738000 0x0 0x1000>; }; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index f5af75b..bff00c3 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -60,6 +60,18 @@ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; }; + vcc5v0_typec0: vcc5v0-typec0-en { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_typec0"; + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + vcc5v0_typec1: vcc5v0-typec1-en { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_typec1"; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + }; + clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -163,7 +175,7 @@ }; &dwc3_typec0 { - rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + vbus-supply = <&vcc5v0_typec0>; status = "okay"; }; @@ -176,7 +188,7 @@ }; &dwc3_typec1 { - rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + vbus-supply = <&vcc5v0_typec1>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index edf48fb..91d3193 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -16,6 +16,7 @@ chosen { stdout-path = &uart2; + u-boot,spl-boot-order = &sdhci, &sdmmc; }; backlight: backlight { @@ -590,6 +591,12 @@ status = "okay"; }; +&sdmmc { + u-boot,dm-pre-reloc; + bus-width = <4>; + status = "okay"; +}; + &sdhci { bus-width = <8>; keep-power-in-suspend; diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index b06bb6c..641df58 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -19,6 +19,7 @@ enum { ROCKCHIP_SYSCON_PMUGRF, ROCKCHIP_SYSCON_PMUSGRF, ROCKCHIP_SYSCON_CIC, + ROCKCHIP_SYSCON_MSCH, }; /* Standard Rockchip clock numbers */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h new file mode 100644 index 0000000..2a2f804 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK322X_H +#define _ASM_ARCH_CRU_RK322X_H + +#include <common.h> + +#define MHz 1000000 +#define OSC_HZ (24 * MHz) + +#define APLL_HZ (600 * MHz) +#define GPLL_HZ (594 * MHz) + +#define CORE_PERI_HZ 150000000 +#define CORE_ACLK_HZ 300000000 + +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk322x_clk_priv { + struct rk322x_cru *cru; + ulong rate; +}; + +struct rk322x_cru { + struct rk322x_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + } pll[4]; + unsigned int reserved0[4]; + unsigned int cru_mode_con; + unsigned int cru_clksel_con[35]; + unsigned int cru_clkgate_con[16]; + unsigned int cru_softrst_con[9]; + unsigned int cru_misc_con; + unsigned int reserved1[2]; + unsigned int cru_glb_cnt_th; + unsigned int reserved2[3]; + unsigned int cru_glb_rst_st; + unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1]; + unsigned int cru_sdmmc_con[2]; + unsigned int cru_sdio_con[2]; + unsigned int reserved4[2]; + unsigned int cru_emmc_con[2]; + unsigned int reserved5[4]; + unsigned int cru_glb_srst_fst_value; + unsigned int cru_glb_srst_snd_value; + unsigned int cru_pll_mask_con; +}; +check_member(rk322x_cru, cru_pll_mask_con, 0x01f8); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLLCON0*/ + PLL_BP_SHIFT = 15, + PLL_POSTDIV1_SHIFT = 12, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, + PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, + + /* PLLCON1 */ + PLL_RST_SHIFT = 14, + PLL_PD_SHIFT = 13, + PLL_PD_MASK = 1 << PLL_PD_SHIFT, + PLL_DSMPD_SHIFT = 12, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_LOCK_STATUS_SHIFT = 10, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_POSTDIV2_SHIFT = 6, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, + PLL_REFDIV_SHIFT = 0, + PLL_REFDIV_MASK = 0x3f, + + /* CRU_MODE */ + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORM, + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORM, + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORM, + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, + APLL_MODE_SLOW = 0, + APLL_MODE_NORM, + + /* CRU_CLK_SEL0_CON */ + BUS_ACLK_PLL_SEL_SHIFT = 13, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_APLL = 0, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_PLL_SEL_HDMIPLL, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, + CORE_CLK_PLL_SEL_SHIFT = 6, + CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, + CORE_CLK_PLL_SEL_APLL = 0, + CORE_CLK_PLL_SEL_GPLL, + CORE_CLK_PLL_SEL_DPLL, + CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, + + /* CRU_CLK_SEL1_CON */ + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, + CORE_ACLK_DIV_SHIFT = 4, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, + CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, + + /* CRU_CLKSEL5_CON */ + GMAC_OUT_PLL_SHIFT = 15, + GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT, + GMAC_OUT_DIV_SHIFT = 8, + GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT, + MAC_PLL_SEL_SHIFT = 7, + MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, + RMII_EXTCLK_SLE_SHIFT = 5, + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT, + RMII_EXTCLK_SEL_INT = 0, + RMII_EXTCLK_SEL_EXT, + CLK_MAC_DIV_SHIFT = 0, + CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT, + + /* CRU_CLKSEL10_CON */ + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT, + PERI_PLL_SEL_SHIFT = 10, + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, + PERI_PLL_CPLL = 0, + PERI_PLL_GPLL, + PERI_PLL_HDMIPLL, + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, + + /* CRU_CLKSEL11_CON */ + EMMC_PLL_SHIFT = 12, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, + EMMC_SEL_APLL = 0, + EMMC_SEL_DPLL, + EMMC_SEL_GPLL, + EMMC_SEL_24M, + SDIO_PLL_SHIFT = 10, + SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, + SDIO_SEL_APLL = 0, + SDIO_SEL_DPLL, + SDIO_SEL_GPLL, + SDIO_SEL_24M, + MMC0_PLL_SHIFT = 8, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, + MMC0_SEL_APLL = 0, + MMC0_SEL_DPLL, + MMC0_SEL_GPLL, + MMC0_SEL_24M, + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT, + + /* CRU_CLKSEL12_CON */ + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, + SDIO_DIV_SHIFT = 0, + SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT, + + /* CRU_CLKSEL26_CON */ + DDR_CLK_PLL_SEL_SHIFT = 8, + DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT, + DDR_CLK_SEL_DPLL = 0, + DDR_CLK_SEL_GPLL, + DDR_CLK_SEL_APLL, + DDR_DIV_SEL_SHIFT = 0, + DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT, + + /* CRU_CLKSEL27_CON */ + VOP_DCLK_DIV_SHIFT = 8, + VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT, + VOP_PLL_SEL_SHIFT = 1, + VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT, + + /* CRU_CLKSEL29_CON */ + GMAC_CLK_SRC_SHIFT = 12, + GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT, + + /* CRU_SOFTRST5_CON */ + DDRCTRL_PSRST_SHIFT = 11, + DDRCTRL_SRST_SHIFT = 10, + DDRPHY_PSRST_SHIFT = 9, + DDRPHY_SRST_SHIFT = 8, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h index 9a59075..35696c7 100644 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h @@ -441,52 +441,4 @@ enum { /* mr1 for ddr3 */ #define DDR3_DLL_DISABLE 1 -/* - *TODO(sjg@chromium.org): We use a PMU register to store SDRAM information for - * passing from SPL to U-Boot. It would probably be better to use a normal C - * structure in SRAM. - * - * sys_reg bitfield struct - * [31] row_3_4_ch1 - * [30] row_3_4_ch0 - * [29:28] chinfo - * [27] rank_ch1 - * [26:25] col_ch1 - * [24] bk_ch1 - * [23:22] cs0_row_ch1 - * [21:20] cs1_row_ch1 - * [19:18] bw_ch1 - * [17:16] dbw_ch1; - * [15:13] ddrtype - * [12] channelnum - * [11] rank_ch0 - * [10:9] col_ch0 - * [8] bk_ch0 - * [7:6] cs0_row_ch0 - * [5:4] cs1_row_ch0 - * [3:2] bw_ch0 - * [1:0] dbw_ch0 -*/ -#define SYS_REG_DDRTYPE_SHIFT 13 -#define SYS_REG_DDRTYPE_MASK 7 -#define SYS_REG_NUM_CH_SHIFT 12 -#define SYS_REG_NUM_CH_MASK 1 -#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) -#define SYS_REG_ROW_3_4_MASK 1 -#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) -#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) -#define SYS_REG_RANK_MASK 1 -#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) -#define SYS_REG_COL_MASK 3 -#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) -#define SYS_REG_BK_MASK 1 -#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) -#define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) -#define SYS_REG_CS1_ROW_MASK 3 -#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) -#define SYS_REG_BW_MASK 3 -#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) -#define SYS_REG_DBW_MASK 3 - #endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h new file mode 100644 index 0000000..26071c8 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h @@ -0,0 +1,519 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK322X_H +#define _ASM_ARCH_GRF_RK322X_H + +#include <common.h> + +struct rk322x_grf { + unsigned int gpio0a_iomux; + unsigned int gpio0b_iomux; + unsigned int gpio0c_iomux; + unsigned int gpio0d_iomux; + + unsigned int gpio1a_iomux; + unsigned int gpio1b_iomux; + unsigned int gpio1c_iomux; + unsigned int gpio1d_iomux; + + unsigned int gpio2a_iomux; + unsigned int gpio2b_iomux; + unsigned int gpio2c_iomux; + unsigned int gpio2d_iomux; + + unsigned int gpio3a_iomux; + unsigned int gpio3b_iomux; + unsigned int gpio3c_iomux; + unsigned int gpio3d_iomux; + + unsigned int reserved1[4]; + unsigned int con_iomux; + unsigned int reserved2[(0x100 - 0x50) / 4 - 1]; + unsigned int gpio0_p[4]; + unsigned int gpio1_p[4]; + unsigned int gpio2_p[4]; + unsigned int gpio3_p[4]; + unsigned int reserved3[(0x200 - 0x13c) / 4 - 1]; + unsigned int gpio0_e[4]; + unsigned int gpio1_e[4]; + unsigned int gpio2_e[4]; + unsigned int gpio3_e[4]; + unsigned int reserved4[(0x400 - 0x23c) / 4 - 1]; + unsigned int soc_con[7]; + unsigned int reserved5[(0x480 - 0x418) / 4 - 1]; + unsigned int soc_status[3]; + unsigned int chip_id; + unsigned int reserved6[(0x500 - 0x48c) / 4 - 1]; + unsigned int cpu_con[4]; + unsigned int reserved7[4]; + unsigned int cpu_status[2]; + unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1]; + unsigned int os_reg[8]; + unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1]; + unsigned int ddrc_stat; +}; +check_member(rk322x_grf, ddrc_stat, 0x604); + +struct rk322x_sgrf { + unsigned int soc_con[11]; + unsigned int busdmac_con[4]; +}; + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A7_SHIFT = 14, + GPIO0A7_MASK = 3 << GPIO0A7_SHIFT, + GPIO0A7_GPIO = 0, + GPIO0A7_I2C3_SDA, + GPIO0A7_HDMI_DDCSDA, + + GPIO0A6_SHIFT = 12, + GPIO0A6_MASK = 3 << GPIO0A6_SHIFT, + GPIO0A6_GPIO = 0, + GPIO0A6_I2C3_SCL, + GPIO0A6_HDMI_DDCSCL, + + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 3 << GPIO0A3_SHIFT, + GPIO0A3_GPIO = 0, + GPIO0A3_I2C1_SDA, + GPIO0A3_SDIO_CMD, + + GPIO0A2_SHIFT = 4, + GPIO0A2_MASK = 3 << GPIO0A2_SHIFT, + GPIO0A2_GPIO = 0, + GPIO0A2_I2C1_SCL, + + GPIO0A1_SHIFT = 2, + GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, + GPIO0A1_GPIO = 0, + GPIO0A1_I2C0_SDA, + + GPIO0A0_SHIFT = 0, + GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, + GPIO0A0_GPIO = 0, + GPIO0A0_I2C0_SCL, +}; + +/* GRF_GPIO0B_IOMUX */ +enum { + GPIO0B7_SHIFT = 14, + GPIO0B7_MASK = 3 << GPIO0B7_SHIFT, + GPIO0B7_GPIO = 0, + GPIO0B7_HDMI_HDP, + + GPIO0B6_SHIFT = 12, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, + GPIO0B6_GPIO = 0, + GPIO0B6_I2S_SDI, + GPIO0B6_SPI_CSN0, + + GPIO0B5_SHIFT = 10, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, + GPIO0B5_GPIO = 0, + GPIO0B5_I2S_SDO, + GPIO0B5_SPI_RXD, + + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, + GPIO0B3_GPIO = 0, + GPIO0B3_I2S1_LRCKRX, + GPIO0B3_SPI_TXD, + + GPIO0B1_SHIFT = 2, + GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, + GPIO0B1_GPIO = 0, + GPIO0B1_I2S_SCLK, + GPIO0B1_SPI_CLK, + + GPIO0B0_SHIFT = 0, + GPIO0B0_MASK = 3, + GPIO0B0_GPIO = 0, + GPIO0B0_I2S_MCLK, +}; + +/* GRF_GPIO0C_IOMUX */ +enum { + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, + GPIO0C4_GPIO = 0, + GPIO0C4_HDMI_CECSDA, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, + GPIO0C1_GPIO = 0, + GPIO0C1_UART0_RSTN, + GPIO0C1_CLK_OUT1, +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D6_SHIFT = 12, + GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_SDIO_PWREN, + GPIO0D6_PWM11, + + + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, + GPIO0D4_GPIO = 0, + GPIO0D4_PWM2, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, + GPIO0D3_GPIO = 0, + GPIO0D3_PWM1, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, + GPIO0D2_GPIO = 0, + GPIO0D2_PWM0, +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A7_SHIFT = 14, + GPIO1A7_MASK = 1, + GPIO1A7_GPIO = 0, + GPIO1A7_SDMMC_WRPRT, +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_SDMMC_CMD, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_SDMMC_PWREN, + + GPIO1B4_SHIFT = 8, + GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, + GPIO1B4_GPIO = 0, + GPIO1B4_SPI_CSN1, + GPIO1B4_PWM12, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, + GPIO1B3_GPIO = 0, + GPIO1B3_UART1_RSTN, + GPIO1B3_PWM13, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_UART1_SIN, + GPIO1B2_UART21_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_UART1_SOUT, + GPIO1B1_UART21_SOUT, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C7_SHIFT = 14, + GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, + GPIO1C7_GPIO = 0, + GPIO1C7_NAND_CS3, + GPIO1C7_EMMC_RSTNOUT, + + GPIO1C6_SHIFT = 12, + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, + GPIO1C6_GPIO = 0, + GPIO1C6_NAND_CS2, + GPIO1C6_EMMC_CMD, + + + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_SDMMC_D3, + GPIO1C5_JTAG_TMS, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_SDMMC_D2, + GPIO1C4_JTAG_TCK, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_SDMMC_D1, + GPIO1C3_UART2_SIN, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , + GPIO1C2_GPIO = 0, + GPIO1C2_SDMMC_D0, + GPIO1C2_UART2_SOUT, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_SDMMC_DETN, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 3 << GPIO1C0_SHIFT, + GPIO1C0_GPIO = 0, + GPIO1C0_SDMMC_CLKOUT, +}; + +/* GRF_GPIO1D_IOMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_NAND_D7, + GPIO1D7_EMMC_D7, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_NAND_D6, + GPIO1D6_EMMC_D6, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_NAND_D5, + GPIO1D5_EMMC_D5, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_NAND_D4, + GPIO1D4_EMMC_D4, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_NAND_D3, + GPIO1D3_EMMC_D3, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_NAND_D2, + GPIO1D2_EMMC_D2, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_NAND_D1, + GPIO1D1_EMMC_D1, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, + GPIO1D0_GPIO = 0, + GPIO1D0_NAND_D0, + GPIO1D0_EMMC_D0, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_NAND_DQS, + GPIO2A7_EMMC_CLKOUT, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_NAND_WP, + GPIO2A5_EMMC_PWREN, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_NAND_RDY, + GPIO2A4_EMMC_CMD, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_NAND_RDN, + GPIO2A4_SPI1_CSN1, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_NAND_WRN, + GPIO2A4_SPI1_CSN0, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_NAND_CLE, + GPIO2A1_SPI1_TXD, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_NAND_ALE, + GPIO2A0_SPI1_RXD, +}; + +/* GRF_GPIO2B_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_GMAC_RXER, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_GMAC_CLK, + GPIO2B6_MAC_LINK, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 3 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_GMAC_TXEN, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_GMAC_MDIO, + + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = 3 << GPIO2B3_SHIFT, + GPIO2B3_GPIO = 0, + GPIO2B3_GMAC_RXCLK, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 3 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_GMAC_CRS, + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = 3 << GPIO2B1_SHIFT, + GPIO2B1_GPIO = 0, + GPIO2B1_GMAC_TXCLK, + + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = 3 << GPIO2B0_SHIFT, + GPIO2B0_GPIO = 0, + GPIO2B0_GMAC_RXDV, + GPIO2B0_MAC_SPEED_IOUT, +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C7_SHIFT = 14, + GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, + GPIO2C7_GPIO = 0, + GPIO2C7_GMAC_TXD3, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 3 << GPIO2C6_SHIFT, + GPIO2C6_GPIO = 0, + GPIO2C6_GMAC_TXD2, + + GPIO2C5_SHIFT = 10, + GPIO2C5_MASK = 3 << GPIO2C5_SHIFT, + GPIO2C5_GPIO = 0, + GPIO2C5_I2C2_SCL, + GPIO2C5_GMAC_RXD2, + + GPIO2C4_SHIFT = 8, + GPIO2C4_MASK = 3 << GPIO2C4_SHIFT, + GPIO2C4_GPIO = 0, + GPIO2C4_I2C2_SDA, + GPIO2C4_GMAC_RXD3, + + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, + GPIO2C3_GPIO = 0, + GPIO2C3_GMAC_TXD0, + + GPIO2C2_SHIFT = 4, + GPIO2C2_MASK = 3 << GPIO2C2_SHIFT, + GPIO2C2_GPIO = 0, + GPIO2C2_GMAC_TXD1, + + GPIO2C1_SHIFT = 2, + GPIO2C1_MASK = 3 << GPIO2C1_SHIFT, + GPIO2C1_GPIO = 0, + GPIO2C1_GMAC_RXD0, + + GPIO2C0_SHIFT = 0, + GPIO2C0_MASK = 3 << GPIO2C0_SHIFT, + GPIO2C0_GPIO = 0, + GPIO2C0_GMAC_RXD1, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_GMAC_MDC, + + GPIO2D0_SHIFT = 0, + GPIO2D0_MASK = 3, + GPIO2D0_GPIO = 0, + GPIO2D0_GMAC_COL, +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, + GPIO3C6_GPIO = 0, + GPIO3C6_DRV_VBUS1, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, + GPIO3C5_GPIO = 0, + GPIO3C5_PWM10, + + GPIO3C1_SHIFT = 2, + GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, + GPIO3C1_GPIO = 0, + GPIO3C1_DRV_VBUS, +}; + +/* GRF_GPIO3D_IOMUX */ +enum { + GPIO3D2_SHIFT = 4, + GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, + GPIO3D2_GPIO = 0, + GPIO3D2_PWM3, +}; + +/* GRF_CON_IOMUX */ +enum { + CON_IOMUX_GMAC_SHIFT = 15, + CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT, + CON_IOMUX_UART1SEL_SHIFT = 11, + CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT, + CON_IOMUX_UART2SEL_SHIFT = 8, + CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, + CON_IOMUX_UART2SEL_2 = 0, + CON_IOMUX_UART2SEL_21, + CON_IOMUX_EMMCSEL_SHIFT = 7, + CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT, + CON_IOMUX_PWM3SEL_SHIFT = 3, + CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT, + CON_IOMUX_PWM2SEL_SHIFT = 2, + CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT, + CON_IOMUX_PWM1SEL_SHIFT = 1, + CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT, + CON_IOMUX_PWM0SEL_SHIFT = 0, + CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index fbc4a0d..818e4c5 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -283,6 +283,163 @@ enum { GPIO3C0_EMMC_CMD, }; +/* GRF_GPIO3DL_IOMUX */ +enum { + GPIO3D3_SHIFT = 12, + GPIO3D3_MASK = 7, + GPIO3D3_GPIO = 0, + GPIO3D3_FLASH1_DATA3, + GPIO3D3_HOST_DOUT3, + GPIO3D3_MAC_RXD3, + GPIO3D3_SDIO1_DATA3, + + GPIO3D2_SHIFT = 8, + GPIO3D2_MASK = 7, + GPIO3D2_GPIO = 0, + GPIO3D2_FLASH1_DATA2, + GPIO3D2_HOST_DOUT2, + GPIO3D2_MAC_RXD2, + GPIO3D2_SDIO1_DATA2, + + GPIO3D1_SHIFT = 4, + GPIO3D1_MASK = 7, + GPIO3D1_GPIO = 0, + GPIO3DL1_FLASH1_DATA1, + GPIO3D1_HOST_DOUT1, + GPIO3D1_MAC_TXD3, + GPIO3D1_SDIO1_DATA1, + + GPIO3D0_SHIFT = 0, + GPIO3D0_MASK = 7, + GPIO3D0_GPIO = 0, + GPIO3D0_FLASH1_DATA0, + GPIO3D0_HOST_DOUT0, + GPIO3D0_MAC_TXD2, + GPIO3D0_SDIO1_DATA0, +}; + +/* GRF_GPIO3HL_IOMUX */ +enum { + GPIO3D7_SHIFT = 12, + GPIO3D7_MASK = 7, + GPIO3D7_GPIO = 0, + GPIO3D7_FLASH1_DATA7, + GPIO3D7_HOST_DOUT7, + GPIO3D7_MAC_RXD1, + GPIO3D7_SDIO1_INTN, + + GPIO3D6_SHIFT = 8, + GPIO3D6_MASK = 7, + GPIO3D6_GPIO = 0, + GPIO3D6_FLASH1_DATA6, + GPIO3D6_HOST_DOUT6, + GPIO3D6_MAC_RXD0, + GPIO3D6_SDIO1_BKPWR, + + GPIO3D5_SHIFT = 4, + GPIO3D5_MASK = 7, + GPIO3D5_GPIO = 0, + GPIO3D5_FLASH1_DATA5, + GPIO3D5_HOST_DOUT5, + GPIO3D5_MAC_TXD1, + GPIO3D5_SDIO1_WRPRT, + + GPIO3D4_SHIFT = 0, + GPIO3D4_MASK = 7, + GPIO3D4_GPIO = 0, + GPIO3D4_FLASH1_DATA4, + GPIO3D4_HOST_DOUT4, + GPIO3D4_MAC_TXD0, + GPIO3D4_SDIO1_DETECTN, +}; + +/* GRF_GPIO4AL_IOMUX */ +enum { + GPIO4A3_SHIFT = 12, + GPIO4A3_MASK = 7, + GPIO4A3_GPIO = 0, + GPIO4A3_FLASH1_ALE, + GPIO4A3_HOST_DOUT9, + GPIO4A3_MAC_CLK, + GPIO4A3_FLASH0_CSN6, + + GPIO4A2_SHIFT = 8, + GPIO4A2_MASK = 7, + GPIO4A2_GPIO = 0, + GPIO4A2_FLASH1_RDN, + GPIO4A2_HOST_DOUT8, + GPIO4A2_MAC_RXER, + GPIO4A2_FLASH0_CSN5, + + GPIO4A1_SHIFT = 4, + GPIO4A1_MASK = 7, + GPIO4A1_GPIO = 0, + GPIO4A1_FLASH1_WP, + GPIO4A1_HOST_CKOUTN, + GPIO4A1_MAC_TXDV, + GPIO4A1_FLASH0_CSN4, + + GPIO4A0_SHIFT = 0, + GPIO4A0_MASK = 3, + GPIO4A0_GPIO = 0, + GPIO4A0_FLASH1_RDY, + GPIO4A0_HOST_CKOUTP, + GPIO4A0_MAC_MDC, +}; + +/* GRF_GPIO4AH_IOMUX */ +enum { + GPIO4A7_SHIFT = 12, + GPIO4A7_MASK = 7, + GPIO4A7_GPIO = 0, + GPIO4A7_FLASH1_CSN1, + GPIO4A7_HOST_DOUT13, + GPIO4A7_MAC_CSR, + GPIO4A7_SDIO1_CLKOUT, + + GPIO4A6_SHIFT = 8, + GPIO4A6_MASK = 7, + GPIO4A6_GPIO = 0, + GPIO4A6_FLASH1_CSN0, + GPIO4A6_HOST_DOUT12, + GPIO4A6_MAC_RXCLK, + GPIO4A6_SDIO1_CMD, + + GPIO4A5_SHIFT = 4, + GPIO4A5_MASK = 3, + GPIO4A5_GPIO = 0, + GPIO4A5_FLASH1_WRN, + GPIO4A5_HOST_DOUT11, + GPIO4A5_MAC_MDIO, + + GPIO4A4_SHIFT = 0, + GPIO4A4_MASK = 7, + GPIO4A4_GPIO = 0, + GPIO4A4_FLASH1_CLE, + GPIO4A4_HOST_DOUT10, + GPIO4A4_MAC_TXEN, + GPIO4A4_FLASH0_CSN7, +}; + +/* GRF_GPIO4BL_IOMUX */ +enum { + GPIO4B1_SHIFT = 4, + GPIO4B1_MASK = 7, + GPIO4B1_GPIO = 0, + GPIO4B1_FLASH1_CSN2, + GPIO4B1_HOST_DOUT15, + GPIO4B1_MAC_TXCLK, + GPIO4B1_SDIO1_PWREN, + + GPIO4B0_SHIFT = 0, + GPIO4B0_MASK = 7, + GPIO4B0_GPIO = 0, + GPIO4B0_FLASH1_DQS, + GPIO4B0_HOST_DOUT14, + GPIO4B0_MAC_COL, + GPIO4B0_FLASH1_CSN3, +}; + /* GRF_GPIO4C_IOMUX */ enum { GPIO4C7_SHIFT = 14, @@ -886,4 +1043,25 @@ enum GRF_SOC_CON8 { RK3288_DPHY_TX0_TURNREQUEST_DIS = 0, }; +/* GPIO Bias settings */ +enum GPIO_BIAS { + GPIO_BIAS_2MA = 0, + GPIO_BIAS_4MA, + GPIO_BIAS_8MA, + GPIO_BIAS_12MA, +}; + +#define GPIO_BIAS_MASK 0x3 +#define GPIO_BIAS_SHIFT(x) ((x) * 2) + +enum GPIO_PU_PD { + GPIO_PULL_NORMAL = 0, + GPIO_PULL_UP, + GPIO_PULL_DOWN, + GPIO_PULL_REPEAT, +}; + +#define GPIO_PULL_MASK 0x3 +#define GPIO_PULL_SHIFT(x) ((x) * 2) + #endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h index 3233dc3..93c4e7d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -92,8 +92,10 @@ struct rk3368_pmu_grf { u32 gpio0d_drv; u32 gpio0l_sr; u32 gpio0h_sr; + u32 reserved[(0x200 - 0x34) / 4 - 1]; + u32 os_reg[4]; }; -check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); +check_member(rk3368_pmu_grf, os_reg[3], 0x20c); /*GRF_GPIO0C_IOMUX*/ enum { diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h index 5d9a178..08ff945 100644 --- a/arch/arm/include/asm/arch-rockchip/pwm.h +++ b/arch/arm/include/asm/arch-rockchip/pwm.h @@ -10,8 +10,8 @@ struct rk3288_pwm { u32 cnt; - u32 duty_lpr; u32 period_hpr; + u32 duty_lpr; u32 ctrl; }; check_member(rk3288_pwm, ctrl, 0xc); diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h new file mode 100644 index 0000000..fec8586 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SDRAM_COMMON_H +#define _ASM_ARCH_SDRAM_COMMON_H +/* + * sys_reg bitfield struct + * [31] row_3_4_ch1 + * [30] row_3_4_ch0 + * [29:28] chinfo + * [27] rank_ch1 + * [26:25] col_ch1 + * [24] bk_ch1 + * [23:22] cs0_row_ch1 + * [21:20] cs1_row_ch1 + * [19:18] bw_ch1 + * [17:16] dbw_ch1; + * [15:13] ddrtype + * [12] channelnum + * [11] rank_ch0 + * [10:9] col_ch0 + * [8] bk_ch0 + * [7:6] cs0_row_ch0 + * [5:4] cs1_row_ch0 + * [3:2] bw_ch0 + * [1:0] dbw_ch0 +*/ +#define SYS_REG_DDRTYPE_SHIFT 13 +#define SYS_REG_DDRTYPE_MASK 7 +#define SYS_REG_NUM_CH_SHIFT 12 +#define SYS_REG_NUM_CH_MASK 1 +#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) +#define SYS_REG_ROW_3_4_MASK 1 +#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) +#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) +#define SYS_REG_RANK_MASK 1 +#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) +#define SYS_REG_COL_MASK 3 +#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) +#define SYS_REG_BK_MASK 1 +#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) +#define SYS_REG_CS0_ROW_MASK 3 +#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) +#define SYS_REG_CS1_ROW_MASK 3 +#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) +#define SYS_REG_BW_MASK 3 +#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) +#define SYS_REG_DBW_MASK 3 + +/* Get sdram size decode from reg */ +size_t rockchip_sdram_size(phys_addr_t reg); + +/* Called by U-Boot board_init_r for Rockchip SoCs */ +int dram_init(void); +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 9b2ef29..bb44c61 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -28,6 +28,19 @@ config ROCKCHIP_RK3188 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK322X + bool "Support Rockchip RK3228/RK3229" + select CPU_V7 + select SUPPORT_SPL + select SPL + select ROCKCHIP_BROM_HELPER + select DEBUG_UART_BOARD_INIT + help + The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7 @@ -111,6 +124,7 @@ config SPL_MMC_SUPPORT source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" +source "arch/arm/mach-rockchip/rk322x/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3328/Kconfig" source "arch/arm/mach-rockchip/rk3368/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 87d2019..cb8d3ef 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -12,13 +12,18 @@ obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o else ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o +obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o else obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o +obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o +ifdef CONFIG_RAM +obj-y += sdram_common.o +endif endif ifndef CONFIG_ARM64 obj-y += rk_timer.o @@ -29,6 +34,7 @@ ifndef CONFIG_TPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ endif +obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index bf2b268..26ea23b 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -60,12 +60,18 @@ int board_init(void) return 0; } +#if !CONFIG_IS_ENABLED(RAM) +/* + * When CONFIG_RAM is enabled, the dram_init() function is implemented + * in sdram_common.c. + */ int dram_init(void) { gd->ram_size = sdram_size(); return 0; } +#endif #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index ec8305c..460dd60 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -710,11 +710,12 @@ static void sdram_all_config(struct rk3036_sdram_priv *priv) os_reg = config.ddr_type << DDR_TYPE_SHIFT | 0 << DDR_CHN_CNT_SHIFT | (config.rank - 1) << DDR_RANK_CNT_SHIFT | - (config.col - 1) << DDR_COL_SHIFT | + (config.col - 9) << DDR_COL_SHIFT | (config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT | (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT | cs1_row << DDR_CS1_ROW_SHIFT | - 1 << DDR_BW_SHIFT | config.bw << DDR_DIE_BW_SHIFT; + 1 << DDR_BW_SHIFT | + (2 >> config.bw) << DDR_DIE_BW_SHIFT; writel(os_reg, &priv->grf->os_reg[1]); } diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 4be711e..3e76100 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -72,28 +72,6 @@ err: #endif } -int dram_init(void) -{ - struct ram_info ram; - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; - } - debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); - gd->ram_size = ram.size; - - return 0; -} - #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c index 946a9f1..9d8b225 100644 --- a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c @@ -22,6 +22,7 @@ #include <asm/arch/grf_rk3188.h> #include <asm/arch/pmu_rk3188.h> #include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> #include <linux/err.h> DECLARE_GLOBAL_DATA_PTR; @@ -796,49 +797,7 @@ error: printf("DRAM init failed!\n"); hang(); } -#endif /* CONFIG_SPL_BUILD */ - -size_t sdram_size_mb(struct rk3188_pmu *pmu) -{ - u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; - size_t chipsize_mb = 0; - size_t size_mb = 0; - u32 ch; - u32 sys_reg = readl(&pmu->sys_reg[2]); - u32 chans; - - chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); - - for (ch = 0; ch < chans; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & - SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & - SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & - SYS_REG_CS1_ROW_MASK); - bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK)); - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); - - if (rank > 1) - chipsize_mb += chipsize_mb >> - (cs0_row - cs1_row); - if (row_3_4) - chipsize_mb = chipsize_mb * 3 / 4; - size_mb += chipsize_mb; - } - - /* there can be no more than 2gb of memory */ - size_mb = min(size_mb, 0x80000000 >> 20); - - return size_mb; -} -#ifdef CONFIG_SPL_BUILD static int setup_sdram(struct udevice *dev) { struct dram_info *priv = dev_get_priv(dev); @@ -851,29 +810,27 @@ static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev) { #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3188_sdram_params *params = dev_get_platdata(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); int ret; /* rk3188 supports only one-channel */ params->num_channels = 1; - ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", - (u32 *)¶ms->pctl_timing, - sizeof(params->pctl_timing) / sizeof(u32)); + ret = dev_read_u32_array(dev, "rockchip,pctl-timing", + (u32 *)¶ms->pctl_timing, + sizeof(params->pctl_timing) / sizeof(u32)); if (ret) { printf("%s: Cannot read rockchip,pctl-timing\n", __func__); return -EINVAL; } - ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing", - (u32 *)¶ms->phy_timing, - sizeof(params->phy_timing) / sizeof(u32)); + ret = dev_read_u32_array(dev, "rockchip,phy-timing", + (u32 *)¶ms->phy_timing, + sizeof(params->phy_timing) / sizeof(u32)); if (ret) { printf("%s: Cannot read rockchip,phy-timing\n", __func__); return -EINVAL; } - ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", - (u32 *)¶ms->base, - sizeof(params->base) / sizeof(u32)); + ret = dev_read_u32_array(dev, "rockchip,sdram-params", + (u32 *)¶ms->base, + sizeof(params->base) / sizeof(u32)); if (ret) { printf("%s: Cannot read rockchip,sdram-params\n", __func__); return -EINVAL; @@ -915,12 +872,15 @@ static int rk3188_dmc_probe(struct udevice *dev) { #ifdef CONFIG_SPL_BUILD struct rk3188_sdram_params *plat = dev_get_platdata(dev); -#endif - struct dram_info *priv = dev_get_priv(dev); struct regmap *map; - int ret; struct udevice *dev_clk; + int ret; +#endif + struct dram_info *priv = dev_get_priv(dev); + + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); +#ifdef CONFIG_SPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = conv_of_platdata(dev); if (ret) @@ -932,12 +892,9 @@ static int rk3188_dmc_probe(struct udevice *dev) priv->chan[0].msch = regmap_get_range(map, 0); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); -#ifdef CONFIG_SPL_BUILD priv->chan[0].pctl = regmap_get_range(plat->map, 0); priv->chan[0].publ = regmap_get_range(plat->map, 1); -#endif ret = rockchip_get_clk(&dev_clk); if (ret) @@ -950,13 +907,14 @@ static int rk3188_dmc_probe(struct udevice *dev) priv->cru = rockchip_get_cru(); if (IS_ERR(priv->cru)) return PTR_ERR(priv->cru); -#ifdef CONFIG_SPL_BUILD ret = setup_sdram(dev); if (ret) return ret; -#endif +#else priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = sdram_size_mb(priv->pmu) << 20; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->pmu->sys_reg[2]); +#endif return 0; } diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c new file mode 100644 index 0000000..15216c7 --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/bootrom.h> +#include <asm/arch/cru_rk322x.h> +#include <asm/arch/grf_rk322x.h> +#include <asm/arch/hardware.h> +#include <asm/arch/timer.h> +#include <asm/arch/uart.h> + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} +DECLARE_GLOBAL_DATA_PTR; + +#define GRF_BASE 0x11000000 +#define SGRF_BASE 0x10140000 + +#define DEBUG_UART_BASE 0x11030000 + +void board_debug_uart_init(void) +{ +static struct rk322x_grf * const grf = (void *)GRF_BASE; + /* Enable early UART2 channel 1 on the RK322x */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->con_iomux, + CON_IOMUX_UART2SEL_MASK, + CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); +} +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("SPL Init"); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + rockchip_timer_init(); + printf("timer init done\n"); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } + +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) + back_to_bootrom(); +#endif +} diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c new file mode 100644 index 0000000..b6543a5 --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <ram.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <asm/arch/grf_rk322x.h> +#include <asm/arch/boot_mode.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GRF_BASE 0x11000000 + +static void setup_boot_mode(void) +{ + struct rk322x_grf *const grf = (void *)GRF_BASE; + int boot_mode = readl(&grf->os_reg[4]); + + debug("boot mode %x.\n", boot_mode); + + /* Clear boot mode */ + writel(BOOT_NORMAL, &grf->os_reg[4]); + + switch (boot_mode) { + case BOOT_FASTBOOT: + printf("enter fastboot!\n"); + setenv("preboot", "setenv preboot; fastboot usb0"); + break; + case BOOT_UMS: + printf("enter UMS!\n"); + setenv("preboot", "setenv preboot; ums mmc 0"); + break; + } +} + +__weak int rk_board_late_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + setup_boot_mode(); + + return rk_board_late_init(); +} + +int board_init(void) +{ +#include <asm/arch/grf_rk322x.h> + /* Enable early UART2 channel 1 on the RK322x */ +#define GRF_BASE 0x11000000 + struct rk322x_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->con_iomux, + CON_IOMUX_UART2SEL_MASK, + CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); + + return 0; +} + +int dram_init_banksize(void) +{ + /* Reserve 0x200000 for OPTEE */ + gd->bd->bi_dram[0].start = 0x60000000; + gd->bd->bi_dram[0].size = 0x8400000; + gd->bd->bi_dram[1].start = 0x6a400000; + gd->bd->bi_dram[1].size = gd->ram_size - gd->bd->bi_dram[1].start; + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rk322x_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-usb"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3288-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&rk322x_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig new file mode 100644 index 0000000..dc8071e --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -0,0 +1,18 @@ +if ROCKCHIP_RK322X + +config TARGET_EVB_RK3229 + bool "EVB_RK3229" + select BOARD_LATE_INIT + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x400 + +config SPL_SERIAL_SUPPORT + default y + +source "board/rockchip/evb_rk3229/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk322x/Makefile b/arch/arm/mach-rockchip/rk322x/Makefile new file mode 100644 index 0000000..ecb3e8d --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2017 Rockchip Electronics Co., Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + + +obj-y += clk_rk322x.o +obj-y += syscon_rk322x.o diff --git a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c new file mode 100644 index 0000000..ef25696 --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk322x.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk322x_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk322x_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c new file mode 100644 index 0000000..1b11b8c --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk322x_syscon_ids[] = { + { .compatible = "rockchip,rk3228-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3228-msch", .data = ROCKCHIP_SYSCON_MSCH }, + { } +}; + +U_BOOT_DRIVER(syscon_rk322x) = { + .name = "rk322x_syscon", + .id = UCLASS_SYSCON, + .of_match = rk322x_syscon_ids, +}; diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 8ca6b1e..5668fd2 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -8,6 +8,7 @@ #include <debug_uart.h> #include <dm.h> #include <fdtdec.h> +#include <i2c.h> #include <led.h> #include <malloc.h> #include <ram.h> @@ -25,6 +26,7 @@ #include <dm/test.h> #include <dm/util.h> #include <power/regulator.h> +#include <power/rk8xx_pmic.h> DECLARE_GLOBAL_DATA_PTR; @@ -157,6 +159,32 @@ static int configure_emmc(struct udevice *pinctrl) } #endif +#if !defined(CONFIG_SPL_OF_PLATDATA) +static int phycore_init(void) +{ + struct udevice *pmic; + int ret; + + ret = uclass_first_device_err(UCLASS_PMIC, &pmic); + if (ret) + return ret; + +#if defined(CONFIG_SPL_POWER_SUPPORT) + /* Increase USB input current to 2A */ + ret = rk818_spl_configure_usb_input_current(pmic, 2000); + if (ret) + return ret; + + /* Close charger when USB lower then 3.26V */ + ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000); + if (ret) + return ret; +#endif + + return 0; +} +#endif + void board_init_f(ulong dummy) { struct udevice *pinctrl; @@ -203,6 +231,18 @@ void board_init_f(ulong dummy) debug("Pinctrl init failed: %d\n", ret); return; } + +#if !defined(CONFIG_SPL_OF_PLATDATA) + if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { + ret = phycore_init(); + if (ret) { + debug("Failed to set up phycore power settings: %d\n", + ret); + return; + } + } +#endif + debug("\nspl:init dram\n"); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index a354d99..613967c 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -157,28 +157,6 @@ err: #endif } -int dram_init(void) -{ - struct ram_info ram; - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; - } - debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); - gd->ram_size = ram.size; - - return 0; -} - #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 8e7355e..53cc9a0 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -66,6 +66,14 @@ config TARGET_MIQI_RK3288 has 1 or 2 GiB SDRAM. Expansion connectors provide access to I2C, SPI, UART, GPIOs and fan control. +config TARGET_PHYCORE_RK3288 + bool "phyCORE-RK3288" + select BOARD_LATE_INIT + help + Add basic support for the PCM-947 carrier board, a RK3288 based + development board made by PHYTEC. This board works in a combination + with the phyCORE-RK3288 System on Module. + config TARGET_POPMETAL_RK3288 bool "PopMetal-RK3288" select BOARD_LATE_INIT @@ -129,6 +137,8 @@ source "board/google/veyron/Kconfig" source "board/mqmaker/miqi_rk3288/Kconfig" +source "board/phytec/phycore_rk3288/Kconfig" + source "board/radxa/rock2/Kconfig" source "board/rockchip/evb_rk3288/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index 2feda61..95efb11 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -22,6 +22,7 @@ #include <asm/arch/grf_rk3288.h> #include <asm/arch/pmu_rk3288.h> #include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> #include <linux/err.h> #include <power/regulator.h> #include <power/rk8xx_pmic.h> @@ -923,53 +924,7 @@ error: printf("DRAM init failed!\n"); hang(); } -#endif /* CONFIG_SPL_BUILD */ - -size_t sdram_size_mb(struct rk3288_pmu *pmu) -{ - u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; - size_t chipsize_mb = 0; - size_t size_mb = 0; - u32 ch; - u32 sys_reg = readl(&pmu->sys_reg[2]); - u32 chans; - - chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); - - for (ch = 0; ch < chans; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & - SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & - SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & - SYS_REG_CS1_ROW_MASK); - bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK)); - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); - - if (rank > 1) - chipsize_mb += chipsize_mb >> - (cs0_row - cs1_row); - if (row_3_4) - chipsize_mb = chipsize_mb * 3 / 4; - size_mb += chipsize_mb; - } - - /* - * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff - * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is - * inaccessible for some IP controller. - */ - size_mb = min(size_mb, 0xfe000000 >> 20); - return size_mb; -} - -#ifdef CONFIG_SPL_BUILD # ifdef CONFIG_ROCKCHIP_FAST_SPL static int veyron_init(struct dram_info *priv) { @@ -1018,29 +973,27 @@ static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev) { #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3288_sdram_params *params = dev_get_platdata(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); int ret; /* Rk3288 supports dual-channel, set default channel num to 2 */ params->num_channels = 2; - ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", - (u32 *)¶ms->pctl_timing, - sizeof(params->pctl_timing) / sizeof(u32)); + ret = dev_read_u32_array(dev, "rockchip,pctl-timing", + (u32 *)¶ms->pctl_timing, + sizeof(params->pctl_timing) / sizeof(u32)); if (ret) { debug("%s: Cannot read rockchip,pctl-timing\n", __func__); return -EINVAL; } - ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing", - (u32 *)¶ms->phy_timing, - sizeof(params->phy_timing) / sizeof(u32)); + ret = dev_read_u32_array(dev, "rockchip,phy-timing", + (u32 *)¶ms->phy_timing, + sizeof(params->phy_timing) / sizeof(u32)); if (ret) { debug("%s: Cannot read rockchip,phy-timing\n", __func__); return -EINVAL; } - ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", - (u32 *)¶ms->base, - sizeof(params->base) / sizeof(u32)); + ret = dev_read_u32_array(dev, "rockchip,sdram-params", + (u32 *)¶ms->base, + sizeof(params->base) / sizeof(u32)); if (ret) { debug("%s: Cannot read rockchip,sdram-params\n", __func__); return -EINVAL; @@ -1087,12 +1040,14 @@ static int rk3288_dmc_probe(struct udevice *dev) { #ifdef CONFIG_SPL_BUILD struct rk3288_sdram_params *plat = dev_get_platdata(dev); -#endif - struct dram_info *priv = dev_get_priv(dev); + struct udevice *dev_clk; struct regmap *map; int ret; - struct udevice *dev_clk; +#endif + struct dram_info *priv = dev_get_priv(dev); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); +#ifdef CONFIG_SPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = conv_of_platdata(dev); if (ret) @@ -1107,14 +1062,12 @@ static int rk3288_dmc_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); - priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); -#ifdef CONFIG_SPL_BUILD priv->chan[0].pctl = regmap_get_range(plat->map, 0); priv->chan[0].publ = regmap_get_range(plat->map, 1); priv->chan[1].pctl = regmap_get_range(plat->map, 2); priv->chan[1].publ = regmap_get_range(plat->map, 3); -#endif + ret = rockchip_get_clk(&dev_clk); if (ret) return ret; @@ -1126,13 +1079,14 @@ static int rk3288_dmc_probe(struct udevice *dev) priv->cru = rockchip_get_cru(); if (IS_ERR(priv->cru)) return PTR_ERR(priv->cru); -#ifdef CONFIG_SPL_BUILD ret = setup_sdram(dev); if (ret) return ret; +#else + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->pmu->sys_reg[2]); #endif - priv->info.base = 0; - priv->info.size = sdram_size_mb(priv->pmu) << 20; return 0; } diff --git a/arch/arm/mach-rockchip/rk3328/Makefile b/arch/arm/mach-rockchip/rk3328/Makefile index bbab036..72873e2 100644 --- a/arch/arm/mach-rockchip/rk3328/Makefile +++ b/arch/arm/mach-rockchip/rk3328/Makefile @@ -6,4 +6,5 @@ obj-y += clk_rk3328.o obj-y += rk3328.o +obj-y += sdram_rk3328.o obj-y += syscon_rk3328.o diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index 857f014..6764494 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -9,17 +9,19 @@ #include <asm/armv8/mmu.h> #include <asm/io.h> +DECLARE_GLOBAL_DATA_PTR; + static struct mm_region rk3328_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, - .size = 0x80000000UL, + .size = 0xff000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .virt = 0xf0000000UL, - .phys = 0xf0000000UL, - .size = 0x10000000UL, + .virt = 0xff000000UL, + .phys = 0xff000000UL, + .size = 0x1000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -31,6 +33,17 @@ static struct mm_region rk3328_mem_map[] = { struct mm_region *mem_map = rk3328_mem_map; +int dram_init_banksize(void) +{ + size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); + + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; + + return 0; +} + int arch_cpu_init(void) { /* We do some SoC one time setting here. */ diff --git a/arch/arm/mach-rockchip/rk3328/sdram_rk3328.c b/arch/arm/mach-rockchip/rk3328/sdram_rk3328.c new file mode 100644 index 0000000..9637a35 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328/sdram_rk3328.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <ram.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3328.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR; +struct dram_info { + struct ram_info info; + struct rk3328_grf_regs *grf; +}; + +static int rk3328_dmc_probe(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->grf->os_reg[2]); + + return 0; +} + +static int rk3328_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3328_dmc_ops = { + .get_info = rk3328_dmc_get_info, +}; + + +static const struct udevice_id rk3328_dmc_ids[] = { + { .compatible = "rockchip,rk3328-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3328) = { + .name = "rockchip_rk3328_dmc", + .id = UCLASS_RAM, + .of_match = rk3328_dmc_ids, + .ops = &rk3328_dmc_ops, + .probe = rk3328_dmc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), +}; diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile index 46798c2..0390716 100644 --- a/arch/arm/mach-rockchip/rk3368/Makefile +++ b/arch/arm/mach-rockchip/rk3368/Makefile @@ -5,4 +5,5 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o +obj-y += sdram_rk3368.o obj-y += syscon_rk3368.o diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index fb829a4..f62d91d 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -13,6 +13,8 @@ #include <asm/arch/grf_rk3368.h> #include <syscon.h> +DECLARE_GLOBAL_DATA_PTR; + #define IMEM_BASE 0xFF8C0000 /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */ @@ -50,6 +52,17 @@ static struct mm_region rk3368_mem_map[] = { struct mm_region *mem_map = rk3368_mem_map; +int dram_init_banksize(void) +{ + size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); + + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; + + return 0; +} + #ifdef CONFIG_ARCH_EARLY_INIT_R static int mcu_init(void) { diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c new file mode 100644 index 0000000..d0d0900 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <ram.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/sdram_common.h> + +DECLARE_GLOBAL_DATA_PTR; +struct dram_info { + struct ram_info info; + struct rk3368_pmu_grf *pmugrf; +}; + +static int rk3368_dmc_probe(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + debug("%s: grf=%p\n", __func__, priv->pmugrf); + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->pmugrf->os_reg[2]); + + return 0; +} + +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible = "rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3368) = { + .name = "rockchip_rk3368_dmc", + .id = UCLASS_RAM, + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), +}; diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index a621a6f..dbc248f 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -9,6 +9,8 @@ #include <asm/io.h> #include <asm/arch/hardware.h> +DECLARE_GLOBAL_DATA_PTR; + #define GRF_EMMCCORE_CON11 0xff77f02c static struct mm_region rk3399_mem_map[] = { @@ -33,6 +35,17 @@ static struct mm_region rk3399_mem_map[] = { struct mm_region *mem_map = rk3399_mem_map; +int dram_init_banksize(void) +{ + size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); + + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; + + return 0; +} + int arch_cpu_init(void) { /* We do some SoC one time setting here. */ diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c index 1b91bb1..63342ab 100644 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -15,6 +15,7 @@ #include <syscon.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/sdram_common.h> #include <asm/arch/sdram_rk3399.h> #include <asm/arch/cru_rk3399.h> #include <asm/arch/grf_rk3399.h> @@ -43,50 +44,6 @@ struct dram_info { struct rk3399_pmugrf_regs *pmugrf; }; -/* - * sys_reg bitfield struct - * [31] row_3_4_ch1 - * [30] row_3_4_ch0 - * [29:28] chinfo - * [27] rank_ch1 - * [26:25] col_ch1 - * [24] bk_ch1 - * [23:22] cs0_row_ch1 - * [21:20] cs1_row_ch1 - * [19:18] bw_ch1 - * [17:16] dbw_ch1; - * [15:13] ddrtype - * [12] channelnum - * [11] rank_ch0 - * [10:9] col_ch0 - * [8] bk_ch0 - * [7:6] cs0_row_ch0 - * [5:4] cs1_row_ch0 - * [3:2] bw_ch0 - * [1:0] dbw_ch0 -*/ -#define SYS_REG_DDRTYPE_SHIFT 13 -#define SYS_REG_DDRTYPE_MASK 7 -#define SYS_REG_NUM_CH_SHIFT 12 -#define SYS_REG_NUM_CH_MASK 1 -#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) -#define SYS_REG_ROW_3_4_MASK 1 -#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) -#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) -#define SYS_REG_RANK_MASK 1 -#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) -#define SYS_REG_COL_MASK 3 -#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) -#define SYS_REG_BK_MASK 1 -#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) -#define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) -#define SYS_REG_CS1_ROW_MASK 3 -#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) -#define SYS_REG_BW_MASK 3 -#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) -#define SYS_REG_DBW_MASK 3 - #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) @@ -1132,13 +1089,11 @@ static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev) { #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_dmc_plat *plat = dev_get_platdata(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); int ret; - ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", - (u32 *)&plat->sdram_params, - sizeof(plat->sdram_params) / sizeof(u32)); + ret = dev_read_u32_array(dev, "rockchip,sdram-params", + (u32 *)&plat->sdram_params, + sizeof(plat->sdram_params) / sizeof(u32)); if (ret) { printf("%s: Cannot read rockchip,sdram-params %d\n", __func__, ret); @@ -1231,50 +1186,6 @@ static int rk3399_dmc_init(struct udevice *dev) } #endif -size_t sdram_size_mb(struct dram_info *dram) -{ - u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; - size_t chipsize_mb = 0; - size_t size_mb = 0; - u32 ch; - - u32 sys_reg = readl(&dram->pmugrf->os_reg2); - u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) - & SYS_REG_NUM_CH_MASK); - - for (ch = 0; ch < ch_num; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & - SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & - SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & - SYS_REG_CS1_ROW_MASK); - bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK)); - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; - - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); - - if (rank > 1) - chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); - if (row_3_4) - chipsize_mb = chipsize_mb * 3 / 4; - size_mb += chipsize_mb; - } - - /* - * we use the 0x00000000~0xf7ffffff space - * since 0xf8000000~0xffffffff is soc register space - * so we reserve it - */ - size_mb = min_t(size_t, size_mb, 0xf8000000/(1<<20)); - - return size_mb; -} - static int rk3399_dmc_probe(struct udevice *dev) { #ifdef CONFIG_SPL_BUILD @@ -1285,8 +1196,9 @@ static int rk3399_dmc_probe(struct udevice *dev) priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); - priv->info.base = 0; - priv->info.size = sdram_size_mb(priv) << 20; + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->pmugrf->os_reg2); #endif return 0; } diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c new file mode 100644 index 0000000..76dbdc8 --- /dev/null +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <ram.h> +#include <asm/io.h> +#include <asm/arch/sdram_common.h> +#include <dm/uclass-internal.h> + +DECLARE_GLOBAL_DATA_PTR; +size_t rockchip_sdram_size(phys_addr_t reg) +{ + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; + size_t chipsize_mb = 0; + size_t size_mb = 0; + u32 ch; + + u32 sys_reg = readl(reg); + u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) + & SYS_REG_NUM_CH_MASK); + + debug("%s %x %x\n", __func__, (u32)reg, sys_reg); + for (ch = 0; ch < ch_num; ch++) { + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & + SYS_REG_RANK_MASK); + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK); + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK); + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & + SYS_REG_ROW_3_4_MASK; + + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + + if (rank > 1) + chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); + if (row_3_4) + chipsize_mb = chipsize_mb * 3 / 4; + size_mb += chipsize_mb; + debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", + rank, col, bk, cs0_row, bw, row_3_4); + } + + return (size_t)size_mb << 20; +} + +int dram_init(void) +{ + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + ret = ram_get_info(dev, &ram); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return ret; + } + gd->ram_size = ram.size; + debug("SDRAM base=%lx, size=%lx\n", + (unsigned long)ram.base, (unsigned long)ram.size); + + return 0; +} + +ulong board_get_usable_ram_top(ulong total_size) +{ + unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + + return (gd->ram_top > top) ? top : gd->ram_top; +} diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c index 75d121d..88b67f9 100644 --- a/board/geekbuying/geekbox/geekbox.c +++ b/board/geekbuying/geekbox/geekbox.c @@ -12,17 +12,3 @@ int board_init(void) { return 0; } - -int dram_init(void) -{ - gd->ram_size = 0x80000000; - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = 0x80000000; - - return 0; -} diff --git a/board/phytec/phycore_rk3288/Kconfig b/board/phytec/phycore_rk3288/Kconfig new file mode 100644 index 0000000..57cd8e2 --- /dev/null +++ b/board/phytec/phycore_rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PHYCORE_RK3288 + +config SYS_BOARD + default "phycore_rk3288" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/phytec/phycore_rk3288/MAINTAINERS b/board/phytec/phycore_rk3288/MAINTAINERS new file mode 100644 index 0000000..9c0de3c --- /dev/null +++ b/board/phytec/phycore_rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +phyCORE-RK3288 +M: Wadim Egorov <w.egorov@phytec.de> +S: Maintained +F: board/phytec/phycore_rk3288 +F: include/configs/phycore_rk3288.h +F: configs/phycore-rk3288_defconfig diff --git a/board/phytec/phycore_rk3288/Makefile b/board/phytec/phycore_rk3288/Makefile new file mode 100644 index 0000000..f379fbe --- /dev/null +++ b/board/phytec/phycore_rk3288/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 PHYTEC Messtechnik GmbH +# Author: Wadim Egorov <w.egorov@phytec.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += phycore-rk3288.o diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c new file mode 100644 index 0000000..20696f6 --- /dev/null +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -0,0 +1,8 @@ +/* + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c index 54e62db..6dca1fc 100644 --- a/board/rockchip/evb_px5/evb-px5.c +++ b/board/rockchip/evb_px5/evb-px5.c @@ -33,19 +33,3 @@ int board_init(void) { return 0; } - -int dram_init(void) -{ - gd->ram_size = 0x40000000; - - return 0; -} - -int dram_init_banksize(void) -{ - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = 0x3fe00000; - - return 0; -} diff --git a/board/rockchip/evb_rk3229/Kconfig b/board/rockchip/evb_rk3229/Kconfig new file mode 100644 index 0000000..361dcb1 --- /dev/null +++ b/board/rockchip/evb_rk3229/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3229 + +config SYS_BOARD + default "evb_rk3229" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3229" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rk3229/MAINTAINERS b/board/rockchip/evb_rk3229/MAINTAINERS new file mode 100644 index 0000000..dfa1090 --- /dev/null +++ b/board/rockchip/evb_rk3229/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3229 +M: Kever Yang <kever.yang@rock-chips.com> +S: Maintained +F: board/rockchip/evb_rk3229 +F: include/configs/evb_rk3229.h +F: configs/evb-rk3229_defconfig diff --git a/board/rockchip/evb_rk3229/Makefile b/board/rockchip/evb_rk3229/Makefile new file mode 100644 index 0000000..65dcd8b --- /dev/null +++ b/board/rockchip/evb_rk3229/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rk3229.o diff --git a/board/rockchip/evb_rk3229/evb_rk3229.c b/board/rockchip/evb_rk3229/evb_rk3229.c new file mode 100644 index 0000000..a9a3a40 --- /dev/null +++ b/board/rockchip/evb_rk3229/evb_rk3229.c @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/uart.h> + +DECLARE_GLOBAL_DATA_PTR; diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c index 0a26ed5..99a73da 100644 --- a/board/rockchip/evb_rk3328/evb-rk3328.c +++ b/board/rockchip/evb_rk3328/evb-rk3328.c @@ -7,31 +7,65 @@ #include <common.h> #include <asm/armv8/mmu.h> #include <dwc3-uboot.h> +#include <power/regulator.h> #include <usb.h> DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - return 0; -} + int ret; -int dram_init(void) -{ - gd->ram_size = 0x80000000; - return 0; + ret = regulators_enable_boot_on(false); + if (ret) + debug("%s: Cannot enable boot on regulator\n", __func__); + + return ret; } -int dram_init_banksize(void) +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rk3328_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) { - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = 0x7e000000; + int node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; - return 0; + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3328-usb"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3328-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + + rk3328_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&rk3328_otg_data); } -int board_usb_init(int index, enum usb_init_type init) +int board_usb_cleanup(int index, enum usb_init_type init) { return 0; } +#endif diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index f63f003..d50c59d 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -67,34 +67,3 @@ int board_init(void) out: return 0; } - -int dram_init(void) -{ - struct ram_info ram; - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; - } - debug("SDRAM base=%llx, size=%x\n", ram.base, (unsigned int)ram.size); - gd->ram_size = ram.size; - - return 0; -} - -int dram_init_banksize(void) -{ - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = 0x7e000000; - - return 0; -} diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c index df1fd9d..17adb02 100644 --- a/board/rockchip/sheep_rk3368/sheep_rk3368.c +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c @@ -20,18 +20,3 @@ int board_init(void) { return 0; } - -int dram_init(void) -{ - gd->ram_size = 0x80000000; - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = 0x7fe00000; - - return 0; -} diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 6fff3e1..36e9cd7 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -180,34 +180,3 @@ void get_board_serial(struct tag_serialnr *serialnr) serialnr->low = (u32)(serial & 0xffffffff); } #endif - -int dram_init(void) -{ - struct ram_info ram; - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; - } - debug("SDRAM base=%llx, size=%x\n", ram.base, (unsigned int)ram.size); - gd->ram_size = ram.size; - - return 0; -} - -int dram_init_banksize(void) -{ - /* Reserve 0x200000 for ATF bl31 */ - gd->bd->bi_dram[0].start = 0x200000; - gd->bd->bi_dram[0].size = 0x7e000000; - - return 0; -} diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index c60d175..321ef71 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -30,7 +30,6 @@ CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3036=y -CONFIG_RAM=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DEBUG_UART_BASE=0x20068000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig new file mode 100644 index 0000000..0c3b6f7 --- /dev/null +++ b/configs/evb-rk3229_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_ROCKCHIP_RK322X=y +CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_TARGET_EVB_RK3229=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200 +CONFIG_FASTBOOT=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK322X=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x11030000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 1384e87..aabc8a4 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -31,12 +31,28 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_RK=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_G_DNL_MANUFACTURER="Rockchip" +CONFIG_G_DNL_VENDOR_NUM=0x2207 +CONFIG_G_DNL_PRODUCT_NUM=0x330a +CONFIG_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_BUF_ADDR=0x00800800 +CONFIG_FASTBOOT_BUF_SIZE=0x08000000 CONFIG_USE_TINY_PRINTF=y CONFIG_ERRNO_STR=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 1c404e5..8d14791 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -26,7 +26,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RV1108=y -CONFIG_RAM=y CONFIG_BAUDRATE=1500000 # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DEBUG_UART_BASE=0x10210000 diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index aacf808..3a51da8 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -62,6 +62,7 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 6190024..6f093f4 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -65,6 +65,7 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 5c2d925..04fb3b7 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -23,7 +23,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_OF_PLATDATA=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y @@ -33,6 +32,7 @@ CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_DM_ETH=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 20e3e98..88d5853 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_CACHE=y CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_FAT_WRITE=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index ba65bc9..715e4b2 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -31,9 +31,9 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3036=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_RAM=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index ffb68f7..c6bfa1e 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -62,6 +62,7 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig new file mode 100644 index 0000000..823db06 --- /dev/null +++ b/configs/phycore-rk3288_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_TARGET_PHYCORE_RK3288=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-phycore-rdk" +CONFIG_DEBUG_UART=y +CONFIG_SILENT_CONSOLE=y +CONFIG_CONSOLE_MUX=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_PINCTRL_ROCKCHIP_RK3288=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 64d38b0..6d02675 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -62,6 +62,7 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 862203f..a6f3cd7 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -19,6 +19,7 @@ CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index 95b1677..1cbbb2c 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -21,6 +21,7 @@ CONFIG_DM_ETH=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index f91b53d..80e6681 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -21,6 +21,7 @@ CONFIG_DM_ETH=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index e2d81ab..5d344fd 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -19,6 +19,7 @@ CONFIG_MMC_SDHCI_BCM2835=y CONFIG_DM_ETH=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_DM_VIDEO=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index a565384..a3f9ef0 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -57,6 +57,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 06fc82c..9e9f781 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -57,6 +57,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 0697e2e..f115702 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -51,6 +51,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index cd64fb9..8f7e459 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -49,6 +49,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index bba90be..7b7909c 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -48,6 +48,7 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y # CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 627b90f..88618f8 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -50,6 +50,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index bf5d63d..864ec59 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -57,6 +57,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 5915faf..706ca72 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -57,6 +57,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 18186e8..21754b4 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -72,6 +72,7 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 35046a9..c46bacc 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -65,6 +65,7 @@ CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 2d8cf9f..dbeb8be 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -36,13 +36,14 @@ You will need: Building ======== -At present eight RK3288 boards are supported: +At present nine RK3288 boards are supported: - EVB RK3288 - use evb-rk3288 configuration - Fennec RK3288 - use fennec-rk3288 configuration - Firefly RK3288 - use firefly-rk3288 configuration - Hisense Chromebook - use chromebook_jerry configuration - MiQi RK3288 - use miqi-rk3288 configuration + - phyCORE-RK3288 RDK - use phycore-rk3288 configuration - PopMetal RK3288 - use popmetal-rk3288 configuration - Radxa Rock 2 - use rock2 configuration - Tinker RK3288 - use tinker-rk3288 configuration diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index e404c0c..c50aff2 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o +obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c new file mode 100644 index 0000000..fdeb816 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -0,0 +1,413 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk322x.h> +#include <asm/arch/hardware.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rk3228-cru.h> +#include <linux/log2.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + VCO_MAX_HZ = 3200U * 1000000, + VCO_MIN_HZ = 800 * 1000000, + OUTPUT_MAX_HZ = 3200U * 1000000, + OUTPUT_MIN_HZ = 24 * 1000000, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ + _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \ + OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \ + #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* use integer mode*/ +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); + +static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +{ + int pll_id = rk_pll_id(clk_id); + struct rk322x_pll *pll = &cru->pll[pll_id]; + + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; + uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; + + debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n", + pll, div->fbdiv, div->refdiv, div->postdiv1, + div->postdiv2, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); + + /* use integer mode */ + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + /* Power down */ + rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); + + rk_clrsetreg(&pll->con0, + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, + (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (div->postdiv2 << PLL_POSTDIV2_SHIFT | + div->refdiv << PLL_REFDIV_SHIFT)); + + /* Power Up */ + rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); + + /* waiting for pll lock */ + while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) + udelay(1); + + return 0; +} + +static void rkclk_init(struct rk322x_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | APLL_MODE_MASK, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | + APLL_MODE_SLOW << APLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + + /* + * select apll as cpu/core clock pll source and + * set up dependent divisors for PERI and ACLK clocks. + * core hz : apll = 1:1 + */ + aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; + assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); + + pclk_div = APLL_HZ / CORE_PERI_HZ - 1; + assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, + CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | + 0 << CORE_DIV_CON_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, + aclk_div << CORE_ACLK_DIV_SHIFT | + pclk_div << CORE_PERI_DIV_SHIFT); + + /* + * select apll as pd_bus bus clock source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; + assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); + + pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1; + assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); + + hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; + assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[0], + BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, + BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | + aclk_div << BUS_ACLK_DIV_SHIFT); + + rk_clrsetreg(&cru->cru_clksel_con[1], + BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, + pclk_div << BUS_PCLK_DIV_SHIFT | + hclk_div << BUS_HCLK_DIV_SHIFT); + + /* + * select gpll as pd_peri bus clock source and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && pclk_div < 0x8); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | + PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, + PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | APLL_MODE_MASK, + GPLL_MODE_NORM << GPLL_MODE_SHIFT | + APLL_MODE_NORM << APLL_MODE_SHIFT); +} + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t refdiv, fbdiv, postdiv1, postdiv2; + uint32_t con; + int pll_id = rk_pll_id(clk_id); + struct rk322x_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, + GPLL_MODE_SHIFT, 0xff + }; + static u32 clk_mask[CLK_COUNT] = { + 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, + GPLL_MODE_MASK, 0xff + }; + uint shift; + uint mask; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + mask = clk_mask[clk_id]; + + switch ((con & mask) >> shift) { + case GPLL_MODE_SLOW: + return OSC_HZ; + case GPLL_MODE_NORM: + + /* normal mode */ + con = readl(&pll->con0); + postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; + fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; + con = readl(&pll->con1); + postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; + refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; + return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; + default: + return 32768; + } +} + +static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, + int periph) +{ + uint src_rate; + uint div, mux; + u32 con; + + switch (periph) { + case HCLK_EMMC: + case SCLK_EMMC: + con = readl(&cru->cru_clksel_con[11]); + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; + con = readl(&cru->cru_clksel_con[12]); + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; + break; + case HCLK_SDMMC: + case SCLK_SDMMC: + con = readl(&cru->cru_clksel_con[11]); + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; + break; + default: + return -EINVAL; + } + + src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; + return DIV_TO_RATE(src_rate, div); +} + +static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, + int periph, uint freq) +{ + int src_clk_div; + int mux; + + debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); + + /* mmc clock auto divide 2 in internal */ + src_clk_div = (clk_general_rate / 2 + freq - 1) / freq; + + if (src_clk_div > 0x7f) { + src_clk_div = (OSC_HZ / 2 + freq - 1) / freq; + mux = EMMC_SEL_24M; + } else { + mux = EMMC_SEL_GPLL; + } + + switch (periph) { + case HCLK_EMMC: + case SCLK_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[11], + EMMC_PLL_MASK, + mux << EMMC_PLL_SHIFT); + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_DIV_MASK, + (src_clk_div - 1) << EMMC_DIV_SHIFT); + break; + case HCLK_SDMMC: + case SCLK_SDMMC: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_PLL_MASK | MMC0_DIV_MASK, + mux << MMC0_PLL_SHIFT | + (src_clk_div - 1) << MMC0_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_mmc_get_clk(cru, clk_general_rate, periph); +} + +static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate) +{ + struct pll_div dpll_cfg; + + /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ + switch (set_rate) { + case 400*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; + break; + case 600*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; + break; + case 800*MHz: + dpll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; + break; + } + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, + DPLL_MODE_SLOW << DPLL_MODE_SHIFT); + rkclk_set_pll(cru, CLK_DDR, &dpll_cfg); + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, + DPLL_MODE_NORM << DPLL_MODE_SHIFT); + + return set_rate; +} +static ulong rk322x_clk_get_rate(struct clk *clk) +{ + struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate, gclk_rate; + + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); + switch (clk->id) { + case 0 ... 63: + rate = rkclk_pll_get_rate(priv->cru, clk->id); + break; + case HCLK_EMMC: + case SCLK_EMMC: + case HCLK_SDMMC: + case SCLK_SDMMC: + rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id); + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate, gclk_rate; + + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); + switch (clk->id) { + case HCLK_EMMC: + case SCLK_EMMC: + case HCLK_SDMMC: + case SCLK_SDMMC: + new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, + clk->id, rate); + break; + case CLK_DDR: + new_rate = rk322x_ddr_set_clk(priv->cru, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static struct clk_ops rk322x_clk_ops = { + .get_rate = rk322x_clk_get_rate, + .set_rate = rk322x_clk_set_rate, +}; + +static int rk322x_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk322x_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev); + + return 0; +} + +static int rk322x_clk_probe(struct udevice *dev) +{ + struct rk322x_clk_priv *priv = dev_get_priv(dev); + + rkclk_init(priv->cru); + + return 0; +} + +static int rk322x_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev); + if (ret) + debug("Warning: No RK3036 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rk322x_clk_ids[] = { + { .compatible = "rockchip,rk3228-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk322x_cru) = { + .name = "clk_rk322x", + .id = UCLASS_CLK, + .of_match = rk322x_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv), + .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata, + .ops = &rk322x_clk_ops, + .bind = rk322x_clk_bind, + .probe = rk322x_clk_probe, +}; diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 25a21e2..e7fcf89 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -44,7 +44,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) ret = clk_set_rate(&priv->clk, freq); if (ret < 0) { - printf("%s: err=%d\n", __func__, ret); + debug("%s: err=%d\n", __func__, ret); return ret; } @@ -59,32 +59,28 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) host->name = dev->name; host->ioaddr = (void *)devfdt_get_addr(dev); - host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "bus-width", 4); + host->buswidth = dev_read_u32_default(dev, "bus-width", 4); host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; host->priv = dev; /* use non-removeable as sdcard and emmc as judgement */ - if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "non-removable")) + if (dev_read_bool(dev, "non-removable")) host->dev_index = 0; else host->dev_index = 1; - priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "fifo-depth", 0); + priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); + if (priv->fifo_depth < 0) return -EINVAL; - priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), - "fifo-mode"); + priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); /* * 'clock-freq-min-max' is deprecated * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b) */ - if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), - "clock-freq-min-max", priv->minmax, 2)) { - int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "max-frequency", -EINVAL); + if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { + int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); if (val < 0) return val; @@ -119,13 +115,14 @@ static int rockchip_dwmmc_probe(struct udevice *dev) host->dev_index = 0; priv->fifo_depth = dtplat->fifo_depth; priv->fifo_mode = 0; - memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax)); + priv->minmax[0] = 400000; /* 400 kHz */ + priv->minmax[1] = dtplat->max_frequency; ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); if (ret < 0) return ret; #else - ret = clk_get_by_name(dev, "ciu", &priv->clk); + ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) return ret; #endif diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 8985878..f31d329 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -50,8 +50,7 @@ static int arasan_sdhci_probe(struct udevice *dev) max_frequency = dtplat->max_frequency; ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk); #else - max_frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "max-frequency", 0); + max_frequency = dev_read_u32_default(dev, "max-frequency", 0); ret = clk_get_by_index(dev, 0, &clk); #endif if (!ret) { diff --git a/drivers/net/designware.c b/drivers/net/designware.c index e8569e6..521e4dd 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -760,15 +760,14 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev) pdata->max_speed = fdt32_to_cpu(*cell); #ifdef CONFIG_DM_GPIO - if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), - "snps,reset-active-low")) + if (dev_read_bool(dev, "snps,reset-active-low")) reset_flags |= GPIOD_ACTIVE_LOW; ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, &priv->reset_gpio, reset_flags); if (ret == 0) { - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), - "snps,reset-delays-us", dw_pdata->reset_delays, 3); + ret = dev_read_u32_array(dev, "snps,reset-delays-us", + dw_pdata->reset_delays, 3); } else if (ret == -ENOENT) { ret = 0; } diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 5e2ca76..c9f9e83 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -43,18 +43,16 @@ struct rk_gmac_ops { static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); /* Check the new naming-style first... */ - pdata->tx_delay = fdtdec_get_int(blob, node, "tx_delay", -ENOENT); - pdata->rx_delay = fdtdec_get_int(blob, node, "rx_delay", -ENOENT); + pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); + pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); /* ... and fall back to the old naming style or default, if necessary */ if (pdata->tx_delay == -ENOENT) - pdata->tx_delay = fdtdec_get_int(blob, node, "tx-delay", 0x30); + pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); if (pdata->rx_delay == -ENOENT) - pdata->rx_delay = fdtdec_get_int(blob, node, "rx-delay", 0x10); + pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); return designware_eth_ofdata_to_platdata(dev); } diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f948783..4ab0b3a 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -178,6 +178,16 @@ config PINCTRL_ROCKCHIP_RK3188 the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_ROCKCHIP_RK322X + bool "Rockchip rk322x pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk322x SoCs. + + The driver is controlled by a device tree node which contains both + the GPIO definitions and pin control functions for each available + multiplex function. + config PINCTRL_ROCKCHIP_RK3288 bool "Rockchip rk3288 pin control driver" depends on DM diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index a1c655d..5251771 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o +obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3328) += pinctrl_rk3328.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3368) += pinctrl_rk3368.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c index 9215d6c..94f6d7a 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c @@ -193,8 +193,7 @@ static int rk3036_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c index 65c1f66..692d8e2 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3188.c @@ -370,8 +370,7 @@ static int rk3188_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c new file mode 100644 index 0000000..7aaf4b5 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c @@ -0,0 +1,294 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk322x.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk322x_pinctrl_priv { + struct rk322x_grf *grf; +}; + +static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id) +{ + u32 mux_con = readl(&grf->con_iomux); + + switch (pwm_id) { + case PERIPH_ID_PWM0: + if (mux_con & CON_IOMUX_PWM0SEL_MASK) + rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK, + GPIO3C5_PWM10 << GPIO3C5_SHIFT); + else + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK, + GPIO0D2_PWM0 << GPIO0D2_SHIFT); + break; + case PERIPH_ID_PWM1: + if (mux_con & CON_IOMUX_PWM1SEL_MASK) + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK, + GPIO0D6_PWM11 << GPIO0D6_SHIFT); + else + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK, + GPIO0D3_PWM1 << GPIO0D3_SHIFT); + break; + case PERIPH_ID_PWM2: + if (mux_con & CON_IOMUX_PWM2SEL_MASK) + rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK, + GPIO1B4_PWM12 << GPIO1B4_SHIFT); + else + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK, + GPIO0D4_PWM2 << GPIO0D4_SHIFT); + break; + case PERIPH_ID_PWM3: + if (mux_con & CON_IOMUX_PWM3SEL_MASK) + rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK, + GPIO1B3_PWM13 << GPIO1B3_SHIFT); + else + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK, + GPIO3D2_PWM3 << GPIO3D2_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A1_MASK | GPIO0A0_MASK, + GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT | + GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT); + + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A3_MASK | GPIO0A2_MASK, + GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT | + GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C5_MASK | GPIO2C4_MASK, + GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT | + GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT); + break; + case PERIPH_ID_I2C3: + rk_clrsetreg(&grf->gpio0a_iomux, + GPIO0A7_MASK | GPIO0A6_MASK, + GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT | + GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT); + + break; + } +} + +static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs) +{ + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK, + GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK, + GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT); + break; + } + rk_clrsetreg(&grf->gpio0b_iomux, + GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK, + GPIO0B5_SPI_RXD << GPIO0B5_SHIFT | + GPIO0B3_SPI_TXD << GPIO0B3_SHIFT | + GPIO0B1_SPI_CLK << GPIO0B1_SHIFT); +} + +static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id) +{ + u32 mux_con = readl(&grf->con_iomux); + + switch (uart_id) { + case PERIPH_ID_UART1: + if (!(mux_con & CON_IOMUX_UART1SEL_MASK)) + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT | + GPIO1B2_UART1_SIN << GPIO1B2_SHIFT); + break; + case PERIPH_ID_UART2: + if (mux_con & CON_IOMUX_UART2SEL_MASK) + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT | + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT); + else + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C3_MASK | GPIO1C2_MASK, + GPIO1C3_UART2_SIN << GPIO1C3_SHIFT | + GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT); + break; + } +} + +static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->gpio1d_iomux, 0xffff, + GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT | + GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT | + GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT | + GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT | + GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT | + GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT | + GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT | + GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A5_MASK | GPIO2A7_MASK, + GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT | + GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT); + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C6_MASK | GPIO1C7_MASK, + GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT | + GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B6_MASK | GPIO1B7_MASK, + GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT | + GPIO1B7_SDMMC_CMD << GPIO1B6_SHIFT); + rk_clrsetreg(&grf->gpio1c_iomux, 0xfff, + GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT | + GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT | + GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT | + GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT | + GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT | + GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT); + break; + } +} + +static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk322x_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + pinctrl_rk322x_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + pinctrl_rk322x_i2c_config(priv->grf, func); + break; + case PERIPH_ID_SPI0: + pinctrl_rk322x_spi_config(priv->grf, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + pinctrl_rk322x_uart_config(priv->grf, func); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk322x_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk322x_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 12: + return PERIPH_ID_SDCARD; + case 14: + return PERIPH_ID_EMMC; + case 36: + return PERIPH_ID_I2C0; + case 37: + return PERIPH_ID_I2C1; + case 38: + return PERIPH_ID_I2C2; + case 49: + return PERIPH_ID_SPI0; + case 50: + return PERIPH_ID_PWM0; + case 55: + return PERIPH_ID_UART0; + case 56: + return PERIPH_ID_UART1; + case 57: + return PERIPH_ID_UART2; + } + return -ENOENT; +} + +static int rk322x_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk322x_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return rk322x_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk322x_pinctrl_ops = { + .set_state_simple = rk322x_pinctrl_set_state_simple, + .request = rk322x_pinctrl_request, + .get_periph_id = rk322x_pinctrl_get_periph_id, +}; + +static int rk322x_pinctrl_probe(struct udevice *dev) +{ + struct rk322x_pinctrl_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + debug("%s: grf=%p\n", __func__, priv->grf); + return 0; +} + +static const struct udevice_id rk322x_pinctrl_ids[] = { + { .compatible = "rockchip,rk322x-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk322x) = { + .name = "pinctrl_rk322x", + .id = UCLASS_PINCTRL, + .of_match = rk322x_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv), + .ops = &rk322x_pinctrl_ops, + .bind = dm_scan_fdt_dev, + .probe = rk322x_pinctrl_probe, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c index cb13d30..3c9ae97 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c @@ -402,6 +402,119 @@ static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id) } } +static void pinctrl_rk3288_gmac_config(struct rk3288_grf *grf, int gmac_id) +{ + switch (gmac_id) { + case PERIPH_ID_GMAC: + rk_clrsetreg(&grf->gpio3dl_iomux, + GPIO3D3_MASK << GPIO3D3_SHIFT | + GPIO3D2_MASK << GPIO3D2_SHIFT | + GPIO3D2_MASK << GPIO3D1_SHIFT | + GPIO3D0_MASK << GPIO3D0_SHIFT, + GPIO3D3_MAC_RXD3 << GPIO3D3_SHIFT | + GPIO3D2_MAC_RXD2 << GPIO3D2_SHIFT | + GPIO3D1_MAC_TXD3 << GPIO3D1_SHIFT | + GPIO3D0_MAC_TXD2 << GPIO3D0_SHIFT); + + rk_clrsetreg(&grf->gpio3dh_iomux, + GPIO3D7_MASK << GPIO3D7_SHIFT | + GPIO3D6_MASK << GPIO3D6_SHIFT | + GPIO3D5_MASK << GPIO3D5_SHIFT | + GPIO3D4_MASK << GPIO3D4_SHIFT, + GPIO3D7_MAC_RXD1 << GPIO3D7_SHIFT | + GPIO3D6_MAC_RXD0 << GPIO3D6_SHIFT | + GPIO3D5_MAC_TXD1 << GPIO3D5_SHIFT | + GPIO3D4_MAC_TXD0 << GPIO3D4_SHIFT); + + /* switch the Tx pins to 12ma drive-strength */ + rk_clrsetreg(&grf->gpio1_e[2][3], + GPIO_BIAS_MASK | + (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1)) | + (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4)) | + (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(5)), + (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(0)) | + (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)) | + (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)) | + (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(5))); + + /* Set normal pull for all GPIO3D pins */ + rk_clrsetreg(&grf->gpio1_p[2][3], + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)), + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7))); + + rk_clrsetreg(&grf->gpio4al_iomux, + GPIO4A3_MASK << GPIO4A3_SHIFT | + GPIO4A1_MASK << GPIO4A1_SHIFT | + GPIO4A0_MASK << GPIO4A0_SHIFT, + GPIO4A3_MAC_CLK << GPIO4A3_SHIFT | + GPIO4A1_MAC_TXDV << GPIO4A1_SHIFT | + GPIO4A0_MAC_MDC << GPIO4A0_SHIFT); + + rk_clrsetreg(&grf->gpio4ah_iomux, + GPIO4A6_MASK << GPIO4A6_SHIFT | + GPIO4A5_MASK << GPIO4A5_SHIFT | + GPIO4A4_MASK << GPIO4A4_SHIFT, + GPIO4A6_MAC_RXCLK << GPIO4A6_SHIFT | + GPIO4A5_MAC_MDIO << GPIO4A5_SHIFT | + GPIO4A4_MAC_TXEN << GPIO4A4_SHIFT); + + /* switch GPIO4A4 to 12ma drive-strength */ + rk_clrsetreg(&grf->gpio1_e[3][0], + GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4), + GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)); + + /* Set normal pull for all GPIO4A pins */ + rk_clrsetreg(&grf->gpio1_p[3][0], + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)), + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7))); + + /* switch GPIO4B1 to 12ma drive-strength */ + rk_clrsetreg(&grf->gpio1_e[3][1], + GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1), + GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)); + + /* Set pull normal for GPIO4B1, pull up for GPIO4B0 */ + rk_clrsetreg(&grf->gpio1_p[3][1], + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)), + (GPIO_PULL_UP << GPIO_PULL_SHIFT(0)) | + (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1))); + + break; + default: + printf("gmac id = %d iomux error!\n", gmac_id); + break; + } +} + #ifndef CONFIG_SPL_BUILD static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id) { @@ -465,6 +578,9 @@ static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk3288_sdmmc_config(priv->grf, func); break; + case PERIPH_ID_GMAC: + pinctrl_rk3288_gmac_config(priv->grf, func); + break; default: return -EINVAL; } @@ -479,12 +595,13 @@ static int rk3288_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; switch (cell[1]) { + case 27: + return PERIPH_ID_GMAC; case 44: return PERIPH_ID_SPI0; case 45: diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c index d0ffeb1..c74163e 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -184,13 +184,11 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, if (com_iomux & IOMUX_SEL_SDMMC_MASK) rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_SEL_MASK, - GPIO0D6_SDMMC0_PWRENM1 - << GPIO0D6_SEL_SHIFT); + GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT); else rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A7_SEL_MASK, - GPIO2A7_SDMMC0_PWRENM0 - << GPIO2A7_SEL_SHIFT); + GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT); rk_clrsetreg(&grf->gpio1a_iomux, GPIO1A0_SEL_MASK, GPIO1A0_CARD_DATA_CLK_CMD_DETN @@ -251,8 +249,7 @@ static int rk3328_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index d93b903..cab268c 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -350,8 +350,7 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; diff --git a/drivers/pinctrl/rockchip/pinctrl_rv1108.c b/drivers/pinctrl/rockchip/pinctrl_rv1108.c index bdf3910..cda94f4 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl_rv1108.c @@ -108,8 +108,7 @@ static int rv1108_pinctrl_get_periph_id(struct udevice *dev, u32 cell[3]; int ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), - "interrupts", cell, ARRAY_SIZE(cell)); + ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); if (ret < 0) return -EINVAL; diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c index c1ece96..7c0a3aa 100644 --- a/drivers/power/regulator/rk8xx.c +++ b/drivers/power/regulator/rk8xx.c @@ -30,6 +30,9 @@ #define RK818_LDO_VSEL_MASK 0x1f #define RK818_LDO3_ON_VSEL_MASK 0xf #define RK818_BOOST_ON_VSEL_MASK 0xe0 +#define RK818_USB_ILIM_SEL_MASK 0x0f +#define RK818_USB_CHG_SD_VSEL_MASK 0x70 + struct rk8xx_reg_info { uint min_uv; @@ -45,6 +48,14 @@ static const struct rk8xx_reg_info rk808_buck[] = { { 1800000, 100000, REG_BUCK4_ON_VSEL, RK808_BUCK4_VSEL_MASK, }, }; +static const struct rk8xx_reg_info rk818_buck[] = { + { 712500, 12500, REG_BUCK1_ON_VSEL, RK818_BUCK_VSEL_MASK, }, + { 712500, 12500, REG_BUCK2_ON_VSEL, RK818_BUCK_VSEL_MASK, }, + { 712500, 12500, -1, RK818_BUCK_VSEL_MASK, }, + { 1800000, 100000, REG_BUCK4_ON_VSEL, RK818_BUCK4_VSEL_MASK, }, +}; + +#ifdef ENABLE_DRIVER static const struct rk8xx_reg_info rk808_ldo[] = { { 1800000, 100000, REG_LDO1_ON_VSEL, RK808_LDO_VSEL_MASK, }, { 1800000, 100000, REG_LDO2_ON_VSEL, RK808_LDO_VSEL_MASK, }, @@ -56,13 +67,6 @@ static const struct rk8xx_reg_info rk808_ldo[] = { { 1800000, 100000, REG_LDO8_ON_VSEL, RK808_LDO_VSEL_MASK, }, }; -static const struct rk8xx_reg_info rk818_buck[] = { - { 712500, 12500, REG_BUCK1_ON_VSEL, RK818_BUCK_VSEL_MASK, }, - { 712500, 12500, REG_BUCK2_ON_VSEL, RK818_BUCK_VSEL_MASK, }, - { 712500, 12500, -1, RK818_BUCK_VSEL_MASK, }, - { 1800000, 100000, REG_BUCK4_ON_VSEL, RK818_BUCK4_VSEL_MASK, }, -}; - static const struct rk8xx_reg_info rk818_ldo[] = { { 1800000, 100000, REG_LDO1_ON_VSEL, RK818_LDO_VSEL_MASK, }, { 1800000, 100000, REG_LDO2_ON_VSEL, RK818_LDO_VSEL_MASK, }, @@ -73,6 +77,15 @@ static const struct rk8xx_reg_info rk818_ldo[] = { { 800000, 100000, REG_LDO7_ON_VSEL, RK818_LDO_VSEL_MASK, }, { 1800000, 100000, REG_LDO8_ON_VSEL, RK818_LDO_VSEL_MASK, }, }; +#endif + +static const u16 rk818_chrg_cur_input_array[] = { + 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000 +}; + +static const uint rk818_chrg_shutdown_vsel_array[] = { + 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000 +}; static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, int num) @@ -86,18 +99,6 @@ static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic, } } -static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, - int num) -{ - struct rk8xx_priv *priv = dev_get_priv(pmic); - switch (priv->variant) { - case RK818_ID: - return &rk818_ldo[num]; - default: - return &rk808_ldo[num]; - } -} - static int _buck_set_value(struct udevice *pmic, int buck, int uvolt) { const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck - 1); @@ -133,6 +134,18 @@ static int _buck_set_enable(struct udevice *pmic, int buck, bool enable) } #ifdef ENABLE_DRIVER +static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic, + int num) +{ + struct rk8xx_priv *priv = dev_get_priv(pmic); + switch (priv->variant) { + case RK818_ID: + return &rk818_ldo[num]; + default: + return &rk808_ldo[num]; + } +} + static int buck_get_value(struct udevice *dev) { int buck = dev->driver_data - 1; @@ -351,3 +364,26 @@ int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt) return _buck_set_enable(pmic, buck, true); } + +int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma) +{ + uint i; + + for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++) + if (current_ma <= rk818_chrg_cur_input_array[i]) + break; + + return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i); +} + +int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt) +{ + uint i; + + for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++) + if (uvolt <= rk818_chrg_shutdown_vsel_array[i]) + break; + + return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK, + i); +} diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 52c52c1..e0e7024 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -434,10 +434,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); #endif - plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "reg-offset", 0); - plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "reg-shift", 0); + plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); + plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); err = clk_get_by_index(dev, 0, &clk); if (!err) { @@ -450,9 +448,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) } if (!plat->clock) - plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", - CONFIG_SYS_NS16550_CLK); + plat->clock = dev_read_u32_default(dev, "clock-frequency", + CONFIG_SYS_NS16550_CLK); if (!plat->clock) { debug("ns16550 clock not defined\n"); return -EINVAL; diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index a8f0eb0..7921ea0 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -182,8 +182,6 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_spi_platdata *plat = dev_get_platdata(bus); struct rockchip_spi_priv *priv = dev_get_priv(bus); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); int ret; plat->base = devfdt_get_addr(bus); @@ -195,12 +193,13 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) return ret; } - plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", - 50000000); - plat->deactivate_delay_us = fdtdec_get_int(blob, node, - "spi-deactivate-delay", 0); - plat->activate_delay_us = fdtdec_get_int(blob, node, - "spi-activate-delay", 0); + plat->frequency = + dev_read_u32_default(bus, "spi-max-frequency", 50000000); + plat->deactivate_delay_us = + dev_read_u32_default(bus, "spi-deactivate-delay", 0); + plat->activate_delay_us = + dev_read_u32_default(bus, "spi-activate-delay", 0); + debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", __func__, (uint)plat->base, plat->frequency, plat->deactivate_delay_us); diff --git a/drivers/sysreset/sysreset_rk322x.c b/drivers/sysreset/sysreset_rk322x.c new file mode 100644 index 0000000..5fce79b --- /dev/null +++ b/drivers/sysreset/sysreset_rk322x.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk322x.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk322x_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case SYSRESET_COLD: + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk322x_sysreset = { + .request = rk322x_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk322x) = { + .name = "rk322x_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk322x_sysreset, +}; diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b824eec..bc2c1f1 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -34,6 +34,8 @@ config USB_XHCI_MVEBU config USB_XHCI_ROCKCHIP bool "Support for Rockchip on-chip xHCI USB controller" depends on ARCH_ROCKCHIP + depends on DM_REGULATOR + depends on DM_USB default y help Enables support for the on-chip xHCI controller on Rockchip SoCs. @@ -199,3 +201,13 @@ config USB_UHCI_HCD if USB_UHCI_HCD endif # USB_UHCI_HCD + +config USB_DWC2 + bool "DesignWare USB2 Core support" + select USB_HOST + ---help--- + The DesignWare USB 2.0 controller is compliant with the + USB-Implementers Forum (USB-IF) USB 2.0 specifications. + Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) + operation is compliant to the controller Supplement. If you want to + enable this controller in host mode, say Y. diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 841e596..64c42ac 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -43,6 +43,10 @@ struct dwc2_priv { struct dwc2_core_regs *regs; int root_hub_devnum; bool ext_vbus; + /* + * The hnp/srp capability must be disabled if the platform + * does't support hnp/srp. Otherwise the force mode can't work. + */ bool hnp_srp_disable; bool oc_disable; }; @@ -1239,7 +1243,6 @@ static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) { struct dwc2_priv *priv = dev_get_priv(dev); - const void *prop; fdt_addr_t addr; addr = devfdt_get_addr(dev); @@ -1247,15 +1250,8 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) return -EINVAL; priv->regs = (struct dwc2_core_regs *)addr; - prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), - "disable-over-current", NULL); - if (prop) - priv->oc_disable = true; - - prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), - "hnp-srp-disable", NULL); - if (prop) - priv->hnp_srp_disable = true; + priv->oc_disable = dev_read_bool(dev, "disable-over-current"); + priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable"); return 0; } diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c index c4ae55f..ec55f4e 100644 --- a/drivers/usb/host/xhci-rockchip.c +++ b/drivers/usb/host/xhci-rockchip.c @@ -48,7 +48,7 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev) */ plat->hcd_base = devfdt_get_addr(dev); if (plat->hcd_base == FDT_ADDR_T_NONE) { - debug("Can't get the XHCI register base address\n"); + error("Can't get the XHCI register base address\n"); return -ENXIO; } @@ -62,17 +62,15 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev) } if (plat->phy_base == FDT_ADDR_T_NONE) { - debug("Can't get the usbphy register address\n"); + error("Can't get the usbphy register address\n"); return -ENXIO; } -#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) /* Vbus regulator */ ret = device_get_supply_regulator(dev, "vbus-supply", &plat->vbus_supply); if (ret) - debug("Can't get vbus supply\n"); -#endif + debug("Can't get VBus regulator!\n"); return 0; } @@ -86,18 +84,15 @@ static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, struct udevice *dev) { u32 reg; - const void *blob = gd->fdt_blob; u32 utmi_bits; /* Set dwc3 usb2 phy config */ reg = readl(&dwc3_reg->g_usb2phycfg[0]); - if (fdtdec_get_bool(blob, dev_of_offset(dev), - "snps,dis-enblslpm-quirk")) + if (dev_read_bool(dev, "snps,dis-enblslpm-quirk")) reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; - utmi_bits = fdtdec_get_int(blob, dev_of_offset(dev), - "snps,phyif-utmi-bits", -1); + utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1); if (utmi_bits == 16) { reg |= DWC3_GUSB2PHYCFG_PHYIF; reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; @@ -108,12 +103,10 @@ static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; } - if (fdtdec_get_bool(blob, dev_of_offset(dev), - "snps,dis-u2-freeclk-exists-quirk")) + if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk")) reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; - if (fdtdec_get_bool(blob, dev_of_offset(dev), - "snps,dis-u2-susphy-quirk")) + if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk")) reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; writel(reg, &dwc3_reg->g_usb2phycfg[0]); @@ -126,7 +119,7 @@ static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, ret = dwc3_core_init(rkxhci->dwc3_reg); if (ret) { - debug("failed to initialize core\n"); + error("failed to initialize core\n"); return ret; } @@ -155,15 +148,17 @@ static int xhci_usb_probe(struct udevice *dev) hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); -#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) - ret = regulator_set_enable(plat->vbus_supply, true); - if (ret) - debug("XHCI: Failed to enable vbus supply\n"); -#endif + if (plat->vbus_supply) { + ret = regulator_set_enable(plat->vbus_supply, true); + if (ret) { + error("XHCI: failed to set VBus supply\n"); + return ret; + } + } ret = rockchip_xhci_core_init(ctx, dev); if (ret) { - debug("XHCI: failed to initialize controller\n"); + error("XHCI: failed to initialize controller\n"); return ret; } @@ -183,13 +178,13 @@ static int xhci_usb_remove(struct udevice *dev) if (ret) return ret; -#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR) - ret = regulator_set_enable(plat->vbus_supply, false); - if (ret) - debug("XHCI: Failed to disable vbus supply\n"); -#endif + if (plat->vbus_supply) { + ret = regulator_set_enable(plat->vbus_supply, false); + if (ret) + error("XHCI: failed to set VBus supply\n"); + } - return 0; + return ret; } static const struct udevice_id xhci_usb_ids[] = { diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index ad00397..1199a30 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; * @txesc_clk: clock for tx esc mode */ struct rk_mipi_priv { - void __iomem *regs; + uintptr_t regs; struct rk3399_grf_regs *grf; struct udevice *panel; struct mipi_dsi *dsi; @@ -76,13 +76,13 @@ static int rk_mipi_read_timing(struct udevice *dev, * use define in rk_mipi.h directly for this parameter * @val: value that will be write to specified bits of register */ -static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val) +static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val) { u32 dat; u32 mask; u32 offset = (reg >> OFFSET_SHIFT) & 0xff; u32 bits = (reg >> BITS_SHIFT) & 0xff; - u64 addr = (reg >> ADDR_SHIFT) + regs; + uintptr_t addr = (reg >> ADDR_SHIFT) + regs; /* Mask for specifiled bits,the corresponding bits will be clear */ mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits))); @@ -108,7 +108,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev, int node, timing_node; int val; struct rk_mipi_priv *priv = dev_get_priv(dev); - u64 regs = (u64)priv->regs; + uintptr_t regs = priv->regs; struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); u32 txbyte_clk = priv->txbyte_clk; u32 txesc_clk = priv->txesc_clk; @@ -224,7 +224,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev, } /* rk mipi dphy write function. It is used to write test data to dphy */ -static void rk_mipi_phy_write(u32 regs, unsigned char test_code, +static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code, unsigned char *test_data, unsigned char size) { int i = 0; @@ -253,7 +253,7 @@ static int rk_mipi_phy_enable(struct udevice *dev) { int i; struct rk_mipi_priv *priv = dev_get_priv(dev); - u64 regs = (u64)priv->regs; + uintptr_t regs = priv->regs; u64 fbdiv; u64 prediv = 1; u32 max_fbdiv = 512; @@ -437,14 +437,14 @@ static int rk_mipi_ofdata_to_platdata(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (priv->grf <= 0) { - debug("%s: Get syscon grf failed (ret=%llu)\n", - __func__, (u64)priv->grf); + debug("%s: Get syscon grf failed (ret=%p)\n", + __func__, priv->grf); return -ENXIO; } - priv->regs = (void *)devfdt_get_addr(dev); + priv->regs = devfdt_get_addr(dev); if (priv->regs <= 0) { - debug("%s: Get MIPI dsi address failed (ret=%llu)\n", __func__, - (u64)priv->regs); + debug("%s: Get MIPI dsi address failed (ret=%lu)\n", __func__, + priv->regs); return -ENXIO; } diff --git a/include/configs/evb_rk3229.h b/include/configs/evb_rk3229.h new file mode 100644 index 0000000..8f8e50f --- /dev/null +++ b/include/configs/evb_rk3229.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk322x_common.h> + + +/* Store env in emmc */ +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE (32 << 10) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#ifndef CONFIG_SPL_BUILD +/* Enable gpt partition table */ +#undef PARTS_DEFAULT +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=loader_a,start=4M,size=4M,uuid=${uuid_gpt_loader};" \ + "name=loader_b,size=4M,uuid=${uuid_gpt_reserved};" \ + "name=trust_a,size=4M,uuid=${uuid_gpt_reserved};" \ + "name=trust_b,size=4M,uuid=${uuid_gpt_reserved};" \ + "name=misc,size=4M,uuid=${uuid_gpt_misc};" \ + "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \ + "name=boot_a,size=32M,uuid=${uuid_gpt_boot_a};" \ + "name=boot_b,size=32M,uuid=${uuid_gpt_boot_b};" \ + "name=system_a,size=818M,uuid=${uuid_gpt_system_a};" \ + "name=system_b,size=818M,uuid=${uuid_gpt_system_b};" \ + "name=vendor_a,size=50M,uuid=${uuid_gpt_vendor_a};" \ + "name=vendor_b,size=50M,uuid=${uuid_gpt_vendor_b};" \ + "name=cache,size=100M,uuid=${uuid_gpt_cache};" \ + "name=persist,size=4M,uuid=${uuid_gpt_persist};" \ + "name=userdata,size=-,uuid=${uuid_gpt_userdata};\0" \ + +#define CONFIG_PREBOOT + +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_SYS_BOOT_RAMDISK_HIGH + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND \ + "mmc read 0x61000000 0x8000 0x5000;" \ + "bootm 0x61000000" \ + +/* Enable atags */ +#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) +#define CONFIG_INITRD_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG + +#endif + +#endif diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 2b4fec4..c7fb8a5 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -54,7 +54,6 @@ #define CONFIG_PL01X_SERIAL #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000 /*#define CONFIG_DWC2_DFLT_SPEED_FULL*/ #define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO diff --git a/include/configs/phycore_rk3288.h b/include/configs/phycore_rk3288.h new file mode 100644 index 0000000..aab43ed --- /dev/null +++ b/include/configs/phycore_rk3288.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2017 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3288_common.h> + +#undef BOOT_TARGET_DEVICES + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 + +#endif diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 836c5e3..18b7dce 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_NR_DRAM_BANKS 1 #define SDRAM_BANK_SIZE (512UL << 20UL) +#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) #define CONFIG_SPI_FLASH #define CONFIG_SPI @@ -71,7 +72,6 @@ /* usb host */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index a1e0eb7..3ee9abd 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_NR_DRAM_BANKS 1 #define SDRAM_BANK_SIZE (2UL << 30) +#define SDRAM_MAX_SIZE 0x80000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI @@ -84,7 +85,6 @@ /* usb host support */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h new file mode 100644 index 0000000..a145b74 --- /dev/null +++ b/include/configs/rk322x_common.h @@ -0,0 +1,92 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_RK322X_COMMON_H +#define __CONFIG_RK322X_COMMON_H + +#include <asm/arch/hardware.h> +#include "rockchip-common.h" + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 +#define CONFIG_SPL_STACK 0x10088000 +#define CONFIG_SPL_TEXT_BASE 0x10081004 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK32" + +/* MMC/SD IP block */ +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 2 +#define SDRAM_BANK_SIZE (512UL << 20UL) +#define SDRAM_MAX_SIZE 0x80000000 + +#ifndef CONFIG_SPL_BUILD +/* usb otg */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_USB_GADGET_VBUS_DRAW 0 + +/* fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_FASTBOOT_FLASH +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 + +/* usb mass storage */ +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#define CONFIG_CMD_USB_MASS_STORAGE + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 +#define CONFIG_G_DNL_PRODUCT_NUM 0x320a + +/* usb host */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#endif +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include <config_distro_bootcmd.h> + +/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x7fffffff\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#define CONFIG_PREBOOT + +#endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index ecf2675..488d679 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -48,6 +48,7 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_NR_DRAM_BANKS 1 #define SDRAM_BANK_SIZE (2UL << 30) +#define SDRAM_MAX_SIZE 0xfe000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI @@ -80,7 +81,6 @@ /* usb host support */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_USB_ETHER_ASIX diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 5a06244..7f9f0c5 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" -#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (32 << 20) @@ -37,6 +36,7 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 8ebf232..b0c858c 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -12,6 +12,8 @@ #include <asm/arch/hardware.h> #include <linux/sizes.h> +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 44dad57..54ea97b 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -51,6 +51,7 @@ /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xf8000000 #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SF_DEFAULT_SPEED 20000000 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index d715eaa..b31e2ac 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -71,7 +71,6 @@ #define CONFIG_VIDEO_BCM2835 #ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX #define CONFIG_TFTP_TSIZE diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c17814b..1bed85e 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -224,9 +224,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 -#endif /* * USB Gadget (DFU, UMS) diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h new file mode 100644 index 0000000..13f9c86 --- /dev/null +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -0,0 +1,238 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define ARMCLK 5 + +/* sclk gates (special clocks) */ +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S0 80 +#define SCLK_I2S1 81 +#define SCLK_I2S2 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_VOP 122 +#define SCLK_HDMI_HDCP 123 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC_EXTCLK 125 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_MAC_PHY 131 +#define SCLK_MAC_OUT 132 + +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_HDMI_PHY 191 + +/* aclk gates */ +#define ACLK_DMAC 194 +#define ACLK_PERI 210 +#define ACLK_VOP 211 +#define ACLK_GMAC 212 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_SPI0 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_TSADC 344 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_PERI 363 +#define PCLK_HDMI_CTRL 364 +#define PCLK_HDMI_PHY 365 +#define PCLK_GMAC 367 + +/* hclk gates */ +#define HCLK_I2S0_8CH 442 +#define HCLK_I2S1_8CH 443 +#define HCLK_I2S2_2CH 444 +#define HCLK_SPDIF_8CH 445 +#define HCLK_VOP 452 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_ACLK_CORE 13 +#define SRST_NOC 14 +#define SRST_L2C 15 + +#define SRST_CPUSYS_H 18 +#define SRST_BUSSYS_H 19 +#define SRST_SPDIF 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_OTG_ADP 23 +#define SRST_I2S0 24 +#define SRST_I2S1 25 +#define SRST_I2S2 26 +#define SRST_ACODEC_P 27 +#define SRST_DFIMON 28 +#define SRST_MSCH 29 +#define SRST_EFUSE1024 30 +#define SRST_EFUSE256 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_PERIPH_NOC_A 36 +#define SRST_PERIPH_NOC_BUS_H 37 +#define SRST_PERIPH_NOC_P 38 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_PHYNOC 42 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_I2C3 46 + +#define SRST_PWM 48 +#define SRST_A53_GIC 49 +#define SRST_DAP 51 +#define SRST_DAP_NOC 52 +#define SRST_CRYPTO 53 +#define SRST_SGRF 54 +#define SRST_GRF 55 +#define SRST_GMAC 56 +#define SRST_PERIPH_NOC_H 58 +#define SRST_MACPHY 63 + +#define SRST_DMA 64 +#define SRST_NANDC 68 +#define SRST_USBOTG 69 +#define SRST_OTGC 70 +#define SRST_USBHOST0 71 +#define SRST_HOST_CTRL0 72 +#define SRST_USBHOST1 73 +#define SRST_HOST_CTRL1 74 +#define SRST_USBHOST2 75 +#define SRST_HOST_CTRL2 76 +#define SRST_USBPOR0 77 +#define SRST_USBPOR1 78 +#define SRST_DDRMSCH 79 + +#define SRST_SMART_CARD 80 +#define SRST_SDMMC 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI 84 +#define SRST_TSP_H 85 +#define SRST_TSP 86 +#define SRST_TSADC 87 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 +#define SRST_HOST0_ECHI 92 +#define SRST_HOST1_ECHI 93 +#define SRST_HOST2_ECHI 94 +#define SRST_VOP_NOC_A 95 + +#define SRST_HDMI_P 96 +#define SRST_VIO_ARBI_H 97 +#define SRST_IEP_NOC_A 98 +#define SRST_VIO_NOC_H 99 +#define SRST_VOP_A 100 +#define SRST_VOP_H 101 +#define SRST_VOP_D 102 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_UTMI2 105 +#define SRST_UTMI3 106 +#define SRST_RGA 107 +#define SRST_RGA_NOC_A 108 +#define SRST_RGA_A 109 +#define SRST_RGA_H 110 +#define SRST_HDCP_A 111 + +#define SRST_VPU_A 112 +#define SRST_VPU_H 113 +#define SRST_VPU_NOC_A 116 +#define SRST_VPU_NOC_H 117 +#define SRST_RKVDEC_A 118 +#define SRST_RKVDEC_NOC_A 119 +#define SRST_RKVDEC_H 120 +#define SRST_RKVDEC_NOC_H 121 +#define SRST_RKVDEC_CORE 122 +#define SRST_RKVDEC_CABAC 123 +#define SRST_IEP_A 124 +#define SRST_IEP_H 125 +#define SRST_GPU_A 126 +#define SRST_GPU_NOC_A 127 + +#define SRST_CORE_DBG 128 +#define SRST_DBG_P 129 +#define SRST_TIMER0 130 +#define SRST_TIMER1 131 +#define SRST_TIMER2 132 +#define SRST_TIMER3 133 +#define SRST_TIMER4 134 +#define SRST_TIMER5 135 +#define SRST_VIO_H2P 136 +#define SRST_HDMIPHY 139 +#define SRST_VDAC 140 +#define SRST_TIMER_6CH_P 141 + +#endif diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h index 589f8c4..47a6b36 100644 --- a/include/power/rk8xx_pmic.h +++ b/include/power/rk8xx_pmic.h @@ -189,5 +189,7 @@ struct rk8xx_priv { }; int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt); +int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma); +int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt); #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 54eee53..1ab6101 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -5115,7 +5115,6 @@ CONFIG_USB_CABLE_CHECK CONFIG_USB_DEVICE CONFIG_USB_DEV_BASE CONFIG_USB_DEV_PULLUP_GPIO -CONFIG_USB_DWC2 CONFIG_USB_DWC2_REG_ADDR CONFIG_USB_EHCI_ARMADA100 CONFIG_USB_EHCI_BASE diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 1056ffa..25b0340 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -74,6 +74,7 @@ struct spl_info { static struct spl_info spl_infos[] = { { "rk3036", "RK30", 0x1000, false, false }, { "rk3188", "RK31", 0x8000 - 0x800, true, false }, + { "rk322x", "RK32", 0x8000 - 0x1000, false, false }, { "rk3288", "RK32", 0x8000, false, false }, { "rk3328", "RK32", 0x8000 - 0x1000, false, false }, { "rk3399", "RK33", 0x30000 - 0x2000, false, true }, |