577 files changed, 80741 insertions, 9388 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 0f67829..3bc119f 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,1903 @@
+commit 2a8dfe08359a1b663418b2faa1da1d7bce34d302
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Mar 21 23:26:15 2007 +0100
+
+    Code cleanup. Update CHANGELOG
+
+commit e6615ecf4eaf4dd52696934aed8f5c6474cfd286
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Mar 21 14:54:29 2007 +0100
+
+    ppc4xx: Fix file mode of include/configs/acadia.h
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d5f4614c9350d9333e575100fb250aab774d0258
+Author: Markus Klotzbuecher <mk@denx.de>
+Date:	Wed Mar 21 14:41:46 2007 +0100
+
+    SPC1920: fix small clock routing bug
+
+    Signed-off-by: Markus Klotzbuecher <mk@denx.de>
+
+commit 16c0cc1c82081a493ab87c51980b28336ce1bce8
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Mar 21 13:39:57 2007 +0100
+
+    [PATCH] Add AMCC Acadia (405EZ) eval board support
+
+    This patch adds support for the new AMCC Acadia eval board.
+
+    Please note that this Acadia/405EZ support is still in a beta stage.
+    Still lot's of cleanup needed but we need a preliminary release now.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e01bd218b00af73499331a1a701625a852cd286f
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Mar 21 13:38:59 2007 +0100
+
+    [PATCH] Add AMCC PPC405EZ support
+
+    This patch adds support for the new AMCC 405EZ PPC. It is in
+    preparation for the AMCC Acadia board support.
+
+    Please note that this Acadia/405EZ support is still in a beta stage.
+    Still lot's of cleanup needed but we need a preliminary release now.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 07e82cb2e284a893df6693f2a1337ab2c47bf6a1
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Wed Mar 21 08:45:17 2007 +0100
+
+    [PATCH] TQM8272: dont change the bits given from the HRCW
+		     for the SIUMCR and BCR Register.
+		     Fix the calculation for the EEprom Size
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 654589873dbafcf104dff133ce0d03a4506e9cc3
+Author: Aubrey Li <aubrey.adi@gmail.com>
+Date:	Tue Mar 20 18:16:24 2007 +0800
+
+    [Blackfin][PATCH] Add BF561 EZKIT board support
+
+commit a6154fd1cfd020f6da8527e0365b1020a11a71d0
+Author: Aubrey Li <aubrey.adi@gmail.com>
+Date:	Mon Mar 19 22:55:58 2007 +0800
+
+    [Blackfin][PATCH] minor cleanup
+
+commit 389b6bb50f745bf5038ce030300d8a8512e96f79
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Mar 19 13:10:08 2007 +0100
+
+    Remove obsoleted POST files.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8e709bbb2636b5670a8f2b575e138eb1f55773f6
+Author: Aubrey Li <aubrey.adi@gmail.com>
+Date:	Mon Mar 19 01:26:11 2007 +0800
+
+    [PATCH] Add flash chip M29W320ET/B support
+
+commit 26bf7deca364a5b33f39e8f14ddd3f4081345015
+Author: Aubrey Li <aubrey.adi@gmail.com>
+Date:	Mon Mar 19 01:24:52 2007 +0800
+
+    [Blackfin][PATCH] Add BF537 stamp board support
+
+commit 8423e5e31a7235d05a482627315fb11d49c17bd7
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Mar 16 21:11:42 2007 +0100
+
+    [PATCH] Use dynamic SDRAM TLB setup on AMCC Ebony eval board
+
+    Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
+    DDR memory are dynamically programmed matching the total size
+    of the equipped memory (DIMM modules).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 76d1466f918b881cda2d259254761e73885093c2
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Tue Mar 13 13:38:05 2007 +0100
+
+    [PATCH] renamed environment variable 'addcon' to 'addcons' for PCI405
+	    boards in terms of unification.
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit a7090b993d3d4d2221ac3f33e6cb1d1b2ccc6bf0
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Mar 13 16:05:55 2007 +0100
+
+    Make SC3 board build with 'make O='; use 'addcons' consistently
+    (SC3 and Jupiter used to use 'addcon' instead).
+
+    Signed-off-by: Wolfgang Denk wd@denx.de
+
+commit 8502e30a28e492c756ea2d7df0ace026388fce4b
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Tue Mar 13 09:40:59 2007 +0100
+
+    [PATCH] update board config for jupiter Board:
+	    added Hush Shell,
+		  CONFIG_CMDLINE_EDITING,
+		  CFG_ENV_ADDR_REDUND activated
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 0d93de11449390a5984b0236c3612e50f6dbb7e8
+Author: Aubrey Li <aubrey.adi@gmail.com>
+Date:	Mon Mar 12 12:11:55 2007 +0800
+
+    [Blackfin][PATCH] minor cleanup
+
+commit bfa5754a58477ac917d21527cd0f079d87cf188e
+Author: Aubrey Li <aubrey.adi@gmail.com>
+Date:	Mon Mar 12 01:42:06 2007 +0800
+
+    [Blackfin][PATCH] Fix BUILD_DIR option of MAKEALL building issue
+
+commit 8440bb14581a294375c34b91b42512f9753d1130
+Author: Aubrey Li <aubrey.adi@gmail.com>
+Date:	Mon Mar 12 00:25:14 2007 +0800
+
+    [Blackfin][PATCH] code cleanup
+
+commit 8db13d63157811c839d15a313d9f2d2f5fd10af3
+Author: Aubrey Li <aubrey.adi@gmail.com>
+Date:	Sat Mar 10 23:49:29 2007 +0800
+
+    [Blackfin][PATCH] code cleanup
+
+commit ef26a08fef928b7bc11ae2c109e638dc3a016d91
+Author: Aubrey.Li <aubrey.adi@gmail.com>
+Date:	Fri Mar 9 13:40:56 2007 +0800
+
+    [Blackfin][PATCH-2/2] Common files changed to support bf533 platform
+
+commit 3f0606ad0b5639f7f22848fe5b4574e754d0470f
+Author: Aubrey.Li <aubrey.adi@gmail.com>
+Date:	Fri Mar 9 13:38:44 2007 +0800
+
+    [Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support
+
+commit 992423ab43c2bcf6b704853bd00af77450915e20
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Mar 8 23:00:08 2007 +0100
+
+    ppc4xx: Fix file mode of sequoia.c
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit eb92f613556800f7483666db09d9a237ad911d4a
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Thu Mar 8 22:52:51 2007 +0100
+
+    Minor cleanup.
+
+commit 8ce16f55c7b9752af3d8bed84521aec5337e2de1
+Author: John Otken john@softadvances.com <john@softadvances.com>
+Date:	Thu Mar 8 09:39:48 2007 -0600
+
+    ppc4xx: Clear Sequoia/Rainier security engine reset bits
+
+    Signed-off-by: John Otken john@softadvances.com <john@softadvances.com>
+
+commit 650a330dd2539130c8c324791e2f9f75aed79d4e
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Mar 8 16:26:52 2007 +0100
+
+    [PATCH] I2C: add some more SPD eeprom decoding for DDR2 modules
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit d9fc703246840c4b268debf48c334ba55c597dc0
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Mar 8 16:25:47 2007 +0100
+
+    [PATCH] I2C: disable flat i2c commands when CONFIG_I2C_CMD_TREE is defined
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit ced5b9029043397348cdc88e0cfcd6b1f629250b
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Mar 8 16:23:11 2007 +0100
+
+    [PATCH] 4xx: allow CONFIG_I2C_CMD_TREE without CONFIG_I2C_MULTI_BUS
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit d8a8ea5c476d37006fc7f85b7f903142795c8b14
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Thu Mar 8 16:20:32 2007 +0100
+
+    [PATCH] I2C: Add missing default CFG_SPD_BUS_NUM
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit f9fc6a5852a6335840882fa2111925010eea1abe
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date:	Wed Mar 7 15:32:01 2007 +0100
+
+    fixed ethernet phy configuration for plu405 board
+
+    Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+commit 769104c9356594deb2092e204a39c05b33202d6c
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Thu Mar 8 21:49:27 2007 +0100
+
+    Minor cleanup
+
+commit 00cdb4ce5e1b42248e7e6522ad0da3421b988afa
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Mar 8 10:13:16 2007 +0100
+
+    [PATCH] Update AMCC Luan 440SP eval board support
+
+    The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR
+    inititializition. This includes DDR auto calibration and support
+    for different DIMM modules, instead of the fixed setup used in
+    the earlier version.
+
+    This patch also enables the cache in FLASH for the startup
+    phase of U-Boot (while running from FLASH). After relocating to
+    SDRAM the cache is disabled again. This will speed up the boot
+    process, especially the SDRAM setup, since there are some loops
+    for memory testing (auto calibration).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2f5df47351910a2936c7741cf111855829200943
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Mar 8 10:10:18 2007 +0100
+
+    [PATCH] Update AMCC Yucca 440SPe eval board support
+
+    The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR
+    inititializition. This includes DDR auto calibration and support
+    for different DIMM modules, instead of the fixed setup used in
+    the earlier version.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2721a68a9ea91f1e494649ce68b2577261f578e2
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Mar 8 10:07:18 2007 +0100
+
+    ppc4xx: Small AMCC Katmai 440SPe update
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit df294497479b1dca6dd86318b2a912f72fede0df
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Mar 8 10:06:09 2007 +0100
+
+    ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SP
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit fa1aef15bcd47736687be1af544506e90fba545d
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Mar 7 16:43:00 2007 +0100
+
+    [PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval board
+
+    Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
+    DDR memory are dynamically programmed matching the total size
+    of the equipped memory (DIMM modules).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e2ebe696818939e2b974628be9c921ea3fe9de13
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Mar 7 16:39:36 2007 +0100
+
+    [PATCH] Fix AMCC 44x SPD SDRAM init code to support 2 DIMM's
+
+    This patch fixes a problem that occurs when 2 DIMM's are
+    used. This problem was first spotted and fixed by Gerald Jackson
+    <gerald.jackson@reaonixsecurity.com> but this patch fixes the
+    problem in a little more clever way.
+
+    This patch also adds the nice functionality to dynamically
+    create the TLB entries for the SDRAM (tlb.c). So we should
+    never run into such problems with wrong (too short) TLB
+    initialization again on these platforms.
+
+    As this feature is new to the "old" 44x SPD DDR driver, it
+    has to be enabled via the CONFIG_PROG_SDRAM_TLB define.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 39218433983417b9df087976a79e3f80dd5e83d6
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Mar 7 16:33:44 2007 +0100
+
+    UC101: fix compiler warnings
+
+commit 8d7e2732221bc2d64df14f700c64c23e0a4c3dce
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Wed Mar 7 16:19:46 2007 +0100
+
+    HMI1001: fix build error, cleanup compiler warnings.
+
+commit ad5bb451ade552c44bef9119d907929ebc2c126f
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Tue Mar 6 18:08:43 2007 +0100
+
+    Restructure POST directory to support of other CPUs, boards, etc.
+
+commit a5284efd125967675b2e9c6ef7b95832268ad360
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Tue Mar 6 18:01:47 2007 +0100
+
+    Fix HOSTARCH handling.
+    Patch by Mike Frysinger, Mar 05 2007
+
+commit 07b7b0037aac5102939917d7cbe561b5c0d5aa44
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Mar 6 07:47:04 2007 +0100
+
+    [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup
+
+    As provided by the AMCC applications team, this patch optimizes the
+    DDR2 setup for 166MHz bus speed. The values provided are also save
+    to use on a "normal" 133MHz PLB bus system. Only the refresh counter
+    setup has to be adjusted as done in this patch.
+
+    For this the NAND booting version had to include the "speed.c" file
+    from the cpu/ppc4xx directory. With this addition the NAND SPL image
+    will just fit into the 4kbytes of program space. gcc version 4.x as
+    provided with ELDK 4.x is needed to generate this optimized code.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 781e026c8aa6f7e9eb5f0e72cc4d20971219b148
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Feb 28 00:02:04 2007 -0600
+
+    mpc83xx: fix implicit declaration of function 'ft_get_prop' warnings
+
+    (cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit)
+
+commit 4feab4de7bfc2cb2fed36ad76f93c3a69659bbaf
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Feb 27 23:51:42 2007 -0600
+
+    mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode
+
+    The config value for:
+    * CFG_ACR_PIPE_DEP
+    * CFG_ACR_RPTCNT
+    * CFG_SPCR_TSEC1EP
+    * CFG_SPCR_TSEC2EP
+    * CFG_SCCR_TSEC1CM
+    * CFG_SCCR_TSEC2CM
+
+    Were not being used when setting the appropriate register
+
+    Added:
+    * CFG_SCCR_USBMPHCM
+    * CFG_SCCR_USBDRCM
+    * CFG_SCCR_PCICM
+    * CFG_SCCR_ENCCM
+
+    To allow full config of the SCCR.
+
+    Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349
+    that were just bogus.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit d51b3cf371cd441030460ef19d36b2924c361b1a
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Thu Feb 22 20:06:57 2007 -0600
+
+    mpc83xx: update [local-]mac-address properties on UEC based devices
+
+    8360 and 832x weren't updating their [local-]mac-address
+    properties. This patch fixes that.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 61f4f912acbe60776c5e00df1ec94094ce672957
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Feb 13 10:41:42 2007 -0600
+
+    mpc83xx: write MAC address to mac-address and local-mac-address
+
+    Some device trees have a mac-address property, some have local-mac-address,
+    and some have both.  To support all of these device trees, this patch
+    updates ftp_cpu_setup() to write the MAC address to mac-address if it exists.
+    This function already updates local-mac-address.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 22d71a71f57fd5d38b27ac3848e50d790360a598
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Feb 27 18:41:08 2007 -0600
+
+    mpc83xx: add command line editing by default
+
+commit 3fc0bd159103b536e1c54c6f4457a09b3aba66ca
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Feb 14 19:50:53 2007 -0600
+
+    mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers
+
+    Disable G1TXCLK, G2TXCLK h/w buffers. This patch
+    fixes a networking timeout issue with MPC8360EA (Rev.2) PBs.
+
+    Verified on Rev. 1.1, Rev. 1.2, and Rev. 2.0 boards.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+    Signed-off-by: Emilian Medve <Emilian.Medve@freescale.com>
+
+commit d61853cf2472e0b8bcbd131461a93d1c49ff0c1f
+Author: Xie Xiaobo <r63061@freescale.com>
+Date:	Wed Feb 14 18:27:17 2007 +0800
+
+    mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xx
+
+    The code supply fixed and SPD initialization for MPC83xx DDR2 Controller.
+    it pass DDR/DDR2 compliance tests.
+
+    Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
+
+commit b110f40bd180c6b560276589beedf753e97c46ce
+Author: Xie Xiaobo <r63061@freescale.com>
+Date:	Wed Feb 14 18:27:06 2007 +0800
+
+    mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDS
+
+    MPC8360E rev2.0 have new spridr,and PVR value,
+    The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM.
+
+    Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
+
+commit 8d172c0f0d85998a256a95b7459a5403a30380ed
+Author: Xie Xiaobo <r63061@freescale.com>
+Date:	Wed Feb 14 18:26:44 2007 +0800
+
+    mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDS
+
+    MPC8349E rev3.1 have new spridr,and PVR value,
+    The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM.
+
+    Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
+
+commit f6f5f709e5c8e4564c4dfeecfdf2279244f9c83b
+Author: Joakim Tjernlund <joakim.tjernlund@transmode.se>
+Date:	Wed Jan 31 11:04:19 2007 +0100
+
+    mpc83xx: Fix empty i2c reads/writes in fsl_i2c.c
+
+    Fix empty i2c reads/writes, i2c_write(0x50, 0x00, 0, NULL, 0)
+    which is used to se if an slave will ACK after receiving its address.
+
+    Correct i2c probing to use this method as the old method could upset
+    a slave as it wrote a data byte to it.
+
+    Add a small delay in i2c_init() to let the controller
+    shutdown any ongoing I2C activity.
+
+    Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
+
+commit 7a78f148d6a7298e4fface680dc7eacd877b1aba
+Author: Timur Tabi <timur@freescale.com>
+Date:	Wed Jan 31 15:54:29 2007 -0600
+
+    mpc83xx: Add support for the MPC8349E-mITX-GP
+
+    Add support for the MPC8349E-mITX-GP, a stripped-down version of the
+    MPC8349E-mITX.  Bonus features include support for low-boot (BMS bit in
+    HRCW is 0) for the ITX and a README for the ITX and the ITX-GP.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit fab16807adad350f618024350c6950165c247c72
+Author: Timur Tabi <timur@freescale.com>
+Date:	Wed Jan 31 15:54:20 2007 -0600
+
+    mpc83xx: Delete sdram_init() for MPC8349E-mITX
+
+    There is no SDRAM on any of the 8349 ITX variants, so function sdram_init()
+    never does anything.  This patch deletes it.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit a87c856eb411b9365937d0d4b9c21e46adbe1c14
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Fri Jan 19 10:43:26 2007 +0800
+
+    mpc83xx: Fix the LAW1/3 bug
+
+    The patch solves the alignment problem of the local bus access windows to
+    render accessible the memory bank and PHY registers of UPC 1 (starting at
+    0xf801 0000). What we actually did was to adjust the sizes of the bus
+    access windows so that the base address alignment requirement would be met.
+
+    Signed-off-by: Chereji Marian <marian.chereji@freescale.com>
+    Signed-off-by: Gridish Shlomi <gridish@freescale.com>
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 97c4b397dce236a7318b304667bf89e59d08b17c
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Jan 30 16:15:31 2007 -0600
+
+    mpc83xx: don't hang if watchdog configured on 8360, 832x
+
+    don't hang if watchdog configured on 8360, 832x
+
+    The watchdog programming model is the same across all 83xx devices;
+    make the code reflect that.
+
+commit b70047478570e371ce7223be342ce98afea0f7d6
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Jan 30 16:15:21 2007 -0600
+
+    mpc83xx: protect memcpy to bad address if a local-mac-address is missing from dt
+
+    protect memcpy to bad address if a local-mac-address is missing from dt
+
+commit 6752ed088c75c26a89b70c46b7326a4cd6015f29
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Jan 30 16:15:04 2007 -0600
+
+    mpc83xx: make 8360 default environment fdt be 8360 (not 8349)
+
+    make 8360 default environment fdt be 8360 (not 8349)
+
+commit a28899c910024a0226331df07207b1038c300c93
+Author: Emilian Medve <Emilian.Medve@freescale.com>
+Date:	Tue Jan 30 16:14:50 2007 -0600
+
+    mpc83xx: Fix alternating tx error / tx buffer not ready bug in QE UEC
+
+    The problem is not gcc4 but the code itself. The BD_STATUS() macro can't
+    be used for busy-waiting since it strips the 'volatile' property from
+    the bd variable. gcc3 was working by pure luck.
+
+    This is a follow on patch to "Fix the UEC driver bug of QE"
+
+commit 3e78a31cfe3d3022f46f67eb88e1281d5cc2eb89
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Jan 30 14:08:30 2007 -0600
+
+    mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X instead
+
+    The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all
+    MPC834X class processors.  Change the protections from CONFIG_MPC8349 to
+    CONFIG_MPC834X so they are more generic.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit ae246dc6c1937c291014eadd90b6d48c438c7cb0
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Thu Jan 25 13:40:55 2007 -0600
+
+    mpc83xx: add MPC832XEMDS and sbc8349 to MAKEALL
+
+commit 4decd84e8f04279c5cfff7f8e907465ef8d8a3fb
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Jan 24 17:18:37 2007 -0600
+
+    mpc83xx: sort Makefile targets
+
+    reordered targets alphabetically
+
+commit 91e25769771c1164ed63ffca0add49f934ae3343
+Author: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date:	Tue Jan 16 11:38:14 2007 -0500
+
+    mpc83xx: U-Boot support for Wind River SBC8349
+
+    I've redone the SBC8349 support to match git-current, which
+    incorporates all the MPC834x updates from Freescale since the 1.1.6
+    release,  including the DDR changes.
+
+    I've kept all the SBC8349 files as parallel as possible to the
+    MPC8349EMDS ones for ease of maintenance and to allow for easy
+    inspection of what was changed to support this board.  Hence the SBC8349
+    U-Boot has FDT support and everything else that the MPC8349EMDS has.
+
+    Fortunately the Freescale updates added support for boards using CS0,
+    but I had to change spd_sdram.c to allow for board specific settings for
+    the sdram_clk_cntl (it is/was hard coded to zero, and that remains the
+    default if the board doesn't specify a value.)
+
+    Hopefully this should be mergeable as-is and require no whitespace
+    cleanups or similar, but if something doesn't measure up then let me
+    know and I'll fix it.
+
+    Thanks,
+    Paul.
+
+commit 05031db456ab227f3e3752f37b9b812b65bb83ad
+Author: Sam Song <samsongshu@yahoo.com.cn>
+Date:	Thu Dec 14 19:03:21 2006 +0800
+
+    mpc83xx: Remove a redundant semicolon in mpc8349itx.c
+
+    A redundant semicolon existed in mpc8349itx.c
+    should be removed.
+
+    Signed-off-by: Sam Song <samsongshu@yahoo.com.cn>
+
+commit f35f358241c549be3f75cfe2eaa642914275b7ba
+Author: Jerry Van Baren <gerald.vanbaren@comcast.net>
+Date:	Wed Dec 6 21:23:55 2006 -0500
+
+    mpc83xx: Put the version (and magic) after the HRCW.
+
+    Put the version (and magic) after the HRCW.  This puts it in a fixed
+    location in flash, not at the start of flash but as close as we can get.
+
+    Signed-off-by: Jerry Van Baren <vanbaren@cideas.com>
+
+commit 48aecd969171a6e99a55fae04933857787f9a5bd
+Author: Dave Liu <r63238@freescale.com>
+Date:	Thu Dec 7 21:14:51 2006 +0800
+
+    mpc83xx: Add the MPC832XEMDS board readme
+
+    Add the MPC832XEMDS board readme
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 24c3aca3f1358b113d3215adb5433b156e99f72b
+Author: Dave Liu <r63238@freescale.com>
+Date:	Thu Dec 7 21:13:15 2006 +0800
+
+    mpc83xx: Add support for the MPC832XEMDS board
+
+    This patch supports DUART, ETH3/4 and PCI etc.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit e080313c32322e15ab5a18eb896a252858c57284
+Author: Dave Liu <r63238@freescale.com>
+Date:	Thu Dec 7 21:11:58 2006 +0800
+
+    mpc83xx: streamline the 83xx immr head file
+
+    For better format and style, I streamlined the 83xx head files,
+    including immap_83xx.h and mpc83xx.h. In the old head files, 1)
+    duplicated macro definition appear in the both files; 2) the structure
+    of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The
+    macro definition put inside the each structure. So, I cleaned up the
+    structure of QE immr from immap_83xx.h, deleted the duplicated stuff and
+    moved the macro definition to mpc83xx.h, Just like MPC8260.
+
+    CHANGELOG
+
+    *streamline the 83xx immr head file
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit ddd02492f43db5408f5ab9f823b0ba5796e28ef0
+Author: Dave Liu <r63238@freescale.com>
+Date:	Wed Dec 6 11:38:17 2006 +0800
+
+    mpc83xx: Fix the UEC driver bug of QE
+
+    The patch prevents the GCC tool chain from striping useful code for
+    optimization. It will make UEC ethernet driver workable, Otherwise the
+    UEC will fail in tx when you are using gcc4.x. but the driver can work
+    when using gcc3.4.3.
+
+    CHANGELOG
+
+    *Prevent the GCC from striping code for optimization, Otherwise the UEC
+    will tx failed when you are using gcc4.x.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Mar 1 21:11:36 2007 +0100
+
+    [PATCH] Update AMCC Katmai 440SPe eval board support
+
+    This patch updates the recently added Katmai board support. The biggest
+    change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
+    driver.
+
+    Please note, that still some problems are left with some memory
+    configurations. See the driver for more details.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8c12045a3b06c5b6675d3fe02fbc9f545988129a
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Mar 1 07:03:25 2007 +0100
+
+    [PATCH] I2C: Add missing default CFG_RTC_BUS_NUM & CFG_DTT_BUS_NUM
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ccbc7036648e465697ca298ba51e0e76dda352a0
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Wed Feb 28 01:28:53 2007 +0100
+
+    SC3: fix typo in default environment
+
+commit e344568b1b46af85ec32d815586f91bc115d6223
+Author: Sergei Poselenov <sposelenov@emcraft.com>
+Date:	Tue Feb 27 20:15:30 2007 +0300
+
+    MCC200: Fixes for update procedure
+
+    - fix logic error in image type handling
+    - make sure file system images (cramfs etc.) get stored in flash
+      with image header stripped so they can be mounted through MTD
+
+commit 743571145b37182757d4e688a77860b36ee77573
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Tue Feb 27 14:26:04 2007 +0100
+
+    Minor code cleanup.
+
+commit 638dd1458bbdc2a55d4b9e25c5c4e1f838a5dc72
+Author: Sergei Poselenov <sposelenov@emcraft.com>
+Date:	Tue Feb 27 12:40:16 2007 +0300
+
+    MCC200 update - add LCD Progress Indicator
+
+commit 6c7cac8c4fce0ea2bf8e15ed8658d87974155b44
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Feb 22 07:43:34 2007 +0100
+
+    [PATCH] get_dev() now unconditionally uses manual relocation
+
+    Since the relocation fix is not included yet and we're not sure how
+    it will be added, this patch removes code that required relocation
+    to be fixed for now.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 8274ec0bd01d2feb2c7f095eba78d42ea009798b
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Feb 22 07:40:23 2007 +0100
+
+    [PATCH] Change systemace driver to select 8 & 16bit mode
+
+    As suggested by Grant Likely this patch enables the Xilinx SystemACE
+    driver to select 8 or 16bit mode upon startup.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 3a197b2fe49d6fa03978e60af2394efe9c70b527
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date:	Wed Feb 21 16:52:31 2007 +0100
+
+    [PATCH v3] Add sync to ensure flash_write_cmd is fully finished
+
+    Some CPUs like PPC, BLACKFIN need sync() to ensure cfi flash write command
+    is fully finished. The sync() is defined in each CPU's io.h file. For
+    those CPUs which do not need sync for now, a dummy sync() is defined in
+    their io.h as well.
+
+    Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit da04995c7dc6772013a9a0dc5c767f190c402478
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Feb 21 13:44:34 2007 +0100
+
+    [PATCH] Fix problem in systemace driver (ace_writew instead of ace_write)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 751bb57107d78978ae08e697c3deba816f5be091
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Feb 20 13:21:57 2007 +0100
+
+    [PATCH] Fix relocation problem with "new" get_dev() function
+
+    This patch enables the "new" get_dev() function for block devices
+    introduced by Grant Likely to be used on systems that still suffer
+    from the relocation problems (manual relocation neede because of
+    problems with linker script).
+
+    Hopefully we can resolve this relocation issue soon for all platform
+    so we don't need this additional code anymore.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d93e2212f962668b3dce091ff5edc33f2347fe37
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Feb 20 13:17:42 2007 +0100
+
+    [PATCH] Update SystemACE driver for 16bit access
+
+    This patch removes some problems when the Xilinx SystemACE driver
+    is used with 16bit access on an big endian platform (like the
+    AMCC Katmai).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 874bb7b88fe9b4648e1288a387af2e31014a72f3
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Feb 20 13:15:40 2007 +0100
+
+    [PATCH] Clean up Katmai (440SPe) linker script
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4745acaa1a603b67f6b9b7970365ebadd7d6586f
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Feb 20 10:57:08 2007 +0100
+
+    [PATCH] Add support for the AMCC Katmai (440SPe) eval board
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0dc018ece13effc689e47479ea9ebf1c98a507f5
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Feb 20 10:51:26 2007 +0100
+
+    [PATCH] I2C: Add support for multiple I2C busses for RTC & DTT
+
+    This patch switches to the desired I2C bus when the date/dtt
+    commands are called. This can be configured using the
+    CFG_RTC_BUS_NUM and/or CFG_DTT_BUS_NUM defines.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4037ed3b63923cfcec27f784a89057c3cbabcedb
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Feb 20 10:43:34 2007 +0100
+
+    [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM support
+
+    This patch adds support for the DDR2 controller used on the
+    440SP and 440SPe. It is tested on the Katmai (440SPe) eval
+    board and works fine with the following DIMM modules:
+
+    - Corsair CM2X512-5400C4 (512MByte per DIMM)
+    - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM)
+    - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM)
+
+    This patch also adds the nice functionality to dynamically
+    create the TLB entries for the SDRAM (tlb.c). So we should
+    never run into such problems with wrong (too short) TLB
+    initialization again on these platforms.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 36d830c9830379045f5daa9f542ac1c990c70068
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Feb 20 10:35:42 2007 +0100
+
+    [PATCH] PPC4xx: Split 4xx SPD SDRAM init routines into 2 files
+
+    Since the existing 4xx SPD SDRAM initialization routines for the
+    405 SDRAM controller and the 440 DDR controller don't have much in
+    common this patch splits both drivers into different files.
+
+    This is in preparation for the 440 DDR2 controller support (440SP/e).
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 79b2d0bb2eae09602448f7a7cb56530d2f31e6c6
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Feb 20 10:27:08 2007 +0100
+
+    [PATCH] PPC4xx: Add support for multiple I2C busses
+
+    This patch adds support for multiple I2C busses on the PPC4xx
+    platforms. Define CONFIG_I2C_MULTI_BUS in the board config file
+    to make use of this feature.
+
+    It also merges the 405 and 440 i2c header files into one common
+    file 4xx_i2c.h.
+
+    Also the 4xx i2c reset procedure is reworked since I experienced
+    some problems with the first access on the 440SPe Katmai board.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit eb867a76238fb38e952c37871b16d0d7fd61c95f
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Feb 20 09:05:45 2007 +0100
+
+    [PATCH 9_9] Use "void *" not "unsigned long *" for block dev read_write buffer pointers
+
+    Block device read/write is anonymous data; there is no need to use a
+    typed pointer.  void * is fine.  Also add a hook for block_read functions
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 53758fa20e935cc87eeb0519ed365df753a6f289
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Feb 20 09:05:38 2007 +0100
+
+    [PATCH 8_9] Add block_write hook to block_dev_desc_t
+
+    Preparation for future patches which support block device writing
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit f4852ebe6ca946a509667eb68be42026f837be76
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Feb 20 09:05:31 2007 +0100
+
+    [PATCH 7_9] Replace ace_readw_ace_writeb functions with macros
+
+    Register read/write does not need to be wrapped in a full function.  The
+    patch replaces them with macros.
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 3a8ce9af6fcb5744a7851b4440c07688acc40844
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Feb 20 09:05:23 2007 +0100
+
+    [PATCH 6_9] Move common_cmd_ace.c to drivers_systemace.c
+
+    The code in this file is not a command; it is a device driver.  Put it in
+    the correct place.	There are zero functional changes in this patch, it
+    only moves the file.
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 984618f3e7794c783ec8d1511e74c6ee2d69bfe4
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Feb 20 09:05:16 2007 +0100
+
+    [PATCH 5_9] Whitespace fixup on common_cmd_ace.c (using Lindent)
+
+    This patch is in preparation of additional changes to the sysace driver.
+    May as well take this opportunity to fixup the inconsistent whitespace since
+    this file is about to undergo major changes anyway.
+
+    There are zero functional changes in this patch.  It only cleans up the
+    the whitespace.
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 80ba981d940471fe7e539e64fa3d2bd80002beda
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Feb 20 09:05:07 2007 +0100
+
+    [PATCH 4_4] Remove local implementation of isprint() in ft_build.c
+
+    isprint is already defined in ctype.c
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit c95c4280d751ca078c2ff58228d2f2b44ccf0600
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Feb 20 09:05:00 2007 +0100
+
+    [PATCH 3_9] Move buffer print code from md command to common function
+
+    Printing a buffer is a darn useful thing.  Move the buffer print code
+    into print_buffer() in lib_generic/
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 99b0f0fd3fbf2572ae1a7723dd90cffc8e85130a
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Feb 20 09:04:52 2007 +0100
+
+    [PATCH 2_4] Use config.h, not xparameters.h, for xilinx targets
+
+    Change the xilinx device drivers and board code to include config.h
+    instead of xparameters.h directly.	config.h always includes the
+    correct xparameters file.  This change reduces the posibility of
+    including the wrong file when adding a new xilinx board port
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 735dd97b1b20e777d059c7b389fe9d70cd3f80c7
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Tue Feb 20 09:04:34 2007 +0100
+
+    [PATCH 1_4] Merge common get_dev() routines for block devices
+
+    Each of the filesystem drivers duplicate the get_dev routine.  This change
+    merges them into a single function in part.c
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit f5fcc3c20b65554e98a165542c36ee0c610a2d81
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Mon Feb 19 23:09:51 2007 +0100
+
+    MCC200: Software Updater: allow both "ramdisk" and "filesystem" types
+    as root file system images.
+
+commit 489c696ae7211218961d159e43e722d74c36fcbc
+Author: Sergei Poselenov <sposelenov@emcraft.com>
+Date:	Wed Feb 14 14:30:28 2007 +0300
+
+    MCC200: Extensions to Software Update Mechanism
+
+    Update / extend Software Update Mechanism for MCC200 board:
+
+    - Add support for rootfs image added. The environment variables
+      "rootfs_st" and "rootfs_nd" can be used to override the default
+      values of the image start and end.
+    - Remove excessive key check code.
+    - Code cleanup.
+
+commit 4be23a12f23f1372634edc3215137b09768b7949
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Feb 19 08:23:15 2007 +0100
+
+    [PATCH] Update Sequoia EBC configuration (NOR FLASH)
+
+    As spotted by Matthias Fuchs, the READY input should not be
+    enabled for the NOR FLASH on the Sequoia board.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2605e90bf676d48123afe5719a846d2b52b24aac
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Fri Feb 16 07:57:42 2007 +0100
+
+    [PATCH] Added support for the jupiter board.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 497d012e5be0194e1084073d0081eb1a844796b2
+Author: Gary Jennejohn <garyj@pollux.denx.de>
+Date:	Mon Feb 12 13:11:50 2007 +0100
+
+    LPC2292: patch from Siemens.
+
+commit b0b1a920aebead0d44146e73676ae9d80fffc8e2
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Feb 10 08:49:31 2007 +0100
+
+    [PATCH] Add missing p3mx.h file to repository (ups)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 53d4a4983fb9b3ae5f7b2f10c599aca2b1b4034a
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Fri Feb 9 10:45:42 2007 +0100
+
+    [Motion-PRO] Preliminary support for the Motion-PRO board.
+
+commit 5a753f98c6a01bd1c61a9a3f95e8329a35f62994
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Feb 7 16:51:08 2007 +0100
+
+    [PATCH] Update some AMCC 4xx board config files (set initrd_high)
+
+    Some boards that can have more than 768MBytes of SDRAM need to
+    set "initrd_high", so that the initrd can be accessed by the
+    Linux kernel.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 7372ca68227930d03cffa548310524cad5b96733
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Feb 2 12:44:22 2007 +0100
+
+    [PATCH] Correctly display PCI arbiter en-/disabled on some 4xx boards
+
+    Previously the strapping DCR/SDR was read to determine if the internal PCI
+    arbiter is enabled or not. This strapping bit can be overridden, so now
+    the current status is read from the correct DCR/SDR register.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2aa54f651a42d198673318f07a20c89a43e4d197
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Feb 2 12:42:08 2007 +0100
+
+    [PATCH] Change configuration output of Sycamore, Yellowstone & Rainier
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 23744d6b5bf17592eb6a0ef4f318f6089f55993b
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Feb 1 13:22:41 2007 +0100
+
+    [PATCH] Remove PCI-PNP configuration from Sequoia/Rainier config file
+
+    When PCI PNP is enabled the pci pnp configuration routine is called
+    which sets the PCI_CACHE_SIZE_LINE to 8. This seems to generate some
+    problems with some PCI cards. For now disable the PCI PNP configuration.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2902fadade3be7659467e8d074048c6b7068f5c0
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 31 16:56:10 2007 +0100
+
+    [PATCH] Update 440EPx/440GRx cpu detection
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d5ea287b02a6945c3977410e364a879dd1a555c8
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 31 16:38:04 2007 +0100
+
+    [PATCH] Update esd cpci5200 files
+
+    Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit 8b7d1f0ab7d7c4fe3160bbf74a7e9690d9f3a3ab
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 31 16:37:34 2007 +0100
+
+    [PATCH] Add support for esd mecp5200 board
+
+    Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+
+commit 71a4e5fda8b60044ab9f46069fa1cfa26bdd07ff
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Jan 31 12:38:50 2007 +0100
+
+    [PATCH] Remove unneccessary yellowstone board config file
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e802594b6fa1b166308820c276b96dc0d7cc731c
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jan 30 17:06:10 2007 +0100
+
+    [PATCH] Update Sequoia (440EPx) config file
+
+    The config file now handles the 2nd target, the Rainier (440GRx)
+    evaluation board better. Additionally the PPC input clock was
+    adjusted to match the correct value of 33.0 MHz.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 700200c67e73b83751418abe7815840dca8fd6cb
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jan 30 17:04:19 2007 +0100
+
+    [PATCH] Merge Yosemite & Yellowstone board ports
+
+    Now the AMCC eval boards Yosemite (440EP) and Yellowstone (440GR)
+    share one config file and all board specific files. This way we
+    don't have to maintain two different sets of files for nearly
+    identical boards.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1bbf5eae322f5f1f6427ecc3ac13a0cb7dba8ad6
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jan 30 15:01:49 2007 +0100
+
+    [PATCH] Update Prodrive SCPU (PDNB3 variant) board
+
+    SCPU doesn't use redundant environment in flash.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6304430ed642ea8fa15c9e5af965ac2e033eec45
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Jan 30 12:51:07 2007 +0100
+
+    [PATCH] alpr: Update alpr board config file
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f8db84f132b1e335f20f96138a1f09ed97b08664
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Tue Jan 30 00:50:40 2007 +0100
+
+    LPC2292 SODIMM port coding style cleanup.
+
+commit 6bd2447ee47ee23c18d2b3c7ccd5a20f7626f5b3
+Author: Gary Jennejohn <garyj@pollux.denx.de>
+Date:	Wed Jan 24 12:16:56 2007 +0100
+
+    Add port for the lpc2292sodimm evaluation board from EmbeddedArtists
+
+commit 2daf046ba627f85f44195815778140039636244e
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Tue Jan 23 17:22:06 2007 +0100
+
+    [iDMR] Add MTD and JFFS2 support, also add default partition definition.
+
+commit f7db33101fbc9c8f0a10738ce87034875a17aeb9
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Tue Jan 23 14:21:14 2007 +0100
+
+    [iDMR] Flash driver on initialisation write-protects some sectors,
+    currently sectors 0-3. Sector 3 does not need to be protected, though
+    (U-boot occupies sectors 0-1 and the environment sector 2). This commit
+    fixes this, i.e., only sectors 0-2 are protected.
+
+commit 0ed47bb119cd2c4c16edb2548789148f9e6dc9de
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Tue Jan 23 14:11:22 2007 +0100
+
+    [iDMR] Using MII-related commands on iDRM board doesn't work now (e.g.,
+    "mii device" results in "Unexpected exception"). Fixing this properly
+    requires some clean-up in the FEC drivers infrastructure for ColdFire, so
+    this commit disables MII commads for now.
+
+commit 363d1d8f9c99b63daef81f5985cab3fc00edde5c
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Tue Jan 23 13:25:22 2007 +0100
+
+    [ColdFire MCF5271 family] Add CPU detection based on the value of Chip
+    Identification Register (CIR).
+
+commit a4012396645533aef218354eeba754dff0deace8
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Fri Jan 19 23:08:39 2007 +0100
+
+    Minor code cleanup.
+
+commit f539b7ba7d7ef6dd187c8209609001cb1cd95e39
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Fri Jan 19 19:57:10 2007 +0100
+
+    [PATCH] SC3 board: added CFG_CMD_AUTOSCRIPT.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit d0b6e14087ddd8789f224a48e1d33f2a5df4d167
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Fri Jan 19 18:05:26 2007 +0100
+
+    [PATCH] CFI: define CFG_WRITE_SWAPPED_DATA for the CFI-Flash driver
+		 if you must swap the bytes between reading/writing.
+		 (Needed for the SC3 board)
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 9d8d5a5bfb64768f29a0cb47fc37cd6f4c40e276
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jan 18 16:05:47 2007 +0100
+
+    [PATCH] Add support for Prodrive SCPU (PDNB3 variant) board
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0057d758e3e874cbe7f24745d0cce8c1cb6c207e
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jan 18 11:54:52 2007 +0100
+
+    [PATCH] Update Prodrive P3Mx support
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 34167a36c29ee946b727465db5c014746a08e978
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jan 18 11:48:10 2007 +0100
+
+    [PATCH] Add missing Taishan config file
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit cb4820725e9fc409c5cbc8e83054a6ed522d2111
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Thu Jan 18 11:28:51 2007 +0100
+
+    [PATCH] Fix: Compilerwarnings for SC3 board.
+		 The EBC Configuration Register is now by CFG_EBC_CFG definable
+		 Added JFFS2 support for the SC3 board.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 5fb692cae57d1710c8f52a427cf7f39a37383fcd
+Author: Stefan Roese <sr@denx.de>
+Date:	Thu Jan 18 10:25:34 2007 +0100
+
+    [PATCH] Add support for AMCC Taishan PPC440GX eval board
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 6d3e0107235aa0e6a6dcb77f9884497280bf85ad
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Tue Jan 16 18:30:50 2007 +0100
+
+    Raname solidcard3 into sc3; add redundant env for sc3
+
+commit 1bbbbdd20fcec9933697000dcf55ff7972622596
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Tue Jan 16 12:46:35 2007 +0100
+
+    Update default environment for Solidcard3
+
+commit 5a5c56986a9ccf71642c8b6374eb18487b15fecd
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Jan 15 09:46:29 2007 +0100
+
+    [PATCH] Fix 440SPe rev B detection from previous patch
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a443d31410c571ee8f970da819a44d698fdd6b1f
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Sun Jan 14 13:35:31 2007 +0100
+
+	[FIX] correct I2C Writes for the LM81 Sensor.
+
+	Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 0bba5452835f19a61204edcda3a58112fd8e2208
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Sat Jan 13 11:17:10 2007 +0100
+
+    Undo commit 3033ebb2: reset command does not take any arguments
+
+    Haiying Wang's modification to the reset command was broken, undo it.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 95981778cff0038fd9941044d6a3eda810e33258
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Jan 13 08:01:03 2007 +0100
+
+    [PATCH] Update 440SP(e) cpu revisions
+
+    Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 77ddc5b9afb325262fd88752ba430a1dded1f0c7
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Jan 13 07:59:56 2007 +0100
+
+    [PATCH] Update Yellowstone (440GR) to display board rev and PCI bus speed
+
+    Now the board revision and the current PCI bus speed are printed after
+    the board message.
+
+    Also the EBC initialising is now done via defines in the board config
+    file.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 36adff362c2c0141ff8a810d42a7e478f779130f
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Jan 13 07:59:19 2007 +0100
+
+    [PATCH] Update Yosemite (440EP) to display board rev and PCI bus speed
+
+    Now the board revision and the current PCI bus speed are printed after
+    the board message.
+
+    Also the EBC initialising is now done via defines in the board config
+    file.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e0b9ea8c8a294de6a5350ae638879d24b5b709d6
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Jan 13 07:57:51 2007 +0100
+
+    [PATCH] Update Sequoia (440EPx) to display board rev and PCI bus speed
+
+    Now the board revision and the current PCI bus speed are printed after
+    the board message.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ca43ba18e910206ef8063e4b22d282630bff3fd2
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Thu Jan 11 15:44:44 2007 +0100
+
+	Added support for the SOLIDCARD III board from Eurodesign
+
+	Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 6abaee42621c07e81a2cd189ad4368b5e8c50280
+Author: Reinhard Thies <Reinhard.Thies@web.de>
+Date:	Wed Jan 10 14:41:14 2007 +0100
+
+    Adjusted default environment for cam5200 board.
+
+commit bab5a90d4ccc1a46a8127b867fa59028cc623ad9
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Wed Jan 10 15:35:52 2007 +0100
+
+    Update CHANGELOG
+
+commit 787fa15860a57833e50bd30555079a9cd4e519b8
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Wed Jan 10 01:28:39 2007 +0100
+
+    Fix auto_update for MCC200 board.
+
+    The invocation of do_auto_update() is moved to the end of the
+    misc_init_r() function, after the flash mappings have been
+    initialized. Please find attached a patch that implements that
+    change.
+
+    Also correct the decoding of the keypad status. With this update, the
+    key that will trigger the update is Column 2, Row 2.
+
+commit d9384de2f571046e71081bae22b49e3d5ca2e3d5
+Author: Marian Balakowicz <m8@semihalf.com>
+Date:	Wed Jan 10 00:26:15 2007 +0100
+
+    CAM5200 flash driver modifications:
+    - use CFI driver (replaces custom flash driver) for main 'cam5200' target
+    - add second build target 'cam5200_niosflash' which still uses custom driver
+
+commit 67fea022fa957f59653b5238c7496f80a6b70432
+Author: Markus Klotzbuecher <mk@denx.de>
+Date:	Tue Jan 9 16:02:48 2007 +0100
+
+    SPC1920: cleanup memory contoller setup
+
+commit 8fc2102faa23593c80381437c09f7745a14deb40
+Author: Markus Klotzbuecher <mk@denx.de>
+Date:	Tue Jan 9 14:57:14 2007 +0100
+
+    Fix the cpu speed setup to work with all boards.
+
+commit 9295acb77481cf099ef9b40e1fa2d145b3c7490c
+Author: Markus Klotzbuecher <mk@denx.de>
+Date:	Tue Jan 9 14:57:13 2007 +0100
+
+    SPC1920: add support for the FM18L08 Ramtron FRAM
+
+commit 38ccd2fdf3364a53fe80e9b365303ecdafc9e223
+Author: Markus Klotzbuecher <mk@denx.de>
+Date:	Tue Jan 9 14:57:13 2007 +0100
+
+    SPC1920: update the HPI register addresses to work with the second
+    generation of hardware
+
+commit 5921e5313fc3eadd42770c2b99badd7fae5ecf1e
+Author: Markus Klotzbuecher <mk@creamnet.de>
+Date:	Tue Jan 9 14:57:13 2007 +0100
+
+    Miscellanious spc1920 related cleanups
+
+commit e4c2d37adc8bb1bf69dcf600cbc6c75f916a6120
+Author: Markus Klotzbuecher <mk@denx.de>
+Date:	Tue Jan 9 14:57:12 2007 +0100
+
+    SPC1920 GO/NOGO led should be set to color red in U-Boot
+
+commit 0be62728aac459ba268d6d752ed49ec0e2bc7348
+Author: Markus Klotzbuecher <mk@creamnet.de>
+Date:	Tue Jan 9 14:57:12 2007 +0100
+
+    Add support for the DS3231 RTC
+
+commit 8139567b60d678584b05f0718a681f2047c5e14f
+Author: Markus Klotzbuecher <mk@creamnet.de>
+Date:	Tue Jan 9 14:57:11 2007 +0100
+
+    SMC1 uses external CLK4 instead of BRG on spc1920
+
+commit d8d9de1a02fbd880b613d607143d1f57342affc7
+Author: Markus Klotzbuecher <mk@creamnet.de>
+Date:	Tue Jan 9 14:57:10 2007 +0100
+
+    Update the SPC1920 CMB PLD driver
+
+commit 3f34f869162750e5e999fd140f884f5de952bcfe
+Author: Markus Klotzbuecher <mk@creamnet.de>
+Date:	Tue Jan 9 14:57:10 2007 +0100
+
+    Add / enable I2C support on the spc1920 board
+
+commit d28707dbce1e9ac2017ad051da4133bf22b4204f
+Author: Markus Klotzbuecher <mk@creamnet.de>
+Date:	Tue Jan 9 14:57:10 2007 +0100
+
+    Add support for the tms320671x host port interface (HPI)
+
+commit f4eb54529bb3664c3a562e488b460fe075f79d67
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Sun Jan 7 00:13:11 2007 +0100
+
+    Prepare for release 1.2.0
+
+commit f07ae7a9daef27a3d0213a4f3fe39d5342173c02
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Jan 6 15:58:09 2007 +0100
+
+    [PATCH] 44x: Fix problem with DDR controller setup (refresh rate)
+
+    This patch fixes a problem with an incorrect setup for the refresh
+    timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f16c1da9577f06c5fc08651a4065537407de4635
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Jan 6 15:56:13 2007 +0100
+
+    [PATCH] Update ALPR board files
+
+    This update brings the ALPR board support to the newest version.
+    It also fixes a problem with the NAND driver.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit cd1d937f90250a32988c37b2b4af8364d25de8ed
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jan 5 11:46:05 2007 +0100
+
+    [PATCH] nand: Fix problem with oobsize calculation
+
+    Here the description from Brian Brelsford <Brian_Brelsford@dell.com>:
+
+    The Hynix part returns a 0x1d in the 4th ID byte. The Samsung part
+    returns a 0x15. In the code fragment below bits [1:0] determine the
+    page size, it is ANDed via "(extid & 0x3)" then shifted out. The
+    next field is also ANDed with 0x3. However this is a one bit field
+    as defined in the Hynix and Samsung parts in the 4th ID byte that
+    determins the oobsize, not a two bit field. It works on Samsung as
+    bits[3:2] are 01. However for the Hynix there is a 11 in these two
+    bits, so the oob size gets messed up.
+
+    I checked the correct linux code and the suggested fix from Brian is
+    also available in the linux nand mtd driver.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit a78bc443ae5a4a8ba87590587d5e35bf5a787b2e
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jan 5 10:40:36 2007 +0100
+
+    [PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx)
+
+    This fix will make the MAL burst disabling patch for the Linux
+    EMAC driver obsolete.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 023889838282b6237b401664f22dd22dfba2c066
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Jan 5 10:38:05 2007 +0100
+
+    [PATCH] Add DDR2 optimization code for Sequoia (440EPx) board
+
+    This code will optimize the DDR2 controller setup on a board specific
+    basis.
+
+    Note: This code doesn't work right now on the NAND booting image for the
+    Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit cce4acbb68398634b8d011ed7bb0d12269c84230
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Thu Dec 28 19:08:21 2006 +0100
+
+    Few V38B changes:
+      - fix a typo in V38B config file
+      - move watchdog initialisation earlier in the boot process
+      - add "wdt=off" to default kernel command line (disables kernel watchdog)
+
+commit 92eb729bad876725aeea908d2addba0800620840
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Wed Dec 27 01:26:13 2006 +0100
+
+    Fix bug in adaption of Stefano Babic's CFI driver patch.
+
+commit 9c0f42ecfe25f7ffce8ec7a815f03864d723ffe3
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Sun Dec 24 01:42:57 2006 +0100
+
+    Minor code cleanup.
+
+commit d784fdb05900ada3686d5778783e1fb328e9fb66
+Author: Stefano Babic <sbabic@denx.de>
+Date:	Tue Dec 12 00:22:42 2006 +0100
+
+    Fix cfi failure with Spansion Flash (Spansion Flash Devices have a different offset to go into CFI mode)
+
+commit 1b3c360c235dc684ec06c2d5f183f0a282ce45e2
+Author: Stefan Roese <sr@denx.de>
+Date:	Fri Dec 22 14:29:40 2006 +0100
+
+    [PATCH] Fix sequoia flash autodetection (finally correct)
+
+    Now 32MByte and 64MByte FLASH is know to work and other
+    configurations should work too.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 82e5236a8b719543643fd26d5827938ab2b94818
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Fri Dec 22 10:30:26 2006 +0100
+
+    Minor code cleanup; update CHANGELOG.
+
+commit fa23044564091f05d9695beb7b5b9a931e7f41a4
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Thu Dec 21 17:17:02 2006 +0100
+
+    Added support for the TQM8272 board from TQ
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit 6dedf3d49dd14c3bf541c8ecee7ffaac5f0e1d6c
+Author: Heiko Schocher <hs@pollux.denx.de>
+Date:	Thu Dec 21 16:14:48 2006 +0100
+
+    [PATCH] Add support for the UC101 board from MAN.
+
+    Signed-off-by: Heiko Schocher <hs@denx.de>
+
+commit c84bad0ef60e7055ab0bd49b93069509cecc382a
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Wed Dec 20 00:29:43 2006 +0100
+
+    Fix to make the baudrate changes immediate for the MCF52x2 family.
+
+commit daa6e418bcc0c717752e8de939c213c790286096
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date:	Wed Dec 20 00:27:32 2006 +0100
+
+    Preliminary support for the iDMR board (ColdFire).
+
+commit cdb97a6678826f85e7c69eae6a1c113d034c9b10
+Author: Andrei Safronov <safronov@pollux.denx.de>
+Date:	Fri Dec 8 16:23:08 2006 +0100
+
+    automatic update mechanism
+
+commit dd520bf314c7add4183c5191692180f576f96b60
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Thu Nov 30 18:02:20 2006 +0100
+
+    Code cleanup.
+
+commit 8d9a8610b8256331132227e9e6585c6bd5742787
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Thu Nov 30 01:54:07 2006 +0100
+
+    Code cleanup. Update CHANGELOG.
+
+commit 726e90aacf0b1ecb0e7055be574622fbe3e450ba
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date:	Wed Nov 29 16:23:42 2006 +0100
+
+    [PATCH] [MPC52xx] Use IPB bus frequency for SOC peripherals
+
+    The soc node of the mpc52xx needs to be loaded with the IPB bus frequency,
+    not the XLB frequency.
+
+    This patch depends on the previous patches for MPC52xx device tree support
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+    Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
+
+commit 1eac2a71417b6675b11aace72102a2e7fde8f5c6
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Nov 29 15:42:37 2006 +0100
+
+    [PATCH] Add support for Prodrive P3M750 & P3M7448 (P3Mx) boards
+
+    This patch adds support for the Prodrive P3M750 (PPC750 & MV64460)
+    and the P3M7448 (MPC7448 & MV64460) PMC modules. Both modules are
+    quite similar and share the same board directory "prodrive/p3mx"
+    and the same config file "p3mx.h".
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1bdd46832aeb569f5e04b1f20f64318525b6525a
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Nov 29 12:53:15 2006 +0100
+
+    [PATCH] common/cmd_elf.c: Enable loadaddr as parameter in bootvx command
+
+    In the bootvx command the load address was only read from the env
+    variable "loadaddr" and not optionally passed as paramter as described
+    in the help. This is fixed with this patch. The behaviour is now the
+    same as in the bootelf command.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4e26f1074c3ac1bd8fd094f0dc4a1c4a0b15a592
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Nov 29 12:03:57 2006 +0100
+
+    [PATCH] include/ppc440.h minor error affecting interrupts
+
+    Fixed include/ppc440.c for UIC address Bug
+
+    Corrects bug affecting the addresses for the universal interrupt
+    controller UIC2 and UIC3 on the PPC440 Epx, GRx, and SPE chips.
+
+    Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1939d969443ccf316cab2bf32ab1027d4db5ba1a
+Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
+Date:	Tue Nov 28 16:17:27 2006 -0600
+
+    Make fsl-i2c not conflict with SOFT I2C
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 14198bf768fdc958e3c1afd2404e5262208e98d7
+Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
+Date:	Tue Nov 28 16:17:18 2006 -0600
+
+    Fix I2C master address initialization.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit cf3d045e51ca8dcc6cf759827140861d6ac25c04
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Nov 28 23:31:19 2006 -0600
+
+    Assign maintainers for mpc8349emds and mpc8360emds
+
+    Dave for mpc8360emds, and me for mpc8349emds.
+
+commit 1aa934c81b77f2080d3ca4b226eab67b17a33961
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Tue Nov 28 23:28:33 2006 -0600
+
+    Eliminate gcc 4 'used uninitialized' warnings in drivers/qe/uccf.c
+
+    give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src
+    since they are passed by reference to ucc_get_cmxucr_reg and assigned.
+
+commit e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Nov 28 12:09:35 2006 -0600
+
+    mpc83xx: Miscellaneous code style fixes
+
+    Implement various code style fixes and similar changes.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit e59581c56ab5d6e0207ddac3b2c1d55cb36ec706
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Nov 28 17:55:49 2006 +0100
+
+    [PATCH] Enable the IceCube/lite5200 variants to pass a device tree to Linux.
+
+    This patch adds the code and configuration necessary to boot with an
+    arch/powerpc Linux kernel.
+
+    Signed-off-by: Grant Likely <grant.likely@gmail.com>
+    Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit e732faec95a83cb468b4850ae807c8301dde8f6a
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Nov 28 16:09:24 2006 +0100
+
+    [PATCH] PPC4xx: 440SP Rev. C detection added
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit e7f3e9ff01fbd7fa72eb42a9675fbed6bc4736b0
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Nov 28 11:04:45 2006 +0100
+
+    [PATCH] nand: Fix patch merge problem
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 58e3b14c18ed3288ceef8d086946dbf3df64ccf2
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Nov 28 11:04:45 2006 +0100
+
+    [PATCH] nand: Fix patch merge problem
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4f4b602ec7524a032bdf3c6d28c7f525a4a67eaa
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Mon Nov 27 22:53:53 2006 +0100
+
+    Update CHANGELOG
+
+commit f6e495f54cdb8fe340b9c03deab40ad746d52fae
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 27 17:43:25 2006 +0100
+
+    [PATCH] 4xx_enet.c: Correct the setting of zmiifer register
+
+    Patch below corrects the setting of the zmiifer register, it was
+    overwritting the register rather than ORing the settings.
+
+    Signed-off-by: Neil Wilson <NWilson@airspan.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit d1a72545296800b7e219f93104ad5836f0003d66
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 27 17:34:10 2006 +0100
+
+    [PATCH] Select NAND embedded environment from board configuration
+
+    The current NAND Bootloader setup forces the environment
+    variables to be in line with the bootloader. This change
+    enables the configuration to be made in the board include
+    file instead so that it can be individually enabled.
+
+    Signed-off-by: Nick Spence <nick.spence@freescale.com>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 15784862857c3c2214498defcfed84ff137fb81e
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 27 17:22:19 2006 +0100
+
+    [PATCH] nand_wait() timeout fixes
+
+    Two fixes for the nand_wait() function in
+    drivers/nand/nand_base.c:
+
+    1. Use correct timeouts. The original timeouts in Linux
+    source are 400ms and 20ms not 40s and 20s
+
+    2. Return correct error value in case of timeout. 0 is
+    interpreted as OK.
+
+    Signed-off-by: Rui Sousa <rui.sousa@laposte.net>
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit da5553b095bf04f4f109ad7e565dae3aba47b230
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 27 17:04:06 2006 +0100
+
+    [PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel
+
+    This patch allows an arch/ppc kernel to be booted by just passing 1 or 2
+    arguments to bootm.  It removes the getenv("disable_of") test that used
+    to be used for this purpose.
+
+    Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+    Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit a9398e018593782c5fa7d0741955fc1256b34c1e
+Author: Wolfgang Denk <wd@pollux.denx.de>
+Date:	Mon Nov 27 15:32:42 2006 +0100
+
+    Minor code cleanup. Update CHANGELOG.
+
+commit 1729b92cde575476684bffe819d0b7791b57bff2
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 27 14:52:04 2006 +0100
+
+    [PATCH] 4xx: Fix problem with board specific reset code (now for real)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit cc5ee8a92a0e3ca6f727af71b8fd206460c7afd7
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 27 14:49:51 2006 +0100
+
+    [PATCH] alpr: remove unused board specific flash driver
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1f94d162e2b5f0edc28d9fb11482502c44d218e1
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 27 14:48:41 2006 +0100
+
+    [PATCH] 4xx: Fix problem with board specific reset code
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ec0c2ec725aec9524a177a77ce75559e644a931a
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 27 14:46:06 2006 +0100
+
+    [PATCH] Remove testing 4xx enet PHY setup
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 1c2ce2262069510f31c7d3fd7efd3d58b8c0c148
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Nov 27 14:12:17 2006 +0100
+
+    [PATCH] Update Prodrive ALPR board support (440GX)
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
 commit 78d620ebb5871d252270dedfad60c6568993b780
 Author: Wolfgang Denk <wd@atlas.denx.de>
 Date:	Thu Nov 23 22:58:58 2006 +0100
@@ -77,6 +1977,379 @@ Date:	Mon Nov 6 17:06:36 2006 +0100
 
     This fixes get_ram_size() problems on MPC5200 Rev. B boards.
 
+commit be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa
+Author: Timur Tabi <timur@freescale.com>
+Date:	Fri Nov 3 19:15:00 2006 -0600
+
+    mpc83xx: Update 83xx to use fsl_i2c.c
+
+    Update the 83xx tree to use I2C support in drivers/fsl_i2c.c.  Delete
+    cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
+    Added multiple I2C bus support to fsl_i2c.c.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit d239d74b1c937984bc519083a8e7de373a390f06
+Author: Timur Tabi <timur@freescale.com>
+Date:	Fri Nov 3 12:00:28 2006 -0600
+
+    mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR
+
+    Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
+    tree matches the other 8xxx trees.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit f7fb2e703ec9688541416962724adff70a7322cb
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Thu Nov 2 19:47:11 2006 -0600
+
+    mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c
+
+commit 90f30a710a3c619b5405860a686c4ddfc495d4b6
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Thu Nov 2 18:05:50 2006 -0600
+
+    mpc83xx: Fix the incorrect dcbz operation
+
+    The 834x rev1.x silicon has one CPU5 errata.
+
+    The issue is when the data cache locked with
+    HID0[DLOCK], the dcbz instruction looks like no-op inst.
+
+    The right behavior of the data cache is when the data cache
+    Locked with HID0[DLOCK], the dcbz instruction allocates
+    new tags in cache.
+
+    The 834x rev3.0 and later and 8360 have not this bug inside.
+
+    So, when 834x rev3.0/8360 are working with ECC, the dcbz
+    instruction will corrupt the stack in cache, the processor will
+    checkstop reset.
+
+    However, the 834x rev1.x can work with ECC with these code,
+    because the sillicon has this cache bug. The dcbz will not
+    corrupt the stack in cache.
+    Really, it is the fault code running on fault sillicon.
+
+    This patch fix the incorrect dcbz operation. Instead of
+    CPU FP writing to initialise the ECC.
+
+    CHANGELOG:
+    * Fix the incorrect dcbz operation instead of CPU FP
+    writing to initialise the ECC memory. Otherwise, it
+    will corrupt the stack in cache, The processor will checkstop
+    reset.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit bf0b542d6773a5a1cbce77691f009b06d9aeb57d
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Nov 1 00:10:40 2006 -0600
+
+    mpc83xx: add OF_FLAT_TREE bits to 83xx boards
+
+    add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and
+    STDOUT_PATH configuration bits to mpc8349emds,
+    mpc8349itx, and mpc8360emds board code.
+
+    redo environment to use bootm with the fdtaddr
+    for booting ARCH=powerpc kernels by default,
+    and provide default fdtaddr values.
+
+commit 48041365b3420589ad464ebc7752e0053538b729
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Nov 1 00:07:25 2006 -0600
+
+    mpc83xx: change ft code to modify local-mac-address property
+
+    Update 83xx OF code to update local-mac-address properties
+    for ethernet instead of the obsolete 'address' property.
+
+commit 9ca880a250870a7d55754291b5591d2b5fe89b54
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Oct 31 21:23:16 2006 -0600
+
+    mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and MPC8360EMDS
+
+    This patch also adds an improved I2C set_speed(), which handles all clock
+    frequencies.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit ac4b5622ce050b5ee1e154b98df630d778661632
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 31 19:54:59 2006 -0600
+
+    mpc83xx: add the README.mpc8360emds
+
+    add doc/README.mpc8360emds to accompany the new board support
+
+commit 7737d5c658c606f999dfbe3e86b0fed49e5c50ef
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Fri Nov 3 12:11:15 2006 -0600
+
+    mpc83xx: add QE ethernet support
+
+    this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
+
+commit 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Fri Nov 3 19:33:44 2006 -0600
+
+    mpc83xx: Add MPC8360EMDS basic board support
+
+    Add support for the Freescale MPC8360EMDS board.
+    Includes DDR, DUART, Local Bus, PCI.
+
+commit 23892e49352de74f7fac36ff90bb1be143d195e3
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 31 19:30:40 2006 -0600
+
+    mpc83xx: add the QUICC Engine (QE) immap file
+
+    common QE immap file.  Also required for 8360.
+
+commit b701652a4992bdcc62fb1a6038a85beef9e55da4
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Tue Oct 31 19:25:38 2006 -0600
+
+    mpc83xx: Add 8360 specifics to 83xx immap
+
+    Mainly add QE device dependencies, with appropriate 8360 protection.
+    Lindent also run.
+
+commit 988833324a7fda482c8ac3ca23eb539f8232e404
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Oct 31 19:14:41 2006 -0600
+
+    mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITX
+
+    PREREQUISITE PATCHES:
+
+    * This patch can only be applied after the following patches have been applied:
+
+      1) DNX#2006092142000015 "Add support for the MPC8349E-mITX  1/2"
+      2) DNX#2006092142000024 "Add support for the MPC8349E-mITX  2/2"
+
+    CHANGELOG:
+
+    * For the 8349E-mITX, fix some size values in pci_init_board(), enable
+      the clock for the 2nd USB board (Linux kernel will hang otherwise),
+      and fix the CONFIG_BOOTARGS macro.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 2ad6b513b31070bd0c003792ed1c3e7f5d740357
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Oct 31 18:44:42 2006 -0600
+
+    mpc83xx: Add support for the MPC8349E-mITX
+
+    PREREQUISITE PATCHES:
+
+    * This patch can only be applied after the following patches have been applied:
+
+      1) DNX#2006090742000024 "Add support for multiple I2C buses"
+      2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
+      3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
+      4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
+      5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"
+
+    CHANGELOG:
+
+    * Add support for the Freescale MPC8349E-mITX reference design platform.
+      The second TSEC (Vitesse 7385 switch) is not supported at this time.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 183da6d9b446cc12123455844ad1187e2375626f
+Author: Ben Warren <bwarren@qstreams.com>
+Date:	Tue Sep 12 10:15:53 2006 -0400
+
+    Additional MPC8349 support for multibus i2c
+
+    Hello,
+
+    Here is a patch for a file that was accidentally left out of a previous
+    attempt.
+
+    It accompanies the patch with ticket DNX#2006090742000024
+
+    CHANGELOG:
+	    Change PCI initialization to use new multi-bus I2C API.
+
+    regards,
+    Ben
+
+commit b24f119d672b709d153ff2ac091d4aa63ec6877d
+Author: Ben Warren <bwarren@qstreams.com>
+Date:	Thu Sep 7 16:51:04 2006 -0400
+
+    Multi-bus I2C implementation of MPC834x
+
+    Hello,
+
+    Attached is a patch implementing multiple I2C buses on the MPC834x CPU
+    family and the MPC8349EMDS board in particular.
+    This patch requires Patch 1 (Add support for multiple I2C buses).
+    Testing was performed on a 533MHz board.
+
+    /*** Note: This patch replaces ticket DNX#2006083042000027 ***/
+
+    Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+    CHANGELOG:
+	    Implemented driver-level code to support two I2C buses on the
+    MPC834x CPU family and the MPC8349EMDS board.  Available I2C bus speeds
+    are 50kHz, 100kHz and 400kHz on each bus.
+
+    regards,
+    Ben
+
+commit bb99ad6d8257bf828f150d40f507b30d80a4a7ae
+Author: Ben Warren <bwarren@qstreams.com>
+Date:	Thu Sep 7 16:50:54 2006 -0400
+
+    Add support for multiple I2C buses
+
+    Hello,
+
+    Attached is a patch providing support for multiple I2C buses at the
+    command level.  The second part of the patch includes an implementation
+    for the MPC834x CPU and MPC8349EMDS board.
+
+    /*** Note: This patch replaces ticket DNX#2006083042000018 ***/
+
+    Signed-off-by: Ben Warren <bwarren@qstreams.com>
+
+    Overview:
+
+    1. Include new 'i2c' command (based on USB implementation) using
+    CONFIG_I2C_CMD_TREE.
+
+    2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS.  Note that
+    the commands to change bus number and speed are only available under the
+    new 'i2c' command mentioned in the first bullet.
+
+    3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus
+    systems.  When CONFIG_I2C_MULTI_BUS is used, this option takes the form
+    of an array of bus-device pairs.  Otherwise, it is an array of uchar.
+
+    CHANGELOG:
+	    Added new 'i2c' master command for all I2C interaction.  This is
+    conditionally compiled with CONFIG_I2C_CMD_TREE.  New commands added for
+    setting I2C bus speed as well as changing the active bus if the board
+    has more than one (conditionally compiled with
+    CONFIG_I2C_MULTI_BUS).  Updated NOPROBE logic to handle multiple buses.
+    Updated README.
+
+    regards,
+    Ben
+
+commit bed85caf872714ebf53013967a695c9d63acfc68
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Oct 31 18:13:36 2006 -0600
+
+    mpc83xx: Add support for Errata DDR6 on MPC 834x systems
+
+    CHANGELOG:
+
+    * Errata DDR6, which affects all current MPC 834x processors, lists changes
+      required to maintain compatibility with various types of DDR memory.  This
+      patch implements those changes.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit afd6e470f639883002c7c59d562690a5cb0f4865
+Author: Timur Tabi <timur@freescale.com>
+Date:	Wed Oct 25 18:45:23 2006 -0500
+
+    mpc83xx: fix TQM build by defining a CFG_FLASH_SIZE for it
+
+commit 31068b7c4abeefcb2c8fd4fbeccc8ec6c6d0475a
+Author: Timur Tabi <timur@freescale.com>
+Date:	Tue Aug 22 17:07:00 2006 -0500
+
+    mpc83xx: Add support for variable flash memory sizes on 83xx systems
+
+    CHANGELOG:
+
+    * On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access
+       window registers, instead of using a hard-coded value of 8MB.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit 2fc34ae66e73fa7841d1a006dc1b5dcbc1f78965
+Author: Tanya Jiang <tanya.jiang@freescale.com>
+Date:	Thu Aug 3 18:38:13 2006 +0800
+
+    mpc83xx: Unified TQM834x variable names with 83xx and consolidated macros
+
+    Unified TQM834x variable names with 83xx and consolidated macro
+    in preparation for the 8360 and other upcoming 83xx devices.
+
+    Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
+
+commit f6eda7f80ccc13d658020268c507d7173cf2e8aa
+Author: Dave Liu <daveliu@freescale.com>
+Date:	Wed Oct 25 14:41:21 2006 -0500
+
+    mpc83xx: Changed to unified mpx83xx names and added common 83xx changes
+
+    Incorporated the common unified variable names and the changes in preparation
+    for releasing mpc8360 patches.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 3894c46c27c64891f93ac04edde86a9fa9758d92
+Author: Tanya Jiang <tanya.jiang@freescale.com>
+Date:	Thu Aug 3 18:36:02 2006 +0800
+
+    mpc83xx: Fix missing build for mpc8349emds pci.c
+
+    Make pci build for mpc8349emds
+
+    Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
+
+commit 09a81ff740b29deea1e2ab08a3c2ac136c2e6219
+Author: Tanya Jiang <tanya.jiang@freescale.com>
+Date:	Thu Aug 3 18:39:49 2006 +0800
+
+    mpc83xx: Removed unused file resetvec.S for mpc83xx cpu
+
+    Removed unused file resetvec.S for mpc83xx cpu
+
+    Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
+
+commit 04f899fc465c3e44f2b55ecc70618f5696fc0ddf
+Author: Nick Spence <Nick.Spence@freescale.com>
+Date:	Sat Sep 30 00:32:59 2006 -0700
+
+    NAND Flash verify across block boundaries
+
+    This patch addresses a problem when CONFIG_MTD_NAND_VERIFY_WRITE is
+    defined
+    and the write crosses a block boundary. The pointer to the verification
+    buffer (bufstart) is not being updated to reflect the starting of the
+    new
+    block so the verification of the second block fails.
+
+    CHANGELOG:
+
+    * Fix NAND FLASH page verification across block boundaries
+
+commit f484dc791a3932537213c43c654cc1295c64b84c
+Author: Nick Spence <nick.spence@freescale.com>
+Date:	Thu Sep 7 07:39:46 2006 -0700
+
+    Added RGMII support to the TSECs and Marvell 881111 Phy
+
+    Added a phy initialization to adjust the RGMII RX and TX timing
+    Always set the R100 bit in 100 BaseT mode regardless of the TSEC mode
+
+    Signed-off-by: Nick Spence <nick.spence@freescale.com>
+
 commit c59200443072353044aa4bf737a5a60f9a9af231
 Author: Wolfgang Denk <wd@pollux.denx.de>
 Date:	Thu Nov 2 15:15:01 2006 +0100
@@ -289,7 +2562,7 @@ Date:	Tue Oct 24 23:47:37 2006 -0500
 
     If a Multi-Image file contains a third image we try to use it as a
     device tree.  The device tree image is assumed to be uncompressed in the
-    image file.	 We automatically allocate space for the device tree in memory
+    image file.  We automatically allocate space for the device tree in memory
     and provide an 8k pad to allow more than a reasonable amount of growth.
 
     Additionally, a device tree that was contained in flash will now automatically
@@ -590,6 +2863,34 @@ Date:	Tue Oct 10 17:02:22 2006 -0500
 
     Fix whitespace and 80-col issues.
 
+commit 5c912cb1c31266c66ca59b36f9b6f87296421d75
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Oct 7 11:36:51 2006 +0200
+
+    CFG_NAND_QUIET_TEST added to not warn upon missing NAND device
+    Patch by Stefan Roese, 07 Oct 2006
+
+commit 5bc528fa4da751d472397b308137238a6465afd2
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Oct 7 11:35:25 2006 +0200
+
+    Update ALPR code (NAND support working now)
+    Patch by Stefan Roese, 07 Oct 2006
+
+commit 77d5034847d328753b80c46b83f960a14a26f40e
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Oct 7 11:33:03 2006 +0200
+
+    Remove compile warnings in fpga code
+    Patch by Stefan Roese, 07 Oct 2006
+
+commit f3443867e90d2979a7dd1c65b0d537777e1f9850
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Oct 7 11:30:52 2006 +0200
+
+    Add CONFIG_BOARD_RESET to configure board specific reset function
+    Patch by Stefan Roese, 07 Oct 2006
+
 commit f55df18187e7a45cb73fec4370d12135e6691ae1
 Author: John Traill <john.traill@freescale.com>
 Date:	Fri Sep 29 08:23:12 2006 +0100
@@ -822,6 +3123,21 @@ Date:	Wed Aug 16 10:54:09 2006 -0500
 
     Signed-off-by: Matthew McClintock <msm@freescale.com>
 
+commit 899620c2d66d4eef3b2a0034d062e71d45d886c9
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Aug 15 14:22:35 2006 +0200
+
+    Add initial support for the ALPR board from Prodrive
+    NAND needs some additional testing
+    Patch by Heiko Schocher, 15 Aug 2006
+
+commit f0ff4692ff3372dec55074a8eb444943ab095abb
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Aug 15 14:15:51 2006 +0200
+
+    Add FPGA Altera Cyclone 2 support
+    Patch by Heiko Schocher, 15 Aug 2006
+
 commit fecf1c7e4de1b2779edc18742b91c22bdc32b68b
 Author: Jon Loeliger <jdl@freescale.com>
 Date:	Mon Aug 14 15:33:38 2006 -0500
diff --git a/CREDITS b/CREDITS
index 3f7b510..0099bd4 100644
--- a/CREDITS
+++ b/CREDITS
@@ -160,6 +160,10 @@ N: Thomas Frieden
 E: ThomasF@hyperion-entertainment.com
 D: Support for AmigaOne
 
+N: Paul Gortmaker
+E: paul.gortmaker@windriver.com
+D: Support for WRS SBC8347/8349 boards
+
 N: Frank Gottschling
 E: fgottschling@eltec.de
 D: Support for ELTEC MHPC/BAB7xx/ELPPC boards, cfb-console, i8042, SMI LynxEM
@@ -465,3 +469,8 @@ N: James MacAulay
 E: james.macaulay@amirix.com
 D: Suppport for Amirix AP1000
 W: www.amirix.com
+
+N: Timur Tabi
+E: timur@freescale.com
+D: Support for MPC8349E-mITX
+W: www.freescale.com
diff --git a/MAINTAINERS b/MAINTAINERS
index 8bb38b5..68233cf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -28,6 +28,7 @@ Pantelis Antoniou <panto@intracom.gr>
 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 
 	cpci5200		MPC5200
+	mecp5200		MPC5200
 	pf5200			MPC5200
 
 	CPCI750			PPC750FX/GX
@@ -277,22 +278,30 @@ Daniel Poirot <dan.poirot@windriver.com>
 
 Stefan Roese <sr@denx.de>
 
+	P3M7448			MPC7448
+
 	uc100			MPC857
 
 	TQM85xx			MPC8540/8541/8555/8560
 
+	acadia			PPC405EZ
+	alpr			PPC440GX
 	bamboo			PPC440EP
 	bunbinga		PPC405EP
 	ebony			PPC440GP
+	katmai			PPC440SPe
 	ocotea			PPC440GX
 	p3p440			PPC440GP
 	pcs440ep		PPC440EP
 	sequoia			PPC440EPx
 	sycamore		PPC405GPr
+	taishan			PPC440GX
 	walnut			PPC405GP
 	yellowstone		PPC440GR
 	yosemite		PPC440EP
 
+	P3M750			PPC750FX/GX/GL
+
 Yusdi Santoso <yusdi_santoso@adaptec.com>
 
 	HIDDEN_DRAGON	MPC8241/MPC8245
@@ -339,6 +348,19 @@ John Zhan <zhanz@sinovee.com>
 
 	svm_sc8xx		MPC8xx
 
+Timur Tabi <timur@freescale.com>
+
+	MPC8349E-mITX		MPC8349
+	MPC8349E-mITX-GP	MPC8349
+
+Kim Phillips <kim.phillips@freescale.com>
+
+	MPC8349EMDS		MPC8349
+
+Dave Liu <daveliu@freescale.com>
+
+	MPC8360EMDS		MPC8360
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -447,6 +469,7 @@ Stefan Roese <sr@denx.de>
 
 	ixdpg425		xscale
 	pdnb3			xscale
+	scpu			xscale
 
 Robert Schwebel <r.schwebel@pengutronix.de>
 
diff --git a/MAKEALL b/MAKEALL
index 879a17f..a02d8c1 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -37,9 +37,10 @@ LIST_5xx="	\
 LIST_5xxx="	\
 	BC3450		cpci5200	EVAL5200	fo300		\
 	icecube_5100	icecube_5200	lite5200b	mcc200		\
-	o2dnt		pf5200		PM520		TB5200		\
-	Total5100	Total5200	Total5200_Rev2	TQM5200		\
-	TQM5200_B	TQM5200S	v38b				\
+	mecp5200	motionpro	o2dnt		pf5200		\
+	PM520		TB5200		Total5100	Total5200	\
+	Total5200_Rev2	TQM5200		TQM5200_B	TQM5200S	\
+	v38b								\
 "
 
 #########################################################################
@@ -74,21 +75,22 @@ LIST_8xx="	\
 #########################################################################
 
 LIST_4xx="	\
-	ADCIOP		AP1000		AR405		ASH405		\
-	bamboo		bubinga		CANBT		CMS700		\
-	CPCI2DP		CPCI405		CPCI4052	CPCI405AB	\
-	CPCI405DT	CPCI440		CPCIISER4	CRAYL1		\
-	csb272		csb472		DASA_SIM	DP405		\
-	DU405		ebony		ERIC		EXBITGEN	\
-	G2000		HH405		HUB405		JSE		\
-	KAREF		luan		METROBOX	MIP405		\
-	MIP405T		ML2		ml300		ocotea		\
-	OCRTC		ORSG		p3p440		PCI405		\
-	pcs440ep	PIP405		PLU405		PMC405		\
-	PPChameleonEVB	sbc405		sequoia		sequoia_nand	\
-	VOH405		VOM405		W7OLMC		W7OLMG		\
-	walnut		WUH405		XPEDITE1K	yellowstone	\
-	yosemite	yucca		bamboo		\
+	acadia		ADCIOP		alpr		AP1000		\
+	AR405		ASH405		bamboo		bubinga		\
+	CANBT		CMS700		CPCI2DP		CPCI405		\
+	CPCI4052	CPCI405AB	CPCI405DT	CPCI440		\
+	CPCIISER4	CRAYL1		csb272		csb472		\
+	DASA_SIM	DP405		DU405		ebony		\
+	ERIC		EXBITGEN	G2000		HH405		\
+	HUB405		JSE		KAREF		katmai		\
+	luan		METROBOX	MIP405		MIP405T		\
+	ML2		ml300		ocotea		OCRTC		\
+	ORSG		p3p440		PCI405		pcs440ep	\
+	PIP405		PLU405		PMC405		PPChameleonEVB	\
+	sbc405		sc3		sequoia		sequoia_nand	\
+	taishan		VOH405		VOM405		W7OLMC		\
+	W7OLMG		walnut		WUH405		XPEDITE1K	\
+	yellowstone	yosemite	yucca				\
 "
 
 #########################################################################
@@ -130,7 +132,8 @@ LIST_8260="	\
 #########################################################################
 
 LIST_83xx="	\
-	TQM834x		MPC8349EMDS					\
+	MPC832XEMDS	MPC8349EMDS	MPC8349ITX	MPC8349ITXGP	\
+	MPC8360EMDS	sbc8349		TQM834x				\
 "
 
 
@@ -151,11 +154,12 @@ LIST_85xx="	\
 
 LIST_74xx="	\
 	DB64360		DB64460		EVB64260	P3G4		\
-	PCIPPC2		PCIPPC6		ZUMA				\
+	p3m7448		PCIPPC2		PCIPPC6		ZUMA		\
 "
 
 LIST_7xx="	\
-	BAB7xx		CPCI750		ELPPC		ppmc7xx		\
+	BAB7xx		CPCI750		ELPPC		p3m750		\
+	ppmc7xx								\
 "
 
 LIST_ppc="${LIST_5xx}  ${LIST_5xxx}		\
@@ -179,7 +183,7 @@ LIST_SA="assabet dnp1110 gcplus lart shannon"
 LIST_ARM7="	\
 	armadillo	B2		ep7312		evb4510		\
 	impa7		integratorap	ap7		ap720t		\
-	modnet50							\
+	lpc2292sodimm	modnet50					\
 "
 
 #########################################################################
@@ -223,7 +227,7 @@ LIST_pxa="	\
 	xsengine	zylonite					\
 "
 
-LIST_ixp="ixdp425	ixdpg425	pdnb3"
+LIST_ixp="ixdp425	ixdpg425	pdnb3		scpu"
 
 
 LIST_arm="	\
@@ -298,8 +302,8 @@ LIST_microblaze="	\
 
 LIST_coldfire="	\
 	cobra5272	EB+MCF-EV123	EB+MCF-EV123_internal		\
-	M5271EVB	M5272C3		M5282EVB	TASREG		\
-	r5200		M5271EVB					\
+	idmr		M5271EVB	M5272C3		M5282EVB	\
+	TASREG		r5200		M5271EVB			\
 "
 
 #########################################################################
@@ -308,6 +312,14 @@ LIST_coldfire="	\
 
 LIST_avr32="atstk1002"
 
+#########################################################################
+## Blackfin Systems
+#########################################################################
+
+LIST_blackfin=" \
+	bf533-ezkit	bf533-stamp	bf537-stamp	bf561-ezkit	\
+"
+
 #-----------------------------------------------------------------------
 
 #----- for now, just run PPC by default -----
@@ -334,14 +346,15 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
-	arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp| \
+	arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa| \
+	avr32| \
+	blackfin| \
+	coldfire| \
 	microblaze| \
 	mips|mips_el| \
 	nios|nios2| \
-	x86|I486| \
-	coldfire| \
-	avr32)
+	ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
+	x86|I486)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}
diff --git a/Makefile b/Makefile
index 98f29c9..f15a6e2 100644
--- a/Makefile
+++ b/Makefile
@@ -22,8 +22,8 @@
 #
 
 VERSION = 1
-PATCHLEVEL = 1
-SUBLEVEL = 6
+PATCHLEVEL = 2
+SUBLEVEL = 0
 EXTRAVERSION =
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 VERSION_FILE = $(obj)include/version_autogenerated.h
@@ -93,7 +93,7 @@ MKCONFIG	:= $(SRCTREE)/mkconfig
 export MKCONFIG
 
 ifneq ($(OBJTREE),$(SRCTREE))
-REMOTE_BUILD 	:= 1
+REMOTE_BUILD	:= 1
 export REMOTE_BUILD
 endif
 
@@ -118,7 +118,7 @@ include $(OBJTREE)/include/config.mk
 export	ARCH CPU BOARD VENDOR SOC
 
 ifndef CROSS_COMPILE
-ifeq ($(HOSTARCH),ppc)
+ifeq ($(HOSTARCH),$(ARCH))
 CROSS_COMPILE =
 else
 ifeq ($(ARCH),ppc)
@@ -128,12 +128,8 @@ ifeq ($(ARCH),arm)
 CROSS_COMPILE = arm-linux-
 endif
 ifeq ($(ARCH),i386)
-ifeq ($(HOSTARCH),i386)
-CROSS_COMPILE =
-else
 CROSS_COMPILE = i386-linux-
 endif
-endif
 ifeq ($(ARCH),mips)
 CROSS_COMPILE = mips_4KC-
 endif
@@ -150,7 +146,7 @@ ifeq ($(ARCH),microblaze)
 CROSS_COMPILE = mb-
 endif
 ifeq ($(ARCH),blackfin)
-CROSS_COMPILE = bfin-elf-
+CROSS_COMPILE = bfin-uclinux-
 endif
 ifeq ($(ARCH),avr32)
 CROSS_COMPILE = avr32-
@@ -174,9 +170,6 @@ endif
 ifeq ($(CPU),ppc4xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
-ifeq ($(CPU),mpc83xx)
-OBJS += cpu/$(CPU)/resetvec.o
-endif
 ifeq ($(CPU),mpc85xx)
 OBJS += cpu/$(CPU)/resetvec.o
 endif
@@ -185,7 +178,15 @@ OBJS += cpu/$(CPU)/resetvec.o
 endif
 ifeq ($(CPU),bf533)
 OBJS += cpu/$(CPU)/start1.o	cpu/$(CPU)/interrupt.o	cpu/$(CPU)/cache.o
-OBJS += cpu/$(CPU)/cplbhdlr.o	cpu/$(CPU)/cplbmgr.o	cpu/$(CPU)/flush.o
+OBJS += cpu/$(CPU)/flush.o	cpu/$(CPU)/init_sdram.o
+endif
+ifeq ($(CPU),bf537)
+OBJS += cpu/$(CPU)/start1.o	cpu/$(CPU)/interrupt.o	cpu/$(CPU)/cache.o
+OBJS += cpu/$(CPU)/flush.o	cpu/$(CPU)/init_sdram.o
+endif
+ifeq ($(CPU),bf561)
+OBJS += cpu/$(CPU)/start1.o	cpu/$(CPU)/interrupt.o	cpu/$(CPU)/cache.o
+OBJS += cpu/$(CPU)/flush.o 	cpu/$(CPU)/init_sdram.o
 endif
 
 OBJS := $(addprefix $(obj),$(OBJS))
@@ -206,8 +207,17 @@ LIBS += dtt/libdtt.a
 LIBS += drivers/libdrivers.a
 LIBS += drivers/nand/libnand.a
 LIBS += drivers/nand_legacy/libnand_legacy.a
+ifeq ($(CPU),mpc83xx)
+LIBS += drivers/qe/qe.a
+endif
 LIBS += drivers/sk98lin/libsk98lin.a
-LIBS += post/libpost.a post/cpu/libcpu.a
+LIBS += post/libpost.a post/drivers/libpostdrivers.a
+LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
+	"post/lib_$(ARCH)/libpost$(ARCH).a"; fi)
+LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
+	"post/cpu/$(CPU)/libpost$(CPU).a"; fi)
+LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
+	"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
 LIBS += common/libcommon.a
 LIBS += $(BOARDLIBS)
 
@@ -220,9 +230,8 @@ PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -
 # The "tools" are needed early, so put this first
 # Don't include stuff already done in $(LIBS)
 SUBDIRS	= tools \
-	  examples \
-	  post \
-	  post/cpu
+	  examples
+
 .PHONY : $(SUBDIRS)
 
 ifeq ($(CONFIG_NAND_U_BOOT),y)
@@ -378,8 +387,8 @@ Lite5200_LOWBOOT08_config		\
 icecube_5200_config			\
 icecube_5200_LOWBOOT_config		\
 icecube_5200_LOWBOOT08_config		\
-icecube_5200_DDR_config 		\
-icecube_5200_DDR_LOWBOOT_config 	\
+icecube_5200_DDR_config			\
+icecube_5200_DDR_LOWBOOT_config		\
 icecube_5200_DDR_LOWBOOT08_config	\
 icecube_5100_config:			unconfig
 	@mkdir -p $(obj)include
@@ -411,6 +420,9 @@ icecube_5100_config:			unconfig
 		}
 	@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
 
+jupiter_config:         unconfig
+	@$(MKCONFIG) jupiter ppc mpc5xxx jupiter
+
 v38b_config: unconfig
 	@./mkconfig -a v38b ppc mpc5xxx v38b
 
@@ -458,7 +470,7 @@ prs200_highboot_DDR_config:	unconfig
 	@[ -n "$(findstring _SDRAM,$@)" ] || \
 		{ if [ -n "$(findstring mcc200,$@)" ]; \
 		  then \
-		  	echo "... with DDR" ; \
+			echo "... with DDR" ; \
 		  else \
 			if [ -n "$(findstring _DDR,$@)" ];\
 			then \
@@ -482,6 +494,9 @@ prs200_highboot_DDR_config:	unconfig
 		}
 	@$(MKCONFIG) -n $@ -a mcc200 ppc mpc5xxx mcc200
 
+mecp5200_config:  unconfig
+	@$(MKCONFIG) -a mecp5200  ppc mpc5xxx mecp5200 esd
+
 o2dnt_config:
 	@$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
 
@@ -557,6 +572,7 @@ Total5200_Rev2_lowboot_config:	unconfig
 	@$(MKCONFIG) -a Total5200 ppc mpc5xxx total5200
 
 cam5200_config \
+cam5200_niosflash_config \
 fo300_config \
 MiniFAP_config \
 TQM5200S_config \
@@ -574,6 +590,10 @@ TQM5200_STK100_config:	unconfig
 		  echo "#define CONFIG_TQM5200_B"	>>$(obj)include/config.h ; \
 		  echo "... TQM5200S on Cam5200" ; \
 		}
+	@[ -z "$(findstring niosflash,$@)" ] || \
+		{ echo "#define CONFIG_CAM5200_NIOSFLASH"	>>$(obj)include/config.h ; \
+		  echo "... with NIOS flash driver" ; \
+		}
 	@[ -z "$(findstring fo300,$@)" ] || \
 		{ echo "#define CONFIG_FO300"	>>$(obj)include/config.h ; \
 		  echo "... TQM5200 on FO300" ; \
@@ -597,6 +617,11 @@ TQM5200_STK100_config:	unconfig
 		{ echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \
 		}
 	@$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200
+uc101_config:         unconfig
+	@$(MKCONFIG) uc101 ppc mpc5xxx uc101
+motionpro_config:         unconfig
+	@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
+
 
 #########################################################################
 ## MPC8xx Systems
@@ -868,9 +893,9 @@ RPXClassic_config:	unconfig
 RPXlite_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx RPXlite
 
-RPXlite_DW_64_config  		\
-RPXlite_DW_LCD_config 		\
-RPXlite_DW_64_LCD_config 	\
+RPXlite_DW_64_config		\
+RPXlite_DW_LCD_config		\
+RPXlite_DW_64_LCD_config	\
 RPXlite_DW_NVRAM_config		\
 RPXlite_DW_NVRAM_64_config      \
 RPXlite_DW_NVRAM_LCD_config	\
@@ -883,12 +908,12 @@ RPXlite_DW_config:         unconfig
 		  echo "... with 64MHz system clock ..."; \
 		}
 	@[ -z "$(findstring _LCD,$@)" ] || \
-		{ echo "#define CONFIG_LCD"          	>>$(obj)include/config.h ; \
+		{ echo "#define CONFIG_LCD"		>>$(obj)include/config.h ; \
 		  echo "#define CONFIG_NEC_NL6448BC20"	>>$(obj)include/config.h ; \
 		  echo "... with LCD display ..."; \
 		}
 	@[ -z "$(findstring _NVRAM,$@)" ] || \
-		{ echo "#define  CFG_ENV_IS_IN_NVRAM" 	>>$(obj)include/config.h ; \
+		{ echo "#define  CFG_ENV_IS_IN_NVRAM"	>>$(obj)include/config.h ; \
 		  echo "... with ENV in NVRAM ..."; \
 		}
 	@$(MKCONFIG) -a RPXlite_DW ppc mpc8xx RPXlite_dw
@@ -984,9 +1009,15 @@ wtk_config:	unconfig
 #########################################################################
 xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1))))))
 
+acadia_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx acadia amcc
+
 ADCIOP_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd
 
+alpr_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx alpr prodrive
+
 AP1000_config:unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx ap1000 amirix
 
@@ -1082,6 +1113,9 @@ JSE_config:	unconfig
 KAREF_config: unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx karef sandburst
 
+katmai_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx katmai amcc
+
 luan_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
 
@@ -1162,18 +1196,16 @@ PPChameleonEVB_HI_33_config:	unconfig
 rainier_config:	unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_RAINIER" > $(obj)include/config.h
-	@echo "Configuring for rainier board as subset of sequoia..."
-	@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
+	@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
 
 rainier_nand_config:	unconfig
 	@mkdir -p $(obj)include
 	@mkdir -p $(obj)nand_spl
 	@mkdir -p $(obj)board/amcc/sequoia
 	@echo "#define CONFIG_RAINIER" > $(obj)include/config.h
-	@echo "Configuring for rainier board as subset of sequoia..."
 	@echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h
 	@echo "Compile NAND boot image for sequoia"
-	@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
+	@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
 	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
 	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
 
@@ -1193,9 +1225,14 @@ sequoia_nand_config:	unconfig
 	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
 	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
 
+sc3_config:unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx sc3
+
 sycamore_config:	unconfig
-	@echo "Configuring for sycamore board as subset of walnut..."
-	@$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc
+	@$(MKCONFIG) -n $@ -a walnut ppc ppc4xx walnut amcc
+
+taishan_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
 
 VOH405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
@@ -1223,7 +1260,9 @@ yosemite_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx yosemite amcc
 
 yellowstone_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc ppc4xx yellowstone amcc
+	@mkdir -p $(obj)include
+	@echo "#define CONFIG_YELLOWSTONE" > $(obj)include/config.h
+	@$(MKCONFIG) -n $@ -a yosemite ppc ppc4xx yosemite amcc
 
 yucca_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
@@ -1539,6 +1578,9 @@ TQM8265_AA_config:  unconfig
 	fi
 	@$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260
 
+TQM8272_config: unconfig
+	@$(MKCONFIG) -a TQM8272 ppc mpc8260 tqm8272
+
 VoVPN-GW_66MHz_config	\
 VoVPN-GW_100MHz_config:		unconfig
 	@mkdir -p $(obj)include
@@ -1569,6 +1611,9 @@ EB+MCF-EV123_internal_config :	unconfig
 	@echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
 	@$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
 
+idmr_config :			unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr
+
 M5271EVB_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5271evb
 
@@ -1588,14 +1633,77 @@ r5200_config :		unconfig
 ## MPC83xx Systems
 #########################################################################
 
-MPC8349ADS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349ads
+MPC832XEMDS_config \
+MPC832XEMDS_HOST_33_config \
+MPC832XEMDS_HOST_66_config \
+MPC832XEMDS_SLAVE_config:	unconfig
+	@echo "" >include/config.h ; \
+	if [ "$(findstring _HOST_,$@)" ] ; then \
+		echo -n "... PCI HOST " ; \
+		echo "#define CONFIG_PCI" >>include/config.h ; \
+	fi ; \
+	if [ "$(findstring _SLAVE_,$@)" ] ; then \
+		echo "...PCI SLAVE 66M"  ; \
+		echo "#define CONFIG_PCI" >>include/config.h ; \
+		echo "#define CONFIG_PCISLAVE" >>include/config.h ; \
+	fi ; \
+	if [ "$(findstring _33_,$@)" ] ; then \
+		echo -n "...33M ..." ; \
+		echo "#define PCI_33M" >>include/config.h ; \
+	fi ; \
+	if [ "$(findstring _66_,$@)" ] ; then \
+		echo -n "...66M..." ; \
+		echo "#define PCI_66M" >>include/config.h ; \
+	fi ;
+	@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds
+
+MPC8349EMDS_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds
+
+MPC8349ITX_config \
+MPC8349ITX_LOWBOOT_config \
+MPC8349ITXGP_config:	unconfig
+	@mkdir -p $(obj)include
+	@mkdir -p $(obj)board/mpc8349itx
+	@echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h
+	@if [ "$(findstring GP,$@)" ] ; then \
+		echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
+	fi
+	@if [ "$(findstring LOWBOOT,$@)" ] ; then \
+		echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
+	fi
+	@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx
+
+MPC8360EMDS_config \
+MPC8360EMDS_HOST_33_config \
+MPC8360EMDS_HOST_66_config \
+MPC8360EMDS_SLAVE_config:	unconfig
+	@echo "" >include/config.h ; \
+	if [ "$(findstring _HOST_,$@)" ] ; then \
+		echo -n "... PCI HOST " ; \
+		echo "#define CONFIG_PCI" >>include/config.h ; \
+	fi ; \
+	if [ "$(findstring _SLAVE_,$@)" ] ; then \
+		echo "...PCI SLAVE 66M"  ; \
+		echo "#define CONFIG_PCI" >>include/config.h ; \
+		echo "#define CONFIG_PCISLAVE" >>include/config.h ; \
+	fi ; \
+	if [ "$(findstring _33_,$@)" ] ; then \
+		echo -n "...33M ..." ; \
+		echo "#define PCI_33M" >>include/config.h ; \
+	fi ; \
+	if [ "$(findstring _66_,$@)" ] ; then \
+		echo -n "...66M..." ; \
+		echo "#define PCI_66M" >>include/config.h ; \
+	fi ;
+	@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
+
+sbc8349_config:		unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
 
 TQM834x_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x
 
-MPC8349EMDS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds
 
 #########################################################################
 ## MPC85xx Systems
@@ -1724,6 +1832,16 @@ EVB64260_750CX_config:	unconfig
 P3G4_config: unconfig
 	@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
 
+p3m750_config	\
+p3m7448_config:		unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring 750_,$@)" ] ; then \
+		echo "#define CONFIG_P3M750" >>$(obj)include/config.h ; \
+	else \
+		echo "#define CONFIG_P3M7448" >>$(obj)include/config.h ; \
+	fi
+	@$(MKCONFIG) -a p3mx ppc 74xx_7xx p3mx prodrive
+
 PCIPPC2_config \
 PCIPPC6_config: unconfig
 	@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx pcippc2
@@ -1787,7 +1905,7 @@ ap966_config		\
 ap922_config		\
 ap922_XA10_config	\
 ap7_config		\
-ap720t_config  		\
+ap720t_config		\
 ap920t_config		\
 ap926ejs_config		\
 ap946es_config: unconfig
@@ -1944,7 +2062,7 @@ cm4008_config	:	unconfig
 cm41xx_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695
 
-gth2_config		: 	unconfig
+gth2_config		:	unconfig
 	@mkdir -p $(obj)include
 	@ >$(obj)include/config.h
 	@echo "#define CONFIG_GTH2 1" >>$(obj)include/config.h
@@ -1976,6 +2094,9 @@ modnet50_config :	unconfig
 evb4510_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm720t evb4510
 
+lpc2292sodimm_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm
+
 #########################################################################
 ## XScale Systems
 #########################################################################
@@ -2013,8 +2134,15 @@ pleb2_config	:	unconfig
 logodl_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa logodl
 
-pdnb3_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm ixp pdnb3 prodrive
+pdnb3_config \
+scpu_config:    unconfig
+	@if [ "$(findstring scpu_,$@)" ] ; then \
+		echo "#define CONFIG_SCPU"      >>include/config.h ; \
+		echo "... on SCPU board variant" ; \
+	else \
+		>include/config.h ; \
+	fi
+	@$(MKCONFIG) -a pdnb3 arm ixp pdnb3 prodrive
 
 pxa255_idp_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
@@ -2090,19 +2218,19 @@ tb0229_config: unconfig
 #########################################################################
 ## MIPS32 AU1X00
 #########################################################################
-dbau1000_config		: 	unconfig
+dbau1000_config		:	unconfig
 	@mkdir -p $(obj)include
 	@ >$(obj)include/config.h
 	@echo "#define CONFIG_DBAU1000 1" >>$(obj)include/config.h
 	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
 
-dbau1100_config		: 	unconfig
+dbau1100_config		:	unconfig
 	@mkdir -p $(obj)include
 	@ >$(obj)include/config.h
 	@echo "#define CONFIG_DBAU1100 1" >>$(obj)include/config.h
 	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
 
-dbau1500_config		: 	unconfig
+dbau1500_config		:	unconfig
 	@mkdir -p $(obj)include
 	@ >$(obj)include/config.h
 	@echo "#define CONFIG_DBAU1500 1" >>$(obj)include/config.h
@@ -2120,7 +2248,7 @@ dbau1550_el_config	:	unconfig
 	@echo "#define CONFIG_DBAU1550 1" >>$(obj)include/config.h
 	@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
 
-pb1000_config		: 	unconfig
+pb1000_config		:	unconfig
 	@mkdir -p $(obj)include
 	@ >$(obj)include/config.h
 	@echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h
@@ -2236,14 +2364,17 @@ suzaku_config:	unconfig
 #########################################################################
 ## Blackfin
 #########################################################################
-ezkit533_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) blackfin bf533 ezkit533
+bf533-ezkit_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-ezkit
+
+bf533-stamp_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-stamp
 
-stamp_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) blackfin bf533 stamp
+bf537-stamp_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) blackfin bf537 bf537-stamp
 
-dspstamp_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) blackfin bf533 dsp_stamp
+bf561-ezkit_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) blackfin bf561 bf561-ezkit
 
 #========================================================================
 # AVR32
@@ -2280,6 +2411,8 @@ clean:
 	rm -f $(obj)board/netstar/*.srec $(obj)board/netstar/*.bin
 	rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
 	rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
+	rm -f $(obj)board/bf533-ezkit/u-boot.lds $(obj)board/bf533-stamp/u-boot.lds
+	rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
 	rm -f $(obj)include/bmp_logo.h
 	rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
 
diff --git a/README b/README
index c04cbad..13ff3ff 100644
--- a/README
+++ b/README
@@ -1269,7 +1269,12 @@ The following options need to be configured:
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 
-		CONFIG_HARD_I2C selects the CPM hardware driver for I2C.
+		CONFIG_I2C_CMD_TREE is a recommended option that places
+		all I2C commands under a single 'i2c' root command.  The
+		older 'imm', 'imd', 'iprobe' etc. commands are considered
+		deprecated and may disappear in the future.
+
+		CONFIG_HARD_I2C selects a hardware I2C controller.
 
 		CONFIG_SOFT_I2C configures u-boot to use a software (aka
 		bit-banging) driver instead of CPM or similar hardware
@@ -1374,6 +1379,52 @@ The following options need to be configured:
 		in u-boot bd_info structure based on u-boot environment
 		variable "i2cfast". (see also i2cfast)
 
+		CONFIG_I2C_MULTI_BUS
+
+		This option allows the use of multiple I2C buses, each of which
+		must have a controller.  At any point in time, only one bus is
+		active.  To switch to a different bus, use the 'i2c dev' command.
+		Note that bus numbering is zero-based.
+
+		CFG_I2C_NOPROBES
+
+		This option specifies a list of I2C devices that will be skipped
+		when the 'i2c probe' command is issued (or 'iprobe' using the legacy
+		command).  If CONFIG_I2C_MULTI_BUS is set, specify a list of bus-device
+		pairs.  Otherwise, specify a 1D array of device addresses
+
+		e.g.
+			#undef	CONFIG_I2C_MULTI_BUS
+			#define CFG_I2C_NOPROBES	{0x50,0x68}
+
+		will skip addresses 0x50 and 0x68 on a board with one I2C bus
+
+			#define	CONFIG_I2C_MULTI_BUS
+			#define CFG_I2C_MULTI_NOPROBES	{{0,0x50},{0,0x68},{1,0x54}}
+
+		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
+
+		CFG_SPD_BUS_NUM
+
+		If defined, then this indicates the I2C bus number for DDR SPD.
+		If not defined, then U-Boot assumes that SPD is on I2C bus 0.
+
+		CFG_RTC_BUS_NUM
+
+		If defined, then this indicates the I2C bus number for the RTC.
+		If not defined, then U-Boot assumes that RTC is on I2C bus 0.
+
+		CFG_DTT_BUS_NUM
+
+		If defined, then this indicates the I2C bus number for the DTT.
+		If not defined, then U-Boot assumes that DTT is on I2C bus 0.
+
+		CONFIG_FSL_I2C
+
+		Define this option if you want to use Freescale's I2C driver in
+		drivers/fsl_i2c.c.
+
+
 - SPI Support:	CONFIG_SPI
 
 		Enables SPI driver (so far only tested with
@@ -2271,6 +2322,24 @@ Low Level (hardware related) configuration options:
   CFG_POCMR2_MASK_ATTRIB: (MPC826x only)
 		Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
 
+- CONFIG_SPD_EEPROM
+		Get DDR timing information from an I2C EEPROM.  Common with pluggable
+		memory modules such as SODIMMs
+  SPD_EEPROM_ADDRESS
+		I2C address of the SPD EEPROM
+
+- CFG_SPD_BUS_NUM
+		If SPD EEPROM is on an I2C bus other than the first one, specify here.
+		Note that the value must resolve to something your driver can deal with.
+
+- CFG_83XX_DDR_USES_CS0
+		Only for 83xx systems. If specified, then DDR should be configured
+		using CS0 and CS1 instead of CS2 and CS3.
+
+- CFG_83XX_DDR_USES_CS0
+		Only for 83xx systems. If specified, then DDR should be configured
+		using CS0 and CS1 instead of CS2 and CS3.
+
 - CONFIG_ETHER_ON_FEC[12]
 		Define to enable FEC[12] on a 8xx series processor.
 
diff --git a/blackfin_config.mk b/blackfin_config.mk
index e2747aa..df324b7 100644
--- a/blackfin_config.mk
+++ b/blackfin_config.mk
@@ -21,4 +21,4 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__
+PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
diff --git a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
index f18313d..dcfd83e 100644
--- a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
+++ b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
@@ -50,13 +50,13 @@ long int initdram (int board_type)
 
 		MCFSDRAMC_DACR0 =	MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0)
 					| MCFSDRAMC_DACR_CASL(1)
- 					| MCFSDRAMC_DACR_CBM(3)
+					| MCFSDRAMC_DACR_CBM(3)
 					| MCFSDRAMC_DACR_PS_16);
 
 		MCFSDRAMC_DMR0 =	MCFSDRAMC_DMR_BAM_16M
 					| MCFSDRAMC_DMR_V;
 
-		MCFSDRAMC_DACR0 |= 	MCFSDRAMC_DACR_IP;
+		MCFSDRAMC_DACR0 |=	MCFSDRAMC_DACR_IP;
 
 		*(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5;
 		MCFSDRAMC_DACR0 |=	MCFSDRAMC_DACR_RE;
@@ -70,10 +70,10 @@ long int initdram (int board_type)
 	#ifdef CFG_SDRAM_BASE1
 		MCFSDRAMC_DACR1 =	MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1)
 					| MCFSDRAMC_DACR_CASL(1)
- 					| MCFSDRAMC_DACR_CBM(3)
+					| MCFSDRAMC_DACR_CBM(3)
 					| MCFSDRAMC_DACR_PS_16;
 
-		MCFSDRAMC_DMR1 = 	MCFSDRAMC_DMR_BAM_16M
+		MCFSDRAMC_DMR1 =	MCFSDRAMC_DMR_BAM_16M
 					| MCFSDRAMC_DMR_V;
 
 		MCFSDRAMC_DACR1 |=	MCFSDRAMC_DACR_IP;
@@ -82,7 +82,7 @@ long int initdram (int board_type)
 		MCFSDRAMC_DACR1 |=	MCFSDRAMC_DACR_RE;
 		for (i=0; i < 2000; i++)
 			asm(" nop");
-		MCFSDRAMC_DACR1 |= 	MCFSDRAMC_DACR_IMRS;
+		MCFSDRAMC_DACR1 |=	MCFSDRAMC_DACR_IMRS;
 		*(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
 		size += CFG_SDRAM_SIZE1 * 1024 * 1024;
 	#endif
diff --git a/board/BuS/EB+MCF-EV123/VCxK.c b/board/BuS/EB+MCF-EV123/VCxK.c
index 4938817..4b46b7c 100644
--- a/board/BuS/EB+MCF-EV123/VCxK.c
+++ b/board/BuS/EB+MCF-EV123/VCxK.c
@@ -66,7 +66,7 @@ int init_vcxk(void)
 	return 1;
 }
 
-void 	vcxk_loadimage(ulong source)
+void	vcxk_loadimage(ulong source)
 {
 	int cnt;
 	vcxk_acknowledge_wait();
diff --git a/board/BuS/EB+MCF-EV123/VCxK.h b/board/BuS/EB+MCF-EV123/VCxK.h
index 74467ba..f591e5c 100644
--- a/board/BuS/EB+MCF-EV123/VCxK.h
+++ b/board/BuS/EB+MCF-EV123/VCxK.h
@@ -25,24 +25,24 @@
 #define __VCXK_H_
 
 extern int init_vcxk(void);
-void 	vcxk_loadimage(ulong source);
+void	vcxk_loadimage(ulong source);
 
 #define VIDEO_ACKNOWLEDGE_PORT	MCFGPTB_GPTPORT
-#define VIDEO_ACKNOWLEDGE_DDR 	MCFGPTB_GPTDDR
+#define VIDEO_ACKNOWLEDGE_DDR	MCFGPTB_GPTDDR
 #define VIDEO_ACKNOWLEDGE_PIN	0x0001
 
-#define VIDEO_ENABLE_PORT    	MCFGPTB_GPTPORT
-#define VIDEO_ENABLE_DDR 	MCFGPTB_GPTDDR
+#define VIDEO_ENABLE_PORT	MCFGPTB_GPTPORT
+#define VIDEO_ENABLE_DDR	MCFGPTB_GPTDDR
 #define VIDEO_ENABLE_PIN	0x0002
 
-#define VIDEO_REQUEST_PORT   	MCFGPTB_GPTPORT
-#define VIDEO_REQUEST_DDR 	MCFGPTB_GPTDDR
+#define VIDEO_REQUEST_PORT	MCFGPTB_GPTPORT
+#define VIDEO_REQUEST_DDR	MCFGPTB_GPTDDR
 #define VIDEO_REQUEST_PIN	0x0004
 
 #define VIDEO_Invert_CFG	MCFGPIO_PEPAR
 #define VIDEO_Invert_IO		MCFGPIO_PEPAR_PEPA2
-#define VIDEO_INVERT_PORT   	MCFGPIO_PORTE
-#define VIDEO_INVERT_DDR 	MCFGPIO_DDRE
+#define VIDEO_INVERT_PORT	MCFGPIO_PORTE
+#define VIDEO_INVERT_DDR	MCFGPIO_DDRE
 #define VIDEO_INVERT_PIN	MCFGPIO_PORT2
 
 #endif
diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.c b/board/BuS/EB+MCF-EV123/cfm_flash.c
index 6ecf0d1..b326384 100644
--- a/board/BuS/EB+MCF-EV123/cfm_flash.c
+++ b/board/BuS/EB+MCF-EV123/cfm_flash.c
@@ -60,7 +60,7 @@ void cfm_flash_init (flash_info_t * info)
 	MCFCFM_MCR = 0;
 	MCFCFM_CLKD = CFM_CLK;
 	debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
-	 	CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
+		CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
 		CFG_CLK);
 	MCFCFM_SACC = 0;
 	MCFCFM_DACC = 0;
diff --git a/board/BuS/EB+MCF-EV123/flash.c b/board/BuS/EB+MCF-EV123/flash.c
index ba76bef..5e2647d 100644
--- a/board/BuS/EB+MCF-EV123/flash.c
+++ b/board/BuS/EB+MCF-EV123/flash.c
@@ -256,7 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		enable_interrupts ();
 
 	if (cflag)
-  		icache_enable ();
+		icache_enable ();
 
 	return rc;
 }
diff --git a/board/BuS/EB+MCF-EV123/u-boot.lds b/board/BuS/EB+MCF-EV123/u-boot.lds
index d790018..ac53245 100644
--- a/board/BuS/EB+MCF-EV123/u-boot.lds
+++ b/board/BuS/EB+MCF-EV123/u-boot.lds
@@ -34,11 +34,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds
index b09fc33..214752d 100644
--- a/board/LEOX/elpt860/u-boot.lds
+++ b/board/LEOX/elpt860/u-boot.lds
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug
index 6f5af91..17f99eb 100644
--- a/board/LEOX/elpt860/u-boot.lds.debug
+++ b/board/LEOX/elpt860/u-boot.lds.debug
@@ -43,11 +43,11 @@ SECTIONS
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text) 	}
+  .rela.text     : { *(.rela.text)	}
   .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data) 	}
-  .rel.rodata    : { *(.rel.rodata) 	}
-  .rela.rodata   : { *(.rela.rodata) 	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
diff --git a/board/MAI/AmigaOneG3SE/Makefile b/board/MAI/AmigaOneG3SE/Makefile
index cb6ea26..fa28d3b 100644
--- a/board/MAI/AmigaOneG3SE/Makefile
+++ b/board/MAI/AmigaOneG3SE/Makefile
@@ -30,7 +30,7 @@ endif
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	= $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \
-		via686.o i8259.o ../bios_emulator/x86interface.o 	\
+		via686.o i8259.o ../bios_emulator/x86interface.o	\
 		../bios_emulator/bios.o ../bios_emulator/glue.o		\
 		interrupts.o ps2kbd.o video.o usb_uhci.o enet.o	        \
 		../menu/cmd_menu.o cmd_boota.o nvram.o
diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c
index 480dae5..45b8195 100644
--- a/board/MAI/AmigaOneG3SE/articiaS_pci.c
+++ b/board/MAI/AmigaOneG3SE/articiaS_pci.c
@@ -368,11 +368,11 @@ void articiaS_pci_init (void)
 	if (articiaS_init_vga() == -1)
 	{
 	    /* If the VGA didn't init and we have stdout set to VGA, reset to serial */
-/* 	    s = getenv("stdout"); */
-/* 	    if (s && strcmp(s, "vga") == 0) */
-/* 	    { */
-/* 		setenv("stdout", "serial"); */
-/* 	    } */
+/*	    s = getenv("stdout"); */
+/*	    if (s && strcmp(s, "vga") == 0) */
+/*	    { */
+/*		setenv("stdout", "serial"); */
+/*	    } */
 	}
     }
     pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);
diff --git a/board/MAI/AmigaOneG3SE/enet.c b/board/MAI/AmigaOneG3SE/enet.c
index d4be889..ad2bcde 100644
--- a/board/MAI/AmigaOneG3SE/enet.c
+++ b/board/MAI/AmigaOneG3SE/enet.c
@@ -41,57 +41,57 @@
 
 /* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */
 
-#define TotalReset 		(0<<11)
-#define SelectWindow 		(1<<11)
-#define StartCoax 		(2<<11)
-#define RxDisable 		(3<<11)
-#define RxEnable 		(4<<11)
-#define RxReset 		(5<<11)
-#define UpStall 		(6<<11)
-#define UpUnstall 		(6<<11)+1
-#define DownStall 		(6<<11)+2
-#define DownUnstall 		(6<<11)+3
-#define RxDiscard 		(8<<11)
-#define TxEnable 		(9<<11)
-#define TxDisable 		(10<<11)
-#define TxReset 		(11<<11)
-#define FakeIntr 		(12<<11)
-#define AckIntr 		(13<<11)
-#define SetIntrEnb 		(14<<11)
-#define SetStatusEnb 		(15<<11)
-#define SetRxFilter 		(16<<11)
-#define SetRxThreshold 		(17<<11)
-#define SetTxThreshold 		(18<<11)
-#define SetTxStart 		(19<<11)
-#define StartDMAUp 		(20<<11)
-#define StartDMADown 		(20<<11)+1
+#define TotalReset		(0<<11)
+#define SelectWindow		(1<<11)
+#define StartCoax		(2<<11)
+#define RxDisable		(3<<11)
+#define RxEnable		(4<<11)
+#define RxReset			(5<<11)
+#define UpStall			(6<<11)
+#define UpUnstall		(6<<11)+1
+#define DownStall		(6<<11)+2
+#define DownUnstall		(6<<11)+3
+#define RxDiscard		(8<<11)
+#define TxEnable		(9<<11)
+#define TxDisable		(10<<11)
+#define TxReset			(11<<11)
+#define FakeIntr		(12<<11)
+#define AckIntr			(13<<11)
+#define SetIntrEnb		(14<<11)
+#define SetStatusEnb		(15<<11)
+#define SetRxFilter		(16<<11)
+#define SetRxThreshold		(17<<11)
+#define SetTxThreshold		(18<<11)
+#define SetTxStart		(19<<11)
+#define StartDMAUp		(20<<11)
+#define StartDMADown		(20<<11)+1
 #define StatsEnable		(21<<11)
 #define StatsDisable		(22<<11)
-#define StopCoax 		(23<<11)
-#define SetFilterBit 		(25<<11)
+#define StopCoax		(23<<11)
+#define SetFilterBit		(25<<11)
 
 /* The SetRxFilter command accepts the following classes */
 
-#define RxStation 		1
+#define RxStation		1
 #define RxMulticast		2
 #define RxBroadcast		4
-#define RxProm 			8
+#define RxProm			8
 
 /* 3Com status word defnitions */
 
-#define IntLatch 		0x0001
-#define HostError 		0x0002
-#define TxComplete 		0x0004
-#define TxAvailable 		0x0008
-#define RxComplete 		0x0010
-#define RxEarly 		0x0020
-#define IntReq 			0x0040
-#define StatsFull 		0x0080
-#define DMADone 		(1<<8)
-#define DownComplete 		(1<<9)
-#define UpComplete 		(1<<10)
-#define DMAInProgress 		(1<<11)			/* DMA controller is still busy.*/
-#define CmdInProgress 		(1<<12)           	/* EL3_CMD is still busy.*/
+#define IntLatch		0x0001
+#define HostError		0x0002
+#define TxComplete		0x0004
+#define TxAvailable		0x0008
+#define RxComplete		0x0010
+#define RxEarly			0x0020
+#define IntReq			0x0040
+#define StatsFull		0x0080
+#define DMADone			(1<<8)
+#define DownComplete		(1<<9)
+#define UpComplete		(1<<10)
+#define DMAInProgress		(1<<11)			/* DMA controller is still busy.*/
+#define CmdInProgress		(1<<12)          	/* EL3_CMD is still busy.*/
 
 /* Polling Registers */
 
@@ -100,17 +100,17 @@
 
 /* Register window 0 offets */
 
-#define Wn0EepromCmd 		10	          	/* Window 0: EEPROM command register. */
-#define Wn0EepromData 		12             		/* Window 0: EEPROM results register. */
+#define Wn0EepromCmd		10	         	/* Window 0: EEPROM command register. */
+#define Wn0EepromData		12            		/* Window 0: EEPROM results register. */
 #define IntrStatus		0x0E	                /* Valid in all windows. */
 
 /* Register window 0 EEPROM bits */
 
-#define EEPROM_Read 		0x80
-#define EEPROM_WRITE 		0x40
-#define EEPROM_ERASE 		0xC0
-#define EEPROM_EWENB 		0x30            	/* Enable erasing/writing for 10 msec. */
-#define EEPROM_EWDIS 		0x00            	/* Disable EWENB before 10 msec timeout. */
+#define EEPROM_Read		0x80
+#define EEPROM_WRITE		0x40
+#define EEPROM_ERASE		0xC0
+#define EEPROM_EWENB		0x30          		/* Enable erasing/writing for 10 msec. */
+#define EEPROM_EWDIS		0x00           		/* Disable EWENB before 10 msec timeout. */
 
 /* EEPROM locations. */
 
@@ -129,13 +129,13 @@
 
 /* Register window 1 offsets, the window used in normal operation */
 
-#define TX_FIFO 		0x10
-#define RX_FIFO 		0x10
-#define RxErrors 		0x14
-#define RxStatus 		0x18
+#define TX_FIFO			0x10
+#define RX_FIFOa		0x10
+#define RxErrors		0x14
+#define RxStatus		0x18
 #define Timer			0x1A
-#define TxStatus 		0x1B
-#define TxFree 			0x1C	 		/* Remaining free bytes in Tx buffer. */
+#define TxStatus		0x1B
+#define TxFree			0x1C			/* Remaining free bytes in Tx buffer. */
 
 /* Register Window 2 */
 
@@ -147,47 +147,47 @@
 #define Wn3_MAC_Ctrl		6
 #define Wn3_Options		8
 
-#define BFEXT(value, offset, bitcount)  					\
+#define BFEXT(value, offset, bitcount)					\
 	((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
 
 #define BFINS(lhs, rhs, offset, bitcount)                                       \
-	(((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) |   		\
+	(((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) |			\
 	(((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
 
 #define RAM_SIZE(v)             BFEXT(v, 0, 3)
-#define RAM_WIDTH(v)    	BFEXT(v, 3, 1)
-#define RAM_SPEED(v)    	BFEXT(v, 4, 2)
+#define RAM_WIDTH(v)		BFEXT(v, 3, 1)
+#define RAM_SPEED(v) 	   	BFEXT(v, 4, 2)
 #define ROM_SIZE(v)             BFEXT(v, 6, 2)
-#define RAM_SPLIT(v)    	BFEXT(v, 16, 2)
+#define RAM_SPLIT(v)		BFEXT(v, 16, 2)
 #define XCVR(v)                 BFEXT(v, 20, 4)
-#define AUTOSELECT(v)   	BFEXT(v, 24, 1)
+#define AUTOSELECT(v)		BFEXT(v, 24, 1)
 
 /* Register Window 4: Xcvr/media bits */
 
-#define Wn4_FIFODiag 		4
-#define Wn4_NetDiag 		6
+#define Wn4_FIFODiag		4
+#define Wn4_NetDiag		6
 #define Wn4_PhysicalMgmt	8
-#define Wn4_Media 		10
+#define Wn4_Media		10
 
-#define Media_SQE 		0x0008     		/* Enable SQE error counting for AUI. */
-#define Media_10TP 		0x00C0			/* Enable link beat and jabber for 10baseT. */
-#define Media_Lnk 		0x0080			/* Enable just link beat for 100TX/100FX. */
-#define Media_LnkBeat 		0x0800
+#define Media_SQE		0x0008		/* Enable SQE error counting for AUI. */
+#define Media_10TP		0x00C0		/* Enable link beat and jabber for 10baseT. */
+#define Media_Lnk		0x0080		/* Enable just link beat for 100TX/100FX. */
+#define Media_LnkBeat		0x0800
 
 /* Register Window 7: Bus Master control */
 
-#define Wn7_MasterAddr 		0
-#define Wn7_MasterLen 		6
-#define Wn7_MasterStatus 	12
+#define Wn7_MasterAddr		0
+#define Wn7_MasterLen		6
+#define Wn7_MasterStatus	12
 
 /* Boomerang bus master control registers. */
 
-#define PktStatus 		0x20
+#define PktStatus		0x20
 #define DownListPtr		0x24
-#define FragAddr 		0x28
-#define FragLen 		0x2c
+#define FragAddr		0x28
+#define FragLen			0x2c
 #define TxFreeThreshold 	0x2f
-#define UpPktStatus 		0x30
+#define UpPktStatus		0x30
 #define UpListPtr 		0x38
 
 /* The Rx and Tx descriptor lists. */
diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
new file mode 100644
index 0000000..183f694
--- /dev/null
+++ b/board/amcc/acadia/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o cpr.o memory.o
+SOBJS	=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
new file mode 100644
index 0000000..c8aaad2
--- /dev/null
+++ b/board/amcc/acadia/acadia.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+extern void board_pll_init_f(void);
+
+/* Some specific Acadia Defines */
+#define CPLD_BASE	0x80000000
+
+void liveoak_gpio_init(void)
+{
+	/*
+	 * GPIO0 setup (select GPIO or alternate function)
+	 */
+       	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
+       	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select */
+       	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
+       	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select */
+       	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+       	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select */
+       	out32(GPIO0_TCR, CFG_GPIO0_TCR);  /* enable output driver for outputs */
+
+	/*
+	 * Ultra (405EZ) was nice enough to add another GPIO controller
+	 */
+	out32(GPIO1_OSRH, CFG_GPIO1_OSRH);	/* output select */
+	out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
+	out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H);	/* input select */
+	out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
+	out32(GPIO1_TSRH, CFG_GPIO1_TSRH);	/* three-state select */
+	out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
+	out32(GPIO1_TCR, CFG_GPIO1_TCR);  /* enable output driver for outputs */
+}
+
+#if 0 /* test-only: not called at all??? */
+void ext_bus_cntlr_init(void)
+{
+#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
+       	mtebc(pb4ap, EBC_PB4AP);
+       	mtebc(pb4cr, EBC_PB4CR);
+#endif
+}
+#endif
+
+int board_early_init_f(void)
+{
+	unsigned int reg;
+
+#if 0 /* test-only */
+	/*
+	 * If CRAM memory and SPI/NAND boot, and if the CRAM memory is
+	 * already initialized by the pre-loader then we can't reinitialize
+	 * CPR registers, GPIO registers and EBC registers as this will
+	 * have the effect of un-initializing CRAM.
+	 */
+	spr_reg = (volatile unsigned long) mfspr(SPRG7);
+	if (spr_reg != LOAK_CRAM) { /* != CRAM */
+		board_pll_init_f();
+		liveoak_gpio_init();
+		ext_bus_cntlr_init();
+
+		mtebc(pb1ap, CFG_EBC_PB1AP);
+		mtebc(pb1cr, CFG_EBC_PB1CR);
+
+		mtebc(pb2ap, CFG_EBC_PB2AP);
+		mtebc(pb2cr, CFG_EBC_PB2CR);
+	}
+#else
+	board_pll_init_f();
+	liveoak_gpio_init();
+/*	ext_bus_cntlr_init(); */
+#endif
+
+#if 0 /* test-only (orig) */
+	/*
+	 * If we boot from NAND Flash, we are running in
+	 * RAM, so disable the EBC_CS0 so that it goes back
+	 * to the NOR Flash.  It will be enabled later
+	 * for the NAND Flash on EBC_CS1
+	 */
+	mfsdr(sdrultra0, reg);
+	mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
+#endif
+#if 0 /* test-only */
+	/* configure for NAND */
+	mfsdr(sdrultra0, reg);
+	reg &= ~SDR_ULTRA0_CSN_MASK;
+	reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS;
+	mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
+#endif
+
+	/* USB Host core needs this bit set */
+	mfsdr(sdrultra1, reg);
+	mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
+
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicer, 0x00000000);	/* disable all ints */
+	mtdcr(uiccr, 0x00000010);
+	mtdcr(uicpr, 0xFE7FFFF0);	/* set int polarities */
+	mtdcr(uictr, 0x00000010);	/* set int trigger levels */
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+int misc_init_f(void)
+{
+	/* Set EPLD to take PHY out of reset */
+	out8(CPLD_BASE + 0x05, 0x00);
+	udelay(100000);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk
new file mode 100644
index 0000000..ce21374
--- /dev/null
+++ b/board/amcc/acadia/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(TOPDIR)/board/amcc/liveoak/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFC0000
+endif
+
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
+
+ifeq ($(CONFIG_SPI_U_BOOT),y)
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-spi.lds
+PAD_TO = 0x00840000
+endif
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/cpr.c
new file mode 100644
index 0000000..23b9e12
--- /dev/null
+++ b/board/amcc/acadia/cpr.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc405.h>
+
+/* test-only: move into cpu directory!!! */
+
+#if defined(PLLMR0_200_133_66)
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------------------
+	 * | CLK   | FREQ (MHz) | DIV RATIO |
+	 * ----------------------------------
+	 * | CPU   |  200.0     |   4 (0x02)|
+	 * | PLB   |  133.3     |   6 (0x06)|
+	 * | OPB   |   66.6     |  12 (0x0C)|
+	 * | EBC   |   66.6     |  12 (0x0C)|
+	 * | SPI   |   66.6     |  12 (0x0C)|
+	 * | UART0 |   10.0     |  40 (0x28)|
+	 * | UART1 |   10.0     |  40 (0x28)|
+	 * | DAC   |    2.0     | 200 (0xC8)|
+	 * | ADC   |    2.0     | 200 (0xC8)|
+	 * | PWM   |  100.0     |   4 (0x04)|
+	 * | EMAC  |   25.0     |  16 (0x10)|
+	 * -----------------------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(cprpllc, 0x0000033c);
+	mtcpr(cprplld, 0x0c010200);
+	mtcpr(cprprimad, 0x04060c0c);
+	mtcpr(cprperd0, 0x000c0000);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_266_160_80)
+
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------------------
+	 * | CLK   | FREQ (MHz) | DIV RATIO |
+	 * ----------------------------------
+	 * | CPU   |  266.64    |   3       |
+	 * | PLB   |  159.98    |   5 (0x05)|
+	 * | OPB   |   79.99    |  10 (0x0A)|
+	 * | EBC   |   79.99    |  10 (0x0A)|
+	 * | SPI   |   79.99    |  10 (0x0A)|
+	 * | UART0 |   28.57    |   7 (0x07)|
+	 * | UART1 |   28.57    |   7 (0x07)|
+	 * | DAC   |   28.57    |   7 (0xA7)|
+	 * | ADC   |    4     	|  50 (0x32)|
+	 * | PWM   |   28.57    |   7 (0x07)|
+	 * | EMAC  |    4       |  50 (0x32)|
+	 * -----------------------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(cprpllc,   0x20000238);
+	mtcpr(cprplld,   0x03010400);
+	mtcpr(cprprimad, 0x03050a0a);
+	mtcpr(cprperc0,  0x00000000);
+	mtcpr(cprperd0,  0x070a0707);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprperd1,  0x07323200);
+	mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_333_166_83)
+
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------------------
+	 * | CLK   | FREQ (MHz) | DIV RATIO |
+	 * ----------------------------------
+	 * | CPU   |  333.33    |   2       |
+	 * | PLB   |  166.66    |   4 (0x04)|
+	 * | OPB   |   83.33    |   8 (0x08)|
+	 * | EBC   |   83.33    |   8 (0x08)|
+	 * | SPI   |   83.33    |   8 (0x08)|
+	 * | UART0 |   16.66    |   5 (0x05)|
+	 * | UART1 |   16.66    |   5 (0x05)|
+	 * | DAC   |   ????     | 166 (0xA6)|
+	 * | ADC   |   ????     | 166 (0xA6)|
+	 * | PWM   |   41.66    |   3 (0x03)|
+	 * | EMAC  |   ????     |   3 (0x03)|
+	 * -----------------------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(cprpllc,   0x0000033C);
+	mtcpr(cprplld,   0x0a010000);
+	mtcpr(cprprimad, 0x02040808);
+	mtcpr(cprperd0,  0x02080505);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprperd1,  0xA6A60300);
+	mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_100_100_12)
+
+void board_pll_init_f(void)
+{
+	/*
+	 * set PLL clocks based on input sysclk is 33M
+	 *
+	 * ----------------------
+	 * | CLK   | FREQ (MHz) |
+	 * ----------------------
+	 * | CPU   |  100.00    |
+	 * | PLB   |  100.00    |
+	 * | OPB   |   12.00    |
+	 * | EBC   |   49.00    |
+	 * ----------------------
+	 */
+
+	/* Initialize PLL */
+	mtcpr(cprpllc,   0x000003BC);
+	mtcpr(cprplld,   0x06060600);
+	mtcpr(cprprimad, 0x02020004);
+	mtcpr(cprperd0,  0x04002828);	/* SPI clk div. eq. OPB clk div. */
+	mtcpr(cprperd1,  0xC8C81600);
+	mtcpr(cprclkupd, 0x40000000);
+}
+#endif /* CPU_<speed>_405EZ */
+
+#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk (void)
+{
+	unsigned long cpr_plld;
+	unsigned long cpr_primad;
+	unsigned long primad_cpudv;
+	unsigned long pllFbkDiv;
+	unsigned long freqProcessor;
+
+	/*
+	 * Read PLL Mode registers
+	 */
+	mfcpr(cprplld, cpr_plld);
+
+	/*
+	 * Read CPR_PRIMAD register
+	 */
+	mfcpr(cprprimad, cpr_primad);
+
+	/*
+	 * Determine CPU clock frequency
+	 */
+	primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
+	if (primad_cpudv == 0)
+		primad_cpudv = 16;
+
+	/*
+	 * Determine FBK_DIV.
+	 */
+	pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
+	if (pllFbkDiv == 0)
+		pllFbkDiv = 256;
+
+	freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
+
+	return (freqProcessor);
+}
+#endif	/* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
diff --git a/board/amcc/acadia/flash.c b/board/amcc/acadia/flash.c
new file mode 100644
index 0000000..0626aba
--- /dev/null
+++ b/board/amcc/acadia/flash.c
@@ -0,0 +1,1108 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+	{0xffc00001}, /* 0:boot from big flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MIXC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AMD016:
+		printf("AM29F016D (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM033C:
+		printf("AM29LV033C (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:
+		printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:
+		printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_STMW320DT:
+		printf ("M29W320DT (32 M, top sector)\n");
+		break;
+	case FLASH_MXLV320T:
+		printf ("MXLV320T (32 Mbit, top sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+	       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s%s",
+		       info->start[i],
+		       erased ? " E" : "  ", info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	/* bit 0 used for big flash marking */
+	if ((ulong)addr & 0x1) {
+		return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+	} else {
+		return flash_get_size_1(addr, info);
+	}
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+	short i;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+		info->flash_id += FLASH_AMD016;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+		info->flash_id += FLASH_AMDLV033C;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CFG_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+		return flash_erase_2(info, s_first, s_last);
+	} else {
+		return flash_erase_1(info, s_first, s_last);
+	}
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_1(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+		return write_word_2(info, dest, data);
+	} else {
+		return write_word_1(info, dest, data);
+	}
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+
+#undef  CFG_FLASH_WORD_SIZE
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	int n;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+#if 0 /* TODO: remove ifdef when Flash responds correctly */
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (CFG_FLASH_WORD_SIZE) MX_MANUFACT:
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+#endif /* TODO: remove ifdef when Flash responds correctly */
+
+	/*
+	 * TODO: Start
+	 * 	 uncomment block above when Flash responds correctly.
+	 *	 also remove the lines below:
+	 */
+	info->flash_id = FLASH_MAN_AMD;
+	DEBUGF("FLASH MANUFACT: FLASH_MAN_AMD\n");
+	/* TODO: End */
+
+	value = addr2[1];	/* device ID            */
+
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+#if 0 /* TODO: remove ifdef when Flash responds correctly */
+	switch (value) {
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+		info->flash_id += FLASH_STMW320DT;
+		info->sector_count = 67;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
+		info->flash_id += FLASH_MXLV320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+#endif /* TODO: remove ifdef when Flash responds correctly */
+
+	/*
+	 * TODO: Start
+	 * 	 uncomment block above when Flash responds correctly.
+	 *	 also remove the lines below:
+	 */
+	DEBUGF("\nFLASH DEVICEID: FLASH_AM320T\n");
+	info->flash_id += FLASH_AM320T;
+	info->sector_count = 71;
+	info->size = 0x00400000;  /* => 4 MB	*/
+	/* TODO: End */
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		/*  1 x 16k boot sector */
+		base -= 16 << 10;
+		--i;
+		info->start[i] = base;
+		/*  2 x 8k  boot sectors */
+		for (n=0; n<2; ++n) {
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		/*  1 x 32k boot sector */
+		base -= 32 << 10;
+		--i;
+		info->start[i] = base;
+
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else if ( ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
+		    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ) {
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00002000;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000a000;
+		info->start[i--] = base + info->size - 0x0000c000;
+		info->start[i--] = base + info->size - 0x0000e000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+	else {
+		if (info->flash_id & FLASH_BTYPE){
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address,(A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+/*
+ * TODO: FIX: this wait loop sometimes fails: DQ7 indicates the erase command
+ *		never was accepted (i.e. didn't start) - why????
+ */
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+	ulong start, now, last, counter = 0;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	DEBUGF("DQ7_2: start = 0x%08lx\n", start);
+	last = start;
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CFG_FLASH_WORD_SIZE) 0x00800080) {
+		DEBUGF("DQ7_2: start = 0x%08lx, now = 0x%08lx\n", start, now);
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+		udelay(1000000); /* 1 sec */
+		putc('.');
+		counter++;
+		if (counter > 5)  {
+			return -1;
+		}
+		DEBUGF("DQ7_2: now = 0x%08lx, last = 0x%08lx\n", now, last);
+	}
+	return 0;
+}
+
+static void wr_flash_cmd(ulong sector, ushort addr, CFG_FLASH_WORD_SIZE value)
+{
+	int fw_size;
+
+	fw_size = sizeof(value);
+	switch (fw_size)
+	{
+	case 1:
+		out8((ulong)(sector + addr), value);
+		break;
+	case 2:
+		out16((ulong)(sector + (addr << 1)), value);
+		break;
+	default:
+		printf("flash_erase: error incorrect chip programing size.\n");
+	}
+	return;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect, count = 0;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first, count = 0; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				/*
+				 * TODO: fix code
+				 */
+				wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0);
+				wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA);
+				wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055);
+				wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00800080);
+				wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA);
+				wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055);
+				wr_flash_cmd((ulong)addr2, 0, (CFG_FLASH_WORD_SIZE) 0x00300030);
+				udelay(2000000);	/* 2 sec */
+				wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0);
+
+#if 0
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+#endif
+			}
+			l_sect = sect;
+			printf("..");
+			printf("..");
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_2(info, sect);
+			count++;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+
+	if (count > 0) {
+		return 0;
+	} else {
+		return 1;
+	}
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+#endif /* CFG_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+	index = 0;
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+				   &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			       i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH)
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+				    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND)
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+				    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#endif
+#endif
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
new file mode 100644
index 0000000..a1b0155
--- /dev/null
+++ b/board/amcc/acadia/memory.c
@@ -0,0 +1,552 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#define CRAM_BANK0_BASE 		0x0
+#define CRAM_DIDR			0x00100000
+#define	MICRON_MT45W8MW16BGX_CRAM_ID	0x1b431b43
+#define	MICRON_MT45W8MW16BGX_CRAM_ID2	0x13431343
+#define	MICRON_DIDR_VENDOR_ID		0x00030003	/* 00011b */
+#define	CRAM_DIDR_VENDOR_ID_MASK	0x001f001f	/* DIDR[4:0] */
+#define	CRAM_DEVID_NOT_SUPPORTED	0x00000000
+
+#define PSRAM_PASS	0x50415353	/* "PASS" */
+#define PSRAM_FAIL	0x4641494C	/* "FAIL" */
+
+static u32 is_cram_inited(void);
+static u32 is_cram(void);
+static long int cram_init(u32);
+static void cram_bcr_write(u32);
+void udelay (unsigned long);
+
+void sdram_init(void)
+{
+	volatile unsigned long spr_reg;
+
+	/*
+	 * If CRAM not initialized or CRAM looks initialized because this
+	 * is after a warm reboot then set SPRG7 to indicate CRAM needs
+	 * initialization.  Note that CRAM is initialized by the SPI and
+	 * NAND preloader.
+	 */
+	spr_reg = (volatile unsigned long) mfspr(SPRG6);
+	if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) {
+		mtspr(SPRG7, LOAK_NONE);	/* "NONE" */
+	}
+#if 1
+	/*
+	 * When running the NAND SPL, the normal EBC configuration is not
+	 * done, so We need to enable EPLD access on EBC_CS_2 and the memory
+	 * on EBC_CS_3
+	 */
+
+	/* Enable CPLD - Needed for PSRAM Access */
+
+
+	/* Init SDRAM by setting EBC Bank 3 for PSRAM */
+	mtebc(pb1ap, CFG_EBC_PB1AP);
+	mtebc(pb1cr, CFG_EBC_PB1CR);
+
+	mtebc(pb2ap, CFG_EBC_PB2AP);
+	mtebc(pb2cr, CFG_EBC_PB2CR);
+
+	/* pre-boot loader code: we are in OCM */
+	mtspr(SPRG6, LOAK_SPL);	/* "SPL " */
+	mtspr(SPRG7, LOAK_OCM);	/* "OCM " */
+#endif
+	return;
+}
+
+static void cram_bcr_write(u32 wr_val)
+{
+	u32 tmp_reg;
+	u32 val;
+	volatile u32 gpio_reg;
+
+	/* # Program CRAM write */
+
+	/*
+	 * set CRAM_CRE = 0x1
+	 * set wr_val = wr_val << 2
+	 */
+	gpio_reg = in32(GPIO1_OR);
+	out32(GPIO1_OR,  gpio_reg | 0x00000400);
+	wr_val = wr_val << 2;
+	/* wr_val = 0x1c048; */
+
+	/*
+	 * # stop PLL clock before programming CRAM
+	 * set EPLD0_MUX_CTL.OESPR3 = 1
+	 * delay 2
+	 */
+
+	/*
+	 * # CS1
+	 * read 0x00200000
+	 * #shift 2 bit left before write
+	 * set val = wr_val + 0x00200000
+	 * write dmem val 0
+	 * read 0x00200000 val
+	 * print val/8x
+	 */
+	tmp_reg = in32(0x00200000);
+	val = wr_val + 0x00200000;
+	/* val = 0x0021c048; */
+	out32(val, 0x0000);
+	udelay(100000);
+	val = in32(0x00200000);
+
+	debug("CRAM VAL: %x for CS1 ", val);
+
+	/*
+	 * # CS2
+	 * read 0x02200000
+	 * #shift 2 bit left before write
+	 * set val = wr_val + 0x02200000
+	 * write dmem val 0
+	 * read 0x02200000 val
+	 * print val/8x
+	 */
+	tmp_reg = in32(0x02200000);
+	val = wr_val + 0x02200000;
+	/* val = 0x0221c048; */
+	out32(val, 0x0000);
+	udelay(100000);
+	val = in32(0x02200000);
+
+	debug("CRAM VAL: %x for CS2 ", val);
+
+	/*
+	 * # Start PLL clock before programming CRAM
+	 * set EPLD0_MUX_CTL.OESPR3 = 0
+	 */
+
+	/*
+	 * set CRAMCR = 0x1
+	 */
+	gpio_reg = in32(GPIO1_OR);
+	out32(GPIO1_OR,  gpio_reg | 0x00000400);
+
+	/*
+	 * # read CRAM config BCR ( bit19:18 = 10b )
+	 * #read 0x00200000
+	 * # 1001_1001_0001_1111 ( 991f ) =>
+	 * #10_0110_0100_0111_1100  =>   2647c => 0022647c
+	 * #0011_0010_0011_1110 (323e)
+	 * #
+	 */
+
+	/*
+	 * set EPLD0_MUX_CTL.CRAMCR = 0x0
+	 */
+	gpio_reg = in32(GPIO1_OR);
+	out32(GPIO1_OR,  gpio_reg & 0xFFFFFBFF);
+	return;
+}
+
+static u32 is_cram_inited()
+{
+	volatile unsigned long spr_reg;
+
+	/*
+ 	 * If CRAM is initialized already, then don't reinitialize it again.
+	 * In the case of NAND boot and SPI boot, CRAM will already be
+	 * initialized by the pre-loader
+	 */
+	spr_reg = (volatile unsigned long) mfspr(SPRG7);
+	if (spr_reg == LOAK_CRAM) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+/******
+ * return 0 if not CRAM
+ * return 1 if CRAM and it's already inited by preloader
+ * else return cram_id (CRAM Device Identification Register)
+ ******/
+static u32 is_cram(void)
+{
+	u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L;
+	volatile u32 gpio_reg;
+	volatile u32 cram_id = 0;
+
+	if (is_cram_inited() == 1) {
+		/* this is CRAM and it is already inited (by preloader) */
+		cram_id = 1;
+	} else {
+		/*
+		 * # CRAM CLOCK
+		 * set GPIO0_TCR.G8 = 1
+		 * set GPIO0_OSRL.G8 = 0
+		 * set GPIO0_OR.G8 = 0
+		 */
+		gpio_reg = in32(GPIO0_TCR);
+		gpio_TCR = gpio_reg;
+		out32(GPIO0_TCR, gpio_reg | 0x00800000);
+		gpio_reg = in32(GPIO0_OSRL);
+		gpio_OSRL = gpio_reg;
+		out32(GPIO0_OSRL, gpio_reg & 0xffffbfff);
+		gpio_reg = in32(GPIO0_OR);
+		gpio_OR = gpio_reg;
+		out32(GPIO0_OR, gpio_reg & 0xff7fffff);
+
+		/*
+		 * # CRAM Addreaa Valid
+		 * set GPIO0_TCR.G10 = 1
+		 * set GPIO0_OSRL.G10 = 0
+		 * set GPIO0_OR.G10 = 0
+		 */
+		gpio_reg = in32(GPIO0_TCR);
+		out32(GPIO0_TCR, gpio_reg | 0x00200000);
+		gpio_reg = in32(GPIO0_OSRL);
+		out32(GPIO0_OSRL, gpio_reg & 0xfffffbff);
+		gpio_reg = in32(GPIO0_OR);
+		out32(GPIO0_OR, gpio_reg & 0xffdfffff);
+
+		/*
+		 * # config input (EBC_WAIT)
+		 * set GPIO0_ISR1L.G9 = 1
+		 * set GPIO0_TCR.G9 = 0
+		 */
+		gpio_reg = in32(GPIO0_ISR1L);
+		gpio_ISR1L = gpio_reg;
+		out32(GPIO0_ISR1L, gpio_reg | 0x00001000);
+		gpio_reg = in32(GPIO0_TCR);
+		out32(GPIO0_TCR, gpio_reg & 0xffbfffff);
+
+		/*
+		 * Enable CRE to read Registers
+		 * set GPIO0_TCR.21 = 1
+		 * set GPIO1_OR.21 = 1
+		 */
+		gpio_reg = in32(GPIO1_TCR);
+		out32(GPIO1_TCR, gpio_reg | 0x00000400);
+
+		gpio_reg = in32(GPIO1_OR);
+		out32(GPIO1_OR,  gpio_reg | 0x00000400);
+
+		/* Read Version ID */
+		cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR);
+		udelay(100000);
+
+		asm volatile("	sync");
+		asm volatile("	eieio");
+
+		debug("Cram ID: %X ", cram_id);
+
+		switch (cram_id) {
+		case MICRON_MT45W8MW16BGX_CRAM_ID:
+		case MICRON_MT45W8MW16BGX_CRAM_ID2:
+			/* supported CRAM vendor/part */
+			break;
+		case CRAM_DEVID_NOT_SUPPORTED:
+		default:
+			/* check for DIDR Vendor ID of Micron */
+			if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) ==
+						MICRON_DIDR_VENDOR_ID)
+			{
+				/* supported CRAM vendor */
+				break;
+			}
+			/* this is not CRAM or not supported CRAM vendor/part */
+			cram_id = 0;
+			/*
+			 * reset the GPIO registers to the values that were
+			 * there before this routine
+			 */
+			out32(GPIO0_TCR, gpio_TCR);
+			out32(GPIO0_OSRL, gpio_OSRL);
+			out32(GPIO0_OR, gpio_OR);
+			out32(GPIO0_ISR1L, gpio_ISR1L);
+			break;
+		}
+	}
+
+	return cram_id;
+}
+
+static long int cram_init(u32 already_inited)
+{
+	volatile u32 tmp_reg;
+	u32 cram_wr_val;
+
+	if (already_inited == 0) return 0;
+
+	/*
+	 * If CRAM is initialized already, then don't reinitialize it again.
+	 * In the case of NAND boot and SPI boot, CRAM will already be
+	 * initialized by the pre-loader
+	 */
+	if (already_inited != 1) {
+		/*
+		 * #o CRAM Card
+		 * #  - CRAMCRE @reg16 = 1; for CRAM to use
+		 * #  - CRAMCRE @reg16 = 0; for CRAM to program
+		 *
+		 * # enable CRAM SEL, move from setEPLD.cmd
+		 * set EPLD0_MUX_CTL.OECRAM = 0
+		 * set EPLD0_MUX_CTL.CRAMCR = 1
+		 * set EPLD0_ETHRSTBOOT.SLCRAM = 0
+		 * #end
+		 */
+
+		/*
+		 * #1. EBC need to program READY, CLK, ADV for ASync mode
+		 * # config output
+		 */
+
+		/*
+		 * # CRAM CLOCK
+		 * set GPIO0_TCR.G8 = 1
+		 * set GPIO0_OSRL.G8 = 0
+		 * set GPIO0_OR.G8 = 0
+		 */
+		tmp_reg = in32(GPIO0_TCR);
+		out32(GPIO0_TCR, tmp_reg | 0x00800000);
+		tmp_reg = in32(GPIO0_OSRL);
+		out32(GPIO0_OSRL, tmp_reg & 0xffffbfff);
+		tmp_reg = in32(GPIO0_OR);
+		out32(GPIO0_OR, tmp_reg & 0xff7fffff);
+
+		/*
+		 * # CRAM Addreaa Valid
+		 * set GPIO0_TCR.G10 = 1
+		 * set GPIO0_OSRL.G10 = 0
+		 * set GPIO0_OR.G10 = 0
+		 */
+		tmp_reg = in32(GPIO0_TCR);
+		out32(GPIO0_TCR, tmp_reg | 0x00200000);
+		tmp_reg = in32(GPIO0_OSRL);
+		out32(GPIO0_OSRL, tmp_reg & 0xfffffbff);
+		tmp_reg = in32(GPIO0_OR);
+		out32(GPIO0_OR, tmp_reg & 0xffdfffff);
+
+		/*
+		 * # config input (EBC_WAIT)
+		 * set GPIO0_ISR1L.G9 = 1
+		 * set GPIO0_TCR.G9 = 0
+		 */
+		tmp_reg = in32(GPIO0_ISR1L);
+		out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
+		tmp_reg = in32(GPIO0_TCR);
+		out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
+
+		/*
+		 * # config CS4 from GPIO
+		 * set GPIO0_TCR.G0 = 1
+		 * set GPIO0_OSRL.G0 = 1
+		 */
+		tmp_reg = in32(GPIO0_TCR);
+		out32(GPIO0_TCR, tmp_reg | 0x80000000);
+		tmp_reg = in32(GPIO0_OSRL);
+		out32(GPIO0_OSRL, tmp_reg | 0x40000000);
+
+		/*
+		 * #2. EBC in Async mode
+		 * # set EBC0_PB1AP = 0x078f0ec0
+		 * set EBC0_PB1AP = 0x078f1ec0
+		 * set EBC0_PB2AP = 0x078f1ec0
+		 */
+		mtebc(pb1ap, 0x078F1EC0);
+		mtebc(pb2ap, 0x078F1EC0);
+
+		/*
+		 * #set EBC0_PB1CR = 0x000bc000
+		 * #enable CS2 for CRAM
+		 * set EBC0_PB2CR = 0x020bc000
+		 */
+		mtebc(pb1cr, 0x000BC000);
+		mtebc(pb2cr, 0x020BC000);
+
+		/*
+		 * #3. set CRAM in Sync mode
+		 * #exec cm_bcr_write.cmd { 0x701f }
+		 * #3. set CRAM in Sync mode (full drv strength)
+		 * exec cm_bcr_write.cmd { 0x701F }
+		 */
+		cram_wr_val = 0x7012;	/* CRAM burst setting */
+		cram_bcr_write(cram_wr_val);
+
+		/*
+		 * #4. EBC in Sync mode
+		 * #set EBC0_PB1AP = 0x9f800fc0
+		 * #set EBC0_PB1AP = 0x900001c0
+		 * set EBC0_PB2AP = 0x9C0201c0
+		 * set EBC0_PB2AP = 0x9C0201c0
+		 */
+		mtebc(pb1ap, 0x9C0201C0);
+		mtebc(pb2ap, 0x9C0201C0);
+
+		/*
+		 * #5. EBC need to program READY, CLK, ADV for Sync mode
+		 * # config output
+		 * set GPIO0_TCR.G8 = 1
+		 * set GPIO0_OSRL.G8 = 1
+		 * set GPIO0_TCR.G10 = 1
+		 * set GPIO0_OSRL.G10 = 1
+		 */
+		tmp_reg = in32(GPIO0_TCR);
+		out32(GPIO0_TCR, tmp_reg | 0x00800000);
+		tmp_reg = in32(GPIO0_OSRL);
+		out32(GPIO0_OSRL, tmp_reg | 0x00004000);
+		tmp_reg = in32(GPIO0_TCR);
+		out32(GPIO0_TCR, tmp_reg | 0x00200000);
+		tmp_reg = in32(GPIO0_OSRL);
+		out32(GPIO0_OSRL, tmp_reg | 0x00000400);
+
+		/*
+		 * # config input
+		 * set GPIO0_ISR1L.G9 = 1
+		 * set GPIO0_TCR.G9 = 0
+		 */
+		tmp_reg = in32(GPIO0_ISR1L);
+		out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
+		tmp_reg = in32(GPIO0_TCR);
+		out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
+
+		/*
+		 * # config EBC to use RDY
+		 * set SDR0_ULTRA0.EBCREN = 1
+		 */
+		mfsdr(sdrultra0, tmp_reg);
+		mtsdr(sdrultra0, tmp_reg | 0x04000000);
+
+		/*
+		 * set EPLD0_MUX_CTL.OESPR3 = 0
+		 */
+		mtspr(SPRG7, LOAK_CRAM);	/* "CRAM" */
+	} /* if (already_inited != 1) */
+
+	return (64 * 1024 * 1024);
+}
+
+/******
+ * return 0 if not PSRAM
+ * return 1 if is PSRAM
+ ******/
+static int is_psram(u32 addr)
+{
+	u32 test_pattern = 0xdeadbeef;
+	volatile u32 readback;
+
+	if (addr == CFG_SDRAM_BASE) {
+		/* This is to temp enable OE for PSRAM */
+		out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
+		udelay(10000);
+	}
+
+	out32(addr, test_pattern);
+	asm volatile("	sync");
+	asm volatile("	eieio");
+
+	readback = (volatile u32) in32(addr);
+	asm volatile("	sync");
+	asm volatile("	eieio");
+	if (readback == test_pattern) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static long int psram_init(void)
+{
+	u32 readback;
+	long psramsize = 0;
+	int i;
+
+	/* This is to temp enable OE for PSRAM */
+	out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
+	udelay(10000);
+
+	/*
+	 * PSRAM bank 1: read then write to address 0x00000000
+	 */
+	for (i = 0; i < 100; i++) {
+		if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) {
+			readback = PSRAM_PASS;
+		} else {
+			readback = PSRAM_FAIL;
+			break;
+		}
+	}
+	if (readback == PSRAM_PASS) {
+		debug("psram_init(bank0): pass\n");
+		psramsize = (16 * 1024 * 1024);
+	} else {
+		debug("psram_init(bank0): fail\n");
+		return 0;
+	}
+
+#if 0
+	/*
+	 * PSRAM bank 1: read then write to address 0x01000000
+	 */
+	for (i = 0; i < 100; i++) {
+		if (is_psram((1 << 24) + (i*256)) == 1) {
+			readback = PSRAM_PASS;
+		} else {
+			readback = PSRAM_FAIL;
+			break;
+		}
+	}
+	if (readback == PSRAM_PASS) {
+		debug("psram_init(bank1): pass\n");
+		psramsize = psramsize + (16 * 1024 * 1024);
+	}
+#endif
+
+	mtspr(SPRG7, LOAK_PSRAM);	/* "PSRA" - PSRAM */
+
+	return psramsize;
+}
+
+long int initdram(int board_type)
+{
+	long int sram_size;
+	u32 cram_inited;
+
+	/* Determine Attached Memory Expansion Card*/
+	cram_inited = is_cram();
+	if (cram_inited != 0) {					/* CRAM */
+		debug("CRAM Expansion Card attached\n");
+		sram_size = cram_init(cram_inited);
+	} else if (is_psram(CFG_SDRAM_BASE+4) == 1) {		/* PSRAM */
+		debug("PSRAM Expansion Card attached\n");
+		sram_size = psram_init();
+	} else { 						/* no SRAM */
+		debug("No Memory Card Attached!!\n");
+		sram_size = 0;
+	}
+
+	return sram_size;
+}
+
+int testdram(void)
+{
+	return (0);
+}
diff --git a/board/amcc/acadia/u-boot.lds b/board/amcc/acadia/u-boot.lds
new file mode 100644
index 0000000..be03092
--- /dev/null
+++ b/board/amcc/acadia/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S
index cc8f8b4..c86076e 100644
--- a/board/amcc/ebony/init.S
+++ b/board/amcc/ebony/init.S
@@ -22,53 +22,7 @@
 
 #include <ppc_asm.tmpl>
 #include <config.h>
-
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K	    0x00000000
-#define SZ_4K	    0x00000010
-#define SZ_16K	    0x00000020
-#define SZ_64K	    0x00000030
-#define SZ_256K	    0x00000040
-#define SZ_1M	    0x00000050
-#define SZ_16M	    0x00000070
-#define SZ_256M	    0x00000090
-
-/* Storage attributes */
-#define SA_W	    0x00000800	    /* Write-through */
-#define SA_I	    0x00000400	    /* Caching inhibited */
-#define SA_M	    0x00000200	    /* Memory coherence */
-#define SA_G	    0x00000100	    /* Guarded */
-#define SA_E	    0x00000080	    /* Endian */
-
-/* Access control */
-#define AC_X	    0x00000024	    /* Execute */
-#define AC_W	    0x00000012	    /* Write */
-#define AC_R	    0x00000009	    /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)		((e) & 0xfffffc00)
-#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)		( (a)&0x00000fbf )
-
-#define tlbtab_start\
-	mflr    r1  ;\
-	bl 0f	    ;
-
-#define tlbtab_end\
-	.long 0, 0, 0	;   \
-0:	mflr    r0	;   \
-	mtlr    r1	;   \
-	blr		;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
 
 /**************************************************************************
  * TLB TABLE
@@ -81,16 +35,23 @@
  *
  *************************************************************************/
 
-    .section .bootpg,"ax"
-    .globl tlbtab
+	.section .bootpg,"ax"
+	.globl tlbtab
 
 tlbtab:
-    tlbtab_start
-    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
-    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
-    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
-    tlbtab_end
+	tlbtab_start
+
+	tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
+	tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
+	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+	tlbtab_end
diff --git a/board/amcc/katmai/Makefile b/board/amcc/katmai/Makefile
new file mode 100644
index 0000000..d06a402
--- /dev/null
+++ b/board/amcc/katmai/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o cmd_katmai.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c
new file mode 100644
index 0000000..684f6a5
--- /dev/null
+++ b/board/amcc/katmai/cmd_katmai.c
@@ -0,0 +1,267 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/byteorder.h>
+
+static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	uchar	chip;
+	ulong	data;
+	int	nbytes;
+	extern char console_buffer[];
+
+	char sysClock[4];
+	char cpuClock[4];
+	char plbClock[4];
+	char pcixClock[4];
+
+	if (argc < 3) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (strcmp(argv[2], "prom0") == 0)
+		chip = IIC0_BOOTPROM_ADDR;
+	else
+		chip = IIC0_ALT_BOOTPROM_ADDR;
+
+	do {
+		printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
+		nbytes = readline (" ? ");
+
+		if (strcmp(console_buffer, "quit") == 0)
+			return 0;
+
+		if ((strcmp(console_buffer, "33") != 0) &
+		    (strcmp(console_buffer, "66") != 0))
+			nbytes=0;
+
+		strcpy(sysClock, console_buffer);
+
+	} while (nbytes == 0);
+
+	do {
+		if (strcmp(sysClock, "66") == 0) {
+			printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
+		} else {
+#ifdef	CONFIG_STRESS
+			printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
+#else
+			printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
+#endif
+		}
+		nbytes = readline (" ? ");
+
+		if (strcmp(console_buffer, "quit") == 0)
+			return 0;
+
+		if (strcmp(sysClock, "66") == 0) {
+			if ((strcmp(console_buffer, "400") != 0) &
+			    (strcmp(console_buffer, "533") != 0)
+#ifdef	CONFIG_STRESS
+			    & (strcmp(console_buffer, "667") != 0)
+#endif
+				) {
+				nbytes = 0;
+			}
+		} else {
+			if ((strcmp(console_buffer, "400") != 0) &
+			    (strcmp(console_buffer, "500") != 0) &
+			    (strcmp(console_buffer, "533") != 0)
+#ifdef	CONFIG_STRESS
+			    & (strcmp(console_buffer, "667") != 0)
+#endif
+				) {
+				nbytes = 0;
+			}
+		}
+
+		strcpy(cpuClock, console_buffer);
+
+	} while (nbytes == 0);
+
+	if (strcmp(cpuClock, "500") == 0)
+		strcpy(plbClock, "166");
+	else if (strcmp(cpuClock, "533") == 0)
+		strcpy(plbClock, "133");
+	else {
+		do {
+			if (strcmp(cpuClock, "400") == 0)
+				printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n");
+
+#ifdef	CONFIG_STRESS
+			if (strcmp(cpuClock, "667") == 0)
+				printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n");
+
+#endif
+			nbytes = readline (" ? ");
+
+			if (strcmp(console_buffer, "quit") == 0)
+				return 0;
+
+			if (strcmp(cpuClock, "400") == 0) {
+				if ((strcmp(console_buffer, "100") != 0) &
+				    (strcmp(console_buffer, "133") != 0))
+					nbytes = 0;
+			}
+#ifdef	CONFIG_STRESS
+			if (strcmp(cpuClock, "667") == 0) {
+				if ((strcmp(console_buffer, "133") != 0) &
+				    (strcmp(console_buffer, "166") != 0))
+					nbytes = 0;
+			}
+#endif
+			strcpy(plbClock, console_buffer);
+
+		} while (nbytes == 0);
+	}
+
+	do {
+		printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n");
+		nbytes = readline (" ? ");
+
+		if (strcmp(console_buffer, "quit") == 0)
+			return 0;
+
+		if ((strcmp(console_buffer, "33") != 0) &
+		    (strcmp(console_buffer, "66") != 0) &
+		    (strcmp(console_buffer, "100") != 0) &
+		    (strcmp(console_buffer, "133") != 0)) {
+			nbytes = 0;
+		}
+		strcpy(pcixClock, console_buffer);
+
+	} while (nbytes == 0);
+
+	printf("\nsys clk   = %sMhz\n", sysClock);
+	printf("cpu clk   = %sMhz\n", cpuClock);
+	printf("plb clk   = %sMhz\n", plbClock);
+	printf("Pci-X clk = %sMhz\n", pcixClock);
+
+	do {
+		printf("\npress [y] to write I2C bootstrap \n");
+		printf("or [n] to abort.  \n");
+		printf("Don't forget to set board switches \n");
+		printf("according to your choice before re-starting \n");
+		printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
+
+		nbytes = readline (" ? ");
+		if (strcmp(console_buffer, "n") == 0)
+			return 0;
+
+	} while (nbytes == 0);
+
+	if (strcmp(sysClock, "33") == 0) {
+		if ((strcmp(cpuClock, "400") == 0) &
+		    (strcmp(plbClock, "100") == 0))
+			data = 0x8678c206;
+
+		if ((strcmp(cpuClock, "400") == 0) &
+		    (strcmp(plbClock, "133") == 0))
+			data = 0x8678c2c6;
+
+		if ((strcmp(cpuClock, "500") == 0))
+			data = 0x8778f2c6;
+
+		if ((strcmp(cpuClock, "533") == 0))
+			data = 0x87790252;
+
+#ifdef	CONFIG_STRESS
+		if ((strcmp(cpuClock, "667") == 0) &
+		    (strcmp(plbClock, "133") == 0))
+			data = 0x87794256;
+
+		if ((strcmp(cpuClock, "667") == 0) &
+		    (strcmp(plbClock, "166") == 0))
+			data = 0x87794206;
+
+#endif
+	}
+	if (strcmp(sysClock, "66") == 0) {
+		if ((strcmp(cpuClock, "400") == 0) &
+		    (strcmp(plbClock, "100") == 0))
+			data = 0x84706206;
+
+		if ((strcmp(cpuClock, "400") == 0) &
+		    (strcmp(plbClock, "133") == 0))
+			data = 0x847062c6;
+
+		if ((strcmp(cpuClock, "533") == 0))
+			data = 0x85708206;
+
+#ifdef	CONFIG_STRESS
+		if ((strcmp(cpuClock, "667") == 0) &
+		    (strcmp(plbClock, "133") == 0))
+			data = 0x8570a256;
+
+		if ((strcmp(cpuClock, "667") == 0) &
+		    (strcmp(plbClock, "166") == 0))
+			data = 0x8570a206;
+
+#endif
+	}
+
+#ifdef	DEBUG
+	printf(" pin strap0 to write in i2c  = %x\n", data);
+#endif	/* DEBUG */
+
+	if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
+		printf("Error writing strap0 in %s\n", argv[2]);
+
+	if (strcmp(pcixClock, "33") == 0)
+		data = 0x00000701;
+
+	if (strcmp(pcixClock, "66") == 0)
+		data = 0x00000601;
+
+	if (strcmp(pcixClock, "100") == 0)
+		data = 0x00000501;
+
+	if (strcmp(pcixClock, "133") == 0)
+		data = 0x00000401;
+
+	if (strcmp(plbClock, "166") == 0)
+		data |= 0x05950000;
+	else
+		data |= 0x05A50000;
+
+#ifdef	DEBUG
+	printf(" pin strap1 to write in i2c  = %x\n", data);
+#endif	/* DEBUG */
+
+	udelay(1000);
+	if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
+		printf("Error writing strap1 in %s\n", argv[2]);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bootstrap,	3,	1,	do_bootstrap,
+	"bootstrap - program the serial device strap\n",
+	"wrclk [prom0|prom1] - program the serial device strap\n"
+	);
diff --git a/board/amcc/katmai/config.mk b/board/amcc/katmai/config.mk
new file mode 100644
index 0000000..115c1ae
--- /dev/null
+++ b/board/amcc/katmai/config.mk
@@ -0,0 +1,38 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440SPe Evaluation (Katmai) board
+#
+
+TEXT_BASE = 0xfffc0000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
new file mode 100644
index 0000000..6b024ee
--- /dev/null
+++ b/board/amcc/katmai/init.S
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+
+/**************************************************************************
+ * TLB table for revA
+ *************************************************************************/
+	.globl tlbtabA
+tlbtabA:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbtab_end
+
+/**************************************************************************
+ * TLB table for revB
+ *
+ * Notice: revB of the 440SPe chip is very strict about PLB real addresses
+ * and ranges to be mapped for config space: it seems to only work with
+ * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
+ * set otherwise) while revA uses c_nnnn_nnnn.
+ *************************************************************************/
+	.globl tlbtabB
+tlbtabB:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+
+	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbtab_end
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
new file mode 100644
index 0000000..fbf1a98
--- /dev/null
+++ b/board/amcc/katmai/katmai.c
@@ -0,0 +1,529 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <asm-ppc/io.h>
+
+#include "../cpu/ppc4xx/440spe_pcie.h"
+
+#undef PCIE_ENDPOINT
+/* #define PCIE_ENDPOINT 1 */
+
+int ppc440spe_init_pcie_rootport(int port);
+void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
+
+int board_early_init_f (void)
+{
+	unsigned long mfr;
+
+	/*----------------------------------------------------------------------+
+	 * Interrupt controller setup for the Katmai 440SPe Evaluation board.
+	 *-----------------------------------------------------------------------+
+	 *-----------------------------------------------------------------------+
+	 * Interrupt | Source                            | Pol.  | Sensi.| Crit. |
+	 *-----------+-----------------------------------+-------+-------+-------+
+	 * IRQ 00    | UART0                             | High  | Level | Non   |
+	 * IRQ 01    | UART1                             | High  | Level | Non   |
+	 * IRQ 02    | IIC0                              | High  | Level | Non   |
+	 * IRQ 03    | IIC1                              | High  | Level | Non   |
+	 * IRQ 04    | PCI0X0 MSG IN                     | High  | Level | Non   |
+	 * IRQ 05    | PCI0X0 CMD Write                  | High  | Level | Non   |
+	 * IRQ 06    | PCI0X0 Power Mgt                  | High  | Level | Non   |
+	 * IRQ 07    | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
+	 * IRQ 08    | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
+	 * IRQ 09    | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
+	 * IRQ 10    | UIC2 Non-critical Int.            | NA    | NA    | Non   |
+	 * IRQ 11    | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
+	 * IRQ 12    | PCI Express MSI Level 0           | Rising| Edge  | Non   |
+	 * IRQ 13    | PCI Express MSI Level 1           | Rising| Edge  | Non   |
+	 * IRQ 14    | PCI Express MSI Level 2           | Rising| Edge  | Non   |
+	 * IRQ 15    | PCI Express MSI Level 3           | Rising| Edge  | Non   |
+	 * IRQ 16    | UIC3 Non-critical Int.            | NA    | NA    | Non   |
+	 * IRQ 17    | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
+	 * IRQ 18    | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
+	 * IRQ 19    | DMA Channel 0 FIFO Full           | High  | Level | Non   |
+	 * IRQ 20    | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
+	 * IRQ 21    | DMA Channel 1 FIFO Full           | High  | Level | Non   |
+	 * IRQ 22    | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
+	 * IRQ 23    | I2O Inbound Doorbell              | High  | Level | Non   |
+	 * IRQ 24    | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
+	 * IRQ 25    | I2O Region 0 LL PLB Write         | High  | Level | Non   |
+	 * IRQ 26    | I2O Region 1 LL PLB Write         | High  | Level | Non   |
+	 * IRQ 27    | I2O Region 0 HB PLB Write         | High  | Level | Non   |
+	 * IRQ 28    | I2O Region 1 HB PLB Write         | High  | Level | Non   |
+	 * IRQ 29    | GPT Down Count Timer              | Rising| Edge  | Non   |
+	 * IRQ 30    | UIC1 Non-critical Int.            | NA    | NA    | Non   |
+	 * IRQ 31    | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
+	 *------------------------------------------------------------------------
+	 * IRQ 32    | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 33    | MAL Serr                          | High  | Level | Non   |
+	 * IRQ 34    | MAL Txde                          | High  | Level | Non   |
+	 * IRQ 35    | MAL Rxde                          | High  | Level | Non   |
+	 * IRQ 36    | DMC CE or DMC UE                  | High  | Level | Non   |
+	 * IRQ 37    | EBC or UART2                      | High  |Lvl Edg| Non   |
+	 * IRQ 38    | MAL TX EOB                        | High  | Level | Non   |
+	 * IRQ 39    | MAL RX EOB                        | High  | Level | Non   |
+	 * IRQ 40    | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
+	 * IRQ 41    | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
+	 * IRQ 42    | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
+	 * IRQ 43    | L2 Cache                          | Risin | Edge  | Non   |
+	 * IRQ 44    | GPT Compare Timer 0               | Risin | Edge  | Non   |
+	 * IRQ 45    | GPT Compare Timer 1               | Risin | Edge  | Non   |
+	 * IRQ 46    | GPT Compare Timer 2               | Risin | Edge  | Non   |
+	 * IRQ 47    | GPT Compare Timer 3               | Risin | Edge  | Non   |
+	 * IRQ 48    | GPT Compare Timer 4               | Risin | Edge  | Non   |
+	 * IRQ 49    | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
+	 * IRQ 50    | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 51    | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 52    | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 53    | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 54    | DMA Error                         | High  | Level | Non   |
+	 * IRQ 55    | DMA I2O Error                     | High  | Level | Non   |
+	 * IRQ 56    | Serial ROM                        | High  | Level | Non   |
+	 * IRQ 57    | PCIX0 Error                       | High  | Edge  | Non   |
+	 * IRQ 58    | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 59    | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
+	 * IRQ 60    | EMAC0 Interrupt                   | High  | Level | Non   |
+	 * IRQ 61    | EMAC0 Wake-up                     | High  | Level | Non   |
+	 * IRQ 62    | Reserved                          | High  | Level | Non   |
+	 * IRQ 63    | XOR                               | High  | Level | Non   |
+	 *-----------------------------------------------------------------------
+	 * IRQ 64    | PE0 AL                            | High  | Level | Non   |
+	 * IRQ 65    | PE0 VPD Access                    | Risin | Edge  | Non   |
+	 * IRQ 66    | PE0 Hot Reset Request             | Risin | Edge  | Non   |
+	 * IRQ 67    | PE0 Hot Reset Request             | Falli | Edge  | Non   |
+	 * IRQ 68    | PE0 TCR                           | High  | Level | Non   |
+	 * IRQ 69    | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
+	 * IRQ 70    | PE0 DCR Error                     | High  | Level | Non   |
+	 * IRQ 71    | Reserved                          | N/A   | N/A   | Non   |
+	 * IRQ 72    | PE1 AL                            | High  | Level | Non   |
+	 * IRQ 73    | PE1 VPD Access                    | Risin | Edge  | Non   |
+	 * IRQ 74    | PE1 Hot Reset Request             | Risin | Edge  | Non   |
+	 * IRQ 75    | PE1 Hot Reset Request             | Falli | Edge  | Non   |
+	 * IRQ 76    | PE1 TCR                           | High  | Level | Non   |
+	 * IRQ 77    | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
+	 * IRQ 78    | PE1 DCR Error                     | High  | Level | Non   |
+	 * IRQ 79    | Reserved                          | N/A   | N/A   | Non   |
+	 * IRQ 80    | PE2 AL                            | High  | Level | Non   |
+	 * IRQ 81    | PE2 VPD Access                    | Risin | Edge  | Non   |
+	 * IRQ 82    | PE2 Hot Reset Request             | Risin | Edge  | Non   |
+	 * IRQ 83    | PE2 Hot Reset Request             | Falli | Edge  | Non   |
+	 * IRQ 84    | PE2 TCR                           | High  | Level | Non   |
+	 * IRQ 85    | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
+	 * IRQ 86    | PE2 DCR Error                     | High  | Level | Non   |
+	 * IRQ 87    | Reserved                          | N/A   | N/A   | Non   |
+	 * IRQ 88    | External IRQ(5)                   | Progr | Progr | Non   |
+	 * IRQ 89    | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
+	 * IRQ 90    | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
+	 * IRQ 91    | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
+	 * IRQ 92    | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
+	 * IRQ 93    | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
+	 * IRQ 94    | Reserved                          | N/A   | N/A   | Non   |
+	 * IRQ 95    | Reserved                          | N/A   | N/A   | Non   |
+	 *-----------------------------------------------------------------------
+	 * IRQ 96    | PE0 INTA                          | High  | Level | Non   |
+	 * IRQ 97    | PE0 INTB                          | High  | Level | Non   |
+	 * IRQ 98    | PE0 INTC                          | High  | Level | Non   |
+	 * IRQ 99    | PE0 INTD                          | High  | Level | Non   |
+	 * IRQ 100   | PE1 INTA                          | High  | Level | Non   |
+	 * IRQ 101   | PE1 INTB                          | High  | Level | Non   |
+	 * IRQ 102   | PE1 INTC                          | High  | Level | Non   |
+	 * IRQ 103   | PE1 INTD                          | High  | Level | Non   |
+	 * IRQ 104   | PE2 INTA                          | High  | Level | Non   |
+	 * IRQ 105   | PE2 INTB                          | High  | Level | Non   |
+	 * IRQ 106   | PE2 INTC                          | High  | Level | Non   |
+	 * IRQ 107   | PE2 INTD                          | Risin | Edge  | Non   |
+	 * IRQ 108   | PCI Express MSI Level 4           | Risin | Edge  | Non   |
+	 * IRQ 109   | PCI Express MSI Level 5           | Risin | Edge  | Non   |
+	 * IRQ 110   | PCI Express MSI Level 6           | Risin | Edge  | Non   |
+	 * IRQ 111   | PCI Express MSI Level 7           | Risin | Edge  | Non   |
+	 * IRQ 116   | PCI Express MSI Level 12          | Risin | Edge  | Non   |
+	 * IRQ 112   | PCI Express MSI Level 8           | Risin | Edge  | Non   |
+	 * IRQ 113   | PCI Express MSI Level 9           | Risin | Edge  | Non   |
+	 * IRQ 114   | PCI Express MSI Level 10          | Risin | Edge  | Non   |
+	 * IRQ 115   | PCI Express MSI Level 11          | Risin | Edge  | Non   |
+	 * IRQ 117   | PCI Express MSI Level 13          | Risin | Edge  | Non   |
+	 * IRQ 118   | PCI Express MSI Level 14          | Risin | Edge  | Non   |
+	 * IRQ 119   | PCI Express MSI Level 15          | Risin | Edge  | Non   |
+	 * IRQ 120   | PCI Express MSI Level 16          | Risin | Edge  | Non   |
+	 * IRQ 121   | PCI Express MSI Level 17          | Risin | Edge  | Non   |
+	 * IRQ 122   | PCI Express MSI Level 18          | Risin | Edge  | Non   |
+	 * IRQ 123   | PCI Express MSI Level 19          | Risin | Edge  | Non   |
+	 * IRQ 124   | PCI Express MSI Level 20          | Risin | Edge  | Non   |
+	 * IRQ 125   | PCI Express MSI Level 21          | Risin | Edge  | Non   |
+	 * IRQ 126   | PCI Express MSI Level 22          | Risin | Edge  | Non   |
+	 * IRQ 127   | PCI Express MSI Level 23          | Risin | Edge  | Non   |
+	 *-----------+-----------------------------------+-------+-------+-------+ */
+	/*-------------------------------------------------------------------------+
+	 * Put UICs in PowerPC440SPemode.
+	 * Initialise UIC registers.  Clear all interrupts.  Disable all interrupts.
+	 * Set critical interrupt values.  Set interrupt polarities.  Set interrupt
+	 * trigger levels.  Make bit 0 High  priority.  Clear all interrupts again.
+	 *------------------------------------------------------------------------*/
+	mtdcr (uic3sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (uic3er, 0x00000000);	/* disable all interrupts */
+	mtdcr (uic3cr, 0x00000000);	/* Set Critical / Non Critical interrupts: */
+	mtdcr (uic3pr, 0xffffffff);	/* Set Interrupt Polarities*/
+	mtdcr (uic3tr, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr (uic3vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (uic3sr, 0x00000000);	/* clear all  interrupts*/
+	mtdcr (uic3sr, 0xffffffff);	/* clear all  interrupts*/
+
+
+	mtdcr (uic2sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (uic2er, 0x00000000);	/* disable all interrupts*/
+	mtdcr (uic2cr, 0x00000000);	/* Set Critical / Non Critical interrupts*/
+	mtdcr (uic2pr, 0xebebebff);	/* Set Interrupt Polarities*/
+	mtdcr (uic2tr, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr (uic2vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (uic2sr, 0x00000000);	/* clear all interrupts */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr (uic1sr, 0xffffffff);	/* Clear all interrupts*/
+	mtdcr (uic1er, 0x00000000);	/* disable all interrupts*/
+	mtdcr (uic1cr, 0x00000000);	/* Set Critical / Non Critical interrupts*/
+	mtdcr (uic1pr, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr (uic1tr, 0x001f8040);	/* Set Interrupt Trigger Levels*/
+	mtdcr (uic1vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (uic1sr, 0x00000000);	/* clear all interrupts*/
+	mtdcr (uic1sr, 0xffffffff);	/* clear all interrupts*/
+
+	mtdcr (uic0sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr (uic0er, 0x00000000);	/* disable all interrupts excepted cascade    to be checked */
+	mtdcr (uic0cr, 0x00104001);	/* Set Critical / Non Critical interrupts*/
+	mtdcr (uic0pr, 0xffffffff);	/* Set Interrupt Polarities*/
+	mtdcr (uic0tr, 0x010f0004);	/* Set Interrupt Trigger Levels */
+	mtdcr (uic0vr, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr (uic0sr, 0x00000000);	/* clear all interrupts*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all interrupts*/
+
+/* SDR0_MFR should be part of Ethernet init */
+	mfsdr (sdr_mfr, mfr);
+	mfr &= ~SDR0_MFR_ECS_MASK;
+/*	mtsdr(sdr_mfr, mfr); */
+
+	mtsdr(SDR0_PFC0, CFG_PFC0);
+
+	out32(GPIO0_OR, CFG_GPIO_OR);
+	out32(GPIO0_ODR, CFG_GPIO_ODR);
+	out32(GPIO0_TCR, CFG_GPIO_TCR);
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Katmai - AMCC 440SPe Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*-------------------------------------------------------------------+
+	 *	The katmai board is always configured as the host & requires the
+	 *	PCI arbiter to be enabled.
+	 *-------------------------------------------------------------------*/
+	mfsdr(sdr_sdstp1, strap);
+	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
+		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+		return 0;
+	}
+
+	return 1;
+}
+#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*-------------------------------------------------------------------+
+	 * Disable everything
+	 *-------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*-------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
+	 * strapping options to not support sizes such as 128/256 MB.
+	 *-------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+	out32r( PCIX0_BAR0, 0 );
+
+	/*-------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *-------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_PCI)
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+int is_pci_host(struct pci_controller *hose)
+{
+	/* The katmai board is always configured as host. */
+	return 1;
+}
+
+int katmai_pcie_card_present(int port)
+{
+	u32 val;
+
+	val = in32(GPIO0_IR);
+	switch (port) {
+	case 0:
+		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0));
+	case 1:
+		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1));
+	case 2:
+		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2));
+	default:
+		return 0;
+	}
+}
+
+static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
+
+void pcie_setup_hoses(void)
+{
+	struct pci_controller *hose;
+	int i, bus;
+
+	/*
+	 * assume we're called after the PCIX hose is initialized, which takes
+	 * bus ID 0 and therefore start numbering PCIe's from 1.
+	 */
+	bus = 1;
+	for (i = 0; i <= 2; i++) {
+		/* Check for katmai card presence */
+		if (!katmai_pcie_card_present(i))
+			continue;
+
+#ifdef PCIE_ENDPOINT
+ 		if (ppc440spe_init_pcie_endport(i)) {
+#else
+		if (ppc440spe_init_pcie_rootport(i)) {
+#endif
+			printf("PCIE%d: initialization failed\n", i);
+			continue;
+		}
+
+		hose = &pcie_hose[i];
+		hose->first_busno = bus;
+		hose->last_busno  = bus;
+		bus++;
+
+		/* setup mem resource */
+		pci_set_region(hose->regions + 0,
+			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
+			       CFG_PCIE_MEMSIZE,
+			       PCI_REGION_MEM
+			);
+		hose->region_count = 1;
+		pci_register_hose(hose);
+
+#ifdef PCIE_ENDPOINT
+		ppc440spe_setup_pcie_endpoint(hose, i);
+		/*
+		 * Reson for no scanning is endpoint can not generate
+		 * upstream configuration accesses.
+		 */
+#else
+		ppc440spe_setup_pcie_rootpoint(hose, i);
+		/*
+		 * Config access can only go down stream
+		 */
+		hose->last_busno = pci_hose_scan(hose);
+#endif
+	}
+}
+#endif	/* defined(CONFIG_PCI) */
+
+int misc_init_f (void)
+{
+	uint reg;
+#if defined(CONFIG_STRESS)
+	uint i ;
+	uint disp;
+#endif
+
+	/* minimal init for PCIe */
+#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
+	/* pci express 0 Endpoint Mode */
+	mfsdr(SDR0_PE0DLPSET, reg);
+	reg &= (~0x00400000);
+	mtsdr(SDR0_PE0DLPSET, reg);
+#else
+	/* pci express 0 Rootpoint  Mode */
+	mfsdr(SDR0_PE0DLPSET, reg);
+	reg |= 0x00400000;
+	mtsdr(SDR0_PE0DLPSET, reg);
+#endif
+	/* pci express 1 Rootpoint  Mode */
+	mfsdr(SDR0_PE1DLPSET, reg);
+	reg |= 0x00400000;
+	mtsdr(SDR0_PE1DLPSET, reg);
+	/* pci express 2 Rootpoint  Mode */
+	mfsdr(SDR0_PE2DLPSET, reg);
+	reg |= 0x00400000;
+	mtsdr(SDR0_PE2DLPSET, reg);
+
+#if defined(CONFIG_STRESS)
+	/*
+	 * All this setting done by linux only needed by stress an charac. test
+	 * procedure
+	 * PCIe 1 Rootpoint PCIe2 Endpoint
+	 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
+	 */
+	for (i=0,disp=0; i<8; i++,disp+=3) {
+		mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
+		reg |= 0x33000000;
+		mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
+	}
+
+	/*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
+	for (i=0,disp=0; i<4; i++,disp+=3) {
+		mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
+		reg |= 0x33000000;
+		mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
+	}
+
+	/*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
+	for (i=0,disp=0; i<4; i++,disp+=3) {
+		mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
+		reg |= 0x33000000;
+		mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
+	}
+
+	reg = 0x21242222;
+	mtsdr(SDR0_PE2UTLSET1, reg);
+	reg = 0x11000000;
+	mtsdr(SDR0_PE2UTLSET2, reg);
+	/* pci express 1 Endpoint  Mode */
+	reg = 0x00004000;
+	mtsdr(SDR0_PE2DLPSET, reg);
+
+	mtsdr(SDR0_UART1, 0x2080005a);	/* patch for TG */
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return (ctrlc());
+}
+#endif
diff --git a/board/amcc/katmai/u-boot.lds b/board/amcc/katmai/u-boot.lds
new file mode 100644
index 0000000..bf8fc5d
--- /dev/null
+++ b/board/amcc/katmai/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/ppc4xx/start.o		(.text)
+    board/amcc/katmai/init.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
index 7830ebd..d5ee117 100644
--- a/board/amcc/luan/init.S
+++ b/board/amcc/luan/init.S
@@ -1,73 +1,31 @@
 /*
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
 
 #include <ppc_asm.tmpl>
 #include <config.h>
-
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K	    0x00000000
-#define SZ_4K	    0x00000010
-#define SZ_16K	    0x00000020
-#define SZ_64K	    0x00000030
-#define SZ_256K	    0x00000040
-#define SZ_1M	    0x00000050
-#define SZ_16M	    0x00000070
-#define SZ_256M	    0x00000090
-
-/* Storage attributes */
-#define SA_W	    0x00000800	    /* Write-through */
-#define SA_I	    0x00000400	    /* Caching inhibited */
-#define SA_M	    0x00000200	    /* Memory coherence */
-#define SA_G	    0x00000100	    /* Guarded */
-#define SA_E	    0x00000080	    /* Endian */
-
-/* Access control */
-#define AC_X	    0x00000024	    /* Execute */
-#define AC_W	    0x00000012	    /* Write */
-#define AC_R	    0x00000009	    /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)		((e) & 0xfffffc00)
-#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)		( (a)&0x00000fbf )
-
-#define tlbtab_start\
-	mflr    r1  ;\
-	bl 0f	    ;
-
-#define tlbtab_end\
-	.long 0, 0, 0	;   \
-0:	mflr    r0	;   \
-	mtlr    r1	;   \
-	blr		;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
 
 /**************************************************************************
  * TLB TABLE
@@ -80,53 +38,37 @@
  *
  *************************************************************************/
 
-    .section .bootpg,"ax"
-    .globl tlbtab
+	.section .bootpg,"ax"
+	.globl tlbtab
 
 tlbtab:
-    tlbtab_start
-
-#if (CFG_LARGE_FLASH == 0xffc00000)	/* if booting from large flash */
-    /* large flash */
-    tlbentry( 0xffc00000,         SZ_1M, 0xffc00000,          1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
-    tlbentry( 0xffd00000,         SZ_1M, 0xffd00000,          1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
-    tlbentry( 0xffe00000,         SZ_1M, 0xffe00000,          1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
-    tlbentry( 0xfff00000,         SZ_1M, 0xfff00000,          1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
-
-    tlbentry( 0xff800000,         SZ_1M, 0xff800000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-    tlbentry( 0xff900000,         SZ_1M, 0xff900000,          1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
-#else					/* else booting from small flash */
-    tlbentry( 0xffe00000,         SZ_1M, 0xffe00000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-    tlbentry( 0xfff00000,         SZ_1M, 0xfff00000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-
-    tlbentry( 0xff800000,         SZ_1M, 0xff800000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-    tlbentry( 0xff900000,         SZ_1M, 0xff900000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-    tlbentry( 0xffa00000,         SZ_1M, 0xffa00000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-    tlbentry( 0xffb00000,         SZ_1M, 0xffb00000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-#endif
-
-    tlbentry( CFG_EPLD_BASE,    SZ_256K, 0xff000000,          1, AC_R|AC_W|SA_G|SA_I )
-
-#if (CFG_SRAM_BASE != 0)		/* if SRAM up high and SDRAM at zero */
-    tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-#elif (CFG_SMALL_FLASH == 0xff900000)	/* else SRAM at 0 */
-    tlbentry( 0x00000000,   SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-#elif (CFG_SMALL_FLASH == 0xfff00000)
-    tlbentry( 0x00000000,   SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-#else
-    #error DONT KNOW SRAM LOCATION
-#endif
-
-    /* internal ram (l2 cache) */
-    tlbentry( CFG_ISRAM_BASE,    SZ_256K, 0x80000000,      0, AC_R|AC_W|AC_X|SA_I )
-
-    /* peripherals at f0000000 */
-    tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I )
-
-    /* PCI */
-#if (CONFIG_COMMANDS & CFG_CMD_PCI)
-    tlbentry( CFG_PCI_BASE,    SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I )
-#endif
-    tlbtab_end
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G)
+
+	tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	/* internal ram (l2 cache) */
+	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
+
+	/* peripherals at f0000000 */
+	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
+
+	/* PCI */
+	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
+	tlbtab_end
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 06a57f6..778aafc 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -106,105 +106,6 @@ int checkboard(void)
 
 
 /*************************************************************************
- *  long int fixed_sdram()
- *
- ************************************************************************/
-static long int fixed_sdram(void)
-{					/* DDR2 init from BDI2000 script */
-	mtdcr( 0x10, 0x00000021 );	/* MCIF0_MCOPT2 - zero DCEN bit */
-	mtdcr( 0x11, 0x84000000 );
-	mtdcr( 0x10, 0x00000020 );	/* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */
-	mtdcr( 0x11, 0x2D122000 );
-	mtdcr( 0x10, 0x00000026 );	/* MCIF0_CODT  - die termination on */
-	mtdcr( 0x11, 0x00800026 );
-	mtdcr( 0x10, 0x00000081 );	/* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */
-	mtdcr( 0x11, 0x82000800 );
-	mtdcr( 0x10, 0x00000080 );	/* MCIF0_CLKTR - advance addr clock by 180 deg */
-	mtdcr( 0x11, 0x80000000 );
-	mtdcr( 0x10, 0x00000040 );	/* MCIF0_MB0CF - turn on CS0, N x 10 coll */
-	mtdcr( 0x11, 0x00000201 );
-	mtdcr( 0x10, 0x00000044 );	/* MCIF0_MB1CF - turn on CS0, N x 10 coll */
-	mtdcr( 0x11, 0x00000201 );
-	mtdcr( 0x10, 0x00000030 );	/* MCIF0_RTR   - refresh every 7.8125uS */
-	mtdcr( 0x11, 0x08200000 );
-	mtdcr( 0x10, 0x00000085 );	/* MCIF0_SDTR1 - timing register 1 */
-	mtdcr( 0x11, 0x80201000 );
-	mtdcr( 0x10, 0x00000086 );	/* MCIF0_SDTR2 - timing register 2 */
-	mtdcr( 0x11, 0x42103242 );
-	mtdcr( 0x10, 0x00000087 );	/* MCIF0_SDTR3 - timing register 3 */
-	mtdcr( 0x11, 0x0C100D14 );
-	mtdcr( 0x10, 0x00000088 );	/* MCIF0_MMODE - CAS is 4 cycles */
-	mtdcr( 0x11, 0x00000642 );
-	mtdcr( 0x10, 0x00000089 );	/* MCIF0_MEMODE - diff DQS disabled */
-	mtdcr( 0x11, 0x00000400 );	/*		  ODT term disabled */
-
-	mtdcr( 0x10, 0x00000050 );	/* MCIF0_INITPLR0 - NOP */
-	mtdcr( 0x11, 0x81b80000 );
-	mtdcr( 0x10, 0x00000051 );	/* MCIF0_INITPLR1 - PRE */
-	mtdcr( 0x11, 0x82100400 );
-	mtdcr( 0x10, 0x00000052 );	/* MCIF0_INITPLR2 - EMR2 */
-	mtdcr( 0x11, 0x80820000 );
-	mtdcr( 0x10, 0x00000053 );	/* MCIF0_INITPLR3 - EMR3 */
-	mtdcr( 0x11, 0x80830000 );
-	mtdcr( 0x10, 0x00000054 );	/* MCIF0_INITPLR4 - EMR DLL ENABLE */
-	mtdcr( 0x11, 0x80810000 );
-	mtdcr( 0x10, 0x00000055 );	/* MCIF0_INITPLR5 - MR DLL RESET */
-	mtdcr( 0x11, 0x80800542 );
-	mtdcr( 0x10, 0x00000056 );	/* MCIF0_INITPLR6 - PRE */
-	mtdcr( 0x11, 0x82100400 );
-	mtdcr( 0x10, 0x00000057 );	/* MCIF0_INITPLR7 - refresh */
-	mtdcr( 0x11, 0x99080000 );
-	mtdcr( 0x10, 0x00000058 );	/* MCIF0_INITPLR8 */
-	mtdcr( 0x11, 0x99080000 );
-	mtdcr( 0x10, 0x00000059 );	/* MCIF0_INITPLR9 */
-	mtdcr( 0x11, 0x99080000 );
-	mtdcr( 0x10, 0x0000005A );	/* MCIF0_INITPLR10 */
-	mtdcr( 0x11, 0x99080000 );
-	mtdcr( 0x10, 0x0000005B );	/* MCIF0_INITPLR11 - MR */
-	mtdcr( 0x11, 0x80800442 );
-	mtdcr( 0x10, 0x0000005C );	/* MCIF0_INITPLR12 - EMR OCD Default */
-	mtdcr( 0x11, 0x80810380 );
-	mtdcr( 0x10, 0x0000005D );	/* MCIF0_INITPLR13 - EMR OCD exit */
-	mtdcr( 0x11, 0x80810000 );
-	udelay( 10*1000 );
-
-	mtdcr( 0x10, 0x00000021 );	/* MCIF0_MCOPT2 - execute preloaded init */
-	mtdcr( 0x11, 0x28000000 );	/*		  set DC_EN */
-	udelay( 100*1000 );
-
-	mtdcr( 0x40, 0x0000F800 );	/* MQ0_B0BAS: base addr 00000000 / 256MB */
-	mtdcr( 0x41, 0x1000F800 );	/* MQ0_B1BAS: base addr 10000000 / 256MB */
-
-	mtdcr( 0x10, 0x00000078 );	/* MCIF0_RDCC - auto set read stage */
-	mtdcr( 0x11, 0x00000000 );
-	mtdcr( 0x10, 0x00000070 );	/* MCIF0_RQDC - read DQS delay control */
-	mtdcr( 0x11, 0x8000003A );	/*		enabled, frac DQS delay */
-	mtdcr( 0x10, 0x00000074 );	/* MCIF0_RFDC - two clock feedback delay */
-	mtdcr( 0x11, 0x00000200 );
-
-	return  512 << 20;
-}
-
-
-/*************************************************************************
- *  long int initdram
- *
- ************************************************************************/
-long int initdram( int board_type )
-{
-	long dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
-	dram_size = spd_sdram (0);
-#else
-	dram_size = fixed_sdram ();
-#endif
-
-	return  dram_size;
-}
-
-
-/*************************************************************************
  *  int testdram()
  *
  ************************************************************************/
diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds
index d122f49..72ce685 100644
--- a/board/amcc/luan/u-boot.lds
+++ b/board/amcc/luan/u-boot.lds
@@ -68,19 +68,6 @@ SECTIONS
 
     cpu/ppc4xx/start.o	(.text)
     board/amcc/luan/init.o	(.text)
-    cpu/ppc4xx/kgdb.o	(.text)
-    cpu/ppc4xx/traps.o	(.text)
-    cpu/ppc4xx/interrupts.o	(.text)
-    cpu/ppc4xx/serial.o	(.text)
-    cpu/ppc4xx/cpu_init.o	(.text)
-    cpu/ppc4xx/speed.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib_generic/crc32.o		(.text)
-    lib_ppc/extable.o	(.text)
-    lib_generic/zlib.o		(.text)
-
-/*    . = env_offset;*/
-/*    common/environment.o(.text)*/
 
     *(.text)
     *(.fixup)
diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S
index 7e0b132..d211c71 100644
--- a/board/amcc/ocotea/init.S
+++ b/board/amcc/ocotea/init.S
@@ -22,55 +22,7 @@
 
 #include <ppc_asm.tmpl>
 #include <config.h>
-
-/* General */
-#define TLB_VALID   0x00000200
-#define _256M       0x10000000
-
-/* Supported page sizes */
-
-#define SZ_1K	    0x00000000
-#define SZ_4K	    0x00000010
-#define SZ_16K	    0x00000020
-#define SZ_64K	    0x00000030
-#define SZ_256K	    0x00000040
-#define SZ_1M	    0x00000050
-#define SZ_8M       0x00000060
-#define SZ_16M	    0x00000070
-#define SZ_256M	    0x00000090
-
-/* Storage attributes */
-#define SA_W	    0x00000800	    /* Write-through */
-#define SA_I	    0x00000400	    /* Caching inhibited */
-#define SA_M	    0x00000200	    /* Memory coherence */
-#define SA_G	    0x00000100	    /* Guarded */
-#define SA_E	    0x00000080	    /* Endian */
-
-/* Access control */
-#define AC_X	    0x00000024	    /* Execute */
-#define AC_W	    0x00000012	    /* Write */
-#define AC_R	    0x00000009	    /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)		((e) & 0xfffffc00)
-#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)		( (a)&0x00000fbf )
-
-#define tlbtab_start\
-	mflr    r1  ;\
-	bl 0f	    ;
-
-#define tlbtab_end\
-	.long 0, 0, 0	;   \
-0:	mflr    r0	;   \
-	mtlr    r1	;   \
-	blr		;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
 
 /**************************************************************************
  * TLB TABLE
@@ -83,19 +35,23 @@
  *
  *************************************************************************/
 
-    .section .bootpg,"ax"
-    .globl tlbtab
+	.section .bootpg,"ax"
+	.globl tlbtab
 
 tlbtab:
-    tlbtab_start
-    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
-    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
-    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
-    tlbtab_end
+	tlbtab_start
+
+	tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
+	tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
+	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+	tlbtab_end
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 3d4ac85..45bcd4b 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -90,7 +90,7 @@ tlbtab:
 	/*
 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
-	*/
+	 */
 #ifndef CONFIG_NAND_SPL
 	tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
 #else
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 53f728d..f8b837e 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -1,5 +1,12 @@
 /*
  * (C) Copyright 2006
+ * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * This program is free software; you can redistribute it and/or
@@ -18,10 +25,352 @@
  * MA 02111-1307 USA
  */
 
+/* define DEBUG for debug output */
+#undef DEBUG
+
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <ppc440.h>
 
+#include "sdram.h"
+
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
+	defined(CONFIG_DDR_DATA_EYE)
+/*-----------------------------------------------------------------------------+
+ * wait_for_dlllock.
+ +----------------------------------------------------------------------------*/
+static int wait_for_dlllock(void)
+{
+	unsigned long val;
+	int wait = 0;
+
+	/* -----------------------------------------------------------+
+	 * Wait for the DCC master delay line to finish calibration
+	 * ----------------------------------------------------------*/
+	mtdcr(ddrcfga, DDR0_17);
+	val = DDR0_17_DLLLOCKREG_UNLOCKED;
+
+	while (wait != 0xffff) {
+		val = mfdcr(ddrcfgd);
+		if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
+			/* dlllockreg bit on */
+			return 0;
+		else
+			wait++;
+	}
+	debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
+	debug("Waiting for dlllockreg bit to raise\n");
+
+	return -1;
+}
+#endif
+
+#if defined(CONFIG_DDR_DATA_EYE)
+/*-----------------------------------------------------------------------------+
+ * wait_for_dram_init_complete.
+ +----------------------------------------------------------------------------*/
+int wait_for_dram_init_complete(void)
+{
+	unsigned long val;
+	int wait = 0;
+
+	/* --------------------------------------------------------------+
+	 * Wait for 'DRAM initialization complete' bit in status register
+	 * -------------------------------------------------------------*/
+	mtdcr(ddrcfga, DDR0_00);
+
+	while (wait != 0xffff) {
+		val = mfdcr(ddrcfgd);
+		if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
+			/* 'DRAM initialization complete' bit */
+			return 0;
+		else
+			wait++;
+	}
+
+	debug("DRAM initialization complete bit in status register did not rise\n");
+
+	return -1;
+}
+
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+/*-----------------------------------------------------------------------------+
+ * denali_core_search_data_eye.
+ +----------------------------------------------------------------------------*/
+void denali_core_search_data_eye(unsigned long memory_size)
+{
+	int k, j;
+	u32 val;
+	u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
+	u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
+	u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
+	u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
+	volatile u32 *ram_pointer;
+	u32 test[NUM_TRIES] = {
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+	ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
+
+	for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
+		/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
+
+		/* -----------------------------------------------------------+
+		 * De-assert 'start' parameter.
+		 * ----------------------------------------------------------*/
+		mtdcr(ddrcfga, DDR0_02);
+		val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
+		mtdcr(ddrcfgd, val);
+
+		/* -----------------------------------------------------------+
+		 * Set 'wr_dqs_shift'
+		 * ----------------------------------------------------------*/
+		mtdcr(ddrcfga, DDR0_09);
+		val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
+			| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
+		mtdcr(ddrcfgd, val);
+
+		/* -----------------------------------------------------------+
+		 * Set 'dqs_out_shift' = wr_dqs_shift + 32
+		 * ----------------------------------------------------------*/
+		dqs_out_shift = wr_dqs_shift + 32;
+		mtdcr(ddrcfga, DDR0_22);
+		val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
+			| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
+		mtdcr(ddrcfgd, val);
+
+		passing_cases = 0;
+
+		for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
+			/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
+			/* -----------------------------------------------------------+
+			 * Set 'dll_dqs_delay_X'.
+			 * ----------------------------------------------------------*/
+			/* dll_dqs_delay_0 */
+			mtdcr(ddrcfga, DDR0_17);
+			val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
+				| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
+			mtdcr(ddrcfgd, val);
+			/* dll_dqs_delay_1 to dll_dqs_delay_4 */
+			mtdcr(ddrcfga, DDR0_18);
+			val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
+				| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
+				| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
+				| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
+				| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
+			mtdcr(ddrcfgd, val);
+			/* dll_dqs_delay_5 to dll_dqs_delay_8 */
+			mtdcr(ddrcfga, DDR0_19);
+			val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
+				| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
+				| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
+				| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
+				| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
+			mtdcr(ddrcfgd, val);
+
+			ppcMsync();
+			ppcMbar();
+
+			/* -----------------------------------------------------------+
+			 * Assert 'start' parameter.
+			 * ----------------------------------------------------------*/
+			mtdcr(ddrcfga, DDR0_02);
+			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
+			mtdcr(ddrcfgd, val);
+
+			ppcMsync();
+			ppcMbar();
+
+			/* -----------------------------------------------------------+
+			 * Wait for the DCC master delay line to finish calibration
+			 * ----------------------------------------------------------*/
+			if (wait_for_dlllock() != 0) {
+				printf("dlllock did not occur !!!\n");
+				printf("denali_core_search_data_eye!!!\n");
+				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
+				       wr_dqs_shift, dll_dqs_delay_X);
+				hang();
+			}
+			ppcMsync();
+			ppcMbar();
+
+			if (wait_for_dram_init_complete() != 0) {
+				printf("dram init complete did not occur !!!\n");
+				printf("denali_core_search_data_eye!!!\n");
+				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
+				       wr_dqs_shift, dll_dqs_delay_X);
+				hang();
+			}
+			udelay(100);  /* wait 100us to ensure init is really completed !!! */
+
+			/* write values */
+			for (j=0; j<NUM_TRIES; j++) {
+				ram_pointer[j] = test[j];
+
+				/* clear any cache at ram location */
+				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+			}
+
+			/* read values back */
+			for (j=0; j<NUM_TRIES; j++) {
+				for (k=0; k<NUM_READS; k++) {
+					/* clear any cache at ram location */
+					__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+					if (ram_pointer[j] != test[j])
+						break;
+				}
+
+				/* read error */
+				if (k != NUM_READS)
+					break;
+			}
+
+			/* See if the dll_dqs_delay_X value passed.*/
+			if (j < NUM_TRIES) {
+				/* Failed */
+				passing_cases = 0;
+				/* break; */
+			} else {
+				/* Passed */
+				if (passing_cases == 0)
+					dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
+				passing_cases++;
+				if (passing_cases >= max_passing_cases) {
+					max_passing_cases = passing_cases;
+					wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
+					dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
+					dll_dqs_delay_X_end_window = dll_dqs_delay_X;
+				}
+			}
+
+			/* -----------------------------------------------------------+
+			 * De-assert 'start' parameter.
+			 * ----------------------------------------------------------*/
+			mtdcr(ddrcfga, DDR0_02);
+			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
+			mtdcr(ddrcfgd, val);
+
+		} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
+
+	} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
+
+	/* -----------------------------------------------------------+
+	 * Largest passing window is now detected.
+	 * ----------------------------------------------------------*/
+
+	/* Compute dll_dqs_delay_X value */
+	dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
+	wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
+
+	debug("DQS calibration - Window detected:\n");
+	debug("max_passing_cases = %d\n", max_passing_cases);
+	debug("wr_dqs_shift      = %d\n", wr_dqs_shift);
+	debug("dll_dqs_delay_X   = %d\n", dll_dqs_delay_X);
+	debug("dll_dqs_delay_X window = %d - %d\n",
+	       dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
+
+	/* -----------------------------------------------------------+
+	 * De-assert 'start' parameter.
+	 * ----------------------------------------------------------*/
+	mtdcr(ddrcfga, DDR0_02);
+	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
+	mtdcr(ddrcfgd, val);
+
+	/* -----------------------------------------------------------+
+	 * Set 'wr_dqs_shift'
+	 * ----------------------------------------------------------*/
+	mtdcr(ddrcfga, DDR0_09);
+	val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
+		| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
+	mtdcr(ddrcfgd, val);
+	debug("DDR0_09=0x%08lx\n", val);
+
+	/* -----------------------------------------------------------+
+	 * Set 'dqs_out_shift' = wr_dqs_shift + 32
+	 * ----------------------------------------------------------*/
+	dqs_out_shift = wr_dqs_shift + 32;
+	mtdcr(ddrcfga, DDR0_22);
+	val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
+		| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
+	mtdcr(ddrcfgd, val);
+	debug("DDR0_22=0x%08lx\n", val);
+
+	/* -----------------------------------------------------------+
+	 * Set 'dll_dqs_delay_X'.
+	 * ----------------------------------------------------------*/
+	/* dll_dqs_delay_0 */
+	mtdcr(ddrcfga, DDR0_17);
+	val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
+		| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
+	mtdcr(ddrcfgd, val);
+	debug("DDR0_17=0x%08lx\n", val);
+
+	/* dll_dqs_delay_1 to dll_dqs_delay_4 */
+	mtdcr(ddrcfga, DDR0_18);
+	val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
+		| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
+		| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
+		| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
+		| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
+	mtdcr(ddrcfgd, val);
+	debug("DDR0_18=0x%08lx\n", val);
+
+	/* dll_dqs_delay_5 to dll_dqs_delay_8 */
+	mtdcr(ddrcfga, DDR0_19);
+	val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
+		| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
+		| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
+		| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
+		| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
+	mtdcr(ddrcfgd, val);
+	debug("DDR0_19=0x%08lx\n", val);
+
+	/* -----------------------------------------------------------+
+	 * Assert 'start' parameter.
+	 * ----------------------------------------------------------*/
+	mtdcr(ddrcfga, DDR0_02);
+	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
+	mtdcr(ddrcfgd, val);
+
+	ppcMsync();
+	ppcMbar();
+
+	/* -----------------------------------------------------------+
+	 * Wait for the DCC master delay line to finish calibration
+	 * ----------------------------------------------------------*/
+	if (wait_for_dlllock() != 0) {
+		printf("dlllock did not occur !!!\n");
+		hang();
+	}
+	ppcMsync();
+	ppcMbar();
+
+	if (wait_for_dram_init_complete() != 0) {
+		printf("dram init complete did not occur !!!\n");
+		hang();
+	}
+	udelay(100);  /* wait 100us to ensure init is really completed !!! */
+}
+#endif /* CONFIG_DDR_DATA_EYE */
+
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
@@ -30,18 +379,18 @@
 long int initdram (int board_type)
 {
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-	volatile ulong val;
+	ulong speed = get_bus_freq(0);
 
 	mtsdram(DDR0_02, 0x00000000);
 
 	mtsdram(DDR0_00, 0x0000190A);
 	mtsdram(DDR0_01, 0x01000000);
 	mtsdram(DDR0_03, 0x02030602);
-	mtsdram(DDR0_04, 0x13030300);
-	mtsdram(DDR0_05, 0x0202050E);
-	mtsdram(DDR0_06, 0x0104C823);
+	mtsdram(DDR0_04, 0x0A020200);
+	mtsdram(DDR0_05, 0x02020308);
+	mtsdram(DDR0_06, 0x0102C812);
 	mtsdram(DDR0_07, 0x000D0100);
-	mtsdram(DDR0_08, 0x02360001);
+	mtsdram(DDR0_08, 0x02430001);
 	mtsdram(DDR0_09, 0x00011D5F);
 	mtsdram(DDR0_10, 0x00000300);
 	mtsdram(DDR0_11, 0x0027C800);
@@ -55,23 +404,27 @@ long int initdram (int board_type)
 	mtsdram(DDR0_22, 0x00267F0B);
 	mtsdram(DDR0_23, 0x00000000);
 	mtsdram(DDR0_24, 0x01010002);
-	mtsdram(DDR0_26, 0x5B260181);
+	if (speed > 133333333)
+		mtsdram(DDR0_26, 0x5B26050C);
+	else
+		mtsdram(DDR0_26, 0x5B260408);
 	mtsdram(DDR0_27, 0x0000682B);
 	mtsdram(DDR0_28, 0x00000000);
 	mtsdram(DDR0_31, 0x00000000);
 	mtsdram(DDR0_42, 0x01000006);
-	mtsdram(DDR0_43, 0x050A0200);
-	mtsdram(DDR0_44, 0x00000005);
+	mtsdram(DDR0_43, 0x030A0200);
+	mtsdram(DDR0_44, 0x00000003);
 	mtsdram(DDR0_02, 0x00000001);
 
-	/*
-	 * Wait for DCC master delay line to finish calibration
-	 */
-	mfsdram(DDR0_17, val);
-	while (((val >> 8) & 0x000007f) == 0) {
-		mfsdram(DDR0_17, val);
-	}
+	wait_for_dlllock();
 #endif /* #ifndef CONFIG_NAND_U_BOOT */
 
+#ifdef CONFIG_DDR_DATA_EYE
+	/* -----------------------------------------------------------+
+	 * Perform data eye search if requested.
+	 * ----------------------------------------------------------*/
+	denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
+#endif
+
 	return (CFG_MBYTES_SDRAM << 20);
 }
diff --git a/board/amcc/sequoia/sdram.h b/board/amcc/sequoia/sdram.h
new file mode 100644
index 0000000..7f847aa
--- /dev/null
+++ b/board/amcc/sequoia/sdram.h
@@ -0,0 +1,505 @@
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPD_SDRAM_DENALI_H_
+#define _SPD_SDRAM_DENALI_H_
+
+#define ppcMsync	sync
+#define ppcMbar		eieio
+
+/* General definitions */
+#define MAX_SPD_BYTE        128         /* highest SPD byte # to read */
+#define DENALI_REG_NUMBER   45          /* 45 Regs in PPC440EPx Denali Core */
+#define SUPPORTED_DIMMS_NB  7           /* Number of supported DIMM modules types */
+#define SDRAM_NONE          0           /* No DIMM detected in Slot */
+#define MAXRANKS            2           /* 2 ranks maximum */
+
+/* Supported PLB Frequencies */
+#define PLB_FREQ_133MHZ     133333333
+#define PLB_FREQ_152MHZ     152000000
+#define PLB_FREQ_160MHZ     160000000
+#define PLB_FREQ_166MHZ     166666666
+
+/* Denali Core Registers */
+#define SDRAM_DCR_BASE 0x10
+
+#define DDR_DCR_BASE 0x10
+#define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
+#define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
+
+/*-----------------------------------------------------------------------------+
+  | Values for ddrcfga register - indirect addressing of these regs
+  +-----------------------------------------------------------------------------*/
+
+#define DDR0_00                         0x00
+#define DDR0_00_INT_ACK_MASK              0x7F000000 /* Write only */
+#define DDR0_00_INT_ACK_ALL               0x7F000000
+#define DDR0_00_INT_ACK_ENCODE(n)           ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_00_INT_ACK_DECODE(n)           ((((unsigned long)(n))>>24)&0x7F)
+/* Status */
+#define DDR0_00_INT_STATUS_MASK           0x00FF0000 /* Read only */
+/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT0           0x00010000
+/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
+#define DDR0_00_INT_STATUS_BIT1           0x00020000
+/* Bit2. Single correctable ECC event detected */
+#define DDR0_00_INT_STATUS_BIT2           0x00040000
+/* Bit3. Multiple correctable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT3           0x00080000
+/* Bit4. Single uncorrectable ECC event detected. */
+#define DDR0_00_INT_STATUS_BIT4           0x00100000
+/* Bit5. Multiple uncorrectable ECC events detected. */
+#define DDR0_00_INT_STATUS_BIT5           0x00200000
+/* Bit6. DRAM initialization complete. */
+#define DDR0_00_INT_STATUS_BIT6           0x00400000
+/* Bit7. Logical OR of all lower bits. */
+#define DDR0_00_INT_STATUS_BIT7           0x00800000
+
+#define DDR0_00_INT_STATUS_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_00_INT_STATUS_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_00_DLL_INCREMENT_MASK        0x00007F00
+#define DDR0_00_DLL_INCREMENT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_00_DLL_INCREMENT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_00_DLL_START_POINT_MASK      0x0000007F
+#define DDR0_00_DLL_START_POINT_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_00_DLL_START_POINT_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
+
+
+#define DDR0_01                         0x01
+#define DDR0_01_PLB0_DB_CS_LOWER_MASK     0x1F000000
+#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n)  ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_01_PLB0_DB_CS_UPPER_MASK     0x001F0000
+#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<16)
+#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n)  ((((unsigned long)(n))>>16)&0x1F)
+#define DDR0_01_OUT_OF_RANGE_TYPE_MASK    0x00000700 /* Read only */
+#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n)               ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n)               ((((unsigned long)(n))>>8)&0x7)
+#define DDR0_01_INT_MASK_MASK             0x000000FF
+#define DDR0_01_INT_MASK_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_01_INT_MASK_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
+#define DDR0_01_INT_MASK_ALL_ON           0x000000FF
+#define DDR0_01_INT_MASK_ALL_OFF          0x00000000
+
+#define DDR0_02                         0x02
+#define DDR0_02_MAX_CS_REG_MASK           0x02000000 /* Read only */
+#define DDR0_02_MAX_CS_REG_ENCODE(n)        ((((unsigned long)(n))&0x2)<<24)
+#define DDR0_02_MAX_CS_REG_DECODE(n)        ((((unsigned long)(n))>>24)&0x2)
+#define DDR0_02_MAX_COL_REG_MASK          0x000F0000 /* Read only */
+#define DDR0_02_MAX_COL_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<16)
+#define DDR0_02_MAX_COL_REG_DECODE(n)       ((((unsigned long)(n))>>16)&0xF)
+#define DDR0_02_MAX_ROW_REG_MASK          0x00000F00 /* Read only */
+#define DDR0_02_MAX_ROW_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_02_MAX_ROW_REG_DECODE(n)       ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_02_START_MASK                0x00000001
+#define DDR0_02_START_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_02_START_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
+#define DDR0_02_START_OFF                 0x00000000
+#define DDR0_02_START_ON                  0x00000001
+
+#define DDR0_03                         0x03
+#define DDR0_03_BSTLEN_MASK               0x07000000
+#define DDR0_03_BSTLEN_ENCODE(n)            ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_03_BSTLEN_DECODE(n)            ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_03_CASLAT_MASK               0x00070000
+#define DDR0_03_CASLAT_ENCODE(n)            ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_03_CASLAT_LIN_MASK           0x00000F00
+#define DDR0_03_CASLAT_LIN_ENCODE(n)        ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_03_CASLAT_LIN_DECODE(n)        ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_03_INITAREF_MASK             0x0000000F
+#define DDR0_03_INITAREF_ENCODE(n)          ((((unsigned long)(n))&0xF)<<0)
+#define DDR0_03_INITAREF_DECODE(n)          ((((unsigned long)(n))>>0)&0xF)
+
+#define DDR0_04                         0x04
+#define DDR0_04_TRC_MASK                  0x1F000000
+#define DDR0_04_TRC_ENCODE(n)               ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_04_TRC_DECODE(n)               ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_04_TRRD_MASK                 0x00070000
+#define DDR0_04_TRRD_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_04_TRRD_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_04_TRTP_MASK                 0x00000700
+#define DDR0_04_TRTP_ENCODE(n)              ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_04_TRTP_DECODE(n)              ((((unsigned long)(n))>>8)&0x7)
+
+#define DDR0_05                         0x05
+#define DDR0_05_TMRD_MASK                 0x1F000000
+#define DDR0_05_TMRD_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_05_TMRD_DECODE(n)              ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_05_TEMRS_MASK                0x00070000
+#define DDR0_05_TEMRS_ENCODE(n)             ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_05_TEMRS_DECODE(n)             ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_05_TRP_MASK                  0x00000F00
+#define DDR0_05_TRP_ENCODE(n)               ((((unsigned long)(n))&0xF)<<8)
+#define DDR0_05_TRP_DECODE(n)               ((((unsigned long)(n))>>8)&0xF)
+#define DDR0_05_TRAS_MIN_MASK             0x000000FF
+#define DDR0_05_TRAS_MIN_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_05_TRAS_MIN_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
+
+#define DDR0_06                         0x06
+#define DDR0_06_WRITEINTERP_MASK          0x01000000
+#define DDR0_06_WRITEINTERP_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_06_WRITEINTERP_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_06_TWTR_MASK                 0x00070000
+#define DDR0_06_TWTR_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
+#define DDR0_06_TWTR_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
+#define DDR0_06_TDLL_MASK                 0x0000FF00
+#define DDR0_06_TDLL_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_06_TDLL_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
+#define DDR0_06_TRFC_MASK                 0x0000007F
+#define DDR0_06_TRFC_ENCODE(n)              ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_06_TRFC_DECODE(n)              ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_07                         0x07
+#define DDR0_07_NO_CMD_INIT_MASK          0x01000000
+#define DDR0_07_NO_CMD_INIT_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_07_NO_CMD_INIT_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_07_TFAW_MASK                 0x001F0000
+#define DDR0_07_TFAW_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<16)
+#define DDR0_07_TFAW_DECODE(n)              ((((unsigned long)(n))>>16)&0x1F)
+#define DDR0_07_AUTO_REFRESH_MODE_MASK    0x00000100
+#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
+#define DDR0_07_AREFRESH_MASK             0x00000001
+#define DDR0_07_AREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_07_AREFRESH_DECODE(n)          ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_08                         0x08
+#define DDR0_08_WRLAT_MASK                0x07000000
+#define DDR0_08_WRLAT_ENCODE(n)             ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_08_WRLAT_DECODE(n)             ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_08_TCPD_MASK                 0x00FF0000
+#define DDR0_08_TCPD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_08_TCPD_DECODE(n)              ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_08_DQS_N_EN_MASK             0x00000100
+#define DDR0_08_DQS_N_EN_ENCODE(n)          ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_08_DQS_N_EN_DECODE(n)          ((((unsigned long)(n))>>8)&0x1)
+#define DDR0_08_DDRII_SDRAM_MODE_MASK     0x00000001
+#define DDR0_08_DDRII_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_08_DDRII_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_09                         0x09
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK  0x1F000000
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
+#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_09_RTT_0_MASK                0x00030000
+#define DDR0_09_RTT_0_ENCODE(n)             ((((unsigned long)(n))&0x3)<<16)
+#define DDR0_09_RTT_0_DECODE(n)             ((((unsigned long)(n))>>16)&0x3)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_09_WR_DQS_SHIFT_MASK         0x0000007F
+#define DDR0_09_WR_DQS_SHIFT_ENCODE(n)      ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_09_WR_DQS_SHIFT_DECODE(n)      ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_10                         0x0A
+#define DDR0_10_WRITE_MODEREG_MASK        0x00010000 /* Write only */
+#define DDR0_10_WRITE_MODEREG_ENCODE(n)     ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_10_WRITE_MODEREG_DECODE(n)     ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_10_CS_MAP_MASK               0x00000300
+#define DDR0_10_CS_MAP_NO_MEM             0x00000000
+#define DDR0_10_CS_MAP_RANK0_INSTALLED    0x00000100
+#define DDR0_10_CS_MAP_RANK1_INSTALLED    0x00000200
+#define DDR0_10_CS_MAP_ENCODE(n)            ((((unsigned long)(n))&0x3)<<8)
+#define DDR0_10_CS_MAP_DECODE(n)            ((((unsigned long)(n))>>8)&0x3)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
+#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
+
+#define DDR0_11                         0x0B
+#define DDR0_11_SREFRESH_MASK             0x01000000
+#define DDR0_11_SREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_11_SREFRESH_DECODE(n)          ((((unsigned long)(n))>>24)&0x1F)
+#define DDR0_11_TXSNR_MASK                0x00FF0000
+#define DDR0_11_TXSNR_ENCODE(n)             ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_11_TXSNR_DECODE(n)             ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_11_TXSR_MASK                 0x0000FF00
+#define DDR0_11_TXSR_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_11_TXSR_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
+
+#define DDR0_12                         0x0C
+#define DDR0_12_TCKE_MASK                 0x0000007
+#define DDR0_12_TCKE_ENCODE(n)              ((((unsigned long)(n))&0x7)<<0)
+#define DDR0_12_TCKE_DECODE(n)              ((((unsigned long)(n))>>0)&0x7)
+
+#define DDR0_13                         0x0D
+
+#define DDR0_14                         0x0E
+#define DDR0_14_DLL_BYPASS_MODE_MASK      0x01000000
+#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<24)
+#define DDR0_14_DLL_BYPASS_MODE_DECODE(n)   ((((unsigned long)(n))>>24)&0x1)
+#define DDR0_14_REDUC_MASK                0x00010000
+#define DDR0_14_REDUC_64BITS              0x00000000
+#define DDR0_14_REDUC_32BITS              0x00010000
+#define DDR0_14_REDUC_ENCODE(n)             ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_14_REDUC_DECODE(n)             ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_14_REG_DIMM_ENABLE_MASK      0x00000100
+#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<8)
+#define DDR0_14_REG_DIMM_ENABLE_DECODE(n)   ((((unsigned long)(n))>>8)&0x1)
+
+#define DDR0_15                         0x0F
+
+#define DDR0_16                         0x10
+
+#define DDR0_17                         0x11
+#define DDR0_17_DLL_DQS_DELAY_0_MASK      0x7F000000
+#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
+#define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
+#define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
+#define DDR0_17_DLLLOCKREG_ENCODE(n)        ((((unsigned long)(n))&0x1)<<16)
+#define DDR0_17_DLLLOCKREG_DECODE(n)        ((((unsigned long)(n))>>16)&0x1)
+#define DDR0_17_DLL_LOCK_MASK             0x00007F00 /* Read only */
+#define DDR0_17_DLL_LOCK_ENCODE(n)          ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_17_DLL_LOCK_DECODE(n)          ((((unsigned long)(n))>>8)&0x7F)
+
+#define DDR0_18                         0x12
+#define DDR0_18_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
+#define DDR0_18_DLL_DQS_DELAY_4_MASK      0x7F000000
+#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_3_MASK      0x007F0000
+#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_2_MASK      0x00007F00
+#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_18_DLL_DQS_DELAY_1_MASK      0x0000007F
+#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_19                         0x13
+#define DDR0_19_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
+#define DDR0_19_DLL_DQS_DELAY_8_MASK      0x7F000000
+#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_7_MASK      0x007F0000
+#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_6_MASK      0x00007F00
+#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_19_DLL_DQS_DELAY_5_MASK      0x0000007F
+#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_20                         0x14
+#define DDR0_20_DLL_DQS_BYPASS_3_MASK      0x7F000000
+#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_2_MASK      0x007F0000
+#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_1_MASK      0x00007F00
+#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_20_DLL_DQS_BYPASS_0_MASK      0x0000007F
+#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_21                         0x15
+#define DDR0_21_DLL_DQS_BYPASS_7_MASK      0x7F000000
+#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
+#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_6_MASK      0x007F0000
+#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_5_MASK      0x00007F00
+#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_21_DLL_DQS_BYPASS_4_MASK      0x0000007F
+#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
+
+#define DDR0_22                         0x16
+/* ECC */
+#define DDR0_22_CTRL_RAW_MASK             0x03000000
+#define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not being used */
+#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC checking is on, but no attempts to correct*/
+#define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* No ECC RAM storage available */
+#define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC checking and correcting on */
+#define DDR0_22_CTRL_RAW_ENCODE(n)          ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_22_CTRL_RAW_DECODE(n)          ((((unsigned long)(n))>>24)&0x3)
+
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
+#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
+#define DDR0_22_DQS_OUT_SHIFT_MASK        0x00007F00
+#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
+#define DDR0_22_DQS_OUT_SHIFT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
+#define DDR0_22_DLL_DQS_BYPASS_8_MASK     0x0000007F
+#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n)  ((((unsigned long)(n))&0x7F)<<0)
+#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n)  ((((unsigned long)(n))>>0)&0x7F)
+
+
+#define DDR0_23                         0x17
+#define DDR0_23_ODT_RD_MAP_CS0_MASK       0x03000000
+#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n)   ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n)   ((((unsigned long)(n))>>24)&0x3)
+#define DDR0_23_ECC_C_SYND_MASK           0x00FF0000 /* Read only */
+#define DDR0_23_ECC_C_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
+#define DDR0_23_ECC_C_SYND_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
+#define DDR0_23_ECC_U_SYND_MASK           0x0000FF00 /* Read only */
+#define DDR0_23_ECC_U_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<8)
+#define DDR0_23_ECC_U_SYND_DECODE(n)        ((((unsigned long)(n))>>8)&0xFF)
+#define DDR0_23_FWC_MASK                  0x00000001 /* Write only */
+#define DDR0_23_FWC_ENCODE(n)               ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_23_FWC_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_24                         0x18
+#define DDR0_24_RTT_PAD_TERMINATION_MASK  0x03000000
+#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
+#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS1_MASK       0x00030000
+#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<16)
+#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>16)&0x3)
+#define DDR0_24_ODT_RD_MAP_CS1_MASK       0x00000300
+#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<8)
+#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>8)&0x3)
+#define DDR0_24_ODT_WR_MAP_CS0_MASK       0x00000003
+#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n)    ((((unsigned long)(n))&0x3)<<0)
+#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n)    ((((unsigned long)(n))>>0)&0x3)
+
+#define DDR0_25                         0x19
+#define DDR0_25_VERSION_MASK              0xFFFF0000 /* Read only */
+#define DDR0_25_VERSION_ENCODE(n)           ((((unsigned long)(n))&0xFFFF)<<16)
+#define DDR0_25_VERSION_DECODE(n)           ((((unsigned long)(n))>>16)&0xFFFF)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK  0x000003FF /* Read only */
+#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
+#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
+
+#define DDR0_26                         0x1A
+#define DDR0_26_TRAS_MAX_MASK             0xFFFF0000
+#define DDR0_26_TRAS_MAX_ENCODE(n)          ((((unsigned long)(n))&0xFFFF)<<16)
+#define DDR0_26_TRAS_MAX_DECODE(n)          ((((unsigned long)(n))>>16)&0xFFFF)
+#define DDR0_26_TREF_MASK                 0x00003FFF
+#define DDR0_26_TREF_ENCODE(n)              ((((unsigned long)(n))&0x3FF)<<0)
+#define DDR0_26_TREF_DECODE(n)              ((((unsigned long)(n))>>0)&0x3FF)
+
+#define DDR0_27                         0x1B
+#define DDR0_27_EMRS_DATA_MASK            0x3FFF0000
+#define DDR0_27_EMRS_DATA_ENCODE(n)         ((((unsigned long)(n))&0x3FFF)<<16)
+#define DDR0_27_EMRS_DATA_DECODE(n)         ((((unsigned long)(n))>>16)&0x3FFF)
+#define DDR0_27_TINIT_MASK                0x0000FFFF
+#define DDR0_27_TINIT_ENCODE(n)             ((((unsigned long)(n))&0xFFFF)<<0)
+#define DDR0_27_TINIT_DECODE(n)             ((((unsigned long)(n))>>0)&0xFFFF)
+
+#define DDR0_28                         0x1C
+#define DDR0_28_EMRS3_DATA_MASK           0x3FFF0000
+#define DDR0_28_EMRS3_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<16)
+#define DDR0_28_EMRS3_DATA_DECODE(n)        ((((unsigned long)(n))>>16)&0x3FFF)
+#define DDR0_28_EMRS2_DATA_MASK           0x00003FFF
+#define DDR0_28_EMRS2_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<0)
+#define DDR0_28_EMRS2_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0x3FFF)
+
+#define DDR0_29                         0x1D
+
+#define DDR0_30                         0x1E
+
+#define DDR0_31                         0x1F
+#define DDR0_31_XOR_CHECK_BITS_MASK       0x0000FFFF
+#define DDR0_31_XOR_CHECK_BITS_ENCODE(n)    ((((unsigned long)(n))&0xFFFF)<<0)
+#define DDR0_31_XOR_CHECK_BITS_DECODE(n)    ((((unsigned long)(n))>>0)&0xFFFF)
+
+#define DDR0_32                         0x20
+#define DDR0_32_OUT_OF_RANGE_ADDR_MASK    0xFFFFFFFF /* Read only */
+#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_33                         0x21
+#define DDR0_33_OUT_OF_RANGE_ADDR_MASK    0x00000001 /* Read only */
+#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_34                         0x22
+#define DDR0_34_ECC_U_ADDR_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_34_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_34_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_35                         0x23
+#define DDR0_35_ECC_U_ADDR_MASK           0x00000001 /* Read only */
+#define DDR0_35_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_35_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_36                         0x24
+#define DDR0_36_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_36_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_36_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_37                         0x25
+#define DDR0_37_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_37_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_37_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_38                         0x26
+#define DDR0_38_ECC_C_ADDR_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_38_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_38_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_39                         0x27
+#define DDR0_39_ECC_C_ADDR_MASK           0x00000001 /* Read only */
+#define DDR0_39_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_39_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_40                         0x28
+#define DDR0_40_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_40_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_40_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_41                         0x29
+#define DDR0_41_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
+#define DDR0_41_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
+#define DDR0_41_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
+
+#define DDR0_42                         0x2A
+#define DDR0_42_ADDR_PINS_MASK            0x07000000
+#define DDR0_42_ADDR_PINS_ENCODE(n)         ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_42_ADDR_PINS_DECODE(n)         ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_42_CASLAT_LIN_GATE_MASK      0x0000000F
+#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n)   ((((unsigned long)(n))&0xF)<<0)
+#define DDR0_42_CASLAT_LIN_GATE_DECODE(n)   ((((unsigned long)(n))>>0)&0xF)
+
+#define DDR0_43                         0x2B
+#define DDR0_43_TWR_MASK                  0x07000000
+#define DDR0_43_TWR_ENCODE(n)               ((((unsigned long)(n))&0x7)<<24)
+#define DDR0_43_TWR_DECODE(n)               ((((unsigned long)(n))>>24)&0x7)
+#define DDR0_43_APREBIT_MASK              0x000F0000
+#define DDR0_43_APREBIT_ENCODE(n)           ((((unsigned long)(n))&0xF)<<16)
+#define DDR0_43_APREBIT_DECODE(n)           ((((unsigned long)(n))>>16)&0xF)
+#define DDR0_43_COLUMN_SIZE_MASK          0x00000700
+#define DDR0_43_COLUMN_SIZE_ENCODE(n)       ((((unsigned long)(n))&0x7)<<8)
+#define DDR0_43_COLUMN_SIZE_DECODE(n)       ((((unsigned long)(n))>>8)&0x7)
+#define DDR0_43_EIGHT_BANK_MODE_MASK      0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_8_BANKS     0x00000001
+#define DDR0_43_EIGHT_BANK_MODE_4_BANKS     0x00000000
+#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<0)
+#define DDR0_43_EIGHT_BANK_MODE_DECODE(n)   ((((unsigned long)(n))>>0)&0x1)
+
+#define DDR0_44                         0x2C
+#define DDR0_44_TRCD_MASK                 0x000000FF
+#define DDR0_44_TRCD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<0)
+#define DDR0_44_TRCD_DECODE(n)              ((((unsigned long)(n))>>0)&0xFF)
+
+#endif /* _SPD_SDRAM_DENALI_H_ */
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index ccf6f0c..daaffe0 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -31,11 +31,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
+ulong flash_get_size (ulong base, int banknum);
+
 int board_early_init_f(void)
 {
-	unsigned long sdr0_cust0;
-	unsigned long sdr0_pfc1, sdr0_pfc2;
-	register uint reg;
+	u32 sdr0_cust0;
+	u32 sdr0_pfc1, sdr0_pfc2;
+	u32 reg;
 
 	mtdcr(ebccfga, xbcfg);
 	mtdcr(ebccfgd, 0xb8400000);
@@ -140,6 +142,7 @@ int misc_init_r(void)
 {
 	uint pbcr;
 	int size_val = 0;
+	u32 reg;
 #ifdef CONFIG_440EPX
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
@@ -152,6 +155,11 @@ int misc_init_r(void)
 	 */
 
 	/* Re-do sizing to get full correct info */
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 	mtdcr(ebccfga, pb3cr);
 #else
@@ -192,9 +200,10 @@ int misc_init_r(void)
 #endif
 	mtdcr(ebccfgd, pbcr);
 
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size(gd->bd->bi_flashstart, 0);
 
 #ifdef CFG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
@@ -327,18 +336,37 @@ int misc_init_r(void)
 	}
 #endif /* CONFIG_440EPX */
 
+	mfsdr(SDR0_SRST1, reg);		/* enable security/kasumi engines */
+	reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
+	mtsdr(SDR0_SRST1, reg);
+
+	/*
+	 * Clear PLB4A0_ACR[WRP]
+	 * This fix will make the MAL burst disabling patch for the Linux
+	 * EMAC driver obsolete.
+	 */
+	reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
+	mtdcr(plb4_acr, reg);
+
 	return 0;
 }
 
 int checkboard(void)
 {
 	char *s = getenv("serial#");
+	u8 rev;
+	u8 val;
 
 #ifdef CONFIG_440EPX
 	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
 #else
 	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
+
+	rev = *(u8 *)(CFG_CPLD + 0);
+	val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+
 	if (s != NULL) {
 		puts(", serial# ");
 		puts(s);
diff --git a/board/amcc/yellowstone/Makefile b/board/amcc/taishan/Makefile
index 261e5d4..462af00 100644
--- a/board/amcc/yellowstone/Makefile
+++ b/board/amcc/taishan/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002-2006
+# (C) Copyright 2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o
+COBJS	= $(BOARD).o lcd.o update.o showinfo.o
 SOBJS	= init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/amcc/taishan/config.mk b/board/amcc/taishan/config.mk
new file mode 100644
index 0000000..4eefff2
--- /dev/null
+++ b/board/amcc/taishan/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440GX Reference Platform (Taishan) board
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/taishan/init.S b/board/amcc/taishan/init.S
new file mode 100644
index 0000000..8db043b
--- /dev/null
+++ b/board/amcc/taishan/init.S
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+#define _256M       0x10000000
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_8M       0x00000060
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbtab_end
diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c
new file mode 100644
index 0000000..8d2dce3
--- /dev/null
+++ b/board/amcc/taishan/lcd.c
@@ -0,0 +1,380 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+#ifdef CONFIG_TAISHAN
+
+#define LCD_DELAY_NORMAL_US	100
+#define LCD_DELAY_NORMAL_MS	2
+#define LCD_CMD_ADDR		((volatile char *)(CFG_EBC2_LCM_BASE))
+#define LCD_DATA_ADDR		((volatile char *)(CFG_EBC2_LCM_BASE+1))
+#define LCD_BLK_CTRL		((volatile char *)(CFG_EBC1_FPGA_BASE+0x2))
+
+#define mdelay(t)	({unsigned long msec=(t); while (msec--) { udelay(1000);}})
+
+static int g_lcd_init_b = 0;
+static char *amcc_logo = "  AMCC TAISHAN  440GX EvalBoard";
+static char addr_flag = 0x80;
+
+static void lcd_bl_ctrl(char val)
+{
+	char cpld_val;
+
+	cpld_val = *LCD_BLK_CTRL;
+	*LCD_BLK_CTRL = val | cpld_val;
+}
+
+static void lcd_putc(char val)
+{
+	int i = 100;
+	char addr;
+
+	while (i--) {
+		if ((*LCD_CMD_ADDR & 0x80) != 0x80) {	/*BF = 1 ? */
+			udelay(LCD_DELAY_NORMAL_US);
+			break;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	if (*LCD_CMD_ADDR & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	addr = *LCD_CMD_ADDR;
+	udelay(LCD_DELAY_NORMAL_US);
+	if ((addr != 0) && (addr % 0x10 == 0)) {
+		addr_flag ^= 0x40;
+		*LCD_CMD_ADDR = addr_flag;
+	}
+
+	udelay(LCD_DELAY_NORMAL_US);
+	*LCD_DATA_ADDR = val;
+	udelay(LCD_DELAY_NORMAL_US);
+}
+
+static void lcd_puts(char *s)
+{
+	char *p = s;
+	int i = 100;
+
+	while (i--) {
+		if ((*LCD_CMD_ADDR & 0x80) != 0x80) {	/*BF = 1 ? */
+			udelay(LCD_DELAY_NORMAL_US);
+			break;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	if (*LCD_CMD_ADDR & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	while (*p)
+		lcd_putc(*p++);
+}
+
+static void lcd_put_logo(void)
+{
+	int i = 100;
+	char *p = amcc_logo;
+
+	while (i--) {
+		if ((*LCD_CMD_ADDR & 0x80) != 0x80) {	/*BF = 1 ? */
+			udelay(LCD_DELAY_NORMAL_US);
+			break;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	if (*LCD_CMD_ADDR & 0x80) {
+		printf("LCD is busy\n");
+		return;
+	}
+
+	*LCD_CMD_ADDR = 0x80;
+	while (*p)
+		lcd_putc(*p++);
+}
+
+int lcd_init(void)
+{
+	if (g_lcd_init_b == 0) {
+		puts("LCD: ");
+		mdelay(100);	/* Waiting for the LCD initialize */
+
+		*LCD_CMD_ADDR = 0x38;	/*set function:8-bit,2-line,5x7 font type */
+		udelay(LCD_DELAY_NORMAL_US);
+
+		*LCD_CMD_ADDR = 0x0f;	/*set display on,cursor on,blink on */
+		udelay(LCD_DELAY_NORMAL_US);
+
+		*LCD_CMD_ADDR = 0x01;	/*display clear */
+		mdelay(LCD_DELAY_NORMAL_MS);
+
+		*LCD_CMD_ADDR = 0x06;	/*set entry */
+		udelay(LCD_DELAY_NORMAL_US);
+
+		lcd_bl_ctrl(0x02);
+		lcd_put_logo();
+
+		puts("  ready\n");
+		g_lcd_init_b = 1;
+	}
+
+	return 0;
+}
+
+static int do_lcd_test(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	lcd_init();
+	return 0;
+}
+
+static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	*LCD_CMD_ADDR = 0x01;
+	mdelay(LCD_DELAY_NORMAL_MS);
+	return 0;
+}
+static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc < 2) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+	lcd_puts(argv[1]);
+	return 0;
+}
+static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc < 2) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+	lcd_putc((char)argv[1][0]);
+	return 0;
+}
+static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	ulong count;
+	ulong dir;
+	char cur_addr;
+
+	if (argc < 3) {
+		printf("%s", cmdtp->usage);
+		return 1;
+	}
+
+	count = simple_strtoul(argv[1], NULL, 16);
+	if (count > 31) {
+		printf("unable to shift > 0x20\n");
+		count = 0;
+	}
+
+	dir = simple_strtoul(argv[2], NULL, 16);
+	cur_addr = *LCD_CMD_ADDR;
+	udelay(LCD_DELAY_NORMAL_US);
+	if (dir == 0x0) {
+		if (addr_flag == 0x80) {
+			if (count >= (cur_addr & 0xf)) {
+				*LCD_CMD_ADDR = 0x80;
+				udelay(LCD_DELAY_NORMAL_US);
+				count = 0;
+			}
+		} else {
+			if (count >= ((cur_addr & 0x0f) + 0x0f)) {
+				*LCD_CMD_ADDR = 0x80;
+				addr_flag = 0x80;
+				udelay(LCD_DELAY_NORMAL_US);
+				count = 0x0;
+			} else if (count >= (cur_addr & 0xf)) {
+				count -= cur_addr & 0xf;
+				*LCD_CMD_ADDR = 0x80 | 0xf;
+				addr_flag = 0x80;
+				udelay(LCD_DELAY_NORMAL_US);
+			}
+		}
+	} else {
+		if (addr_flag == 0x80) {
+			if (count >= (0x1f - (cur_addr & 0xf))) {
+				count = 0x0;
+				addr_flag = 0xc0;
+				*LCD_CMD_ADDR = 0xc0 | 0xf;
+				udelay(LCD_DELAY_NORMAL_US);
+			} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
+				count = count + (cur_addr & 0xf) - 0x0f;
+				addr_flag = 0xc0;
+				*LCD_CMD_ADDR = 0xc0;
+				udelay(LCD_DELAY_NORMAL_US);
+			}
+		} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
+			count = 0x0;
+			*LCD_CMD_ADDR = 0xc0 | 0xf;
+			udelay(LCD_DELAY_NORMAL_US);
+		}
+	}
+
+	while (count--) {
+		if (dir == 0) {
+			*LCD_CMD_ADDR = 0x10;
+		} else {
+			*LCD_CMD_ADDR = 0x14;
+		}
+		udelay(LCD_DELAY_NORMAL_US);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd_test - lcd test display\n", NULL);
+U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd_cls - lcd clear display\n", NULL);
+U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts,
+	   "lcd_puts - display string on lcd\n",
+	   "<string> - <string> to be displayed\n");
+U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc,
+	   "lcd_putc - display char on lcd\n",
+	   "<char> - <char> to be displayed\n");
+U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur,
+	   "lcd_cur - shift cursor on lcd\n",
+	   "<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n"
+	   " <count> - 0~31\n" " <dir> - 0,backward; 1, forward\n");
+
+#if 0 /* test-only */
+void set_phy_loopback_mode(void)
+{
+	char devemac2[32];
+	char devemac3[32];
+
+	sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
+	sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
+
+#if 0
+	unsigned short reg_short;
+
+	miiphy_read(devemac2, 0x1, 1, &reg_short);
+	if (reg_short & 0x04) {
+		/*
+		 * printf("EMAC2 link up,do nothing\n");
+		 */
+	} else {
+		udelay(1000);
+		miiphy_write(devemac2, 0x1, 0, 0x6000);
+		udelay(1000);
+		miiphy_read(devemac2, 0x1, 0, &reg_short);
+		if (reg_short != 0x6000) {
+			printf
+			    ("\nEMAC2 error set LOOPBACK mode error,reg2[0]=%x\n",
+			     reg_short);
+		}
+	}
+
+	miiphy_read(devemac3, 0x3, 1, &reg_short);
+	if (reg_short & 0x04) {
+		/*
+		 * printf("EMAC3 link up,do nothing\n");
+		 */
+	} else {
+		udelay(1000);
+		miiphy_write(devemac3, 0x3, 0, 0x6000);
+		udelay(1000);
+		miiphy_read(devemac3, 0x3, 0, &reg_short);
+		if (reg_short != 0x6000) {
+			printf
+			    ("\nEMAC3 error set LOOPBACK mode error,reg2[0]=%x\n",
+			     reg_short);
+		}
+	}
+#else
+	/* Set PHY as LOOPBACK MODE, for Linux emac initializing */
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0, 0x6000);
+	udelay(1000);
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0, 0x6000);
+	udelay(1000);
+#endif	/* 0 */
+}
+
+void set_phy_normal_mode(void)
+{
+	char devemac2[32];
+	char devemac3[32];
+	unsigned short reg_short;
+
+	sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
+	sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
+
+	/* Set phy of EMAC2 */
+	miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x16, &reg_short);
+	reg_short &= ~(0x7);
+	reg_short |= 0x6;	/* RGMII DLL Delay */
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x16, reg_short);
+
+	miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x17, &reg_short);
+	reg_short &= ~(0x40);
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x17, reg_short);
+
+	miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x1c, 0x74f0);
+
+	/* Set phy of EMAC3 */
+	miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x16, &reg_short);
+	reg_short &= ~(0x7);
+	reg_short |= 0x6;	/* RGMII DLL Delay */
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x16, reg_short);
+
+	miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x17, &reg_short);
+	reg_short &= ~(0x40);
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x17, reg_short);
+
+	miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x1c, 0x74f0);
+}
+#endif	/* 0 - test only */
+
+static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	volatile unsigned int *GpioOr =
+		(volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
+	*GpioOr |= 0x00300000;
+	return 0;
+}
+
+static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	volatile unsigned int *GpioOr =
+		(volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
+	*GpioOr &= ~0x00300000;
+	return 0;
+}
+
+U_BOOT_CMD(ledon, 1, 1, do_led_test_on,
+	   "ledon - led test light on\n", NULL);
+
+U_BOOT_CMD(ledoff, 1, 1, do_led_test_off,
+	   "ledoff - led test light off\n", NULL);
+#endif
diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c
new file mode 100644
index 0000000..57b9d1c
--- /dev/null
+++ b/board/amcc/taishan/showinfo.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+void show_reset_reg(void)
+{
+	unsigned long reg;
+
+	/* read clock regsiter */
+	printf("===== Display reset and initialize register Start =========\n");
+	mfclk(clk_pllc,reg);
+	printf("cpr_pllc   = %#010x\n",reg);
+
+	mfclk(clk_plld,reg);
+	printf("cpr_plld   = %#010x\n",reg);
+
+	mfclk(clk_primad,reg);
+	printf("cpr_primad = %#010x\n",reg);
+
+	mfclk(clk_primbd,reg);
+	printf("cpr_primbd = %#010x\n",reg);
+
+	mfclk(clk_opbd,reg);
+	printf("cpr_opbd   = %#010x\n",reg);
+
+	mfclk(clk_perd,reg);
+	printf("cpr_perd   = %#010x\n",reg);
+
+	mfclk(clk_mald,reg);
+	printf("cpr_mald   = %#010x\n",reg);
+
+	/* read sdr register */
+	mfsdr(sdr_ebc,reg);
+	printf("sdr_ebc    = %#010x\n",reg);
+
+	mfsdr(sdr_cp440,reg);
+	printf("sdr_cp440  = %#010x\n",reg);
+
+	mfsdr(sdr_xcr,reg);
+	printf("sdr_xcr    = %#010x\n",reg);
+
+	mfsdr(sdr_xpllc,reg);
+	printf("sdr_xpllc  = %#010x\n",reg);
+
+	mfsdr(sdr_xplld,reg);
+	printf("sdr_xplld  = %#010x\n",reg);
+
+	mfsdr(sdr_pfc0,reg);
+	printf("sdr_pfc0   = %#010x\n",reg);
+
+	mfsdr(sdr_pfc1,reg);
+	printf("sdr_pfc1   = %#010x\n",reg);
+
+	mfsdr(sdr_cust0,reg);
+	printf("sdr_cust0  = %#010x\n",reg);
+
+	mfsdr(sdr_cust1,reg);
+	printf("sdr_cust1  = %#010x\n",reg);
+
+	mfsdr(sdr_uart0,reg);
+	printf("sdr_uart0  = %#010x\n",reg);
+
+	mfsdr(sdr_uart1,reg);
+	printf("sdr_uart1  = %#010x\n",reg);
+
+	printf("===== Display reset and initialize register End   =========\n");
+}
+
+void show_xbridge_info(void)
+{
+	unsigned long reg;
+
+	printf("PCI-X chip control registers\n");
+	mfsdr(sdr_xcr, reg);
+	printf("sdr_xcr    = %#010x\n", reg);
+
+	mfsdr(sdr_xpllc, reg);
+	printf("sdr_xpllc  = %#010x\n", reg);
+
+	mfsdr(sdr_xplld, reg);
+	printf("sdr_xplld  = %#010x\n", reg);
+
+	printf("PCI-X Bridge Configure registers\n");
+	printf("PCIX0_VENDID            = %#06x\n", in16r(PCIX0_VENDID));
+	printf("PCIX0_DEVID             = %#06x\n", in16r(PCIX0_DEVID));
+	printf("PCIX0_CMD               = %#06x\n", in16r(PCIX0_CMD));
+	printf("PCIX0_STATUS            = %#06x\n", in16r(PCIX0_STATUS));
+	printf("PCIX0_REVID             = %#04x\n", in8(PCIX0_REVID));
+	printf("PCIX0_CACHELS           = %#04x\n", in8(PCIX0_CACHELS));
+	printf("PCIX0_LATTIM            = %#04x\n", in8(PCIX0_LATTIM));
+	printf("PCIX0_HDTYPE            = %#04x\n", in8(PCIX0_HDTYPE));
+	printf("PCIX0_BIST              = %#04x\n", in8(PCIX0_BIST));
+
+	printf("PCIX0_BAR0              = %#010x\n", in32r(PCIX0_BAR0));
+	printf("PCIX0_BAR1              = %#010x\n", in32r(PCIX0_BAR1));
+	printf("PCIX0_BAR2              = %#010x\n", in32r(PCIX0_BAR2));
+	printf("PCIX0_BAR3              = %#010x\n", in32r(PCIX0_BAR3));
+	printf("PCIX0_BAR4              = %#010x\n", in32r(PCIX0_BAR4));
+	printf("PCIX0_BAR5              = %#010x\n", in32r(PCIX0_BAR5));
+
+	printf("PCIX0_CISPTR            = %#010x\n", in32r(PCIX0_CISPTR));
+	printf("PCIX0_SBSSYSVID         = %#010x\n", in16r(PCIX0_SBSYSVID));
+	printf("PCIX0_SBSSYSID          = %#010x\n", in16r(PCIX0_SBSYSID));
+	printf("PCIX0_EROMBA            = %#010x\n", in32r(PCIX0_EROMBA));
+	printf("PCIX0_CAP               = %#04x\n", in8(PCIX0_CAP));
+	printf("PCIX0_INTLN             = %#04x\n", in8(PCIX0_INTLN));
+	printf("PCIX0_INTPN             = %#04x\n", in8(PCIX0_INTPN));
+	printf("PCIX0_MINGNT            = %#04x\n", in8(PCIX0_MINGNT));
+	printf("PCIX0_MAXLTNCY          = %#04x\n", in8(PCIX0_MAXLTNCY));
+
+	printf("PCIX0_BRDGOPT1          = %#010x\n", in32r(PCIX0_BRDGOPT1));
+	printf("PCIX0_BRDGOPT2          = %#010x\n", in32r(PCIX0_BRDGOPT2));
+
+	printf("PCIX0_POM0LAL           = %#010x\n", in32r(PCIX0_POM0LAL));
+	printf("PCIX0_POM0LAH           = %#010x\n", in32r(PCIX0_POM0LAH));
+	printf("PCIX0_POM0SA            = %#010x\n", in32r(PCIX0_POM0SA));
+	printf("PCIX0_POM0PCILAL        = %#010x\n", in32r(PCIX0_POM0PCIAL));
+	printf("PCIX0_POM0PCILAH        = %#010x\n", in32r(PCIX0_POM0PCIAH));
+	printf("PCIX0_POM1LAL           = %#010x\n", in32r(PCIX0_POM1LAL));
+	printf("PCIX0_POM1LAH           = %#010x\n", in32r(PCIX0_POM1LAH));
+	printf("PCIX0_POM1SA            = %#010x\n", in32r(PCIX0_POM1SA));
+	printf("PCIX0_POM1PCILAL        = %#010x\n", in32r(PCIX0_POM1PCIAL));
+	printf("PCIX0_POM1PCILAH        = %#010x\n", in32r(PCIX0_POM1PCIAH));
+	printf("PCIX0_POM2SA            = %#010x\n", in32r(PCIX0_POM2SA));
+
+	printf("PCIX0_PIM0SA            = %#010x\n", in32r(PCIX0_PIM0SA));
+	printf("PCIX0_PIM0LAL           = %#010x\n", in32r(PCIX0_PIM0LAL));
+	printf("PCIX0_PIM0LAH           = %#010x\n", in32r(PCIX0_PIM0LAH));
+	printf("PCIX0_PIM1SA            = %#010x\n", in32r(PCIX0_PIM1SA));
+	printf("PCIX0_PIM1LAL           = %#010x\n", in32r(PCIX0_PIM1LAL));
+	printf("PCIX0_PIM1LAH           = %#010x\n", in32r(PCIX0_PIM1LAH));
+	printf("PCIX0_PIM2SA            = %#010x\n", in32r(PCIX0_PIM1SA));
+	printf("PCIX0_PIM2LAL           = %#010x\n", in32r(PCIX0_PIM1LAL));
+	printf("PCIX0_PIM2LAH           = %#010x\n", in32r(PCIX0_PIM1LAH));
+
+	printf("PCIX0_XSTS              = %#010x\n", in32r(PCIX0_STS));
+}
+
+int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	show_xbridge_info();
+	return 0;
+}
+
+U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
+	   "xbriinfo  - Show PCIX bridge info\n", NULL);
+
+#define TAISHAN_PCI_DEV_ID0 0x800
+#define TAISHAN_PCI_DEV_ID1 0x1000
+
+void show_pcix_device_info(void)
+{
+	int ii;
+	int dev;
+	u8 capp;
+	u8 xcapid;
+	u16 status;
+	u16 xcommand;
+	u32 xstatus;
+
+	for (ii = 0; ii < 2; ii++) {
+		if (ii == 0)
+			dev = TAISHAN_PCI_DEV_ID0;
+		else
+			dev = TAISHAN_PCI_DEV_ID1;
+
+		pci_read_config_word(dev, PCI_STATUS, &status);
+		if (status & PCI_STATUS_CAP_LIST) {
+			pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
+
+			pci_read_config_byte(dev, (int)(capp), &xcapid);
+			if (xcapid == 0x07) {
+				pci_read_config_word(dev, (int)(capp + 2),
+						     &xcommand);
+				pci_read_config_dword(dev, (int)(capp + 4),
+						      &xstatus);
+				printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
+				       (ii + 1), xcommand, xstatus);
+			} else {
+				printf("BUS0 dev%d PCI-X CAP ID error,"
+				       "CAP=%#04x,XCAPID=%#04x\n",
+				       (ii + 1), capp, xcapid);
+			}
+		} else {
+			printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
+			       ii + 1);
+		}
+	}
+
+}
+
+int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
+			     char *argv[])
+{
+	show_pcix_device_info();
+	return 0;
+}
+
+U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
+	   "xdevinfo  - Show PCIX Device info\n", NULL);
+
+extern void show_reset_reg(void);
+
+int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	show_reset_reg();
+	return 0;
+}
+
+U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
+	   "resetinfo  - Show Reset REG info\n", NULL);
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
new file mode 100644
index 0000000..1a2e53b
--- /dev/null
+++ b/board/amcc/taishan/taishan.c
@@ -0,0 +1,331 @@
+/*
+ *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
+ *
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <ppc4xx_enet.h>
+
+#ifdef CFG_INIT_SHOW_RESET_REG
+void show_reset_reg(void);
+#endif
+
+int lcd_init(void);
+
+int board_early_init_f (void)
+{
+	unsigned long reg;
+	volatile unsigned int *GpioOdr;
+	volatile unsigned int *GpioTcr;
+	volatile unsigned int *GpioOr;
+
+	/*-------------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------------*/
+	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
+	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
+	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+	/*-------------------------------------------------------------------------+
+	  | 64MB FLASH. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
+	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
+	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | FPGA. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
+	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
+	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | LCM. Initialize bank 2 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
+	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | TMP. Initialize bank 3 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
+	      EBC_BXAP_BCE_DISABLE |
+	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
+	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
+	      EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | Connector 4~7. Initialize bank 3~ 7 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb4ap,0);
+	mtebc(pb4cr,0);
+	mtebc(pb5ap,0);
+	mtebc(pb5cr,0);
+	mtebc(pb6ap,0);
+	mtebc(pb6cr,0);
+	mtebc(pb7ap,0);
+	mtebc(pb7cr,0);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
+	mtdcr (uicb0er, 0x00000000);	/* disable all */
+	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000);	/* */
+	mtdcr (uicb0tr, 0x00000000);	/* */
+	mtdcr (uicb0vr, 0x00000001);	/* */
+
+	/* Enable two GPIO 10~11 and TraceA signal */
+	mfsdr(sdr_pfc0,reg);
+	reg |= 0x00300000;
+	mtsdr(sdr_pfc0,reg);
+
+	mfsdr(sdr_pfc1,reg);
+	reg |= 0x00100000;
+	mtsdr(sdr_pfc1,reg);
+
+	/* Set GPIO 10 and 11 as output */
+	GpioOdr	= (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
+	GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
+	GpioOr  = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);
+
+	*GpioOdr &= ~(0x00300000);
+	*GpioTcr |= 0x00300000;
+	*GpioOr  |= 0x00300000;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	lcd_init();
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	putc ('\n');
+
+#ifdef CFG_INIT_SHOW_RESET_REG
+	show_reset_reg();
+#endif
+
+	return (0);
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x04000000;
+	uint *pend = (uint *) 0x0fc00000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 *	The ocotea board is always configured as the host & requires the
+	 *	PCI arbiter to be enabled.
+	 *--------------------------------------------------------------------------*/
+	mfsdr(sdr_sdstp1, strap);
+	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
+		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+		return 0;
+	}
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* The ocotea board is always configured as host. */
+	return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return (ctrlc());
+}
+#endif
diff --git a/board/amcc/yellowstone/u-boot.lds b/board/amcc/taishan/u-boot.lds
index a0ba44d..664716e 100644
--- a/board/amcc/yellowstone/u-boot.lds
+++ b/board/amcc/taishan/u-boot.lds
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2002
+ * (C) Copyright 2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -67,7 +67,7 @@ SECTIONS
     /* the sector layout of our flash chips!	XXX FIXME XXX	*/
 
     cpu/ppc4xx/start.o	(.text)
-    board/amcc/yellowstone/init.o	(.text)
+    board/amcc/taishan/init.o	(.text)
     cpu/ppc4xx/kgdb.o	(.text)
     cpu/ppc4xx/traps.o	(.text)
     cpu/ppc4xx/interrupts.o	(.text)
diff --git a/board/amcc/taishan/update.c b/board/amcc/taishan/update.c
new file mode 100644
index 0000000..ed2c196
--- /dev/null
+++ b/board/amcc/taishan/update.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+#if defined(CONFIG_TAISHAN)
+
+const uchar bootstrap_buf[16] = {
+	0x86,
+	0x78,
+	0xc1,
+	0xa6,
+	0x09,
+	0x67,
+	0x04,
+	0x63,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00,
+	0x00
+};
+
+static int update_boot_eeprom(void)
+{
+	ulong len = 0x10;
+	uchar chip = CFG_BOOTSTRAP_IIC_ADDR;
+	uchar *pbuf = (uchar *)bootstrap_buf;
+	int ii, jj;
+
+	for (ii = 0; ii < len; ii++) {
+		if (i2c_write(chip, ii, 1, &pbuf[ii], 1) != 0) {
+			printf("i2c_write failed\n");
+			return -1;
+		}
+
+		/* wait 10ms */
+		for (jj = 0; jj < 10; jj++)
+			udelay(1000);
+	}
+	return 0;
+}
+
+int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	return update_boot_eeprom();
+}
+
+U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom,
+	   "update_boot_eeprom  - update bootstrap eeprom content\n", NULL);
+#endif
diff --git a/board/amcc/yellowstone/init.S b/board/amcc/yellowstone/init.S
deleted file mode 100644
index 425ad08..0000000
--- a/board/amcc/yellowstone/init.S
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K	    0x00000000
-#define SZ_4K	    0x00000010
-#define SZ_16K	    0x00000020
-#define SZ_64K	    0x00000030
-#define SZ_256K	    0x00000040
-#define SZ_1M	    0x00000050
-#define SZ_8M       0x00000060
-#define SZ_16M	    0x00000070
-#define SZ_256M	    0x00000090
-
-/* Storage attributes */
-#define SA_W	    0x00000800	    /* Write-through */
-#define SA_I	    0x00000400	    /* Caching inhibited */
-#define SA_M	    0x00000200	    /* Memory coherence */
-#define SA_G	    0x00000100	    /* Guarded */
-#define SA_E	    0x00000080	    /* Endian */
-
-/* Access control */
-#define AC_X	    0x00000024	    /* Execute */
-#define AC_W	    0x00000012	    /* Write */
-#define AC_R	    0x00000009	    /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)		((e) & 0xfffffc00)
-#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)		( (a)&0x00000fbf )
-
-#define tlbtab_start\
-	mflr    r1  ;\
-	bl 0f	    ;
-
-#define tlbtab_end\
-	.long 0, 0, 0	;   \
-0:	mflr    r0	;   \
-	mtlr    r1	;   \
-	blr		;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-
-    .section .bootpg,"ax"
-    .globl tlbtab
-
-tlbtab:
-    tlbtab_start
-
-    /*
-     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-     * speed up boot process. It is patched after relocation to enable SA_I
-     */
-    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
-
-    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
-
-    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
-
-    /* PCI */
-    tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
-
-    /* USB 2.0 Device */
-    tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
-
-    tlbtab_end
diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c
deleted file mode 100644
index 92dc9d4..0000000
--- a/board/amcc/yellowstone/yellowstone.c
+++ /dev/null
@@ -1,554 +0,0 @@
-/*
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <ppc4xx.h>
-#include <asm/processor.h>
-#include <spd_sdram.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-int board_early_init_f(void)
-{
-	register uint reg;
-
-	/*--------------------------------------------------------------------
-	 * Setup the external bus controller/chip selects
-	 *-------------------------------------------------------------------*/
-	mtdcr(ebccfga, xbcfg);
-	reg = mfdcr(ebccfgd);
-	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
-
-	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */
-	mtebc(pb0cr, 0xfc0da000);	/* BAS=0xfc0 64MB r/w 16-bit */
-
-	mtebc(pb1ap, 0x00000000);
-	mtebc(pb1cr, 0x00000000);
-
-	mtebc(pb2ap, 0x04814500);
-	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */
-
-	mtebc(pb3ap, 0x00000000);
-	mtebc(pb3cr, 0x00000000);
-
-	mtebc(pb4ap, 0x00000000);
-	mtebc(pb4cr, 0x00000000);
-
-	mtebc(pb5ap, 0x00000000);
-	mtebc(pb5cr, 0x00000000);
-
-	/*--------------------------------------------------------------------
-	 * Setup the GPIO pins
-	 *-------------------------------------------------------------------*/
-	/*CPLD cs */
-	/*setup Address lines for flash size 64Meg. */
-	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
-
-	/*setup emac */
-	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
-	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
-	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
-
-	/*UART1 */
-	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
-	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
-	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
-
-	/* external interrupts IRQ0...3 */
-	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
-	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
-	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
-
-#if 0 /* test-only */
-	/*setup USB 2.0 */
-	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
-	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
-	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
-	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
-	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
-#endif
-
-	/*--------------------------------------------------------------------
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 *-------------------------------------------------------------------*/
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-	mtdcr(uic0er, 0x00000000);	/* disable all */
-	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
-	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic0sr, 0xffffffff);	/* clear all */
-
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-	mtdcr(uic1er, 0x00000000);	/* disable all */
-	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(uic1sr, 0xffffffff);	/* clear all */
-
-	/*--------------------------------------------------------------------
-	 * Setup other serial configuration
-	 *-------------------------------------------------------------------*/
-	mfsdr(sdr_pci0, reg);
-	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
-	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */
-	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */
-
-	/*clear tmrclk divisor */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
-
-	/*enable ethernet */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
-
-#if 0 /* test-only */
-	/*enable usb 1.1 fs device and remove usb 2.0 reset */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
-#endif
-
-	/*get rid of flash write protect */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
-
-	return 0;
-}
-
-int misc_init_r (void)
-{
-	uint pbcr;
-	int size_val = 0;
-
-	/* Re-do sizing to get full correct info */
-	mtdcr(ebccfga, pb0cr);
-	pbcr = mfdcr(ebccfgd);
-	switch (gd->bd->bi_flashsize) {
-	case 1 << 20:
-		size_val = 0;
-		break;
-	case 2 << 20:
-		size_val = 1;
-		break;
-	case 4 << 20:
-		size_val = 2;
-		break;
-	case 8 << 20:
-		size_val = 3;
-		break;
-	case 16 << 20:
-		size_val = 4;
-		break;
-	case 32 << 20:
-		size_val = 5;
-		break;
-	case 64 << 20:
-		size_val = 6;
-		break;
-	case 128 << 20:
-		size_val = 7;
-		break;
-	}
-	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-	mtdcr(ebccfga, pb0cr);
-	mtdcr(ebccfgd, pbcr);
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char *s = getenv("serial#");
-
-	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
-	if (s != NULL) {
-		puts(", serial# ");
-		puts(s);
-	}
-	putc('\n');
-
-	return (0);
-}
-
-/*************************************************************************
- *  sdram_init -- doesn't use serial presence detect.
- *
- *  Assumes:    256 MB, ECC, non-registered
- *              PLB @ 133 MHz
- *
- ************************************************************************/
-#define NUM_TRIES 64
-#define NUM_READS 10
-
-void sdram_tr1_set(int ram_address, int* tr1_value)
-{
-	int i;
-	int j, k;
-	volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
-	int first_good = -1, last_bad = 0x1ff;
-
-	unsigned long test[NUM_TRIES] = {
-		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
-		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
-		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
-		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
-		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
-		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
-		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
-		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
-		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
-		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
-		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
-		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
-		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
-		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
-
-	/* go through all possible SDRAM0_TR1[RDCT] values */
-	for (i=0; i<=0x1ff; i++) {
-		/* set the current value for TR1 */
-		mtsdram(mem_tr1, (0x80800800 | i));
-
-		/* write values */
-		for (j=0; j<NUM_TRIES; j++) {
-			ram_pointer[j] = test[j];
-
-			/* clear any cache at ram location */
-			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-		}
-
-		/* read values back */
-		for (j=0; j<NUM_TRIES; j++) {
-			for (k=0; k<NUM_READS; k++) {
-				/* clear any cache at ram location */
-				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-
-				if (ram_pointer[j] != test[j])
-					break;
-			}
-
-			/* read error */
-			if (k != NUM_READS) {
-				break;
-			}
-		}
-
-		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
-		if (j == NUM_TRIES) {
-			if (first_good == -1)
-				first_good = i;		/* found beginning of window */
-		} else { /* bad read */
-			/* if we have not had a good read then don't care */
-			if(first_good != -1) {
-				/* first failure after a good read */
-				last_bad = i-1;
-				break;
-			}
-		}
-	}
-
-	/* return the current value for TR1 */
-	*tr1_value = (first_good + last_bad) / 2;
-}
-
-void sdram_init(void)
-{
-	register uint reg;
-	int tr1_bank1, tr1_bank2;
-
-	/*--------------------------------------------------------------------
-	 * Setup some default
-	 *------------------------------------------------------------------*/
-	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
-	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
-	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
-	mtsdram(mem_clktr, 0x40000000);	/* ?? */
-	mtsdram(mem_wddctr, 0x40000000);	/* ?? */
-
-	/*clear this first, if the DDR is enabled by a debugger
-	  then you can not make changes. */
-	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */
-
-	/*--------------------------------------------------------------------
-	 * Setup for board-specific specific mem
-	 *------------------------------------------------------------------*/
-	/*
-	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
-	 */
-	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
-	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */
-
-	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
-	mtsdram(mem_rtr, 0x04080000);	/* ?? */
-	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
-	mtsdram(mem_cfg0, 0x30000000);	/* Disable EEC */
-	udelay(400);		/* Delay 200 usecs (min)            */
-
-	/*--------------------------------------------------------------------
-	 * Enable the controller, then wait for DCEN to complete
-	 *------------------------------------------------------------------*/
-	mtsdram(mem_cfg0, 0x80000000);	/* Enable */
-
-	for (;;) {
-		mfsdram(mem_mcsts, reg);
-		if (reg & 0x80000000)
-			break;
-	}
-
-	sdram_tr1_set(0x00000000, &tr1_bank1);
-	sdram_tr1_set(0x08000000, &tr1_bank2);
-	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
-}
-
-/*************************************************************************
- *  long int initdram
- *
- ************************************************************************/
-long int initdram(int board)
-{
-	sdram_init();
-	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);	/* return bytes */
-}
-
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-	unsigned long *mem = (unsigned long *)0;
-	const unsigned long kend = (1024 / sizeof(unsigned long));
-	unsigned long k, n;
-
-	mtmsr(0);
-
-	for (k = 0; k < CFG_KBYTES_SDRAM;
-	     ++k, mem += (1024 / sizeof(unsigned long))) {
-		if ((k & 1023) == 0) {
-			printf("%3d MB\r", k / 1024);
-		}
-
-		memset(mem, 0xaaaaaaaa, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0xaaaaaaaa) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-
-		memset(mem, 0x55555555, 1024);
-		for (n = 0; n < kend; ++n) {
-			if (mem[n] != 0x55555555) {
-				printf("SDRAM test fails at: %08x\n",
-				       (uint) & mem[n]);
-				return 1;
-			}
-		}
-	}
-	printf("SDRAM test passes\n");
-	return 0;
-}
-#endif
-
-/*************************************************************************
- *  pci_pre_init
- *
- *  This routine is called just prior to registering the hose and gives
- *  the board the opportunity to check things. Returning a value of zero
- *  indicates that things are bad & PCI initialization should be aborted.
- *
- *	Different boards may wish to customize the pci controller structure
- *	(add regions, override default access routines, etc) or perform
- *	certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
-int pci_pre_init(struct pci_controller *hose)
-{
-	unsigned long addr;
-
-	/*-------------------------------------------------------------------------+
-	  | Set priority for all PLB3 devices to 0.
-	  | Set PLB3 arbiter to fair mode.
-	  +-------------------------------------------------------------------------*/
-	mfsdr(sdr_amp1, addr);
-	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
-	addr = mfdcr(plb3_acr);
-	mtdcr(plb3_acr, addr | 0x80000000);
-
-	/*-------------------------------------------------------------------------+
-	  | Set priority for all PLB4 devices to 0.
-	  +-------------------------------------------------------------------------*/
-	mfsdr(sdr_amp0, addr);
-	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
-	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
-	mtdcr(plb4_acr, addr);
-
-	/*-------------------------------------------------------------------------+
-	  | Set Nebula PLB4 arbiter to fair mode.
-	  +-------------------------------------------------------------------------*/
-	/* Segment0 */
-	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
-	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
-	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
-	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
-	mtdcr(plb0_acr, addr);
-
-	/* Segment1 */
-	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
-	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
-	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
-	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
-	mtdcr(plb1_acr, addr);
-
-	return 1;
-}
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
-
-/*************************************************************************
- *  pci_target_init
- *
- *	The bootstrap configuration provides default settings for the pci
- *	inbound map (PIM). But the bootstrap config choices are limited and
- *	may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-	/*--------------------------------------------------------------------------+
-	 * Set up Direct MMIO registers
-	 *--------------------------------------------------------------------------*/
-	/*--------------------------------------------------------------------------+
-	  | PowerPC440 EP PCI Master configuration.
-	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
-	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
-	  |   Use byte reversed out routines to handle endianess.
-	  | Make this region non-prefetchable.
-	  +--------------------------------------------------------------------------*/
-	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
-
-	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
-
-	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
-	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
-	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
-
-	/*--------------------------------------------------------------------------+
-	 * Set up Configuration registers
-	 *--------------------------------------------------------------------------*/
-
-	/* Program the board's subsystem id/vendor id */
-	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
-
-	/* Configure command register as bus master */
-	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
-	/* 240nS PCI clock */
-	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
-	/* No error reporting */
-	pci_write_config_word(0, PCI_ERREN, 0);
-
-	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-
-/*************************************************************************
- *  pci_master_init
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
-	unsigned short temp_short;
-
-	/*--------------------------------------------------------------------------+
-	  | Write the PowerPC440 EP PCI Configuration regs.
-	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
-	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
-	  +--------------------------------------------------------------------------*/
-	pci_read_config_word(0, PCI_COMMAND, &temp_short);
-	pci_write_config_word(0, PCI_COMMAND,
-			      temp_short | PCI_COMMAND_MASTER |
-			      PCI_COMMAND_MEMORY);
-}
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
-
-/*************************************************************************
- *  is_pci_host
- *
- *	This routine is called to determine if a pci scan should be
- *	performed. With various hardware environments (especially cPCI and
- *	PPMC) it's insufficient to depend on the state of the arbiter enable
- *	bit in the strap register, or generic host/adapter assumptions.
- *
- *	Rather than hard-code a bad assumption in the general 440 code, the
- *	440 pci code requires the board to decide at runtime.
- *
- *	Return 0 for adapter mode, non-zero for host (monarch) mode.
- *
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
-	/* Bamboo is always configured as host. */
-	return (1);
-}
-#endif				/* defined(CONFIG_PCI) */
-
-/*************************************************************************
- *  hw_watchdog_reset
- *
- *	This routine is called to reset (keep alive) the watchdog timer
- *
- ************************************************************************/
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
-
-}
-#endif
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 7f2e718..c2e12ba 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -39,24 +39,6 @@ int board_early_init_f(void)
 	reg = mfdcr(ebccfgd);
 	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
 
-	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */
-	mtebc(pb0cr, 0xfc0da000);	/* BAS=0xfc0 64MB r/w 16-bit */
-
-	mtebc(pb1ap, 0x00000000);
-	mtebc(pb1cr, 0x00000000);
-
-	mtebc(pb2ap, 0x04814500);
-	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */
-
-	mtebc(pb3ap, 0x00000000);
-	mtebc(pb3cr, 0x00000000);
-
-	mtebc(pb4ap, 0x00000000);
-	mtebc(pb4cr, 0x00000000);
-
-	mtebc(pb5ap, 0x00000000);
-	mtebc(pb5cr, 0x00000000);
-
 	/*--------------------------------------------------------------------
 	 * Setup the GPIO pins
 	 *-------------------------------------------------------------------*/
@@ -83,12 +65,14 @@ int board_early_init_f(void)
 	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
 	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
 
+#ifdef CONFIG_440EP
 	/*setup USB 2.0 */
 	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
 	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
 	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
 	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
 	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+#endif
 
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
@@ -123,8 +107,10 @@ int board_early_init_f(void)
 	/*enable ethernet */
 	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
 
+#ifdef CONFIG_440EP
 	/*enable usb 1.1 fs device and remove usb 2.0 reset */
 	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+#endif
 
 	/*get rid of flash write protect */
 	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
@@ -186,8 +172,19 @@ int misc_init_r (void)
 int checkboard(void)
 {
 	char *s = getenv("serial#");
+	u8 rev;
+	u8 val;
 
+#ifdef CONFIG_440EP
 	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
+#else
+	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
+#endif
+
+	rev = *(u8 *)(CFG_CPLD + 0);
+	val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
+
 	if (s != NULL) {
 		puts(", serial# ");
 		puts(s);
@@ -548,3 +545,9 @@ void hw_watchdog_reset(void)
 
 }
 #endif
+
+void board_reset(void)
+{
+	/* give reset to BCSR */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
+}
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index c9eca68..c92dcf7 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
  *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -19,56 +22,10 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-/* port to AMCC 440SPE evaluatioon board - SG April 12,2005  */
 
 #include <ppc_asm.tmpl>
 #include <config.h>
-
-/* General */
-#define TLB_VALID   0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K	0x00000000
-#define SZ_4K	0x00000010
-#define SZ_16K	0x00000020
-#define SZ_64K	0x00000030
-#define SZ_256K	0x00000040
-#define SZ_1M	0x00000050
-#define SZ_16M	0x00000070
-#define SZ_256M	0x00000090
-
-/* Storage attributes */
-#define SA_W	0x00000800	/* Write-through */
-#define SA_I	0x00000400	/* Caching inhibited */
-#define SA_M	0x00000200	/* Memory coherence */
-#define SA_G	0x00000100	/* Guarded */
-#define SA_E	0x00000080	/* Endian */
-
-/* Access control */
-#define AC_X	0x00000024	/* Execute */
-#define AC_W	0x00000012	/* Write */
-#define AC_R	0x00000009	/* Read */
-
-/* Some handy macros */
-
-#define EPN(e)		((e) & 0xfffffc00)
-#define TLB0(epn,sz)	((EPN((epn)) | (sz) | TLB_VALID ))
-#define TLB1(rpn,erpn)	(((rpn) & 0xfffffc00) | (erpn))
-#define TLB2(a)		((a) & 0x00000fbf)
-
-#define tlbtab_start\
-	mflr	r1	;\
-	bl	0f	;
-
-#define tlbtab_end\
-	.long 0, 0, 0	;\
-0:	mflr	r0	;\
-	mtlr	r1	;\
-	blr		;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+#include <asm-ppc/mmu.h>
 
 /**************************************************************************
  * TLB TABLE
@@ -89,12 +46,18 @@
 	.globl tlbtabA
 tlbtabA:
 	tlbtab_start
-	tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
 
-	tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
 
 	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
 	tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
@@ -126,12 +89,18 @@ tlbtabA:
 	.globl tlbtabB
 tlbtabB:
 	tlbtab_start
-	tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
 
-	tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
 
 	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
 	tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index e9b34dd..90eaab1 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -44,8 +44,6 @@ int compare_to_true(char *str );
 char *remove_l_w_space(char *in_str );
 char *remove_t_w_space(char *in_str );
 int get_console_port(void);
-unsigned long ppcMfcpr(unsigned long cpr_reg);
-unsigned long ppcMfsdr(unsigned long sdr_reg);
 
 int ppc440spe_init_pcie_rootport(int port);
 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
@@ -221,7 +219,7 @@ int board_early_init_f (void)
 	 |
 	 +-------------------------------------------------------------------*/
 	/* Read Pin Strap Register in PPC440SP */
-	sdr0_pinstp = ppcMfsdr(SDR0_PINSTP);
+	mfsdr(SDR0_PINSTP, sdr0_pinstp);
 	bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
 
 	switch (bootstrap_settings) {
@@ -246,7 +244,7 @@ int board_early_init_f (void)
 			 * Boot Settings in IIC EEprom address 0x50 or 0x54
 			 * Read Serial Device Strap Register1 in PPC440SPe
 			 */
-			sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1);
+			mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
 			boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
 			ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
 
@@ -564,277 +562,6 @@ int checkboard (void)
 	return 0;
 }
 
-static long int yucca_probe_for_dimms(void)
-{
-	int 	dimm_installed[MAXDIMMS];
-	int	dimm_num, result;
-	int	dimms_found = 0;
-	uchar	dimm_addr = IIC0_DIMM0_ADDR;
-	uchar   dimm_spd_data[MAX_SPD_BYTES];
-
-	for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
-		/* check if there is a chip at the dimm address	*/
-		switch (dimm_num) {
-			case 0:
-				dimm_addr = IIC0_DIMM0_ADDR;
-				break;
-			case 1:
-				dimm_addr = IIC0_DIMM1_ADDR;
-				break;
-		}
-
-		result = i2c_probe(dimm_addr);
-
-		memset(dimm_spd_data, 0, MAX_SPD_BYTES * sizeof(char));
-		if (result == 0) {
-			/* read first byte of SPD data, if there is any data */
-			result = i2c_read(dimm_addr, 0, 1, dimm_spd_data, 1);
-
-			if (result == 0) {
-				result = dimm_spd_data[0];
-				result = result > MAX_SPD_BYTES ?
-						MAX_SPD_BYTES : result;
-				result = i2c_read(dimm_addr, 0, 1,
-							dimm_spd_data, result);
-			}
-		}
-
-		if ((result == 0) &&
-		    (dimm_spd_data[64] == MICRON_SPD_JEDEC_ID)) {
-			dimm_installed[dimm_num] = TRUE;
-			dimms_found++;
-			debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
-		} else {
-			dimm_installed[dimm_num] = FALSE;
-			debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
-		}
-	}
-
-	if (dimms_found == 0) {
-		printf("ERROR - No memory installed.  Install a DDR-SDRAM DIMM.\n\n");
-		hang();
-	}
-
-	if (dimm_installed[0] != TRUE) {
-		printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
-		printf("        Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
-		hang();
-	}
-
-	return dimms_found;
-}
-
-/*************************************************************************
- * init SDRAM controller with fixed value
- * the initialization values are for 2x MICRON DDR2
- * PN: MT18HTF6472DY-53EB2
- * 512MB, DDR2, 533, CL4, ECC, REG
- ************************************************************************/
-static long int fixed_sdram(void)
-{
-	long int yucca_dimms = 0;
-
-	yucca_dimms = yucca_probe_for_dimms();
-
-	/* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT	*/
-	mtdcr( 0x10, 0x00000021 );
-	mtdcr( 0x11, 0x84000000 );
-
-	/* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2	*/
-	mtdcr( 0x10, 0x00000020 );
-	mtdcr( 0x11, 0x2D122000 );
-
-	/* SET MCIF0_CODT   Die Termination On	*/
-	mtdcr( 0x10, 0x00000026 );
-	if (yucca_dimms == 2)
-		mtdcr( 0x11, 0x2A800021 );
-	else if (yucca_dimms == 1)
-		mtdcr( 0x11, 0x02800021 );
-
-	/* On-Die Termination for Bank 0	*/
-	mtdcr( 0x10, 0x00000022 );
-	if (yucca_dimms == 2)
-		mtdcr( 0x11, 0x18000000 );
-	else if (yucca_dimms == 1)
-		mtdcr( 0x11, 0x06000000 );
-
-	/*	On-Die Termination for Bank 1	*/
-	mtdcr( 0x10, 0x00000023 );
-	if (yucca_dimms == 2)
-		mtdcr( 0x11, 0x18000000 );
-	else if (yucca_dimms == 1)
-		mtdcr( 0x11, 0x01800000 );
-
-	/*	On-Die Termination for Bank 2	*/
-	mtdcr( 0x10, 0x00000024 );
-	if (yucca_dimms == 2)
-		mtdcr( 0x11, 0x01800000 );
-	else if (yucca_dimms == 1)
-		mtdcr( 0x11, 0x00000000 );
-
-	/*	On-Die Termination for Bank 3	*/
-	mtdcr( 0x10, 0x00000025 );
-	if (yucca_dimms == 2)
-		mtdcr( 0x11, 0x01800000 );
-	else if (yucca_dimms == 1)
-		mtdcr( 0x11, 0x00000000 );
-
-	/* Refresh Time register (0x30) Refresh every 7.8125uS	*/
-	mtdcr( 0x10, 0x00000030 );
-	mtdcr( 0x11, 0x08200000 );
-
-	/* SET MCIF0_MMODE  	 CL 4	*/
-	mtdcr( 0x10, 0x00000088 );
-	mtdcr( 0x11, 0x00000642 );
-
-	/* MCIF0_MEMODE	*/
-	mtdcr( 0x10, 0x00000089 );
-	mtdcr( 0x11, 0x00000004 );
-
-	/*SET MCIF0_MB0CF 	*/
-	mtdcr( 0x10, 0x00000040 );
-	mtdcr( 0x11, 0x00000201 );
-
-	/* SET MCIF0_MB1CF 	*/
-	mtdcr( 0x10, 0x00000044 );
-	mtdcr( 0x11, 0x00000201 );
-
-	/* SET MCIF0_MB2CF 	*/
-	mtdcr( 0x10, 0x00000048 );
-	if (yucca_dimms == 2)
-		mtdcr( 0x11, 0x00000201 );
-	else if (yucca_dimms == 1)
-		mtdcr( 0x11, 0x00000000 );
-
-	/* SET MCIF0_MB3CF 	*/
-	mtdcr( 0x10, 0x0000004c );
-	if (yucca_dimms == 2)
-		mtdcr( 0x11, 0x00000201 );
-	else if (yucca_dimms == 1)
-		mtdcr( 0x11, 0x00000000 );
-
-	/* SET MCIF0_INITPLR0  # NOP		*/
-	mtdcr( 0x10, 0x00000050 );
-	mtdcr( 0x11, 0xB5380000 );
-
-	/* SET MCIF0_INITPLR1  # PRE		*/
-	mtdcr( 0x10, 0x00000051 );
-	mtdcr( 0x11, 0x82100400 );
-
-	/* SET MCIF0_INITPLR2  # EMR2		*/
-	mtdcr( 0x10, 0x00000052 );
-	mtdcr( 0x11, 0x80820000 );
-
-	/* SET MCIF0_INITPLR3  # EMR3		*/
-	mtdcr( 0x10, 0x00000053 );
-	mtdcr( 0x11, 0x80830000 );
-
-	/* SET MCIF0_INITPLR4  # EMR DLL ENABLE	*/
-	mtdcr( 0x10, 0x00000054 );
-	mtdcr( 0x11, 0x80810000 );
-
-	/* SET MCIF0_INITPLR5  # MR DLL RESET	*/
-	mtdcr( 0x10, 0x00000055 );
-	mtdcr( 0x11, 0x80800542 );
-
-	/* SET MCIF0_INITPLR6  # PRE		*/
-	mtdcr( 0x10, 0x00000056 );
-	mtdcr( 0x11, 0x82100400 );
-
-	/* SET MCIF0_INITPLR7  # Refresh	*/
-	mtdcr( 0x10, 0x00000057 );
-	mtdcr( 0x11, 0x8A080000 );
-
-	/* SET MCIF0_INITPLR8  # Refresh	*/
-	mtdcr( 0x10, 0x00000058 );
-	mtdcr( 0x11, 0x8A080000 );
-
-	/* SET MCIF0_INITPLR9  # Refresh	*/
-	mtdcr( 0x10, 0x00000059 );
-	mtdcr( 0x11, 0x8A080000 );
-
-	/* SET MCIF0_INITPLR10 # Refresh	*/
-	mtdcr( 0x10, 0x0000005A );
-	mtdcr( 0x11, 0x8A080000 );
-
-	/* SET MCIF0_INITPLR11 # MR		*/
-	mtdcr( 0x10, 0x0000005B );
-	mtdcr( 0x11, 0x80800442 );
-
-	/* SET MCIF0_INITPLR12 # EMR OCD Default*/
-	mtdcr( 0x10, 0x0000005C );
-	mtdcr( 0x11, 0x80810380 );
-
-	/* SET MCIF0_INITPLR13 # EMR OCD Exit	*/
-	mtdcr( 0x10, 0x0000005D );
-	mtdcr( 0x11, 0x80810000 );
-
-	/* 0x80: Adv Addr clock by 180 deg	*/
-	mtdcr( 0x10, 0x00000080 );
-	mtdcr( 0x11, 0x80000000 );
-
-	/* 0x21: Exit self refresh, set DC_EN	*/
-	mtdcr( 0x10, 0x00000021 );
-	mtdcr( 0x11, 0x28000000 );
-
-	/* 0x81: Write DQS Adv 90 + Fractional DQS Delay	*/
-	mtdcr( 0x10, 0x00000081 );
-	mtdcr( 0x11, 0x80000800 );
-
-	/* MCIF0_SDTR1	*/
-	mtdcr( 0x10, 0x00000085 );
-	mtdcr( 0x11, 0x80201000 );
-
-	/* MCIF0_SDTR2	*/
-	mtdcr( 0x10, 0x00000086 );
-	mtdcr( 0x11, 0x42103242 );
-
-	/* MCIF0_SDTR3	*/
-	mtdcr( 0x10, 0x00000087 );
-	mtdcr( 0x11, 0x0C100D14 );
-
-	/* SET MQ0_B0BAS  base addr 00000000 / 256MB	*/
-	mtdcr( 0x40, 0x0000F800 );
-
-	/* SET MQ0_B1BAS  base addr 10000000 / 256MB	*/
-	mtdcr( 0x41, 0x0400F800 );
-
-	/* SET MQ0_B2BAS  base addr 20000000 / 256MB	*/
-	if (yucca_dimms == 2)
-		mtdcr( 0x42, 0x0800F800 );
-	else if (yucca_dimms == 1)
-		mtdcr( 0x42, 0x00000000 );
-
-	/* SET MQ0_B3BAS  base addr 30000000 / 256MB	*/
-	if (yucca_dimms == 2)
-		mtdcr( 0x43, 0x0C00F800 );
-	else if (yucca_dimms == 1)
-		mtdcr( 0x43, 0x00000000 );
-
-	/* SDRAM_RQDC	*/
-	mtdcr( 0x10, 0x00000070 );
-	mtdcr( 0x11, 0x8000003F );
-
-	/* SDRAM_RDCC	*/
-	mtdcr( 0x10, 0x00000078 );
-	mtdcr( 0x11, 0x80000000 );
-
-	/* SDRAM_RFDC	*/
-	mtdcr( 0x10, 0x00000074 );
-	mtdcr( 0x11, 0x00000220 );
-
-	return (yucca_dimms * 512) << 20;
-}
-
-long int initdram (int board_type)
-{
-	long dram_size = 0;
-
-	dram_size = fixed_sdram();
-
-	return dram_size;
-}
-
 #if defined(CFG_DRAM_TEST)
 int testdram (void)
 {
@@ -1267,42 +994,3 @@ int onboard_pci_arbiter_selected(int core_pci)
 #endif
 	return (BOARD_OPTION_NOT_SELECTED);
 }
-
-/*---------------------------------------------------------------------------+
- | ppcMfcpr.
- +---------------------------------------------------------------------------*/
-unsigned long ppcMfcpr(unsigned long cpr_reg)
-{
-	unsigned long msr;
-	unsigned long cpr_cfgaddr_temp;
-	unsigned long cpr_value;
-
-	msr = (mfmsr () & ~(MSR_EE));
-	cpr_cfgaddr_temp =  mfdcr(CPR0_CFGADDR);
-	mtdcr(CPR0_CFGADDR, cpr_reg);
-	cpr_value =  mfdcr(CPR0_CFGDATA);
-	mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp);
-	mtmsr(msr);
-
-	return (cpr_value);
-}
-
-/*----------------------------------------------------------------------------+
-| Indirect Access of the System DCR's (SDR)
-| ppcMfsdr
-+----------------------------------------------------------------------------*/
-unsigned long ppcMfsdr(unsigned long sdr_reg)
-{
-	unsigned long msr;
-	unsigned long sdr_cfgaddr_temp;
-	unsigned long sdr_value;
-
-	msr = (mfmsr () & ~(MSR_EE));
-	sdr_cfgaddr_temp =  mfdcr(SDR0_CFGADDR);
-	mtdcr(SDR0_CFGADDR, sdr_reg);
-	sdr_value =  mfdcr(SDR0_CFGDATA);
-	mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp);
-	mtmsr(msr);
-
-	return (sdr_value);
-}
diff --git a/board/stamp/Makefile b/board/bf533-ezkit/Makefile
index ee52007..4fe7d78 100644
--- a/board/stamp/Makefile
+++ b/board/bf533-ezkit/Makefile
@@ -1,7 +1,7 @@
 #
 # U-boot - Makefile
 #
-# Copyright (c) 2005 blackfin.uclinux.org
+# Copyright (c) 2007 Analog Device Inc.
 #
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -25,41 +25,28 @@
 # MA 02111-1307 USA
 #
 
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
 include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o stamp.o
+COBJS	:= $(BOARD).o flash.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+u-boot.lds: u-boot.lds.S
+	$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+	mv -f $@.tmp $@
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
 
 #########################################################################
 
diff --git a/board/ezkit533/ezkit533.c b/board/bf533-ezkit/bf533-ezkit.c
index 8d6c8de..feaeb00 100644
--- a/board/ezkit533/ezkit533.c
+++ b/board/bf533-ezkit/bf533-ezkit.c
@@ -30,24 +30,28 @@
 #include "psd4256.h"
 #endif
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
+#if (BFIN_CPU == ADSP_BF531)
+	printf("CPU:   ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
+#elif (BFIN_CPU == ADSP_BF532)
+	printf("CPU:   ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28);
+#else
 	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+#endif
 	printf("Board: ADI BF533 EZ-Kit Lite board\n");
 	printf("       Support: http://blackfin.uclinux.org/\n");
-	printf("       Richard Klingler <richard@uclinux.net>\n");
 	return 0;
 }
 
 long int initdram(int board_type)
 {
+	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
 	int brate;
 	char *tmp = getenv("baudrate");
 	brate = simple_strtoul(tmp, NULL, 16);
-	printf("Serial Port initialized with Baud rate = %x\n",brate);
+	printf("Serial Port initialized with Baud rate = %x\n", brate);
 	printf("SDRAM attributes:\n");
 	printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
 	       "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
@@ -64,9 +68,13 @@ long int initdram(int board_type)
 /* miscellaneous platform dependent initialisations */
 int misc_init_r(void)
 {
-	/* Set direction bits for Video en/decoder reset as output	*/
-	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST;
-	/* Deactivate Video en/decoder reset lines			*/
-	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST;
+	/* Set direction bits for Video en/decoder reset as output      */
+	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) =
+	    PSDA_VDEC_RST | PSDA_VENC_RST;
+	/* Deactivate Video en/decoder reset lines                      */
+	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) =
+	    PSDA_VDEC_RST | PSDA_VENC_RST;
+
+	return 0;
 }
 #endif
diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk
new file mode 100644
index 0000000..f39be5f
--- /dev/null
+++ b/board/bf533-ezkit/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
+#  256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
+TEXT_BASE = 0x01FC0000
diff --git a/board/ezkit533/flash-defines.h b/board/bf533-ezkit/flash-defines.h
index 8f9dff5..e211918 100644
--- a/board/ezkit533/flash-defines.h
+++ b/board/bf533-ezkit/flash-defines.h
@@ -52,17 +52,13 @@
 #define CFG_FLASH0_BASE		0x20000000
 #define RESET_VAL		0xF0
 
-
-asm("#define FLASH_START_L 0x0000");
-asm("#define FLASH_START_H 0x2000");
-
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
 
 int get_codes(void);
 int poll_toggle_bit(long lOffset);
 void reset_flash(void);
 int erase_flash(void);
-int erase_block_flash(int,unsigned long);
+int erase_block_flash(int, unsigned long);
 void unlock_flash(long lOffset);
 int write_data(long lStart, long lCount, long lStride, int *pnData);
 int FillData(long lStart, long lCount, long lStride, int *pnData);
diff --git a/board/ezkit533/flash.c b/board/bf533-ezkit/flash.c
index b0a0796..067a260 100644
--- a/board/ezkit533/flash.c
+++ b/board/bf533-ezkit/flash.c
@@ -26,6 +26,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm/io.h>
 #include "flash-defines.h"
 
 void flash_reset(void)
@@ -33,14 +34,13 @@ void flash_reset(void)
 	reset_flash();
 }
 
-unsigned long flash_get_size(ulong baseaddr, flash_info_t * info,
-			     int bank_flag)
+unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
 {
 	int id = 0, i = 0;
 	static int FlagDev = 1;
 
 	id = get_codes();
-	if(FlagDev)	{
+	if (FlagDev) {
 #ifdef DEBUG
 		printf("Device ID of the Flash is %x\n", id);
 #endif
@@ -100,10 +100,11 @@ unsigned long flash_init(void)
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
 		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0 >> 20);
+		       size_b0, size_b0 >> 20);
 	}
 
-	(void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]);
+	(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH0_BASE,
+			    (flash_info[0].start[2] - 1), &flash_info[0]);
 
 	return (size_b0 + size_b1 + size_b2);
 }
@@ -122,15 +123,14 @@ void flash_print_info(flash_info_t * info)
 		printf("ST Microelectronics ");
 		break;
 	default:
-		printf("Unknown Vendor ");
+		printf("Unknown Vendor: (0x%08X) ", info->flash_id);
 		break;
 	}
 	for (i = 0; i < info->sector_count; ++i) {
 		if ((i % 5) == 0)
 			printf("\n   ");
 		printf(" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
 	}
 	printf("\n");
 	return;
@@ -138,8 +138,8 @@ void flash_print_info(flash_info_t * info)
 
 int flash_erase(flash_info_t * info, int s_first, int s_last)
 {
-	int cnt = 0,i;
-	int prot,sect;
+	int cnt = 0, i;
+	int prot, sect;
 
 	prot = 0;
 	for (sect = s_first; sect <= s_last; ++sect) {
@@ -148,15 +148,16 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 	}
 
 	if (prot)
-		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
 	else
-		printf ("\n");
+		printf("\n");
 
 	cnt = s_last - s_first + 1;
 
 	if (cnt == FLASH_TOT_SECT) {
 		printf("Erasing flash, Please Wait \n");
-		if(erase_flash() < 0) {
+		if (erase_flash() < 0) {
 			printf("Erasing flash failed \n");
 			return FLASH_FAIL;
 		}
@@ -164,7 +165,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 		printf("Erasing Flash locations, Please Wait\n");
 		for (i = s_first; i <= s_last; i++) {
 			if (info->protect[i] == 0) {	/* not protected */
-				if(erase_block_flash(i, info->start[i]) < 0) {
+				if (erase_block_flash(i, info->start[i]) < 0) {
 					printf("Error Sector erasing \n");
 					return FLASH_FAIL;
 				}
@@ -178,13 +179,12 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	int ret;
 
-	ret = write_data(addr, cnt, 1, (int *) src);
-	if(ret == FLASH_FAIL)
+	ret = write_data(addr, cnt, 1, (int *)src);
+	if (ret == FLASH_FAIL)
 		return ERR_NOT_ERASED;
 	return FLASH_SUCCESS;
 }
 
-
 int write_data(long lStart, long lCount, long lStride, int *pnData)
 {
 	long i = 0;
@@ -198,20 +198,23 @@ int write_data(long lStart, long lCount, long lStride, int *pnData)
 
 	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
 		for (iShift = 0, j = 0; (j < iNumWords);
-			j++, ulOffset += (lStride * 2)) {
+		     j++, ulOffset += (lStride * 2)) {
 			if ((ulOffset >= INVALIDLOCNSTART)
-			&& (ulOffset < INVALIDLOCNEND)) {
-				printf("Invalid locations, Try writing to another location \n");
+			    && (ulOffset < INVALIDLOCNEND)) {
+				printf
+				    ("Invalid locations, Try writing to another location \n");
 				return FLASH_FAIL;
 			}
 			get_sector_number(ulOffset, &nSector);
-			read_flash(ulOffset,&d);
-			if(d != 0xffff) {
-				printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset);
+			read_flash(ulOffset, &d);
+			if (d != 0xffff) {
+				printf
+				    ("Flash not erased at offset 0x%x Please erase to reprogram \n",
+				     ulOffset);
 				return FLASH_FAIL;
 			}
 			unlock_flash(ulOffset);
-			if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
+			if (write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
 				printf("Error programming the flash \n");
 				return FLASH_FAIL;
 			}
@@ -220,17 +223,18 @@ int write_data(long lStart, long lCount, long lStride, int *pnData)
 	}
 	if (nLeftover > 0) {
 		if ((ulOffset >= INVALIDLOCNSTART)
-			&& (ulOffset < INVALIDLOCNEND))
-				return FLASH_FAIL;
+		    && (ulOffset < INVALIDLOCNEND))
+			return FLASH_FAIL;
 		get_sector_number(ulOffset, &nSector);
-		read_flash(ulOffset,&d);
-		if(d != 0xffff) {
-			printf("Flash already programmed. Please erase to reprogram \n");
-			printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d);
+		read_flash(ulOffset, &d);
+		if (d != 0xffff) {
+			printf
+			    ("Flash already programmed. Please erase to reprogram \n");
+			printf("uloffset = 0x%x \t d = 0x%x\n", ulOffset, d);
 			return FLASH_FAIL;
 		}
 		unlock_flash(ulOffset);
-		if(write_flash(ulOffset, pnData[i]) < 0) {
+		if (write_flash(ulOffset, pnData[i]) < 0) {
 			printf("Error programming the flash \n");
 			return FLASH_FAIL;
 		}
@@ -252,8 +256,8 @@ int read_data(long ulStart, long lCount, long lStride, int *pnData)
 	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
 		for (iShift = 0, j = 0; j < iNumWords; j += 2) {
 			if ((ulOffset >= INVALIDLOCNSTART)
-				&& (ulOffset < INVALIDLOCNEND))
-					return FLASH_FAIL;
+			    && (ulOffset < INVALIDLOCNEND))
+				return FLASH_FAIL;
 
 			get_sector_number(ulOffset, &nSector);
 			read_flash(ulOffset, &nLow);
@@ -265,8 +269,8 @@ int read_data(long ulStart, long lCount, long lStride, int *pnData)
 	}
 	if (nLeftover > 0) {
 		if ((ulOffset >= INVALIDLOCNSTART)
-			&& (ulOffset < INVALIDLOCNEND))
-				return FLASH_FAIL;
+		    && (ulOffset < INVALIDLOCNEND))
+			return FLASH_FAIL;
 
 		get_sector_number(ulOffset, &nSector);
 		read_flash(ulOffset, &pnData[i]);
@@ -279,10 +283,10 @@ int write_flash(long nOffset, int nValue)
 	long addr;
 
 	addr = (CFG_FLASH_BASE + nOffset);
-	asm("ssync;");
-	*(unsigned volatile short *) addr = nValue;
-	asm("ssync;");
-	if(poll_toggle_bit(nOffset) < 0)
+	sync();
+	*(unsigned volatile short *)addr = nValue;
+	sync();
+	if (poll_toggle_bit(nOffset) < 0)
 		return FLASH_FAIL;
 	return FLASH_SUCCESS;
 }
@@ -294,29 +298,30 @@ int read_flash(long nOffset, int *pnValue)
 
 	if (nOffset != 0x2)
 		reset_flash();
-	asm("ssync;");
-	nValue = *(volatile unsigned short *) addr;
-	asm("ssync;");
+	sync();
+	nValue = *(volatile unsigned short *)addr;
+	sync();
 	*pnValue = nValue;
 	return TRUE;
 }
 
 int poll_toggle_bit(long lOffset)
 {
-	unsigned int u1,u2;
+	unsigned int u1, u2;
 	unsigned long timeout = 0xFFFFFFFF;
-	volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset);
-	while(1) {
-		if(timeout < 0)
+	volatile unsigned long *FB =
+	    (volatile unsigned long *)(0x20000000 + lOffset);
+	while (1) {
+		if (timeout < 0)
 			break;
 		u1 = *(volatile unsigned short *)FB;
 		u2 = *(volatile unsigned short *)FB;
-		if((u1 & 0x0040) == (u2 & 0x0040))
+		if ((u1 & 0x0040) == (u2 & 0x0040))
 			return FLASH_SUCCESS;
-		if((u2 & 0x0020) == 0x0000)
+		if ((u2 & 0x0020) == 0x0000)
 			continue;
 		u1 = *(volatile unsigned short *)FB;
-		if((u2 & 0x0040) == (u1 & 0x0040))
+		if ((u2 & 0x0040) == (u1 & 0x0040))
 			return FLASH_SUCCESS;
 		else {
 			reset_flash();
@@ -325,7 +330,8 @@ int poll_toggle_bit(long lOffset)
 		timeout--;
 	}
 	printf("Time out occured \n");
-	if(timeout <0)	return FLASH_FAIL;
+	if (timeout < 0)
+		return FLASH_FAIL;
 }
 
 void reset_flash(void)
@@ -344,7 +350,7 @@ int erase_flash(void)
 	write_flash(WRITESEQ5, WRITEDATA5);
 	write_flash(WRITESEQ6, WRITEDATA6);
 
-	if(poll_toggle_bit(0x0000) < 0)
+	if (poll_toggle_bit(0x0000) < 0)
 		return FLASH_FAIL;
 
 	write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
@@ -354,7 +360,7 @@ int erase_flash(void)
 	write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
 	write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
 
-	if(poll_toggle_bit(SecFlashASec1Off) < 0)
+	if (poll_toggle_bit(SecFlashASec1Off) < 0)
 		return FLASH_FAIL;
 
 	write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
@@ -364,7 +370,7 @@ int erase_flash(void)
 	write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
 	write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
 
-	if(poll_toggle_bit(PriFlashBOff) <0)
+	if (poll_toggle_bit(PriFlashBOff) < 0)
 		return FLASH_FAIL;
 
 	write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
@@ -374,7 +380,7 @@ int erase_flash(void)
 	write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
 	write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
 
-	if(poll_toggle_bit(SecFlashBOff) < 0)
+	if (poll_toggle_bit(SecFlashBOff) < 0)
 		return FLASH_FAIL;
 
 	return FLASH_SUCCESS;
@@ -397,7 +403,7 @@ int erase_block_flash(int nBlock, unsigned long address)
 
 	write_flash(ulSectorOff, BlockEraseVal);
 
-	if(poll_toggle_bit(ulSectorOff) < 0)
+	if (poll_toggle_bit(ulSectorOff) < 0)
 		return FLASH_FAIL;
 
 	return FLASH_SUCCESS;
@@ -435,34 +441,34 @@ void get_sector_number(long ulOffset, int *pnSector)
 
 	if (ulOffset >= SecFlashAOff) {
 		if ((ulOffset < SecFlashASec1Off)
-			&& (ulOffset < SecFlashASec2Off)) {
-				nSector = SECT32;
+		    && (ulOffset < SecFlashASec2Off)) {
+			nSector = SECT32;
 		} else if ((ulOffset >= SecFlashASec2Off)
-			&& (ulOffset < SecFlashASec3Off)) {
-				nSector = SECT33;
+			   && (ulOffset < SecFlashASec3Off)) {
+			nSector = SECT33;
 		} else if ((ulOffset >= SecFlashASec3Off)
-			&& (ulOffset < SecFlashASec4Off)) {
-				nSector = SECT34;
+			   && (ulOffset < SecFlashASec4Off)) {
+			nSector = SECT34;
 		} else if ((ulOffset >= SecFlashASec4Off)
-			&& (ulOffset < SecFlashAEndOff)) {
-				nSector = SECT35;
+			   && (ulOffset < SecFlashAEndOff)) {
+			nSector = SECT35;
 		}
 	} else if (ulOffset >= SecFlashBOff) {
 		if ((ulOffset < SecFlashBSec1Off)
-			&& (ulOffset < SecFlashBSec2Off)) {
-				nSector = SECT36;
+		    && (ulOffset < SecFlashBSec2Off)) {
+			nSector = SECT36;
 		}
 		if ((ulOffset < SecFlashBSec2Off)
-			&& (ulOffset < SecFlashBSec3Off)) {
-				nSector = SECT37;
+		    && (ulOffset < SecFlashBSec3Off)) {
+			nSector = SECT37;
 		}
 		if ((ulOffset < SecFlashBSec3Off)
-			&& (ulOffset < SecFlashBSec4Off)) {
-				nSector = SECT38;
+		    && (ulOffset < SecFlashBSec4Off)) {
+			nSector = SECT38;
 		}
 		if ((ulOffset < SecFlashBSec4Off)
-			&& (ulOffset < SecFlashBEndOff)) {
-				nSector = SECT39;
+		    && (ulOffset < SecFlashBEndOff)) {
+			nSector = SECT39;
 		}
 	} else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
 		nSector = ulOffset & 0xffff0000;
diff --git a/board/ezkit533/psd4256.h b/board/bf533-ezkit/psd4256.h
index 01f6566..9776516 100644
--- a/board/ezkit533/psd4256.h
+++ b/board/bf533-ezkit/psd4256.h
@@ -49,19 +49,19 @@
  * Flash A Port A Bit definitions
  */
 
-#define	PSDA_PPICLK1	0x20		/* PPI Clock select bit 1		*/
-#define	PSDA_PPICLK0	0x10		/* PPI Clock select bit 0		*/
-#define	PSDA_VDEC_RST	0x08		/* Video decoder reset, 0 = RESET	*/
-#define	PSDA_VENC_RST	0x04		/* Video encoder reset, 0 = RESET	*/
-#define	PSDA_CODEC_RST	0x01		/* Codec reset, 0 = RESET		*/
+#define	PSDA_PPICLK1	0x20	/* PPI Clock select bit 1               */
+#define	PSDA_PPICLK0	0x10	/* PPI Clock select bit 0               */
+#define	PSDA_VDEC_RST	0x08	/* Video decoder reset, 0 = RESET       */
+#define	PSDA_VENC_RST	0x04	/* Video encoder reset, 0 = RESET       */
+#define	PSDA_CODEC_RST	0x01	/* Codec reset, 0 = RESET               */
 
 /*
  * Flash A Port B Bit definitions
  */
 
-#define	PSDA_LED9	0x20		/* LED 9, 1 = LED ON			*/
-#define	PSDA_LED8	0x10		/* LED 8, 1 = LED ON			*/
-#define	PSDA_LED7	0x08		/* LED 7, 1 = LED ON			*/
-#define	PSDA_LED6	0x04		/* LED 6, 1 = LED ON			*/
-#define	PSDA_LED5	0x02		/* LED 5, 1 = LED ON			*/
-#define	PSDA_LED4	0x01		/* LED 4, 1 = LED ON			*/
+#define	PSDA_LED9	0x20	/* LED 9, 1 = LED ON                    */
+#define	PSDA_LED8	0x10	/* LED 8, 1 = LED ON                    */
+#define	PSDA_LED7	0x08	/* LED 7, 1 = LED ON                    */
+#define	PSDA_LED6	0x04	/* LED 6, 1 = LED ON                    */
+#define	PSDA_LED5	0x02	/* LED 5, 1 = LED ON                    */
+#define	PSDA_LED4	0x01	/* LED 4, 1 = LED ON                    */
diff --git a/board/ezkit533/u-boot.lds b/board/bf533-ezkit/u-boot.lds.S
index 10203ff..9742e02 100644
--- a/board/ezkit533/u-boot.lds
+++ b/board/bf533-ezkit/u-boot.lds.S
@@ -1,7 +1,7 @@
 /*
- * U-boot - u-boot.lds
+ * U-boot - u-boot.lds.S
  *
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Device Inc.
  *
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -25,6 +25,8 @@
  * MA 02111-1307 USA
  */
 
+#include <config.h>
+
 OUTPUT_ARCH(bfin)
 SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
 /* Do we need any of these for elf?
@@ -55,6 +57,7 @@ SECTIONS
   .rela.plt      : { *(.rela.plt)	}
   .init          : { *(.init)		}
   .plt : { *(.plt) }
+  . = CFG_MONITOR_BASE;
   .text      :
   {
     /* WARNING - the following is hand-optimized to fit within	*/
@@ -68,10 +71,11 @@ SECTIONS
     cpu/bf533/interrupt.o	(.text)
     cpu/bf533/serial.o		(.text)
     common/dlmalloc.o		(.text)
-    lib_generic/vsprintf.o	(.text)
+/*  lib_blackfin/bf533_string.o	(.text) */
+/*  lib_generic/vsprintf.o	(.text) */
     lib_generic/crc32.o		(.text)
     lib_generic/zlib.o		(.text)
-    board/ezkit533/ezkit533.o		(.text)
+    board/bf533-ezkit/bf533-ezkit.o		(.text)
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/environment.o	(.text)
@@ -119,9 +123,9 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
+  ___u_boot_cmd_start = .;
   .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+  ___u_boot_cmd_end = .;
 
 
   __start___ex_table = .;
diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile
new file mode 100644
index 0000000..8223d59
--- /dev/null
+++ b/board/bf533-stamp/Makefile
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o spi.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+u-boot.lds: u-boot.lds.S
+	$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+	mv -f $@.tmp $@
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/stamp/stamp.c b/board/bf533-stamp/bf533-stamp.c
index 7e3af20..2f6e751 100644
--- a/board/stamp/stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -27,9 +27,8 @@
 
 #include <common.h>
 #include <asm/mem_init.h>
-#include "stamp.h"
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <asm/io.h>
+#include "bf533-stamp.h"
 
 #define STATUS_LED_OFF 0
 #define STATUS_LED_ON  1
@@ -40,42 +39,45 @@ DECLARE_GLOBAL_DATA_PTR;
 # define SHOW_BOOT_PROGRESS(arg)
 #endif
 
-int checkboard (void)
+int checkboard(void)
 {
-	printf ("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
-	printf ("Board: ADI BF533 Stamp board\n");
-	printf ("       Support: http://blackfin.uclinux.org/\n");
-	printf ("       Richard Klingler <richard@uclinux.net>\n");
+#if (BFIN_CPU == ADSP_BF531)
+	printf("CPU:   ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
+#elif (BFIN_CPU == ADSP_BF532)
+	printf("CPU:   ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28);
+#else
+	printf("CPU:   ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
+#endif
+	printf("Board: ADI BF533 Stamp board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
 	return 0;
 }
 
-long int initdram (int board_type)
+long int initdram(int board_type)
 {
+	DECLARE_GLOBAL_DATA_PTR;
 #ifdef DEBUG
-	printf ("SDRAM attributes:\n");
-	printf ("  tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
-		"CAS Latency:%d cycles\n",
-		(SDRAM_tRCD >> 15),
-		(SDRAM_tRP >> 11),
-		(SDRAM_tRAS >> 6),
-		(SDRAM_tWR >> 19),
-		(SDRAM_CL >> 2));
-	printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
-	printf ("Bank size = %d MB\n", 128);
+	printf("SDRAM attributes:\n");
+	printf
+	    ("  tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
+	     "CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
+	     (SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2));
+	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf("Bank size = %d MB\n", 128);
 #endif
 	gd->bd->bi_memstart = CFG_SDRAM_BASE;
 	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
 	return (gd->bd->bi_memsize);
 }
 
-void swap_to (int device_id)
+void swap_to(int device_id)
 {
 
 	if (device_id == ETHERNET) {
 		*pFIO_DIR = PF0;
-		asm ("ssync;");
+		sync();
 		*pFIO_FLAG_S = PF0;
-		asm ("ssync;");
+		sync();
 	} else if (device_id == FLASH) {
 		*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
 		*pFIO_FLAG_S = (PF4 | PF3 | PF2);
@@ -85,9 +87,9 @@ void swap_to (int device_id)
 		*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
 		*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
 		*pFIO_FLAG_D = (PF4 | PF3 | PF2);
-		asm ("ssync;");
+		sync();
 	} else {
-		printf ("Unknown bank to switch\n");
+		printf("Unknown bank to switch\n");
 	}
 
 	return;
@@ -95,7 +97,7 @@ void swap_to (int device_id)
 
 #if defined(CONFIG_MISC_INIT_R)
 /* miscellaneous platform dependent initialisations */
-int misc_init_r (void)
+int misc_init_r(void)
 {
 	int i;
 	int cf_stat = 0;
@@ -104,7 +106,7 @@ int misc_init_r (void)
 	*pFIO_EDGE = FIO_EDGE_CF_BITS;
 	*pFIO_POLAR = FIO_POLAR_CF_BITS;
 	for (i = 0; i < 0x300; i++)
-		asm ("nop;");
+		asm("nop;");
 
 	if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
 		cf_stat = 0;
@@ -115,37 +117,36 @@ int misc_init_r (void)
 	*pFIO_EDGE = FIO_EDGE_BITS;
 	*pFIO_POLAR = FIO_POLAR_BITS;
 
-
 	if (cf_stat) {
-		printf ("Booting from COMPACT flash\n");
+		printf("Booting from COMPACT flash\n");
 
 		/* Set cycle time for CF */
-		*(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL;
+		*(volatile unsigned long *)ambctl1 = CF_AMBCTL1VAL;
 
 		for (i = 0; i < 0x1000; i++)
-			asm ("nop;");
+			asm("nop;");
 		for (i = 0; i < 0x1000; i++)
-			asm ("nop;");
+			asm("nop;");
 		for (i = 0; i < 0x1000; i++)
-			asm ("nop;");
+			asm("nop;");
 
-		serial_setbrg ();
-		ide_init ();
+		serial_setbrg();
+		ide_init();
 
-		setenv ("bootargs", "");
-		setenv ("bootcmd",
-			"fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
+		setenv("bootargs", "");
+		setenv("bootcmd",
+		       "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
 	} else {
-		printf ("Booting from FLASH\n");
+		printf("Booting from FLASH\n");
 	}
 
-	return 1;
+	return 0;
 }
 #endif
 
 #ifdef CONFIG_STAMP_CF
 
-void cf_outb (unsigned char val, volatile unsigned char *addr)
+void cf_outb(unsigned char val, volatile unsigned char *addr)
 {
 	/*
 	 * Set PF1 PF0 respectively to 0 1 to divert address
@@ -153,70 +154,70 @@ void cf_outb (unsigned char val, volatile unsigned char *addr)
 	 */
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	asm ("ssync;");
+	sync();
 
 	*(addr) = val;
-	asm ("ssync;");
+	sync();
 
 	/* Setback PF1 PF0 to 0 0 to address external
 	 * memory banks  */
-	*(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0;
-	asm ("ssync;");
+	*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
+	sync();
 }
 
-unsigned char cf_inb (volatile unsigned char *addr)
+unsigned char cf_inb(volatile unsigned char *addr)
 {
 	volatile unsigned char c;
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	asm ("ssync;");
+	sync();
 
 	c = *(addr);
-	asm ("ssync;");
+	sync();
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	asm ("ssync;");
+	sync();
 
 	return c;
 }
 
-void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words)
+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
 {
 	int i;
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	asm ("ssync;");
+	sync();
 
 	for (i = 0; i < words; i++) {
 		*(sect_buf + i) = *(addr);
-		asm ("ssync;");
+		sync();
 	}
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	asm ("ssync;");
+	sync();
 }
 
-void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words)
+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
 {
 	int i;
 
 	*pFIO_FLAG_S = CF_PF0;
 	*pFIO_FLAG_C = CF_PF1;
-	asm ("ssync;");
+	sync();
 
 	for (i = 0; i < words; i++) {
 		*(addr) = *(sect_buf + i);
-		asm ("ssync;");
+		sync();
 	}
 
 	*pFIO_FLAG_C = CF_PF1_PF0;
-	asm ("ssync;");
+	sync();
 }
 #endif
 
-void stamp_led_set (int LED1, int LED2, int LED3)
+void stamp_led_set(int LED1, int LED2, int LED3)
 {
 	*pFIO_INEN &= ~(PF2 | PF3 | PF4);
 	*pFIO_DIR |= (PF2 | PF3 | PF4);
@@ -233,31 +234,31 @@ void stamp_led_set (int LED1, int LED2, int LED3)
 		*pFIO_FLAG_S = PF4;
 	else
 		*pFIO_FLAG_C = PF4;
-	asm ("ssync;");
+	sync();
 }
 
-void show_boot_progress (int status)
+void show_boot_progress(int status)
 {
 	switch (status) {
 	case 1:
-		stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
+		stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
 		break;
 	case 2:
-		stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
+		stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
 		break;
 	case 3:
-		stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
+		stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
 		break;
 	case 4:
-		stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
+		stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
 		break;
 	case 5:
 	case 6:
-		stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
+		stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
 		break;
 	case 7:
 	case 8:
-		stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
+		stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
 		break;
 	case 9:
 	case 10:
@@ -266,11 +267,10 @@ void show_boot_progress (int status)
 	case 13:
 	case 14:
 	case 15:
-		stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF,
-			       STATUS_LED_OFF);
+		stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF);
 		break;
 	default:
-		stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
+		stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
 		break;
 	}
 }
diff --git a/board/stamp/stamp.h b/board/bf533-stamp/bf533-stamp.h
index 7bc33b4..b2b51aa 100644
--- a/board/stamp/stamp.h
+++ b/board/bf533-stamp/bf533-stamp.h
@@ -36,7 +36,6 @@ extern volatile unsigned long *amgctl;
 
 extern unsigned long pll_div_fact;
 extern void serial_setbrg(void);
-extern void pll_set(int vco, int crystal_frq, int pll_div);
 
 /* Definitions used in  Compact Flash Boot support */
 #define FIO_EDGE_CF_BITS 	0x0000
diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk
new file mode 100644
index 0000000..113438b
--- /dev/null
+++ b/board/bf533-stamp/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
+#  256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
+TEXT_BASE = 0x07FC0000
diff --git a/board/bf533-stamp/spi.c b/board/bf533-stamp/spi.c
new file mode 100644
index 0000000..d30750f
--- /dev/null
+++ b/board/bf533-stamp/spi.c
@@ -0,0 +1,473 @@
+/****************************************************************************
+ *  SPI flash driver for M25P64
+ ****************************************************************************/
+#include <common.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_SPI)
+
+ /*Application definitions */
+
+#define	NUM_SECTORS 	128	/* number of sectors */
+#define SECTOR_SIZE		0x10000
+#define NOP_NUM		1000
+
+#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL)	/*Settings to the SPI_CTL */
+#define TIMOD01 (0x01)		/*stes the SPI to work with core instructions */
+
+ /*Flash commands */
+#define SPI_WREN	(0x06)	/*Set Write Enable Latch */
+#define SPI_WRDI	(0x04)	/*Reset Write Enable Latch */
+#define SPI_RDSR	(0x05)	/*Read Status Register */
+#define SPI_WRSR	(0x01)	/*Write Status Register */
+#define SPI_READ	(0x03)	/*Read data from memory */
+#define SPI_PP  	(0x02)	/*Program Data into memory */
+#define SPI_SE  	(0xD8)	/*Erase one sector in memory */
+#define SPI_BE		(0xC7)	/*Erase all memory */
+#define WIP		(0x1)	/*Check the write in progress bit of the SPI status register */
+#define WEL		(0x2)	/*Check the write enable bit of the SPI status register */
+
+#define TIMEOUT 350000000
+
+typedef enum {
+	NO_ERR,
+	POLL_TIMEOUT,
+	INVALID_SECTOR,
+	INVALID_BLOCK,
+} ERROR_CODE;
+
+void spi_init_f(void);
+void spi_init_r(void);
+ssize_t spi_read(uchar *, int, uchar *, int);
+ssize_t spi_write(uchar *, int, uchar *, int);
+
+char ReadStatusRegister(void);
+void Wait_For_SPIF(void);
+void SetupSPI(const int spi_setting);
+void SPI_OFF(void);
+void SendSingleCommand(const int iCommand);
+
+ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
+ERROR_CODE EraseBlock(int nBlock);
+ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
+ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
+ERROR_CODE Wait_For_Status(char Statusbit);
+ERROR_CODE Wait_For_WEL(void);
+
+/* -------------------
+ * Variables
+ * ------------------- */
+
+/* **************************************************************************
+ *
+ *  Function:    spi_init_f
+ *
+ *  Description: Init SPI-Controller (ROM part)
+ *
+ *  return:      ---
+ *
+ * *********************************************************************** */
+void spi_init_f(void)
+{
+}
+
+/* **************************************************************************
+ *
+ *  Function:    spi_init_r
+ *
+ *  Description: Init SPI-Controller (RAM part) -
+ *		 The malloc engine is ready and we can move our buffers to
+ *		 normal RAM
+ *
+ *  return:      ---
+ *
+ * *********************************************************************** */
+void spi_init_r(void)
+{
+	return;
+}
+
+/****************************************************************************
+ *  Function:    spi_write
+ **************************************************************************** */
+ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
+{
+	unsigned long offset;
+	int start_block, end_block;
+	int start_byte, end_byte;
+	ERROR_CODE result = NO_ERR;
+	uchar temp[SECTOR_SIZE];
+	int i, num;
+
+	offset = addr[0] << 16 | addr[1] << 8 | addr[2];
+	/* Get the start block number */
+	result = GetSectorNumber(offset, &start_block);
+	if (result == INVALID_SECTOR) {
+		printf("Invalid sector! ");
+		return 0;
+	}
+	/* Get the end block number */
+	result = GetSectorNumber(offset + len - 1, &end_block);
+	if (result == INVALID_SECTOR) {
+		printf("Invalid sector! ");
+		return 0;
+	}
+
+	for (num = start_block; num <= end_block; num++) {
+		ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
+		start_byte = num * SECTOR_SIZE;
+		end_byte = (num + 1) * SECTOR_SIZE - 1;
+		if (start_byte < offset)
+			start_byte = offset;
+		if (end_byte > (offset + len))
+			end_byte = (offset + len - 1);
+		for (i = start_byte; i <= end_byte; i++)
+			temp[i - num * SECTOR_SIZE] = buffer[i - offset];
+		EraseBlock(num);
+		result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
+		if (result != NO_ERR)
+			return 0;
+		printf(".");
+	}
+	return len;
+}
+
+/****************************************************************************
+ *  Function:    spi_read
+ **************************************************************************** */
+ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
+{
+	unsigned long offset;
+	offset = addr[0] << 16 | addr[1] << 8 | addr[2];
+	ReadData(offset, len, (int *)buffer);
+	return len;
+}
+
+void SendSingleCommand(const int iCommand)
+{
+	unsigned short dummy;
+
+	/*turns on the SPI in single write mode */
+	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+
+	/*sends the actual command to the SPI TX register */
+	*pSPI_TDBR = iCommand;
+	sync();
+
+	/*The SPI status register will be polled to check the SPIF bit */
+	Wait_For_SPIF();
+
+	dummy = *pSPI_RDBR;
+
+	/*The SPI will be turned off */
+	SPI_OFF();
+
+}
+
+void SetupSPI(const int spi_setting)
+{
+
+	if (icache_status() || dcache_status())
+		udelay(CONFIG_CCLK_HZ / 50000000);
+	/*sets up the PF2 to be the slave select of the SPI */
+	*pSPI_FLG = 0xFB04;
+	*pSPI_BAUD = CONFIG_SPI_BAUD;
+	*pSPI_CTL = spi_setting;
+	sync();
+}
+
+void SPI_OFF(void)
+{
+
+	*pSPI_CTL = 0x0400;	/* disable SPI */
+	*pSPI_FLG = 0;
+	*pSPI_BAUD = 0;
+	sync();
+	udelay(CONFIG_CCLK_HZ / 50000000);
+
+}
+
+void Wait_For_SPIF(void)
+{
+	unsigned short dummyread;
+	while ((*pSPI_STAT & TXS)) ;
+	while (!(*pSPI_STAT & SPIF)) ;
+	while (!(*pSPI_STAT & RXS)) ;
+	dummyread = *pSPI_RDBR;	/* Read dummy to empty the receive register      */
+
+}
+
+ERROR_CODE Wait_For_WEL(void)
+{
+	int i;
+	char status_register = 0;
+	ERROR_CODE ErrorCode = NO_ERR;	/* tells us if there was an error erasing flash */
+
+	for (i = 0; i < TIMEOUT; i++) {
+		status_register = ReadStatusRegister();
+		if ((status_register & WEL)) {
+			ErrorCode = NO_ERR;	/* tells us if there was an error erasing flash */
+			break;
+		}
+		ErrorCode = POLL_TIMEOUT;	/* Time out error */
+	};
+
+	return ErrorCode;
+}
+
+ERROR_CODE Wait_For_Status(char Statusbit)
+{
+	int i;
+	char status_register = 0xFF;
+	ERROR_CODE ErrorCode = NO_ERR;	/* tells us if there was an error erasing flash */
+
+	for (i = 0; i < TIMEOUT; i++) {
+		status_register = ReadStatusRegister();
+		if (!(status_register & Statusbit)) {
+			ErrorCode = NO_ERR;	/* tells us if there was an error erasing flash */
+			break;
+		}
+		ErrorCode = POLL_TIMEOUT;	/* Time out error */
+	};
+
+	return ErrorCode;
+}
+
+char ReadStatusRegister(void)
+{
+	char status_register = 0;
+
+	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turn on the SPI */
+
+	*pSPI_TDBR = SPI_RDSR;	/* send instruction to read status register */
+	sync();
+	Wait_For_SPIF();	/*wait until the instruction has been sent */
+	*pSPI_TDBR = 0;		/*send dummy to receive the status register */
+	sync();
+	Wait_For_SPIF();	/*wait until the data has been sent */
+	status_register = *pSPI_RDBR;	/*read the status register */
+
+	SPI_OFF();		/* Turn off the SPI */
+
+	return status_register;
+}
+
+ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
+{
+	int nSector = 0;
+	ERROR_CODE ErrorCode = NO_ERR;
+
+	if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
+		ErrorCode = INVALID_SECTOR;
+		return ErrorCode;
+	}
+
+	nSector = (int)ulOffset / 0x10000;
+	*pnSector = nSector;
+
+	/* ok */
+	return ErrorCode;
+}
+
+ERROR_CODE EraseBlock(int nBlock)
+{
+	unsigned long ulSectorOff = 0x0, ShiftValue;
+	ERROR_CODE ErrorCode = NO_ERR;
+
+	/* if the block is invalid just return */
+	if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
+		ErrorCode = INVALID_BLOCK;	/* tells us if there was an error erasing flash */
+		return ErrorCode;
+	}
+	/* figure out the offset of the block in flash */
+	if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
+		ulSectorOff = (nBlock * SECTOR_SIZE);
+
+	} else {
+		ErrorCode = INVALID_BLOCK;	/* tells us if there was an error erasing flash */
+		return ErrorCode;
+	}
+
+	/* A write enable instruction must previously have been executed */
+	SendSingleCommand(SPI_WREN);
+
+	/*The status register will be polled to check the write enable latch "WREN" */
+	ErrorCode = Wait_For_WEL();
+
+	if (POLL_TIMEOUT == ErrorCode) {
+		printf("SPI Erase block error\n");
+		return ErrorCode;
+	} else
+		/*Turn on the SPI to send single commands */
+		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+
+	/* Send the erase block command to the flash followed by the 24 address  */
+	/* to point to the start of a sector. */
+	*pSPI_TDBR = SPI_SE;
+	sync();
+	Wait_For_SPIF();
+	ShiftValue = (ulSectorOff >> 16);	/* Send the highest byte of the 24 bit address at first */
+	*pSPI_TDBR = ShiftValue;
+	sync();
+	Wait_For_SPIF();	/* Wait until the instruction has been sent */
+	ShiftValue = (ulSectorOff >> 8);	/* Send the middle byte of the 24 bit address  at second */
+	*pSPI_TDBR = ShiftValue;
+	sync();
+	Wait_For_SPIF();	/* Wait until the instruction has been sent */
+	*pSPI_TDBR = ulSectorOff;	/* Send the lowest byte of the 24 bit address finally */
+	sync();
+	Wait_For_SPIF();	/* Wait until the instruction has been sent */
+
+	/*Turns off the SPI */
+	SPI_OFF();
+
+	/* Poll the status register to check the Write in Progress bit */
+	/* Sector erase takes time */
+	ErrorCode = Wait_For_Status(WIP);
+
+	/* block erase should be complete */
+	return ErrorCode;
+}
+
+/*****************************************************************************
+* ERROR_CODE ReadData()
+*
+* Read a value from flash for verify purpose
+*
+* Inputs:	unsigned long ulStart - holds the SPI start address
+*			int pnData - pointer to store value read from flash
+*			long lCount - number of elements to read
+***************************************************************************** */
+ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
+{
+	unsigned long ShiftValue;
+	char *cnData;
+	int i;
+
+	cnData = (char *)pnData;	/* Pointer cast to be able to increment byte wise */
+
+	/* Start SPI interface   */
+	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+
+	*pSPI_TDBR = SPI_READ;	/* Send the read command to SPI device */
+	sync();
+	Wait_For_SPIF();	/* Wait until the instruction has been sent */
+	ShiftValue = (ulStart >> 16);	/* Send the highest byte of the 24 bit address at first */
+	*pSPI_TDBR = ShiftValue;	/* Send the byte to the SPI device */
+	sync();
+	Wait_For_SPIF();	/* Wait until the instruction has been sent */
+	ShiftValue = (ulStart >> 8);	/* Send the middle byte of the 24 bit address  at second */
+	*pSPI_TDBR = ShiftValue;	/* Send the byte to the SPI device */
+	sync();
+	Wait_For_SPIF();	/* Wait until the instruction has been sent */
+	*pSPI_TDBR = ulStart;	/* Send the lowest byte of the 24 bit address finally */
+	sync();
+	Wait_For_SPIF();	/* Wait until the instruction has been sent */
+
+	/* After the SPI device address has been placed on the MOSI pin the data can be */
+	/* received on the MISO pin. */
+	for (i = 0; i < lCount; i++) {
+		*pSPI_TDBR = 0;	/*send dummy */
+		sync();
+		while (!(*pSPI_STAT & RXS)) ;
+		*cnData++ = *pSPI_RDBR;	/*read  */
+
+		if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
+			printf(".");
+	}
+
+	SPI_OFF();		/* Turn off the SPI */
+
+	return NO_ERR;
+}
+
+ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
+		      int *iDataSource, long *lWriteCount)
+{
+
+	unsigned long ulWAddr;
+	long lWTransferCount = 0;
+	int i;
+	char iData;
+	char *temp = (char *)iDataSource;
+	ERROR_CODE ErrorCode = NO_ERR;	/* tells us if there was an error erasing flash */
+
+	/* First, a Write Enable Command must be sent to the SPI. */
+	SendSingleCommand(SPI_WREN);
+
+	/* Second, the SPI Status Register will be tested whether the  */
+	/*         Write Enable Bit has been set.  */
+	ErrorCode = Wait_For_WEL();
+	if (POLL_TIMEOUT == ErrorCode) {
+		printf("SPI Write Time Out\n");
+		return ErrorCode;
+	} else
+		/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
+		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turns the SPI on */
+	*pSPI_TDBR = SPI_PP;
+	sync();
+	Wait_For_SPIF();	/*wait until the instruction has been sent */
+	ulWAddr = (ulStartAddr >> 16);
+	*pSPI_TDBR = ulWAddr;
+	sync();
+	Wait_For_SPIF();	/*wait until the instruction has been sent */
+	ulWAddr = (ulStartAddr >> 8);
+	*pSPI_TDBR = ulWAddr;
+	sync();
+	Wait_For_SPIF();	/*wait until the instruction has been sent */
+	ulWAddr = ulStartAddr;
+	*pSPI_TDBR = ulWAddr;
+	sync();
+	Wait_For_SPIF();	/*wait until the instruction has been sent */
+	/* Fourth, maximum number of 256 bytes will be taken from the Buffer */
+	/* and sent to the SPI device. */
+	for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
+		iData = *temp;
+		*pSPI_TDBR = iData;
+		sync();
+		Wait_For_SPIF();	/*wait until the instruction has been sent */
+		temp++;
+	}
+
+	SPI_OFF();		/* Turns the SPI off */
+
+	/* Sixth, the SPI Write in Progress Bit must be toggled to ensure the  */
+	/* programming is done before start of next transfer. */
+	ErrorCode = Wait_For_Status(WIP);
+
+	if (POLL_TIMEOUT == ErrorCode) {
+		printf("SPI Program Time out!\n");
+		return ErrorCode;
+	} else
+
+		*lWriteCount = lWTransferCount;
+
+	return ErrorCode;
+}
+
+ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
+{
+
+	unsigned long ulWStart = ulStart;
+	long lWCount = lCount, lWriteCount;
+	long *pnWriteCount = &lWriteCount;
+
+	ERROR_CODE ErrorCode = NO_ERR;
+
+	while (lWCount != 0) {
+		ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
+
+		/* After each function call of WriteFlash the counter must be adjusted */
+		lWCount -= *pnWriteCount;
+
+		/* Also, both address pointers must be recalculated. */
+		ulWStart += *pnWriteCount;
+		pnData += *pnWriteCount / 4;
+	}
+
+	/* return the appropriate error code */
+	return ErrorCode;
+}
+
+#endif				/* CONFIG_SPI */
diff --git a/board/stamp/u-boot.lds b/board/bf533-stamp/u-boot.lds.S
index 9a22e50..03ef72b 100644
--- a/board/stamp/u-boot.lds
+++ b/board/bf533-stamp/u-boot.lds.S
@@ -1,7 +1,7 @@
 /*
- * U-boot - u-boot.lds
+ * U-boot - u-boot.lds.S
  *
- * Copyright (c) 2005 blackfin.uclinux.org
+ * Copyright (c) 2005-2007 Analog Device Inc.
  *
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -25,6 +25,8 @@
  * MA 02111-1307 USA
  */
 
+#include <config.h>
+
 OUTPUT_ARCH(bfin)
 SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
 /* Do we need any of these for elf?
@@ -55,6 +57,7 @@ SECTIONS
   .rela.plt      : { *(.rela.plt)	}
   .init          : { *(.init)		}
   .plt : { *(.plt) }
+  . = CFG_MONITOR_BASE;
   .text      :
   {
     /* WARNING - the following is hand-optimized to fit within	*/
@@ -68,9 +71,11 @@ SECTIONS
     cpu/bf533/interrupt.o	(.text)
     cpu/bf533/serial.o		(.text)
     common/dlmalloc.o		(.text)
-    lib_generic/vsprintf.o	(.text)
+/*  lib_blackfin/bf533_string.o	(.text)	*/
+/*  lib_generic/vsprintf.o	(.text) */
     lib_generic/crc32.o		(.text)
-    lib_generic/zlib.o		(.text)
+/*  lib_generic/zlib.o		(.text) */
+/*  board/stamp/stamp.o		(.text) */
 
     . = DEFINED(env_offset) ? env_offset : .;
     common/environment.o	(.text)
@@ -118,9 +123,9 @@ SECTIONS
   _edata  =  .;
   PROVIDE (edata = .);
 
-  __u_boot_cmd_start = .;
+  ___u_boot_cmd_start = .;
   .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+  ___u_boot_cmd_end = .;
 
 
   __start___ex_table = .;
diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
new file mode 100644
index 0000000..e488844
--- /dev/null
+++ b/board/bf537-stamp/Makefile
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o flash.o ether_bf537.o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+u-boot.lds: u-boot.lds.S
+	$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+	mv -f $@.tmp $@
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c
new file mode 100644
index 0000000..cc4e998
--- /dev/null
+++ b/board/bf537-stamp/bf537-stamp.c
@@ -0,0 +1,437 @@
+/*
+ * U-boot - BF537.c
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include "ether_bf537.h"
+
+#define POST_WORD_ADDR 0xFF903FFC
+
+/*
+ * the bootldr command loads an address, checks to see if there
+ *   is a Boot stream that the on-chip BOOTROM can understand,
+ *   and loads it via the BOOTROM Callback. It is possible
+ *   to also add booting from SPI, or TWI, but this function does
+ *   not currently support that.
+ */
+int do_bootldr(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr, entry;
+	ulong *data;
+
+	/* Get the address */
+	if (argc < 2) {
+		addr = load_addr;
+	} else {
+		addr = simple_strtoul(argv[1], NULL, 16);
+	}
+
+	/* Check if it is a LDR file */
+	data = (ulong *) addr;
+	if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) {
+		/* We want to boot from FLASH or SDRAM */
+		entry = _BOOTROM_BOOT_DXE_FLASH;
+		printf("## Booting ldr image at 0x%08lx ...\n", addr);
+		if (icache_status())
+			icache_disable();
+		if (dcache_status())
+			dcache_disable();
+
+	      __asm__("R7=%[a];\n" "P0=%[b];\n" "JUMP (P0);\n":
+	      :[a] "d"(addr),[b] "a"(entry)
+	      :"R7", "P0");
+
+	} else {
+		printf("## No ldr image at address 0x%08lx\n", addr);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(bootldr, 2, 0, do_bootldr,
+	   "bootldr - boot ldr image from memory\n",
+	   "[addr]\n         - boot ldr image stored in memory\n");
+
+int checkboard(void)
+{
+#if (BFIN_CPU == ADSP_BF534)
+	printf("CPU:   ADSP BF534 Rev.: 0.%d\n", *pCHIPID >> 28);
+#elif (BFIN_CPU == ADSP_BF536)
+	printf("CPU:   ADSP BF536 Rev.: 0.%d\n", *pCHIPID >> 28);
+#else
+	printf("CPU:   ADSP BF537 Rev.: 0.%d\n", *pCHIPID >> 28);
+#endif
+	printf("Board: ADI BF537 stamp board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+#if defined(CONFIG_BFIN_IDE)
+
+void cf_outb(unsigned char val, volatile unsigned char *addr)
+{
+	*(addr) = val;
+	sync();
+}
+
+unsigned char cf_inb(volatile unsigned char *addr)
+{
+	volatile unsigned char c;
+
+	c = *(addr);
+	sync();
+
+	return c;
+}
+
+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
+{
+	int i;
+
+	for (i = 0; i < words; i++)
+		*(sect_buf + i) = *(addr);
+	sync();
+}
+
+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
+{
+	int i;
+
+	for (i = 0; i < words; i++)
+		*(addr) = *(sect_buf + i);
+	sync();
+}
+#endif				/* CONFIG_BFIN_IDE */
+
+long int initdram(int board_type)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+	int brate;
+	char *tmp = getenv("baudrate");
+	brate = simple_strtoul(tmp, NULL, 16);
+	printf("Serial Port initialized with Baud rate = %x\n", brate);
+	printf("SDRAM attributes:\n");
+	printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
+	       "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
+	       3, 3, 6, 2, 3);
+	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+#endif
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+	return CFG_MAX_RAM_SIZE;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+	char nid[32];
+	unsigned char *pMACaddr = (unsigned char *)0x203F0000;
+	u8 SrcAddr[6] = { 0x02, 0x80, 0xAD, 0x20, 0x31, 0xB8 };
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+	/* The 0xFF check here is to make sure we don't use the address
+	 * in flash if it's simply been erased (aka all 0xFF values) */
+	if (getenv("ethaddr") == NULL && is_valid_ether_addr(pMACaddr)) {
+		sprintf(nid, "%02x:%02x:%02x:%02x:%02x:%02x",
+			pMACaddr[0], pMACaddr[1],
+			pMACaddr[2], pMACaddr[3], pMACaddr[4], pMACaddr[5]);
+		setenv("ethaddr", nid);
+	}
+	if (getenv("ethaddr")) {
+		SetupMacAddr(SrcAddr);
+	}
+#endif				/* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif				/* BFIN_BOOT_MODE == BF537_BYPASS_BOOT */
+
+#if defined(CONFIG_BFIN_IDE)
+#if defined(CONFIG_BFIN_TRUE_IDE)
+	/* Enable ATASEL when in True IDE mode */
+	printf("Using CF True IDE Mode\n");
+	cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
+	udelay(1000);
+#elif defined(CONFIG_BFIN_CF_IDE)
+	/* Disable ATASEL when we're in Common Memory Mode */
+	printf("Using CF Common Memory Mode\n");
+	cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
+	udelay(1000);
+#elif defined(CONFIG_BFIN_HDD_IDE)
+	printf("Using HDD IDE Mode\n");
+#endif
+	ide_init();
+#endif				/* CONFIG_BFIN_IDE */
+	return 0;
+}
+#endif				/* CONFIG_MISC_INIT_R */
+
+#ifdef CONFIG_POST
+#if (BFIN_BOOT_MODE != BF537_BYPASS_BOOT)
+/* Using sw10-PF5 as the hotkey */
+int post_hotkeys_pressed(void)
+{
+	return 0;
+}
+#else
+/* Using sw10-PF5 as the hotkey */
+int post_hotkeys_pressed(void)
+{
+	int delay = 3;
+	int i;
+	unsigned short value;
+
+	*pPORTF_FER &= ~PF5;
+	*pPORTFIO_DIR &= ~PF5;
+	*pPORTFIO_INEN |= PF5;
+
+	printf("########Press SW10 to enter Memory POST########: %2d ", delay);
+	while (delay--) {
+		for (i = 0; i < 100; i++) {
+			value = *pPORTFIO & PF5;
+			if (value != 0) {
+				break;
+			}
+			udelay(10000);
+		}
+		printf("\b\b\b%2d ", delay);
+	}
+	printf("\b\b\b 0");
+	printf("\n");
+	if (value == 0)
+		return 0;
+	else {
+		printf("Hotkey has been pressed, Enter POST . . . . . .\n");
+		return 1;
+	}
+}
+#endif
+#endif
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+void post_word_store(ulong a)
+{
+	volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
+	*save_addr = a;
+}
+
+ulong post_word_load(void)
+{
+	volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
+	return *save_addr;
+}
+#endif
+
+#ifdef CONFIG_POST
+int uart_post_test(int flags)
+{
+	return 0;
+}
+
+#define BLOCK_SIZE 0x10000
+#define VERIFY_ADDR 0x2000000
+extern int erase_block_flash(int);
+extern int write_data(long lStart, long lCount, uchar * pnData);
+int flash_post_test(int flags)
+{
+	unsigned short *pbuf, *temp;
+	int offset, n, i;
+	int value = 0;
+	int result = 0;
+	printf("\n");
+	pbuf = (unsigned short *)VERIFY_ADDR;
+	temp = pbuf;
+	for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
+		offset = (n - 7) * BLOCK_SIZE;
+		printf("--------Erase   block:%2d..", n);
+		erase_block_flash(n);
+		printf("OK\r");
+		printf("--------Program block:%2d...", n);
+		write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
+		printf("OK\r");
+		printf("--------Verify  block:%2d...", n);
+		for (i = 0; i < BLOCK_SIZE; i += 2) {
+			if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
+			    *temp++) {
+				value = 1;
+				result = 1;
+			}
+		}
+		if (value)
+			printf("failed\n");
+		else
+			printf("OK		%3d%%\r",
+			       (int)(
+				     (n + 1 -
+				      FLASH_START_POST_BLOCK) *
+				     100 / (FLASH_END_POST_BLOCK -
+					    FLASH_START_POST_BLOCK)));
+
+		temp = pbuf;
+		value = 0;
+	}
+	printf("\n");
+	if (result)
+		return -1;
+	else
+		return 0;
+}
+
+/****************************************************
+ * LED1 ---- PF6	LED2 ---- PF7		    *
+ * LED3 ---- PF8	LED4 ---- PF9		    *
+ * LED5 ---- PF10	LED6 ---- PF11		    *
+ ****************************************************/
+int led_post_test(int flags)
+{
+	*pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
+	*pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
+	*pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
+	*pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
+	udelay(1000000);
+	printf("LED1 on");
+	*pPORTFIO |= PF6;
+	udelay(1000000);
+	printf("\b\b\b\b\b\b\b");
+	printf("LED2 on");
+	*pPORTFIO |= PF7;
+	udelay(1000000);
+	printf("\b\b\b\b\b\b\b");
+	printf("LED3 on");
+	*pPORTFIO |= PF8;
+	udelay(1000000);
+	printf("\b\b\b\b\b\b\b");
+	printf("LED4 on");
+	*pPORTFIO |= PF9;
+	udelay(1000000);
+	printf("\b\b\b\b\b\b\b");
+	printf("LED5 on");
+	*pPORTFIO |= PF10;
+	udelay(1000000);
+	printf("\b\b\b\b\b\b\b");
+	printf("lED6 on");
+	*pPORTFIO |= PF11;
+	printf("\b\b\b\b\b\b\b ");
+	return 0;
+}
+
+/************************************************
+ *  SW10 ---- PF5	SW11 ---- PF4		*
+ *  SW12 ---- PF3	SW13 ---- PF2		*
+ ************************************************/
+int button_post_test(int flags)
+{
+	int i, delay = 5;
+	unsigned short value = 0;
+	int result = 0;
+
+	*pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
+	*pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
+	*pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
+
+	printf("\n--------Press SW10: %2d ", delay);
+	while (delay--) {
+		for (i = 0; i < 100; i++) {
+			value = *pPORTFIO & PF5;
+			if (value != 0) {
+				break;
+			}
+			udelay(10000);
+		}
+		printf("\b\b\b%2d ", delay);
+	}
+	if (value != 0)
+		printf("\b\bOK");
+	else {
+		result = -1;
+		printf("\b\bfailed");
+	}
+
+	delay = 5;
+	printf("\n--------Press SW11: %2d ", delay);
+	while (delay--) {
+		for (i = 0; i < 100; i++) {
+			value = *pPORTFIO & PF4;
+			if (value != 0) {
+				break;
+			}
+			udelay(10000);
+		}
+		printf("\b\b\b%2d ", delay);
+	}
+	if (value != 0)
+		printf("\b\bOK");
+	else {
+		result = -1;
+		printf("\b\bfailed");
+	}
+
+	delay = 5;
+	printf("\n--------Press SW12: %2d ", delay);
+	while (delay--) {
+		for (i = 0; i < 100; i++) {
+			value = *pPORTFIO & PF3;
+			if (value != 0) {
+				break;
+			}
+			udelay(10000);
+		}
+		printf("\b\b\b%2d ", delay);
+	}
+	if (value != 0)
+		printf("\b\bOK");
+	else {
+		result = -1;
+		printf("\b\bfailed");
+	}
+
+	delay = 5;
+	printf("\n--------Press SW13: %2d ", delay);
+	while (delay--) {
+		for (i = 0; i < 100; i++) {
+			value = *pPORTFIO & PF2;
+			if (value != 0) {
+				break;
+			}
+			udelay(10000);
+		}
+		printf("\b\b\b%2d ", delay);
+	}
+	if (value != 0)
+		printf("\b\bOK");
+	else {
+		result = -1;
+		printf("\b\bfailed");
+	}
+	printf("\n");
+	return result;
+}
+#endif
diff --git a/board/bf537-stamp/cmd_bf537led.c b/board/bf537-stamp/cmd_bf537led.c
new file mode 100644
index 0000000..fa650f2
--- /dev/null
+++ b/board/bf537-stamp/cmd_bf537led.c
@@ -0,0 +1,201 @@
+/*
+ * U-boot - cmd_bf537led.c
+ *
+ * Copyright (C) 2006 Aaron Gage, Ocean Optics Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm-blackfin/string.h>
+#ifdef CONFIG_BF537_STAMP_LEDCMD
+
+/* Define the command usage in a reusable way */
+#define USAGE_LONG \
+	"led <number> <action>\n" \
+	"    <number>  - Index (0-5) of LED to change, or \"all\"\n" \
+	"    <action>  - Must be one of:\n" \
+	"		on off toggle\n"
+
+/* Number of LEDs supported by the board */
+#define NUMBER_LEDS     6
+/* The BF537 stamp has 6 LEDs.  This mask indicates that all should be lit. */
+#define LED_ALL_MASK    0x003F
+
+void show_cmd_usage(void);
+void set_led_state(int index, int state);
+void configure_GPIO_to_output(int index);
+
+/* Map of LEDs according to their GPIO ports.  This can be rearranged or
+ * otherwise changed to account for different GPIO configurations.
+ */
+int led_ports[] = { PF6, PF7, PF8, PF9, PF10, PF11 };
+
+#define ACTION_TOGGLE   -1
+#define ACTION_OFF      0
+#define ACTION_ON       1
+
+#define LED_STATE_OFF   0
+#define LED_STATE_ON    1
+
+/* This is a trivial atoi implementation since we don't have one available */
+int atoi(char *string)
+{
+	int length;
+	int retval = 0;
+	int i;
+	int sign = 1;
+
+	length = strlen(string);
+	for (i = 0; i < length; i++) {
+		if (0 == i && string[0] == '-') {
+			sign = -1;
+			continue;
+		}
+		if (string[i] > '9' || string[i] < '0') {
+			break;
+		}
+		retval *= 10;
+		retval += string[i] - '0';
+	}
+	retval *= sign;
+	return retval;
+}
+
+int do_bf537led(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int led_mask = 0;
+	int led_current_state = 0;
+	int action = ACTION_OFF;
+	int temp;
+
+	if (3 != argc) {
+		/* Not enough arguments, so just show usage information */
+		show_cmd_usage();
+		return 1;
+	}
+
+	if (strcmp(argv[1], "all") == 0) {
+		led_mask = LED_ALL_MASK;
+	} else {
+		temp = atoi(argv[1]);
+		if (temp < 0 || temp >= NUMBER_LEDS) {
+			printf("Invalid LED number [%s]\n", argv[1]);
+			show_cmd_usage();
+			return 2;
+		}
+		led_mask |= (1 << temp);
+	}
+
+	if (strcmp(argv[2], "off") == 0) {
+		action = ACTION_OFF;
+	} else if (strcmp(argv[2], "on") == 0) {
+		action = ACTION_ON;
+	} else if (strcmp(argv[2], "toggle") == 0) {
+		action = ACTION_TOGGLE;
+	} else {
+		printf("Invalid action [%s]\n", argv[2]);
+		show_cmd_usage();
+		return 3;
+	}
+
+	for (temp = 0; temp < NUMBER_LEDS; temp++) {
+		if ((led_mask & (1 << temp)) > 0) {
+			/*
+			 * It is possible that the user has wired one of PF6-PF11 to
+			 * something other than an LED, so this will only change a pin
+			 * to output if the user has indicated a state change.  This may
+			 * happen a lot, but this way is safer than just setting all pins
+			 * to output.
+			 */
+			configure_GPIO_to_output(temp);
+
+			led_current_state =
+			    ((*pPORTFIO & led_ports[temp]) >
+			     0) ? LED_STATE_ON : LED_STATE_OFF;
+	/*
+		printf("LED state for index %d (%x) is %d\n", temp, led_ports[temp],
+			led_current_state);
+		printf("*pPORTFIO is %x\n", *pPORTFIO);
+	*/
+			if (ACTION_ON == action
+			    || (ACTION_TOGGLE == action
+				&& 0 == led_current_state)) {
+				printf("Turning LED %d on\n", temp);
+				set_led_state(temp, LED_STATE_ON);
+			} else {
+				printf("Turning LED %d off\n", temp);
+				set_led_state(temp, LED_STATE_OFF);
+			}
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * The GPIO pins that go to the LEDs on the BF537 stamp must be configured
+ * as output.  This function simply configures them that way.  This could
+ * be done to all of the GPIO lines at once, but if a user is using a
+ * custom board, this will try to be nice and only change the GPIO lines
+ * that the user specifically names.
+ */
+void configure_GPIO_to_output(int index)
+{
+	int port;
+
+	port = led_ports[index];
+
+	/* Clear the Port F Function Enable Register */
+	*pPORTF_FER &= ~port;
+	/* Set the Port F I/O direction register */
+	*pPORTFIO_DIR |= port;
+	/* Clear the Port F I/O Input Enable Register */
+	*pPORTFIO_INEN &= ~port;
+}
+
+/* Enforce the given state on the GPIO line for the indicated LED */
+void set_led_state(int index, int state)
+{
+	int port;
+
+	port = led_ports[index];
+
+	if (LED_STATE_OFF == state) {
+		/* Clear the bit to turn off the LED */
+		*pPORTFIO &= ~port;
+	} else {
+		/* Set the bit to turn on the LED */
+		*pPORTFIO |= port;
+	}
+}
+
+/* Display usage information */
+void show_cmd_usage()
+{
+	printf("Usage:\n%s", USAGE_LONG);
+}
+
+/* Register information for u-boot to find this command */
+U_BOOT_CMD(led, 3, 1, do_bf537led,
+	   "led- Control BF537 stamp LEDs\n", USAGE_LONG);
+
+#endif
diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk
new file mode 100644
index 0000000..a623c3d
--- /dev/null
+++ b/board/bf537-stamp/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
+#  256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
+TEXT_BASE = 0x03FC0000
diff --git a/board/bf537-stamp/ether_bf537.c b/board/bf537-stamp/ether_bf537.c
new file mode 100644
index 0000000..f00837a
--- /dev/null
+++ b/board/bf537-stamp/ether_bf537.c
@@ -0,0 +1,545 @@
+/*
+ * ADI Blackfin 537 MAC Ethernet
+ *
+ * Copyright (c) 2005 Analog Device, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <net.h>
+#include <command.h>
+#include <malloc.h>
+#include "ether_bf537.h"
+
+#ifdef CONFIG_POST
+#include <post.h>
+#endif
+
+#undef DEBUG_ETHERNET
+
+#ifdef DEBUG_ETHERNET
+#define DEBUGF(fmt,args...) printf(fmt,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+#define RXBUF_BASE_ADDR		0xFF900000
+#define TXBUF_BASE_ADDR		0xFF800000
+#define TX_BUF_CNT		1
+
+#define TOUT_LOOP 		1000000
+
+ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
+ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
+static u16 txIdx;		/* index of the current RX buffer */
+static u16 rxIdx;		/* index of the current TX buffer */
+
+u8 SrcAddr[6];
+u16 PHYregs[NO_PHY_REGS];	/* u16 PHYADDR; */
+
+/* DMAx_CONFIG values at DMA Restart */
+const ADI_DMA_CONFIG_REG rxdmacfg = { 1, 1, 2, 0, 0, 0, 0, 5, 7 };
+
+#if 0
+	rxdmacfg.b_DMA_EN = 1;	/* enabled */
+	rxdmacfg.b_WNR    = 1;	/* write to memory */
+	rxdmacfg.b_WDSIZE = 2;	/* wordsize is 32 bits */
+	rxdmacfg.b_DMA2D  = 0;	/* N/A */
+	rxdmacfg.b_RESTART= 0;	/* N/A */
+	rxdmacfg.b_DI_SEL = 0;	/* N/A */
+	rxdmacfg.b_DI_EN  = 0;	/* no interrupt */
+	rxdmacfg.b_NDSIZE = 5;	/* 5 half words is desc size. */
+	rxdmacfg.b_FLOW   = 7;	/* large desc flow  */
+#endif
+
+const ADI_DMA_CONFIG_REG txdmacfg = { 1, 0, 2, 0, 0, 0, 0, 5, 7 };
+
+#if 0
+	txdmacfg.b_DMA_EN = 1;	/* enabled */
+	txdmacfg.b_WNR    = 0;	/* read from memory */
+	txdmacfg.b_WDSIZE = 2;	/* wordsize is 32 bits */
+	txdmacfg.b_DMA2D  = 0;	/* N/A */
+	txdmacfg.b_RESTART= 0;	/* N/A */
+	txdmacfg.b_DI_SEL = 0;	/* N/A */
+	txdmacfg.b_DI_EN  = 0;	/* no interrupt */
+	txdmacfg.b_NDSIZE = 5;	/* 5 half words is desc size. */
+	txdmacfg.b_FLOW   = 7;	/* large desc flow */
+#endif
+
+ADI_ETHER_BUFFER *SetupRxBuffer(int no);
+ADI_ETHER_BUFFER *SetupTxBuffer(int no);
+
+static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd);
+static void bfin_EMAC_halt(struct eth_device *dev);
+static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
+			  int length);
+static int bfin_EMAC_recv(struct eth_device *dev);
+
+int bfin_EMAC_initialize(bd_t * bis)
+{
+	struct eth_device *dev;
+	dev = (struct eth_device *)malloc(sizeof(*dev));
+	if (dev == NULL)
+		hang();
+
+	memset(dev, 0, sizeof(*dev));
+	sprintf(dev->name, "BF537 ETHERNET");
+
+	dev->iobase = 0;
+	dev->priv = 0;
+	dev->init = bfin_EMAC_init;
+	dev->halt = bfin_EMAC_halt;
+	dev->send = bfin_EMAC_send;
+	dev->recv = bfin_EMAC_recv;
+
+	eth_register(dev);
+
+	return 1;
+}
+
+static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
+			  int length)
+{
+	int i;
+	int result = 0;
+	unsigned int *buf;
+	buf = (unsigned int *)packet;
+
+	if (length <= 0) {
+		printf("Ethernet: bad packet size: %d\n", length);
+		goto out;
+	}
+
+	if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
+		printf("Ethernet: tx DMA error\n");
+		goto out;
+	}
+
+	for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
+		if (i > TOUT_LOOP) {
+			puts("Ethernet: tx time out\n");
+			goto out;
+		}
+	}
+	txbuf[txIdx]->FrmData->NoBytes = length;
+	memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
+	txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
+	*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
+	*pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
+	*pEMAC_OPMODE |= TE;
+
+	for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
+		if (i > TOUT_LOOP) {
+			puts("Ethernet: tx error\n");
+			goto out;
+		}
+	}
+	result = txbuf[txIdx]->StatusWord;
+	txbuf[txIdx]->StatusWord = 0;
+	if ((txIdx + 1) >= TX_BUF_CNT)
+		txIdx = 0;
+	else
+		txIdx++;
+      out:
+	DEBUGF("BFIN EMAC send: length = %d\n", length);
+	return result;
+}
+
+static int bfin_EMAC_recv(struct eth_device *dev)
+{
+	int length = 0;
+
+	for (;;) {
+		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
+			length = -1;
+			break;
+		}
+		if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
+			printf("Ethernet: rx dma overrun\n");
+			break;
+		}
+		if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
+			printf("Ethernet: rx error\n");
+			break;
+		}
+		length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
+		if (length <= 4) {
+			printf("Ethernet: bad frame\n");
+			break;
+		}
+		NetRxPackets[rxIdx] =
+		    (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
+		NetReceive(NetRxPackets[rxIdx], length - 4);
+		*pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
+		rxbuf[rxIdx]->StatusWord = 0x00000000;
+		if ((rxIdx + 1) >= PKTBUFSRX)
+			rxIdx = 0;
+		else
+			rxIdx++;
+	}
+
+	return length;
+}
+
+/**************************************************************
+ *
+ * Ethernet Initialization Routine
+ *
+ *************************************************************/
+
+static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd)
+{
+	u32 opmode;
+	int dat;
+	int i;
+	DEBUGF("Eth_init: ......\n");
+
+	txIdx = 0;
+	rxIdx = 0;
+
+/* Initialize System Register */
+	if (SetupSystemRegs(&dat) < 0)
+		return -1;
+
+/* Initialize EMAC address */
+	SetupMacAddr(SrcAddr);
+
+/* Initialize TX and RX buffer */
+	for (i = 0; i < PKTBUFSRX; i++) {
+		rxbuf[i] = SetupRxBuffer(i);
+		if (i > 0) {
+			rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
+			    &(rxbuf[i]->Dma[0]);
+			if (i == (PKTBUFSRX - 1))
+				rxbuf[i]->Dma[1].NEXT_DESC_PTR =
+				    &(rxbuf[0]->Dma[0]);
+		}
+	}
+	for (i = 0; i < TX_BUF_CNT; i++) {
+		txbuf[i] = SetupTxBuffer(i);
+		if (i > 0) {
+			txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
+			    &(txbuf[i]->Dma[0]);
+			if (i == (TX_BUF_CNT - 1))
+				txbuf[i]->Dma[1].NEXT_DESC_PTR =
+				    &(txbuf[0]->Dma[0]);
+		}
+	}
+
+	/* Set RX DMA */
+	*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
+	*pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
+
+	/* Wait MII done */
+	PollMdcDone();
+
+	/* We enable only RX here */
+	/* ASTP   : Enable Automatic Pad Stripping
+	   PR     : Promiscuous Mode for test
+	   PSF    : Receive frames with total length less than 64 bytes.
+	   FDMODE : Full Duplex Mode
+	   LB	  : Internal Loopback for test
+	   RE     : Receiver Enable */
+	if (dat == FDMODE)
+		opmode = ASTP | FDMODE | PSF;
+	else
+		opmode = ASTP | PSF;
+	opmode |= RE;
+#ifdef CONFIG_BFIN_MAC_RMII
+	opmode |= TE | RMII;
+#endif
+	/* Turn on the EMAC */
+	*pEMAC_OPMODE = opmode;
+	return 0;
+}
+
+static void bfin_EMAC_halt(struct eth_device *dev)
+{
+	DEBUGF("Eth_halt: ......\n");
+	/* Turn off the EMAC */
+	*pEMAC_OPMODE = 0x00000000;
+	/* Turn off the EMAC RX DMA */
+	*pDMA1_CONFIG = 0x0000;
+	*pDMA2_CONFIG = 0x0000;
+
+}
+
+void SetupMacAddr(u8 * MACaddr)
+{
+	char *tmp, *end;
+	int i;
+	/* this depends on a little-endian machine */
+	tmp = getenv("ethaddr");
+	if (tmp) {
+		for (i = 0; i < 6; i++) {
+			MACaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+			if (tmp)
+				tmp = (*end) ? end + 1 : end;
+		}
+
+#ifndef CONFIG_NETCONSOLE
+		printf("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n",
+		       MACaddr[0], MACaddr[1],
+		       MACaddr[2], MACaddr[3], MACaddr[4], MACaddr[5]);
+#endif
+		*pEMAC_ADDRLO = MACaddr[0] | MACaddr[1] << 8 |
+		    MACaddr[2] << 16 | MACaddr[3] << 24;
+		*pEMAC_ADDRHI = MACaddr[4] | MACaddr[5] << 8;
+	}
+}
+
+void PollMdcDone(void)
+{
+	/* poll the STABUSY bit */
+	while (*pEMAC_STAADD & STABUSY) ;
+}
+
+void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
+{
+	PollMdcDone();
+
+	*pEMAC_STADAT = Data;
+
+	*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
+	    STAOP | STAIE | STABUSY;
+}
+
+/*********************************************************************************
+ *		Read an off-chip register in a PHY through the MDC/MDIO port     *
+ *********************************************************************************/
+u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
+{
+	u16 Data;
+
+	PollMdcDone();
+
+	*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
+	    STAIE | STABUSY;
+
+	PollMdcDone();
+
+	Data = (u16) * pEMAC_STADAT;
+
+	PHYregs[RegAddr] = Data;	/* save shadow copy */
+
+	return Data;
+}
+
+void SoftResetPHY(void)
+{
+	u16 phydat;
+	/* set the reset bit */
+	WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
+	/* and clear it again */
+	WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
+	do {
+		/* poll until reset is complete */
+		phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
+	} while ((phydat & PHY_RESET) != 0);
+}
+
+int SetupSystemRegs(int *opmode)
+{
+	u16 sysctl, phydat;
+	int count = 0;
+	/* Enable PHY output */
+	*pVR_CTL |= PHYCLKOE;
+	/* MDC  = 2.5 MHz */
+	sysctl = SET_MDCDIV(24);
+	/* Odd word alignment for Receive Frame DMA word */
+	/* Configure checksum support and rcve frame word alignment */
+	sysctl |= RXDWA | RXCKS;
+	*pEMAC_SYSCTL = sysctl;
+	/* auto negotiation on  */
+	/* full duplex */
+	/* 100 Mbps */
+	phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
+	WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
+	do {
+		udelay(1000);
+		phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
+		if (count > 3000) {
+			printf
+			    ("Link is down, please check your network connection\n");
+			return -1;
+		}
+		count++;
+	} while (!(phydat & 0x0004));
+
+	phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
+
+	if ((phydat & 0x0100) || (phydat & 0x0040))
+		*opmode = FDMODE;
+	else
+		*opmode = 0;
+
+	*pEMAC_MMC_CTL = RSTC | CROLL;
+
+	/* Initialize the TX DMA channel registers */
+	*pDMA2_X_COUNT = 0;
+	*pDMA2_X_MODIFY = 4;
+	*pDMA2_Y_COUNT = 0;
+	*pDMA2_Y_MODIFY = 0;
+
+	/* Initialize the RX DMA channel registers */
+	*pDMA1_X_COUNT = 0;
+	*pDMA1_X_MODIFY = 4;
+	*pDMA1_Y_COUNT = 0;
+	*pDMA1_Y_MODIFY = 0;
+	return 0;
+}
+
+ADI_ETHER_BUFFER *SetupRxBuffer(int no)
+{
+	ADI_ETHER_FRAME_BUFFER *frmbuf;
+	ADI_ETHER_BUFFER *buf;
+	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
+	int total_size = nobytes_buffer + RECV_BUFSIZE;
+
+	buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
+	frmbuf =
+	    (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
+					nobytes_buffer);
+
+	memset(buf, 0x00, nobytes_buffer);
+	buf->FrmData = frmbuf;
+	memset(frmbuf, 0xfe, RECV_BUFSIZE);
+
+	/* set up first desc to point to receive frame buffer */
+	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
+	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
+	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
+	buf->Dma[0].CONFIG.b_WNR = 1;	/* Write to memory */
+	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
+	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
+	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */
+
+	/* set up second desc to point to status word */
+	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
+	buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
+	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
+	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
+	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
+	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
+	buf->Dma[1].CONFIG.b_NDSIZE = 5;	/* must be 0 when FLOW is 0 */
+	buf->Dma[1].CONFIG.b_FLOW = 7;	/* stop */
+
+	return buf;
+}
+
+ADI_ETHER_BUFFER *SetupTxBuffer(int no)
+{
+	ADI_ETHER_FRAME_BUFFER *frmbuf;
+	ADI_ETHER_BUFFER *buf;
+	int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2;	/* ensure a multi. of 4 */
+	int total_size = nobytes_buffer + RECV_BUFSIZE;
+
+	buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
+	frmbuf =
+	    (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
+					nobytes_buffer);
+
+	memset(buf, 0x00, nobytes_buffer);
+	buf->FrmData = frmbuf;
+	memset(frmbuf, 0x00, RECV_BUFSIZE);
+
+	/* set up first desc to point to receive frame buffer */
+	buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
+	buf->Dma[0].START_ADDR = (u32) buf->FrmData;
+	buf->Dma[0].CONFIG.b_DMA_EN = 1;	/* enabled */
+	buf->Dma[0].CONFIG.b_WNR = 0;	/* Read to memory */
+	buf->Dma[0].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
+	buf->Dma[0].CONFIG.b_NDSIZE = 5;	/* 5 half words is desc size. */
+	buf->Dma[0].CONFIG.b_FLOW = 7;	/* large desc flow */
+
+	/* set up second desc to point to status word */
+	buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
+	buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
+	buf->Dma[1].CONFIG.b_DMA_EN = 1;	/* enabled */
+	buf->Dma[1].CONFIG.b_WNR = 1;	/* Write to memory */
+	buf->Dma[1].CONFIG.b_WDSIZE = 2;	/* wordsize is 32 bits */
+	buf->Dma[1].CONFIG.b_DI_EN = 1;	/* enable interrupt */
+	buf->Dma[1].CONFIG.b_NDSIZE = 0;	/* must be 0 when FLOW is 0 */
+	buf->Dma[1].CONFIG.b_FLOW = 0;	/* stop */
+
+	return buf;
+}
+
+#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
+int ether_post_test(int flags)
+{
+	uchar buf[64];
+	int i, value = 0;
+	int length;
+
+	printf("\n--------");
+	bfin_EMAC_init(NULL, NULL);
+	/* construct the package */
+	buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
+	buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
+	buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
+	buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
+	buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
+	buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
+	buf[12] = 0x08;		/* Type: ARP */
+	buf[13] = 0x06;
+	buf[14] = 0x00;		/* Hardware type: Ethernet */
+	buf[15] = 0x01;
+	buf[16] = 0x08;		/* Protocal type: IP */
+	buf[17] = 0x00;
+	buf[18] = 0x06;		/* Hardware size    */
+	buf[19] = 0x04;		/* Protocol size    */
+	buf[20] = 0x00;		/* Opcode: request  */
+	buf[21] = 0x01;
+
+	for (i = 0; i < 42; i++)
+		buf[i + 22] = i;
+	printf("--------Send 64 bytes......\n");
+	bfin_EMAC_send(NULL, (volatile void *)buf, 64);
+	for (i = 0; i < 100; i++) {
+		udelay(10000);
+		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
+			value = 1;
+			break;
+		}
+	}
+	if (value == 0) {
+		printf("--------EMAC can't receive any data\n");
+		eth_halt();
+		return -1;
+	}
+	length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
+	for (i = 0; i < length; i++) {
+		if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
+			printf("--------EMAC receive error data!\n");
+			eth_halt();
+			return -1;
+		}
+	}
+	printf("--------receive %d bytes, matched\n", length);
+	bfin_EMAC_halt(NULL);
+	return 0;
+}
+#endif
+#endif				/* CFG_CMD_NET */
diff --git a/board/bf537-stamp/ether_bf537.h b/board/bf537-stamp/ether_bf537.h
new file mode 100644
index 0000000..64240ba
--- /dev/null
+++ b/board/bf537-stamp/ether_bf537.h
@@ -0,0 +1,110 @@
+#define PHYADDR			0x01
+#define NO_PHY_REGS		0x20
+
+#define DEFAULT_PHY_PHYID1	0x0007
+#define DEFAULT_PHY_PHYID2	0xC0A3
+#define PHY_MODECTL		0x00
+#define PHY_MODESTAT		0x01
+#define PHY_PHYID1		0x02
+#define PHY_PHYID2		0x03
+#define PHY_ANAR		0x04
+#define PHY_ANLPAR		0x05
+#define PHY_ANER		0x06
+
+#define PHY_RESET		0x8000
+#define PHY_ANEG_EN		0x1000
+#define PHY_DUPLEX		0x0100
+#define PHY_SPD_SET		0x2000
+
+#define RECV_BUFSIZE		(0x614)
+
+typedef volatile u32 reg32;
+typedef volatile u16 reg16;
+
+typedef struct ADI_DMA_CONFIG_REG {
+	u16 b_DMA_EN:1;		/* 0	Enabled				*/
+	u16 b_WNR:1;		/* 1	Direction			*/
+	u16 b_WDSIZE:2;		/* 2:3	Transfer word size		*/
+	u16 b_DMA2D:1;		/* 4	DMA mode			*/
+	u16 b_RESTART:1;	/* 5	Retain FIFO			*/
+	u16 b_DI_SEL:1;		/* 6	Data interrupt timing select	*/
+	u16 b_DI_EN:1;		/* 7	Data interrupt enabled		*/
+	u16 b_NDSIZE:4;		/* 8:11	Flex descriptor size		*/
+	u16 b_FLOW:3;		/* 12:14Flow				*/
+} ADI_DMA_CONFIG_REG;
+
+typedef struct adi_ether_frame_buffer {
+	u16 NoBytes;		/* the no. of following bytes	*/
+	u8 Dest[6];		/* destination MAC address	*/
+	u8 Srce[6];		/* source MAC address		*/
+	u16 LTfield;		/* length/type field		*/
+	u8 Data[0];		/* payload bytes		*/
+} ADI_ETHER_FRAME_BUFFER;
+/* 16 bytes/struct	*/
+
+typedef struct dma_descriptor {
+	struct dma_descriptor *NEXT_DESC_PTR;
+	u32 START_ADDR;
+	ADI_DMA_CONFIG_REG CONFIG;
+} DMA_DESCRIPTOR;
+/* 10 bytes/struct in 12 bytes */
+
+typedef struct adi_ether_buffer {
+	DMA_DESCRIPTOR Dma[2];		/* first for the frame, second for the status */
+	ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
+	struct adi_ether_buffer *pNext;	/* next buffer */
+	struct adi_ether_buffer *pPrev;	/* prev buffer */
+	u16 IPHdrChksum;		/* the IP header checksum */
+	u16 IPPayloadChksum;		/* the IP header and payload checksum */
+	volatile u32 StatusWord;	/* the frame status word */
+} ADI_ETHER_BUFFER;
+/* 40 bytes/struct in 44 bytes */
+
+void SetupMacAddr(u8 * MACaddr);
+
+void PollMdcDone(void);
+void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
+u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
+void SoftResetPHY(void);
+void DumpPHYRegs(void);
+
+int SetupSystemRegs(int *opmode);
+
+/**
+ * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is all zeroes.
+ */
+static inline int is_zero_ether_addr(const u8 * addr)
+{
+	return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
+}
+
+/**
+ * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is a multicast address.
+ * By definition the broadcast address is also a multicast address.
+ */
+static inline int is_multicast_ether_addr(const u8 * addr)
+{
+	return (0x01 & addr[0]);
+}
+
+/**
+ * is_valid_ether_addr - Determine if the given Ethernet address is valid
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
+ * a multicast address, and is not FF:FF:FF:FF:FF:FF.
+ *
+ * Return true if the address is valid.
+ */
+static inline int is_valid_ether_addr(const u8 * addr)
+{
+	/* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
+	 * explicitly check for it here. */
+	return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
+}
diff --git a/board/bf537-stamp/flash-defines.h b/board/bf537-stamp/flash-defines.h
new file mode 100644
index 0000000..f19e171
--- /dev/null
+++ b/board/bf537-stamp/flash-defines.h
@@ -0,0 +1,123 @@
+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define V_ULONG(a)		(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)		(*(volatile unsigned char *)( a ))
+#define TRUE			0x1
+#define FALSE			0x0
+#define BUFFER_SIZE		0x80000
+#define NO_COMMAND		0
+#define GET_CODES		1
+#define RESET			2
+#define WRITE			3
+#define FILL			4
+#define ERASE_ALL		5
+#define ERASE_SECT		6
+#define READ			7
+#define GET_SECTNUM		8
+#define FLASH_START_L 		0x0000
+#define FLASH_START_H 		0x2000
+#define FLASH_MAN_ST 		2
+#define RESET_VAL		0xF0
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+int get_codes(void);
+int poll_toggle_bit(long lOffset);
+void reset_flash(void);
+int erase_flash(void);
+int erase_block_flash(int);
+void unlock_flash(long lOffset);
+int write_data(long lStart, long lCount, uchar * pnData);
+int read_flash(long nOffset, int *pnValue);
+int write_flash(long nOffset, int nValue);
+void get_sector_number(long lOffset, int *pnSector);
+int GetSectorProtectionStatus(flash_info_t * info, int nSector);
+int GetOffset(int nBlock);
+int AFP_NumSectors = 71;
+long AFP_SectorSize2 = 0x10000;
+int AFP_SectorSize1 = 0x2000;
+
+#define NUM_SECTORS		71
+
+#define WRITESEQ1		0x0AAA
+#define WRITESEQ2		0x0554
+#define WRITESEQ3		0x0AAA
+#define WRITESEQ4		0x0AAA
+#define WRITESEQ5		0x0554
+#define WRITESEQ6		0x0AAA
+#define WRITEDATA1		0xaa
+#define WRITEDATA2		0x55
+#define WRITEDATA3		0x80
+#define WRITEDATA4		0xaa
+#define WRITEDATA5		0x55
+#define WRITEDATA6		0x10
+#define PriFlashABegin		0
+#define SecFlashABegin		8
+#define SecFlashBBegin		36
+#define PriFlashAOff		0x0
+#define PriFlashBOff		0x100000
+#define SecFlashAOff		0x10000
+#define SecFlashBOff		0x280000
+#define INVALIDLOCNSTART	0x20270000
+#define INVALIDLOCNEND		0x20280000
+#define BlockEraseVal		0x30
+#define UNLOCKDATA1		0xaa
+#define UNLOCKDATA2		0x55
+#define UNLOCKDATA3		0xa0
+#define GETCODEDATA1		0xaa
+#define GETCODEDATA2		0x55
+#define GETCODEDATA3		0x90
+#define SecFlashASec1Off	0x200000
+#define SecFlashASec2Off	0x204000
+#define SecFlashASec3Off	0x206000
+#define SecFlashASec4Off	0x208000
+#define SecFlashAEndOff		0x210000
+#define SecFlashBSec1Off	0x280000
+#define SecFlashBSec2Off	0x284000
+#define SecFlashBSec3Off	0x286000
+#define SecFlashBSec4Off	0x288000
+#define SecFlashBEndOff		0x290000
+
+#define SECT32			32
+#define SECT33			33
+#define SECT34			34
+#define SECT35			35
+#define SECT36			36
+#define SECT37			37
+#define SECT38			38
+#define SECT39			39
+
+#define FLASH_SUCCESS	0
+#define FLASH_FAIL	-1
+
+#endif
diff --git a/board/bf537-stamp/flash.c b/board/bf537-stamp/flash.c
new file mode 100644
index 0000000..42dcf06
--- /dev/null
+++ b/board/bf537-stamp/flash.c
@@ -0,0 +1,403 @@
+/*
+ * U-boot - flash.c Flash driver for PSD4256GV
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <malloc.h>
+#include <config.h>
+#include <asm/io.h>
+#include "flash-defines.h"
+
+void flash_reset(void)
+{
+	reset_flash();
+}
+
+unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
+{
+	int id = 0, i = 0;
+	static int FlagDev = 1;
+
+	id = get_codes();
+	if (FlagDev) {
+		FlagDev = 0;
+	}
+	info->flash_id = id;
+	switch (bank_flag) {
+	case 0:
+		for (i = PriFlashABegin; i < SecFlashABegin; i++)
+			info->start[i] = (baseaddr + (i * AFP_SectorSize1));
+		for (i = SecFlashABegin; i < NUM_SECTORS; i++)
+			info->start[i] =
+			    (baseaddr + SecFlashAOff +
+			     ((i - SecFlashABegin) * AFP_SectorSize2));
+		info->size = 0x400000;
+		info->sector_count = NUM_SECTORS;
+		break;
+	case 1:
+		info->start[0] = baseaddr + SecFlashASec1Off;
+		info->start[1] = baseaddr + SecFlashASec2Off;
+		info->start[2] = baseaddr + SecFlashASec3Off;
+		info->start[3] = baseaddr + SecFlashASec4Off;
+		info->size = 0x10000;
+		info->sector_count = 4;
+		break;
+	case 2:
+		info->start[0] = baseaddr + SecFlashBSec1Off;
+		info->start[1] = baseaddr + SecFlashBSec2Off;
+		info->start[2] = baseaddr + SecFlashBSec3Off;
+		info->start[3] = baseaddr + SecFlashBSec4Off;
+		info->size = 0x10000;
+		info->sector_count = 4;
+		break;
+	}
+	return (info->size);
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b;
+	int i;
+
+	size_b = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b = flash_get_size(CFG_FLASH_BASE, &flash_info[0], 0);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b == 0) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		       size_b, size_b >> 20);
+	}
+
+	/* flash_protect (int flag, ulong from, ulong to, flash_info_t *info) */
+	(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,
+			    (flash_info[0].start[2] - 1), &flash_info[0]);
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+	(void)flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF,
+			    &flash_info[0]);
+#endif
+
+	return (size_b);
+}
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id) {
+	case (STM_ID_29W320EB & 0xFFFF):
+	case (STM_ID_29W320DB & 0xFFFF):
+		printf("ST Microelectronics ");
+		break;
+	default:
+		printf("Unknown Vendor: (0x%08X) ", info->flash_id);
+		break;
+	}
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+	return;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int cnt = 0, i;
+	int prot, sect;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	else
+		printf("\n");
+
+	cnt = s_last - s_first + 1;
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+	printf("Erasing Flash locations, Please Wait\n");
+	for (i = s_first; i <= s_last; i++) {
+		if (info->protect[i] == 0) {	/* not protected */
+			if (erase_block_flash(i) < 0) {
+				printf("Error Sector erasing \n");
+				return FLASH_FAIL;
+			}
+		}
+	}
+#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+	if (cnt == FLASH_TOT_SECT) {
+		printf("Erasing flash, Please Wait \n");
+		if (erase_flash() < 0) {
+			printf("Erasing flash failed \n");
+			return FLASH_FAIL;
+		}
+	} else {
+		printf("Erasing Flash locations, Please Wait\n");
+		for (i = s_first; i <= s_last; i++) {
+			if (info->protect[i] == 0) {	/* not protected */
+				if (erase_block_flash(i) < 0) {
+					printf("Error Sector erasing \n");
+					return FLASH_FAIL;
+				}
+			}
+		}
+	}
+#endif
+	printf("\n");
+	return FLASH_SUCCESS;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int d;
+	if (addr % 2) {
+		read_flash(addr - 1 - CFG_FLASH_BASE, &d);
+		d = (int)((d & 0x00FF) | (*src++ << 8));
+		write_data(addr - 1, 2, (uchar *) & d);
+		write_data(addr + 1, cnt - 1, src);
+	} else
+		write_data(addr, cnt, src);
+	return FLASH_SUCCESS;
+}
+
+int write_data(long lStart, long lCount, uchar * pnData)
+{
+	long i = 0;
+	unsigned long ulOffset = lStart - CFG_FLASH_BASE;
+	int d;
+	int nSector = 0;
+	int flag = 0;
+
+	if (lCount % 2) {
+		flag = 1;
+		lCount = lCount - 1;
+	}
+
+	for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset, &d);
+		if (d != 0xffff) {
+			printf
+			    ("Flash not erased at offset 0x%x Please erase to reprogram \n",
+			     ulOffset);
+			return FLASH_FAIL;
+		}
+		unlock_flash(ulOffset);
+		d = (int)(pnData[i] | pnData[i + 1] << 8);
+		write_flash(ulOffset, d);
+		if (poll_toggle_bit(ulOffset) < 0) {
+			printf("Error programming the flash \n");
+			return FLASH_FAIL;
+		}
+		if ((i > 0) && (!(i % AFP_SectorSize2)))
+			printf(".");
+	}
+	if (flag) {
+		get_sector_number(ulOffset, &nSector);
+		read_flash(ulOffset, &d);
+		if (d != 0xffff) {
+			printf
+			    ("Flash not erased at offset 0x%x Please erase to reprogram \n",
+			     ulOffset);
+			return FLASH_FAIL;
+		}
+		unlock_flash(ulOffset);
+		d = (int)(pnData[i] | (d & 0xFF00));
+		write_flash(ulOffset, d);
+		if (poll_toggle_bit(ulOffset) < 0) {
+			printf("Error programming the flash \n");
+			return FLASH_FAIL;
+		}
+	}
+	return FLASH_SUCCESS;
+}
+
+int write_flash(long nOffset, int nValue)
+{
+	long addr;
+
+	addr = (CFG_FLASH_BASE + nOffset);
+	*(unsigned volatile short *)addr = nValue;
+	sync();
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+	if (icache_status())
+		udelay(CONFIG_CCLK_HZ / 1000000);
+#endif
+	return FLASH_SUCCESS;
+}
+
+int read_flash(long nOffset, int *pnValue)
+{
+	unsigned short *pFlashAddr =
+	    (unsigned short *)(CFG_FLASH_BASE + nOffset);
+
+	*pnValue = *pFlashAddr;
+
+	return TRUE;
+}
+
+int poll_toggle_bit(long lOffset)
+{
+	unsigned int u1, u2;
+	volatile unsigned long *FB =
+	    (volatile unsigned long *)(CFG_FLASH_BASE + lOffset);
+	while (1) {
+		u1 = *(volatile unsigned short *)FB;
+		u2 = *(volatile unsigned short *)FB;
+		u1 ^= u2;
+		if (!(u1 & 0x0040))
+			break;
+		if (!(u2 & 0x0020))
+			continue;
+		else {
+			u1 = *(volatile unsigned short *)FB;
+			u2 = *(volatile unsigned short *)FB;
+			u1 ^= u2;
+			if (!(u1 & 0x0040))
+				break;
+			else {
+				reset_flash();
+				return FLASH_FAIL;
+			}
+		}
+	}
+	return FLASH_SUCCESS;
+}
+
+void reset_flash(void)
+{
+	write_flash(WRITESEQ1, RESET_VAL);
+	/* Wait for 10 micro seconds */
+	udelay(10);
+}
+
+int erase_flash(void)
+{
+	write_flash(WRITESEQ1, WRITEDATA1);
+	write_flash(WRITESEQ2, WRITEDATA2);
+	write_flash(WRITESEQ3, WRITEDATA3);
+	write_flash(WRITESEQ4, WRITEDATA4);
+	write_flash(WRITESEQ5, WRITEDATA5);
+	write_flash(WRITESEQ6, WRITEDATA6);
+
+	if (poll_toggle_bit(0x0000) < 0)
+		return FLASH_FAIL;
+
+	return FLASH_SUCCESS;
+}
+
+int erase_block_flash(int nBlock)
+{
+	long ulSectorOff = 0x0;
+
+	if ((nBlock < 0) || (nBlock > AFP_NumSectors))
+		return FALSE;
+
+	/* figure out the offset of the block in flash */
+	if ((nBlock >= 0) && (nBlock < SecFlashABegin))
+		ulSectorOff = nBlock * AFP_SectorSize1;
+
+	else if ((nBlock >= SecFlashABegin) && (nBlock < NUM_SECTORS))
+		ulSectorOff =
+		    SecFlashAOff + (nBlock - SecFlashABegin) * AFP_SectorSize2;
+	/* no such sector */
+	else
+		return FLASH_FAIL;
+
+	write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
+	write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
+	write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
+	write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
+	write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
+
+	write_flash(ulSectorOff, BlockEraseVal);
+
+	if (poll_toggle_bit(ulSectorOff) < 0)
+		return FLASH_FAIL;
+	printf(".");
+
+	return FLASH_SUCCESS;
+}
+
+void unlock_flash(long ulOffset)
+{
+	unsigned long ulOffsetAddr = ulOffset;
+	ulOffsetAddr &= 0xFFFF0000;
+
+	write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
+	write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
+	write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
+}
+
+int get_codes()
+{
+	int dev_id = 0;
+
+	write_flash(WRITESEQ1, GETCODEDATA1);
+	write_flash(WRITESEQ2, GETCODEDATA2);
+	write_flash(WRITESEQ3, GETCODEDATA3);
+
+	read_flash(0x0402, &dev_id);
+	dev_id &= 0x0000FFFF;
+
+	reset_flash();
+
+	return dev_id;
+}
+
+void get_sector_number(long ulOffset, int *pnSector)
+{
+	int nSector = 0;
+	long lMainEnd = 0x400000;
+	long lBootEnd = 0x10000;
+
+	/* sector numbers for the FLASH A boot sectors */
+	if (ulOffset < lBootEnd) {
+		nSector = (int)ulOffset / AFP_SectorSize1;
+	}
+	/* sector numbers for the FLASH B boot sectors */
+	else if ((ulOffset >= lBootEnd) && (ulOffset < lMainEnd)) {
+		nSector = ((ulOffset / (AFP_SectorSize2)) + 7);
+	}
+	/* if it is a valid sector, set it */
+	if ((nSector >= 0) && (nSector < AFP_NumSectors))
+		*pnSector = nSector;
+
+}
diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c
new file mode 100644
index 0000000..4d6e776
--- /dev/null
+++ b/board/bf537-stamp/nand.c
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2006 Aubrey.Li, aubrey.li@analog.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+
+#define CONCAT(a,b,c,d) a ## b ## c ## d
+#define PORT(a,b)  CONCAT(pPORT,a,b,)
+
+#ifndef CONFIG_NAND_GPIO_PORT
+#define CONFIG_NAND_GPIO_PORT F
+#endif
+
+/*
+ * hardware specific access to control-lines
+ */
+static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	register struct nand_chip *this = mtd->priv;
+
+	switch (cmd) {
+
+	case NAND_CTL_SETCLE:
+		this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
+		break;
+	case NAND_CTL_CLRCLE:
+		this->IO_ADDR_W = CFG_NAND_BASE;
+		break;
+
+	case NAND_CTL_SETALE:
+		this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
+		break;
+	case NAND_CTL_CLRALE:
+		this->IO_ADDR_W = CFG_NAND_BASE;
+		break;
+	case NAND_CTL_SETNCE:
+	case NAND_CTL_CLRNCE:
+		break;
+	}
+
+	this->IO_ADDR_R = this->IO_ADDR_W;
+
+	/* Drain the writebuffer */
+	sync();
+}
+
+int bfin_device_ready(struct mtd_info *mtd)
+{
+	int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
+	sync();
+	return ret;
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for  accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
+ *   only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ *   read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ *   nand_scan about special functionality. See the defines for further
+ *   explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+	*PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
+	*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
+	*PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
+
+	nand->hwcontrol = bfin_hwcontrol;
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->dev_ready = bfin_device_ready;
+	nand->chip_delay = 30;
+}
+#endif				/* (CONFIG_COMMANDS & CFG_CMD_NAND) */
diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
new file mode 100644
index 0000000..6039350
--- /dev/null
+++ b/board/bf537-stamp/post-memory.c
@@ -0,0 +1,322 @@
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_POST
+
+#include <post.h>
+#include <watchdog.h>
+
+#if CONFIG_POST & CFG_POST_MEMORY
+#define CLKIN 25000000
+#define PATTERN1 0x5A5A5A5A
+#define PATTERN2 0xAAAAAAAA
+
+#define CCLK_NUM	4
+#define SCLK_NUM	3
+
+void post_out_buff(char *buff);
+int post_key_pressed(void);
+void post_init_pll(int mult, int div);
+int post_init_sdram(int sclk);
+void post_init_uart(int sclk);
+
+const int pll[CCLK_NUM][SCLK_NUM][2] = {
+	{{20, 4}, {20, 5}, {20, 10}},	/* CCLK = 500M */
+	{{16, 4}, {16, 5}, {16, 8}},	/* CCLK = 400M */
+	{{8, 2}, {8, 4}, {8, 5}},	/* CCLK = 200M */
+	{{4, 1}, {4, 2}, {4, 4}}	/* CCLK = 100M */
+};
+const char *const log[CCLK_NUM][SCLK_NUM] = {
+	{"CCLK-500Mhz SCLK-125Mhz:    Writing...\0",
+	 "CCLK-500Mhz SCLK-100Mhz:    Writing...\0",
+	 "CCLK-500Mhz SCLK- 50Mhz:    Writing...\0",},
+	{"CCLK-400Mhz SCLK-100Mhz:    Writing...\0",
+	 "CCLK-400Mhz SCLK- 80Mhz:    Writing...\0",
+	 "CCLK-400Mhz SCLK- 50Mhz:    Writing...\0",},
+	{"CCLK-200Mhz SCLK-100Mhz:    Writing...\0",
+	 "CCLK-200Mhz SCLK- 50Mhz:    Writing...\0",
+	 "CCLK-200Mhz SCLK- 40Mhz:    Writing...\0",},
+	{"CCLK-100Mhz SCLK-100Mhz:    Writing...\0",
+	 "CCLK-100Mhz SCLK- 50Mhz:    Writing...\0",
+	 "CCLK-100Mhz SCLK- 25Mhz:    Writing...\0",},
+};
+
+int memory_post_test(int flags)
+{
+	int addr;
+	int m, n;
+	int sclk, sclk_temp;
+	int ret = 1;
+
+	sclk_temp = CLKIN / 1000000;
+	sclk_temp = sclk_temp * CONFIG_VCO_MULT;
+	for (sclk = 0; sclk_temp > 0; sclk++)
+		sclk_temp -= CONFIG_SCLK_DIV;
+	sclk = sclk * 1000000;
+	post_init_uart(sclk);
+	if (post_key_pressed() == 0)
+		return 0;
+
+	for (m = 0; m < CCLK_NUM; m++) {
+		for (n = 0; n < SCLK_NUM; n++) {
+			/* Calculate the sclk */
+			sclk_temp = CLKIN / 1000000;
+			sclk_temp = sclk_temp * pll[m][n][0];
+			for (sclk = 0; sclk_temp > 0; sclk++)
+				sclk_temp -= pll[m][n][1];
+			sclk = sclk * 1000000;
+
+			post_init_pll(pll[m][n][0], pll[m][n][1]);
+			post_init_sdram(sclk);
+			post_init_uart(sclk);
+			post_out_buff("\n\r\0");
+			post_out_buff(log[m][n]);
+			for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4)
+				*(unsigned long *)addr = PATTERN1;
+			post_out_buff("Reading...\0");
+			for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) {
+				if ((*(unsigned long *)addr) != PATTERN1) {
+					post_out_buff("Error\n\r\0");
+					ret = 0;
+				}
+			}
+			post_out_buff("OK\n\r\0");
+		}
+	}
+	if (ret)
+		post_out_buff("memory POST passed\n\r\0");
+	else
+		post_out_buff("memory POST failed\n\r\0");
+
+	post_out_buff("\n\r\n\r\0");
+	return 1;
+}
+
+void post_init_uart(int sclk)
+{
+	int divisor;
+
+	for (divisor = 0; sclk > 0; divisor++)
+		sclk -= 57600 * 16;
+
+	*pPORTF_FER = 0x000F;
+	*pPORTH_FER = 0xFFFF;
+
+	*pUART_GCTL = 0x00;
+	*pUART_LCR = 0x83;
+	sync();
+	*pUART_DLL = (divisor & 0xFF);
+	sync();
+	*pUART_DLH = ((divisor >> 8) & 0xFF);
+	sync();
+	*pUART_LCR = 0x03;
+	sync();
+	*pUART_GCTL = 0x01;
+	sync();
+}
+
+void post_out_buff(char *buff)
+{
+
+	int i = 0;
+	for (i = 0; i < 0x80000; i++) ;
+	i = 0;
+	while ((buff[i] != '\0') && (i != 100)) {
+		while (!(*pUART_LSR & 0x20)) ;
+		*pUART_THR = buff[i];
+		sync();
+		i++;
+	}
+	for (i = 0; i < 0x80000; i++) ;
+}
+
+/* Using sw10-PF5 as the hotkey */
+#define KEY_LOOP 0x80000
+#define KEY_DELAY 0x80
+int post_key_pressed(void)
+{
+	int i, n;
+	unsigned short value;
+
+	*pPORTF_FER &= ~PF5;
+	*pPORTFIO_DIR &= ~PF5;
+	*pPORTFIO_INEN |= PF5;
+	sync();
+
+	post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
+	for (i = 0; i < KEY_LOOP; i++) {
+		value = *pPORTFIO & PF5;
+		if (*pUART0_RBR == 0x0D) {
+			value = 0;
+			goto key_pressed;
+		}
+		if (value != 0) {
+			goto key_pressed;
+		}
+		for (n = 0; n < KEY_DELAY; n++)
+			asm("nop");
+	}
+	post_out_buff("\b2\0");
+
+	for (i = 0; i < KEY_LOOP; i++) {
+		value = *pPORTFIO & PF5;
+		if (*pUART0_RBR == 0x0D) {
+			value = 0;
+			goto key_pressed;
+		}
+		if (value != 0) {
+			goto key_pressed;
+		}
+		for (n = 0; n < KEY_DELAY; n++)
+			asm("nop");
+	}
+	post_out_buff("\b1\0");
+
+	for (i = 0; i < KEY_LOOP; i++) {
+		value = *pPORTFIO & PF5;
+		if (*pUART0_RBR == 0x0D) {
+			value = 0;
+			goto key_pressed;
+		}
+		if (value != 0) {
+			goto key_pressed;
+		}
+		for (n = 0; n < KEY_DELAY; n++)
+			asm("nop");
+	}
+      key_pressed:
+	post_out_buff("\b0");
+	post_out_buff("\n\r\0");
+	if (value == 0)
+		return 0;
+	post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
+	return 1;
+}
+
+void post_init_pll(int mult, int div)
+{
+
+	*pSIC_IWR = 0x01;
+	*pPLL_CTL = (mult << 9);
+	*pPLL_DIV = div;
+	asm("CLI R2;");
+	asm("IDLE;");
+	asm("STI R2;");
+	while (!(*pPLL_STAT & 0x20)) ;
+}
+
+int post_init_sdram(int sclk)
+{
+	int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
+	    SDRAM_tWR;
+	int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
+	    mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
+
+	if ((sclk > 119402985)) {
+		SDRAM_tRP = TRP_2;
+		SDRAM_tRP_num = 2;
+		SDRAM_tRAS = TRAS_7;
+		SDRAM_tRAS_num = 7;
+		SDRAM_tRCD = TRCD_2;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 104477612) && (sclk <= 119402985)) {
+		SDRAM_tRP = TRP_2;
+		SDRAM_tRP_num = 2;
+		SDRAM_tRAS = TRAS_6;
+		SDRAM_tRAS_num = 6;
+		SDRAM_tRCD = TRCD_2;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 89552239) && (sclk <= 104477612)) {
+		SDRAM_tRP = TRP_2;
+		SDRAM_tRP_num = 2;
+		SDRAM_tRAS = TRAS_5;
+		SDRAM_tRAS_num = 5;
+		SDRAM_tRCD = TRCD_2;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 74626866) && (sclk <= 89552239)) {
+		SDRAM_tRP = TRP_2;
+		SDRAM_tRP_num = 2;
+		SDRAM_tRAS = TRAS_4;
+		SDRAM_tRAS_num = 4;
+		SDRAM_tRCD = TRCD_2;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 66666667) && (sclk <= 74626866)) {
+		SDRAM_tRP = TRP_2;
+		SDRAM_tRP_num = 2;
+		SDRAM_tRAS = TRAS_3;
+		SDRAM_tRAS_num = 3;
+		SDRAM_tRCD = TRCD_2;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 59701493) && (sclk <= 66666667)) {
+		SDRAM_tRP = TRP_1;
+		SDRAM_tRP_num = 1;
+		SDRAM_tRAS = TRAS_4;
+		SDRAM_tRAS_num = 4;
+		SDRAM_tRCD = TRCD_1;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 44776119) && (sclk <= 59701493)) {
+		SDRAM_tRP = TRP_1;
+		SDRAM_tRP_num = 1;
+		SDRAM_tRAS = TRAS_3;
+		SDRAM_tRAS_num = 3;
+		SDRAM_tRCD = TRCD_1;
+		SDRAM_tWR = TWR_2;
+	} else if ((sclk > 29850746) && (sclk <= 44776119)) {
+		SDRAM_tRP = TRP_1;
+		SDRAM_tRP_num = 1;
+		SDRAM_tRAS = TRAS_2;
+		SDRAM_tRAS_num = 2;
+		SDRAM_tRCD = TRCD_1;
+		SDRAM_tWR = TWR_2;
+	} else if (sclk <= 29850746) {
+		SDRAM_tRP = TRP_1;
+		SDRAM_tRP_num = 1;
+		SDRAM_tRAS = TRAS_1;
+		SDRAM_tRAS_num = 1;
+		SDRAM_tRCD = TRCD_1;
+		SDRAM_tWR = TWR_2;
+	} else {
+		SDRAM_tRP = TRP_1;
+		SDRAM_tRP_num = 1;
+		SDRAM_tRAS = TRAS_1;
+		SDRAM_tRAS_num = 1;
+		SDRAM_tRCD = TRCD_1;
+		SDRAM_tWR = TWR_2;
+	}
+	/*SDRAM INFORMATION: */
+	SDRAM_Tref = 64;	/* Refresh period in milliseconds */
+	SDRAM_NRA = 4096;	/* Number of row addresses in SDRAM */
+	SDRAM_CL = CL_3;	/* 2 */
+
+	SDRAM_SIZE = EBSZ_64;
+	SDRAM_WIDTH = EBCAW_10;
+
+	mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
+
+	/* Equation from section 17 (p17-46) of BF533 HRM */
+	mem_SDRRC =
+	    (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
+	    (SDRAM_tRAS_num + SDRAM_tRP_num);
+
+	/* Enable SCLK Out */
+	mem_SDGCTL =
+	    (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
+	     | PSS);
+
+	sync();
+
+	*pEBIU_SDGCTL |= 0x1000000;
+	/* Set the SDRAM Refresh Rate control register based on SSCLK value */
+	*pEBIU_SDRRC = mem_SDRRC;
+
+	/* SDRAM Memory Bank Control Register */
+	*pEBIU_SDBCTL = mem_SDBCTL;
+
+	/* SDRAM Memory Global Control Register */
+	*pEBIU_SDGCTL = mem_SDGCTL;
+	sync();
+	return mem_SDRRC;
+}
+
+#endif				/* CONFIG_POST & CFG_POST_MEMORY */
+#endif				/* CONFIG_POST */
diff --git a/board/bf537-stamp/stm_m25p64.c b/board/bf537-stamp/stm_m25p64.c
new file mode 100644
index 0000000..7077e85
--- /dev/null
+++ b/board/bf537-stamp/stm_m25p64.c
@@ -0,0 +1,515 @@
+/****************************************************************************
+ *  SPI flash driver for M25P64
+ ****************************************************************************/
+#include <common.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_SPI)
+
+/* Application definitions */
+
+#define	NUM_SECTORS 	128	/* number of sectors */
+#define SECTOR_SIZE	0x10000
+#define NOP_NUM		1000
+
+#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /* Settings to the SPI_CTL */
+#define TIMOD01 (0x01)	/* stes the SPI to work with core instructions */
+
+/* Flash commands */
+#define	SPI_WREN	(0x06)	/*Set Write Enable Latch */
+#define	SPI_WRDI	(0x04)	/*Reset Write Enable Latch */
+#define	SPI_RDSR	(0x05)	/*Read Status Register */
+#define	SPI_WRSR	(0x01)	/*Write Status Register */
+#define	SPI_READ	(0x03)	/*Read data from memory */
+#define	SPI_FAST_READ	(0x0B)	/*Read data from memory */
+#define	SPI_PP		(0x02)	/*Program Data into memory */
+#define	SPI_SE		(0xD8)	/*Erase one sector in memory */
+#define	SPI_BE		(0xC7)	/*Erase all memory */
+#define	WIP		(0x1)	/*Check the write in progress bit of the SPI status register */
+#define	WEL		(0x2)	/*Check the write enable bit of the SPI status register */
+
+#define	TIMEOUT		350000000
+
+typedef enum {
+	NO_ERR,
+	POLL_TIMEOUT,
+	INVALID_SECTOR,
+	INVALID_BLOCK,
+} ERROR_CODE;
+
+void spi_init_f(void);
+void spi_init_r(void);
+ssize_t spi_read(uchar *, int, uchar *, int);
+ssize_t spi_write(uchar *, int, uchar *, int);
+
+char ReadStatusRegister(void);
+void Wait_For_SPIF(void);
+void SetupSPI(const int spi_setting);
+void SPI_OFF(void);
+void SendSingleCommand(const int iCommand);
+
+ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
+ERROR_CODE EraseBlock(int nBlock);
+ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
+ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
+ERROR_CODE Wait_For_Status(char Statusbit);
+ERROR_CODE Wait_For_WEL(void);
+
+/*
+ * Function:    spi_init_f
+ * Description: Init SPI-Controller (ROM part)
+ * return:      ---
+ */
+void spi_init_f(void)
+{
+}
+
+/*
+ * Function:    spi_init_r
+ * Description: Init SPI-Controller (RAM part) -
+ *		 The malloc engine is ready and we can move our buffers to
+ *		 normal RAM
+ *  return:      ---
+ */
+void spi_init_r(void)
+{
+	return;
+}
+
+/*
+ * Function:    spi_write
+ */
+ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
+{
+	unsigned long offset;
+	int start_block, end_block;
+	int start_byte, end_byte;
+	ERROR_CODE result = NO_ERR;
+	uchar temp[SECTOR_SIZE];
+	int i, num;
+
+	offset = addr[0] << 16 | addr[1] << 8 | addr[2];
+	/* Get the start block number */
+	result = GetSectorNumber(offset, &start_block);
+	if (result == INVALID_SECTOR) {
+		printf("Invalid sector! ");
+		return 0;
+	}
+	/* Get the end block number */
+	result = GetSectorNumber(offset + len - 1, &end_block);
+	if (result == INVALID_SECTOR) {
+		printf("Invalid sector! ");
+		return 0;
+	}
+
+	for (num = start_block; num <= end_block; num++) {
+		ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
+		start_byte = num * SECTOR_SIZE;
+		end_byte = (num + 1) * SECTOR_SIZE - 1;
+		if (start_byte < offset)
+			start_byte = offset;
+		if (end_byte > (offset + len))
+			end_byte = (offset + len - 1);
+		for (i = start_byte; i <= end_byte; i++)
+			temp[i - num * SECTOR_SIZE] = buffer[i - offset];
+		EraseBlock(num);
+		result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
+		if (result != NO_ERR)
+			return 0;
+		printf(".");
+	}
+	return len;
+}
+
+/*
+ * Function: spi_read
+ */
+ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
+{
+	unsigned long offset;
+	offset = addr[0] << 16 | addr[1] << 8 | addr[2];
+	ReadData(offset, len, (int *)buffer);
+	return len;
+}
+
+void SendSingleCommand(const int iCommand)
+{
+	unsigned short dummy;
+
+	/* turns on the SPI in single write mode */
+	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+
+	/* sends the actual command to the SPI TX register */
+	*pSPI_TDBR = iCommand;
+	sync();
+
+	/* The SPI status register will be polled to check the SPIF bit */
+	Wait_For_SPIF();
+
+	dummy = *pSPI_RDBR;
+
+	/* The SPI will be turned off */
+	SPI_OFF();
+
+}
+
+void SetupSPI(const int spi_setting)
+{
+
+	if (icache_status() || dcache_status())
+		udelay(CONFIG_CCLK_HZ / 50000000);
+	/*sets up the PF10 to be the slave select of the SPI */
+	*pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
+	*pSPI_FLG = 0xFF02;
+	*pSPI_BAUD = CONFIG_SPI_BAUD;
+	*pSPI_CTL = spi_setting;
+	sync();
+
+	*pSPI_FLG = 0xFD02;
+	sync();
+}
+
+void SPI_OFF(void)
+{
+
+	*pSPI_CTL = 0x0400;	/* disable SPI */
+	*pSPI_FLG = 0;
+	*pSPI_BAUD = 0;
+	sync();
+	udelay(CONFIG_CCLK_HZ / 50000000);
+
+}
+
+void Wait_For_SPIF(void)
+{
+	unsigned short dummyread;
+	while ((*pSPI_STAT & TXS)) ;
+	while (!(*pSPI_STAT & SPIF)) ;
+	while (!(*pSPI_STAT & RXS)) ;
+	/* Read dummy to empty the receive register */
+	dummyread = *pSPI_RDBR;
+}
+
+ERROR_CODE Wait_For_WEL(void)
+{
+	int i;
+	char status_register = 0;
+	ERROR_CODE ErrorCode = NO_ERR;
+
+	for (i = 0; i < TIMEOUT; i++) {
+		status_register = ReadStatusRegister();
+		if ((status_register & WEL)) {
+			ErrorCode = NO_ERR;
+			break;
+		}
+		ErrorCode = POLL_TIMEOUT;	/* Time out error */
+	};
+
+	return ErrorCode;
+}
+
+ERROR_CODE Wait_For_Status(char Statusbit)
+{
+	int i;
+	char status_register = 0xFF;
+	ERROR_CODE ErrorCode = NO_ERR;
+
+	for (i = 0; i < TIMEOUT; i++) {
+		status_register = ReadStatusRegister();
+		if (!(status_register & Statusbit)) {
+			ErrorCode = NO_ERR;
+			break;
+		}
+		ErrorCode = POLL_TIMEOUT;	/* Time out error */
+	};
+
+	return ErrorCode;
+}
+
+char ReadStatusRegister(void)
+{
+	char status_register = 0;
+
+	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));	/* Turn on the SPI */
+
+	*pSPI_TDBR = SPI_RDSR;	/* send instruction to read status register */
+	sync();
+	Wait_For_SPIF();	/*wait until the instruction has been sent */
+	*pSPI_TDBR = 0;		/*send dummy to receive the status register */
+	sync();
+	Wait_For_SPIF();	/*wait until the data has been sent */
+	status_register = *pSPI_RDBR;	/*read the status register */
+
+	SPI_OFF();		/* Turn off the SPI */
+
+	return status_register;
+}
+
+ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
+{
+	int nSector = 0;
+	ERROR_CODE ErrorCode = NO_ERR;
+
+	if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
+		ErrorCode = INVALID_SECTOR;
+		return ErrorCode;
+	}
+
+	nSector = (int)ulOffset / 0x10000;
+	*pnSector = nSector;
+
+	return ErrorCode;
+}
+
+ERROR_CODE EraseBlock(int nBlock)
+{
+	unsigned long ulSectorOff = 0x0, ShiftValue;
+	ERROR_CODE ErrorCode = NO_ERR;
+
+	/* if the block is invalid just return */
+	if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
+		ErrorCode = INVALID_BLOCK;
+		return ErrorCode;
+	}
+	/* figure out the offset of the block in flash */
+	if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
+		ulSectorOff = (nBlock * SECTOR_SIZE);
+
+	} else {
+		ErrorCode = INVALID_BLOCK;
+		return ErrorCode;
+	}
+
+	/* A write enable instruction must previously have been executed */
+	SendSingleCommand(SPI_WREN);
+
+	/* The status register will be polled to check the write enable latch "WREN" */
+	ErrorCode = Wait_For_WEL();
+
+	if (POLL_TIMEOUT == ErrorCode) {
+		printf("SPI Erase block error\n");
+		return ErrorCode;
+	} else
+
+	/* Turn on the SPI to send single commands */
+	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+
+	/*
+	 * Send the erase block command to the flash followed by the 24 address
+	 * to point to the start of a sector
+	 */
+	*pSPI_TDBR = SPI_SE;
+	sync();
+	Wait_For_SPIF();
+	/* Send the highest byte of the 24 bit address at first */
+	ShiftValue = (ulSectorOff >> 16);
+	*pSPI_TDBR = ShiftValue;
+	sync();
+	/* Wait until the instruction has been sent */
+	Wait_For_SPIF();
+	/* Send the middle byte of the 24 bit address  at second */
+	ShiftValue = (ulSectorOff >> 8);
+	*pSPI_TDBR = ShiftValue;
+	sync();
+	/* Wait until the instruction has been sent */
+	Wait_For_SPIF();
+	/* Send the lowest byte of the 24 bit address finally */
+	*pSPI_TDBR = ulSectorOff;
+	sync();
+	/* Wait until the instruction has been sent */
+	Wait_For_SPIF();
+
+	/* Turns off the SPI */
+	SPI_OFF();
+
+	/* Poll the status register to check the Write in Progress bit */
+	/* Sector erase takes time */
+	ErrorCode = Wait_For_Status(WIP);
+
+	/* block erase should be complete */
+	return ErrorCode;
+}
+
+/*
+ * ERROR_CODE ReadData()
+ * Read a value from flash for verify purpose
+ * Inputs:	unsigned long ulStart - holds the SPI start address
+ *			int pnData - pointer to store value read from flash
+ *			long lCount - number of elements to read
+ */
+ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
+{
+	unsigned long ShiftValue;
+	char *cnData;
+	int i;
+
+	/* Pointer cast to be able to increment byte wise */
+
+	cnData = (char *)pnData;
+	/* Start SPI interface */
+	SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+
+#ifdef CONFIG_SPI_FLASH_FAST_READ
+	/* Send the read command to SPI device */
+	*pSPI_TDBR = SPI_FAST_READ;
+#else
+	/* Send the read command to SPI device */
+	*pSPI_TDBR = SPI_READ;
+#endif
+	sync();
+	/* Wait until the instruction has been sent */
+	Wait_For_SPIF();
+	/* Send the highest byte of the 24 bit address at first */
+	ShiftValue = (ulStart >> 16);
+	/* Send the byte to the SPI device */
+	*pSPI_TDBR = ShiftValue;
+	sync();
+	/* Wait until the instruction has been sent */
+	Wait_For_SPIF();
+	/* Send the middle byte of the 24 bit address  at second */
+	ShiftValue = (ulStart >> 8);
+	/* Send the byte to the SPI device */
+	*pSPI_TDBR = ShiftValue;
+	sync();
+	/* Wait until the instruction has been sent */
+	Wait_For_SPIF();
+	/* Send the lowest byte of the 24 bit address finally */
+	*pSPI_TDBR = ulStart;
+	sync();
+	/* Wait until the instruction has been sent */
+	Wait_For_SPIF();
+
+#ifdef CONFIG_SPI_FLASH_FAST_READ
+	/* Send dummy for FAST_READ */
+	*pSPI_TDBR = 0;
+	sync();
+	/* Wait until the instruction has been sent */
+	Wait_For_SPIF();
+#endif
+
+	/* After the SPI device address has been placed on the MOSI pin the data can be */
+	/* received on the MISO pin. */
+	for (i = 0; i < lCount; i++) {
+		*pSPI_TDBR = 0;
+		sync();
+		while (!(*pSPI_STAT & RXS)) ;
+		*cnData++ = *pSPI_RDBR;
+
+		if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
+			printf(".");
+	}
+
+	/* Turn off the SPI */
+	SPI_OFF();
+
+	return NO_ERR;
+}
+
+ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
+		      int *iDataSource, long *lWriteCount)
+{
+
+	unsigned long ulWAddr;
+	long lWTransferCount = 0;
+	int i;
+	char iData;
+	char *temp = (char *)iDataSource;
+	ERROR_CODE ErrorCode = NO_ERR;
+
+	/* First, a Write Enable Command must be sent to the SPI. */
+	SendSingleCommand(SPI_WREN);
+
+	/*
+	 * Second, the SPI Status Register will be tested whether the
+	 * Write Enable Bit has been set
+	 */
+	ErrorCode = Wait_For_WEL();
+	if (POLL_TIMEOUT == ErrorCode) {
+		printf("SPI Write Time Out\n");
+		return ErrorCode;
+	} else
+		/* Third, the 24 bit address will be shifted out
+		 * the SPI MOSI bytewise.
+		 * Turns the SPI on
+		 */
+		SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
+	*pSPI_TDBR = SPI_PP;
+	sync();
+	/*wait until the instruction has been sent */
+	Wait_For_SPIF();
+	ulWAddr = (ulStartAddr >> 16);
+	*pSPI_TDBR = ulWAddr;
+	sync();
+	/*wait until the instruction has been sent */
+	Wait_For_SPIF();
+	ulWAddr = (ulStartAddr >> 8);
+	*pSPI_TDBR = ulWAddr;
+	sync();
+	/*wait until the instruction has been sent */
+	Wait_For_SPIF();
+	ulWAddr = ulStartAddr;
+	*pSPI_TDBR = ulWAddr;
+	sync();
+	/*wait until the instruction has been sent */
+	Wait_For_SPIF();
+	/*
+	 * Fourth, maximum number of 256 bytes will be taken from the Buffer
+	 * and sent to the SPI device.
+	 */
+	for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
+		iData = *temp;
+		*pSPI_TDBR = iData;
+		sync();
+		/*wait until the instruction has been sent */
+		Wait_For_SPIF();
+		temp++;
+	}
+
+	/* Turns the SPI off */
+	SPI_OFF();
+
+	/*
+	 * Sixth, the SPI Write in Progress Bit must be toggled to ensure the
+	 * programming is done before start of next transfer
+	 */
+	ErrorCode = Wait_For_Status(WIP);
+
+	if (POLL_TIMEOUT == ErrorCode) {
+		printf("SPI Program Time out!\n");
+		return ErrorCode;
+	} else
+
+		*lWriteCount = lWTransferCount;
+
+	return ErrorCode;
+}
+
+ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
+{
+
+	unsigned long ulWStart = ulStart;
+	long lWCount = lCount, lWriteCount;
+	long *pnWriteCount = &lWriteCount;
+
+	ERROR_CODE ErrorCode = NO_ERR;
+
+	while (lWCount != 0) {
+		ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
+
+		/*
+		 * After each function call of WriteFlash the counter
+		 * must be adjusted
+		 */
+		lWCount -= *pnWriteCount;
+
+		/* Also, both address pointers must be recalculated. */
+		ulWStart += *pnWriteCount;
+		pnData += *pnWriteCount / 4;
+	}
+
+	/* return the appropriate error code */
+	return ErrorCode;
+}
+
+#endif				/* CONFIG_SPI */
diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S
new file mode 100644
index 0000000..3fb2d0c
--- /dev/null
+++ b/board/bf537-stamp/u-boot.lds.S
@@ -0,0 +1,190 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2007 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+MEMORY
+ {
+ ram : 	   ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
+ l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
+ l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
+ }
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS; /*0x1000;*/
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  . = CFG_MONITOR_BASE;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector before the environment sector. If it throws 	*/
+    /* an error during compilation remove an object here to get	*/
+    /* it linked after the configuration sector.		*/
+
+    cpu/bf537/start.o		(.text)
+    cpu/bf537/start1.o		(.text)
+    cpu/bf537/traps.o		(.text)
+    cpu/bf537/interrupt.o	(.text)
+    cpu/bf537/serial.o		(.text)
+    common/dlmalloc.o		(.text)
+/*  lib_blackfin/bf533_string.o	(.text) */
+/*  lib_generic/vsprintf.o	(.text) */
+    lib_generic/crc32.o		(.text)
+/*  lib_generic/zlib.o		(.text) */
+/*  board/bf537-stamp/bf537-stamp.o		(.text) */
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .text)
+    *(.fixup)
+    *(.got1)
+  }  > ram
+  _etext = .;
+  PROVIDE (etext = .);
+  .text_l1	:
+  {
+  . = ALIGN(4) ;
+  _text_l1 = .;
+  PROVIDE (text_l1 = .);
+  board/bf537-stamp/post-memory.o   (.text)
+  . = ALIGN(4) ;
+  _etext_l1 = .;
+  PROVIDE (etext_l1 = .);
+  } > l1_code AT > ram
+
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata)
+    *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata1)
+    *(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata.str1.4)
+    *(.eh_frame)
+    . = ALIGN(4);
+  } > ram
+
+  . = ALIGN(4);
+  _erodata = .;
+  PROVIDE (erodata = .);
+  .rodata_l1 :
+ {
+   . = ALIGN(4) ;
+   _rodata_l1 = .;
+   PROVIDE (rodata_l1 = .);
+   board/bf537-stamp/post-memory.o (.rodata)
+   board/bf537-stamp/post-memory.o (.rodata1)
+   board/bf537-stamp/post-memory.o (.rodata.str1.4)
+   . = ALIGN(4) ;
+   _erodata_l1 = .;
+   PROVIDE(erodata_l1 = .);
+ } > l1_data AT > ram
+
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  } > ram
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  ___u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) } > ram
+  ___u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bss       :
+  {
+  __bss_start = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  } > ram
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile
new file mode 100644
index 0000000..a3c2e5b
--- /dev/null
+++ b/board/bf561-ezkit/Makefile
@@ -0,0 +1,58 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+u-boot.lds: u-boot.lds.S
+	$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
+	mv -f $@.tmp $@
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c
new file mode 100644
index 0000000..71281c0
--- /dev/null
+++ b/board/bf561-ezkit/bf561-ezkit.c
@@ -0,0 +1,73 @@
+/*
+ * U-boot - ezkit561.c
+ *
+ * Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl>
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+int checkboard(void)
+{
+	printf("CPU:   ADSP BF561\n");
+	printf("Board: ADI BF561 EZ-Kit Lite board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+#ifdef DEBUG
+	int brate;
+	char *tmp = getenv("baudrate");
+	brate = simple_strtoul(tmp, NULL, 16);
+	printf("Serial Port initialized with Baud rate = %x\n", brate);
+	printf("SDRAM attributes:\n");
+	printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
+	       "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
+	       3, 3, 6, 2, 3);
+	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+#endif
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+	return CFG_MAX_RAM_SIZE;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+	/* Keep PF12 low to be able to drive the USB-LAN Extender */
+	*pFIO0_DIR = 0x0000;
+	*pFIO0_FLAG_C = 0x1000;	/* Clear PF12 */
+	sync();
+	*pFIO0_POLAR = 0x0000;
+	sync();
+
+	return 0;
+}
+#endif
diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk
new file mode 100644
index 0000000..a623c3d
--- /dev/null
+++ b/board/bf561-ezkit/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
+#  256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
+TEXT_BASE = 0x03FC0000
diff --git a/board/bf561-ezkit/u-boot.lds.S b/board/bf561-ezkit/u-boot.lds.S
new file mode 100644
index 0000000..84df5fc
--- /dev/null
+++ b/board/bf561-ezkit/u-boot.lds.S
@@ -0,0 +1,153 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2007 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+OUTPUT_ARCH(bfin)
+OUTPUT_ARCH(bfin)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash		: { *(.hash)		}
+  .dynsym	: { *(.dynsym)		}
+  .dynstr	: { *(.dynstr)		}
+  .rel.text	: { *(.rel.text)	}
+  .rela.text	: { *(.rela.text) 	}
+  .rel.data	: { *(.rel.data)	}
+  .rela.data	: { *(.rela.data) 	}
+  .rel.rodata	: { *(.rel.rodata) 	}
+  .rela.rodata	: { *(.rela.rodata) 	}
+  .rel.got	: { *(.rel.got)		}
+  .rela.got	: { *(.rela.got)	}
+  .rel.ctors	: { *(.rel.ctors)	}
+  .rela.ctors	: { *(.rela.ctors)	}
+  .rel.dtors	: { *(.rel.dtors)	}
+  .rela.dtors	: { *(.rela.dtors)	}
+  .rel.bss	: { *(.rel.bss)	}
+  .rela.bss	: { *(.rela.bss)	}
+  .rel.plt	: { *(.rel.plt)	}
+  .rela.plt	: { *(.rela.plt)	}
+  .init		: { *(.init)		}
+  .plt : { *(.plt) }
+  . = CFG_MONITOR_BASE;
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector before the environment sector. If it throws 	*/
+    /* an error during compilation remove an object here to get	*/
+    /* it linked after the configuration sector.		*/
+
+    cpu/bf561/start.o		(.text)
+    cpu/bf561/start1.o		(.text)
+    cpu/bf561/traps.o		(.text)
+    cpu/bf561/interrupt.o	(.text)
+    cpu/bf561/serial.o		(.text)
+    common/dlmalloc.o		(.text)
+/*  lib_blackfin/bf533_string.o	(.text) */
+/*  lib_generic/vsprintf.o	(.text) */
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    board/bf561-ezkit/bf561-ezkit.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  ___u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  ___u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index a7114eb..a0fac7f 100644
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
-#include <405gp_i2c.h>
+#include <4xx_i2c.h>
 #include <command.h>
 #include <rtc.h>
 #include <post.h>
diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c
index 40a827c..f5c3dd9 100644
--- a/board/dave/PPChameleonEVB/nand.c
+++ b/board/dave/PPChameleonEVB/nand.c
@@ -105,7 +105,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
  * Members with a "?" were not set in the merged testing-NAND branch,
  * so they are not set here either.
  */
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 
 	nand->hwcontrol = ppchameleonevb_hwcontrol;
@@ -113,5 +113,6 @@ void board_nand_init(struct nand_chip *nand)
 	nand->eccmode = NAND_ECC_SOFT;
 	nand->chip_delay = NAND_BIG_DELAY_US;
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
+	return 0;
 }
 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
diff --git a/board/delta/nand.c b/board/delta/nand.c
index fe648fc..d170938 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -448,7 +448,7 @@ static void dfc_gpio_init(void)
  * Members with a "?" were not set in the merged testing-NAND branch,
  * so they are not set here either.
  */
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
 
@@ -576,6 +576,7 @@ void board_nand_init(struct nand_chip *nand)
 	nand->cmdfunc = dfc_cmdfunc;
 	nand->autooob = &delta_oob;
 	nand->badblock_pattern = &delta_bbt_descr;
+	return 0;
 }
 
 #else
diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c
index 12acc57..d741e6b 100644
--- a/board/emk/top5200/top5200.c
+++ b/board/emk/top5200/top5200.c
@@ -190,7 +190,7 @@ void init_ide_reset (void)
 {
 	debug ("init_ide_reset\n");
 
-    	/* Configure PSC1_4 as GPIO output for ATA reset */
+	/* Configure PSC1_4 as GPIO output for ATA reset */
 	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 }
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index 5cd3423..001fd68 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -33,6 +33,7 @@
 #include <asm/byteorder.h>
 #include <linux/mtd/nand_legacy.h>
 #include <fat.h>
+#include <part.h>
 
 #include "auto_update.h"
 
@@ -71,8 +72,6 @@ extern int transfer_pic(unsigned char, unsigned char *, int, int);
 extern int flash_sect_erase(ulong, ulong);
 extern int flash_sect_protect (int, ulong, ulong);
 extern int flash_write (char *, ulong, ulong);
-/* change char* to void* to shutup the compiler */
-extern block_dev_desc_t *get_dev (char*, int);
 
 #if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
 /* references to names in cmd_nand.c */
diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c
index f14331b..a925b84 100644
--- a/board/esd/cpci5200/cpci5200.c
+++ b/board/esd/cpci5200/cpci5200.c
@@ -191,8 +191,7 @@ static struct pci_controller hose;
 
 extern void pci_mpc5xxx_init(struct pci_controller *);
 
-void pci_init_board(void
-    ) {
+void pci_init_board(void) {
 	pci_mpc5xxx_init(&hose);
 }
 #endif
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index dbed597..17e3568 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -29,6 +29,7 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <74xx_7xx.h>
 #include "../../Marvell/include/memory.h"
 #include "../../Marvell/include/pci.h"
@@ -365,12 +366,12 @@ int misc_init_r ()
 	dcache_lock ();
 #endif
 	if (flash_info[3].size < CFG_FLASH_INCREMENT) {
-	        unsigned int flash_offset;
+		unsigned int flash_offset;
 		unsigned int l;
 
 		flash_offset =  CFG_FLASH_INCREMENT - flash_info[3].size;
 		for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
-		        if (flash_info[3].start[l] != 0) {
+			if (flash_info[3].start[l] != 0) {
 			      flash_info[3].start[l] += flash_offset;
 			}
 		}
@@ -502,7 +503,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
 {
 	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
 	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
-      : : : "fr0");		/* Clobbers fr0         */
+      : : : "fr0");		/* Clobbers fr0		*/
 	return;
 }
 
@@ -580,9 +581,9 @@ int mem_test_data (void)
 		move64 (&(pattern[i]), pmem);
 		move64 (pmem, &temp64);
 
-		/* hi = (temp64>>32) & 0xffffffff;          */
-		/* lo = temp64 & 0xffffffff;                */
-		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+		/* hi = (temp64>>32) & 0xffffffff;		*/
+		/* lo = temp64 & 0xffffffff;			*/
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo);	*/
 
 		hi = (pattern[i] >> 32) & 0xffffffff;
 		lo = pattern[i] & 0xffffffff;
@@ -855,11 +856,11 @@ int testdram (void)
 }
 #endif /* CFG_DRAM_TEST */
 
-/* ronen - the below functions are used by the bootm function           */
+/* ronen - the below functions are used by the bootm function		*/
 /*  - we map the base register to fbe00000 (same mapping as in the LSP) */
 /*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
-/*    the kernel data areas.                                            */
-/*  - we diable and invalidate the icache and dcache.                   */
+/*    the kernel data areas.						*/
+/*  - we diable and invalidate the icache and dcache.			*/
 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
 {
 	u32 temp;
@@ -899,3 +900,22 @@ void board_prebootm_init ()
 	flush_data_cache ();
 	dcache_disable ();
 }
+
+
+int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int reset_sample_low;
+	unsigned int reset_sample_high;
+
+	GT_REG_READ(0x3c4, &reset_sample_low);
+	GT_REG_READ(0x3d4, &reset_sample_high);
+	printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
+
+	return(0);
+}
+
+U_BOOT_CMD(
+	show_cfg,	1,	1,	do_show_cfg,
+	"show_cfg- Show Marvell strapping register\n",
+	"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
+	);
diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
index 6bdfc1d..c094755 100644
--- a/board/esd/cpci750/sdram_init.c
+++ b/board/esd/cpci750/sdram_init.c
@@ -1504,6 +1504,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 
 /*	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
 	{
+	        int l, l1;
+
 		i = info->slot;
 		DP (printf
 		    ("\n*** Running a MRS cycle for bank %d ***\n", i));
@@ -1511,20 +1513,39 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
 		/* map the bank */
 		memory_map_bank (i, 0, GB / 4);
 #if 1				/* test only */
-		/* set SDRAM mode */ /* To_do check it */
+
+		tmp = GTREGREAD (SDRAM_MODE);
+		GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
+		GT_REG_WRITE (SDRAM_OPERATION, 0x4);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		        DP (printf
+			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+		}
+
+		GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
 		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
-		check = GTREGREAD (SDRAM_OPERATION);
-		DP (printf
-		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
-		     check));
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		        DP (printf
+			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+		}
+		l1 = 0;
+		for (l=0;l<200;l++)
+		        l1 += GTREGREAD (SDRAM_OPERATION);
 
+		GT_REG_WRITE (SDRAM_MODE, tmp);
+		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		        DP (printf
+			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+		}
 
 		/* switch back to normal operation mode */
-		GT_REG_WRITE (SDRAM_OPERATION, 0);
-		check = GTREGREAD (SDRAM_OPERATION);
-		DP (printf
-		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
-		     check));
+		GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+		while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		        DP (printf
+			    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+		}
+
 #endif /* test only */
 		/* unmap the bank */
 		memory_map_bank (i, 0, 0);
diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
index a019ce4..6943213 100644
--- a/board/esd/du405/du405.c
+++ b/board/esd/du405/du405.c
@@ -25,7 +25,7 @@
 #include "du405.h"
 #include <asm/processor.h>
 #include <ppc4xx.h>
-#include <405gp_i2c.h>
+#include <4xx_i2c.h>
 #include <command.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/esd/mecp5200/Makefile b/board/esd/mecp5200/Makefile
new file mode 100644
index 0000000..45efdb0
--- /dev/null
+++ b/board/esd/mecp5200/Makefile
@@ -0,0 +1,51 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esd/mecp5200/config.mk b/board/esd/mecp5200/config.mk
new file mode 100644
index 0000000..07b5de1
--- /dev/null
+++ b/board/esd/mecp5200/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IceCube board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0xFF000000   boot low for 16 MiB boards
+#	0xFF800000   boot low for  8 MiB boards
+#	0x00100000   boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c
new file mode 100644
index 0000000..c4b91e9
--- /dev/null
+++ b/board/esd/mecp5200/mecp5200.c
@@ -0,0 +1,261 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * pf5200.c - main board support/init for the esd pf5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+
+#include "mt46v16m16-75.h"
+
+void init_power_switch(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+long int initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size(CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size(CFG_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_power_switch();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd CPX CPU5200 (mecp5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == CFG_FLASH_SIZE) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CFG_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CFG_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset)
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+	else
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+#endif				/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_power_switch(void)
+{
+	debug("init_power_switch\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+}
diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h
new file mode 100644
index 0000000..22d0a55
--- /dev/null
+++ b/board/esd/mecp5200/mt46v16m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/esd/mecp5200/u-boot.lds b/board/esd/mecp5200/u-boot.lds
new file mode 100644
index 0000000..d999dd1
--- /dev/null
+++ b/board/esd/mecp5200/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
index 1f30d45..77e164b 100644
--- a/board/esd/pf5200/pf5200.c
+++ b/board/esd/pf5200/pf5200.c
@@ -191,8 +191,7 @@ static struct pci_controller hose;
 
 extern void pci_mpc5xxx_init(struct pci_controller *);
 
-void pci_init_board(void
-    ) {
+void pci_init_board(void) {
 	pci_mpc5xxx_init(&hose);
 }
 #endif
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index 37b92fb..59171f8 100644
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -215,12 +215,6 @@ int checkboard (void)
 	}
 
 	putc ('\n');
-
-	/*
-	 * Disable sleep mode in LXT971
-	 */
-	lxt971_no_sleep();
-
 	return 0;
 }
 
@@ -292,3 +286,14 @@ void board_auto_update_show(int au_active)
 	}
 }
 #endif
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c
index 237e863..9fa0e74 100644
--- a/board/hmi1001/hmi1001.c
+++ b/board/hmi1001/hmi1001.c
@@ -103,9 +103,9 @@ long int initdram (int board_type)
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
 	sdram_start(1);
-	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -179,7 +179,7 @@ struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
 	return kbd_data;
 }
 
-static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str)
+static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
 {
 	char s1 = str[0];
 	char s2;
@@ -222,11 +222,11 @@ static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str)
 	return 0;
 }
 
-static uchar *key_match (const struct kbd_data_t *kbd_data)
+static char *key_match (const struct kbd_data_t *kbd_data)
 {
-	uchar magic[sizeof (kbd_magic_prefix) + 1];
-	uchar *suffix;
-	uchar *kbd_magic_keys;
+	char magic[sizeof (kbd_magic_prefix) + 1];
+	char *suffix;
+	char *kbd_magic_keys;
 
 	/*
 	 * The following string defines the characters that can be appended
@@ -247,7 +247,7 @@ static uchar *key_match (const struct kbd_data_t *kbd_data)
 		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
 
 		if (compare_magic(kbd_data, getenv(magic)) == 0) {
-			uchar cmd_name[sizeof (kbd_command_prefix) + 1];
+			char cmd_name[sizeof (kbd_command_prefix) + 1];
 			char *cmd;
 
 			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
@@ -267,7 +267,7 @@ int misc_init_r (void)
 #ifdef CONFIG_PREBOOT
 	struct kbd_data_t kbd_data;
 	/* Decode keys */
-	uchar *str = strdup (key_match (get_keys (&kbd_data)));
+	char *str = strdup (key_match (get_keys (&kbd_data)));
 	/* Set or delete definition */
 	setenv ("preboot", str);
 	free (str);
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index f958b32..700c9d9 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -29,6 +29,10 @@
 #include <pci.h>
 #include <asm/processor.h>
 
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
 #if defined(CONFIG_LITE5200B)
 #include "mt46v32m16.h"
 #else
@@ -312,7 +316,7 @@ void init_ide_reset (void)
 {
 	debug ("init_ide_reset\n");
 
-    	/* Configure PSC1_4 as GPIO output for ATA reset */
+	/* Configure PSC1_4 as GPIO output for ATA reset */
 	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 	/* Deassert reset */
@@ -332,3 +336,11 @@ void ide_set_reset (int idereset)
 	}
 }
 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif
diff --git a/board/ezkit533/Makefile b/board/idmr/Makefile
index 4f3c223..cf07cf4 100644
--- a/board/ezkit533/Makefile
+++ b/board/idmr/Makefile
@@ -1,8 +1,4 @@
 #
-# U-boot - Makefile
-#
-# Copyright (c) 2005 blackfin.uclinux.org
-#
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -29,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o flash.o ezkit533.o
+COBJS	= $(BOARD).o flash.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/idmr/config.mk b/board/idmr/config.mk
new file mode 100644
index 0000000..f7c2258
--- /dev/null
+++ b/board/idmr/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xff800000
diff --git a/board/idmr/flash.c b/board/idmr/flash.c
new file mode 100644
index 0000000..33512b8
--- /dev/null
+++ b/board/idmr/flash.c
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define FLASH_BANK_SIZE 0x800000
+#define EN29LV640 0x227e227e
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (EN29LV640 & FLASH_TYPEMASK):
+		printf ("EN29LV640 (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+      Done:
+	return;
+}
+
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(EN29LV640 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured to many flash banks!\n");
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + 0x10000 * j;
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + 0x2ffff, &flash_info[0]);
+
+	return size;
+}
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts ();
+
+	printf ("\n");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		set_timer (0);
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr =
+				(volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	printf("Waiting 10 ms...");
+	 udelay (10000);
+
+/*	for (i = 0; i < 10 * 1000 * 1000; ++i)
+		asm(" nop");
+*/
+
+	printf("done\n");
+	if (iflag)
+		enable_interrupts ();
+
+
+	return rc;
+}
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	}
+
+#if 0
+	if (cnt & 1) {
+		printf ("odd transfer sizes not supported\n");
+		return ERR_ALIGN;
+	}
+#endif
+
+	wp = addr;
+
+	if (addr & 1) {
+		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+							  src);
+		if ((rc = write_word (info, wp - 1, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src) << 8) |
+			*((volatile u8 *) (wp + 1));
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c
new file mode 100644
index 0000000..58cdba1
--- /dev/null
+++ b/board/idmr/idmr.c
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5271.h>
+#include <asm/immap_5271.h>
+
+int checkboard (void) {
+	puts ("Board: iDMR\n");
+	return 0;
+};
+
+long int initdram (int board_type) {
+	int i;
+
+	/*
+	 * After reset, CS0 is configured to cover entire address space. We
+	 * need to configure it to its proper values, so that writes to
+	 * CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do
+	 * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
+	 */
+
+	/* Flash chipselect, CS0 */
+	/* ;CSAR0: Flash at 0xFF800000 */
+	mbar_writeShort(0x0080, 0xFF80);
+
+	/* CSCR0: Flash 6 waits, 16bit */
+	mbar_writeShort(0x008A, 0x1980);
+
+	/* CSMR0: Flash 8MB, R/W, valid */
+	mbar_writeLong(0x0084, 0x007F0001);
+
+
+	/*
+	 * SDRAM configuration proper
+	 */
+
+	/*
+	 * Address/Data Pin Assignment Reg.: enable address lines 23-21; do
+	 * not enable data pins D[15:0], as we have 16 bit port to SDRAM
+	 */
+	mbar_writeByte(MCF_GPIO_PAR_AD,
+			MCF_GPIO_AD_ADDR23 |
+			MCF_GPIO_AD_ADDR22 |
+			MCF_GPIO_AD_ADDR21);
+
+	/* No need to configure BS pins - reset values are OK */
+
+	/* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
+	mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
+
+	/* SDRAM Control Pin Assignment Reg. */
+	mbar_writeByte(MCF_GPIO_PAR_SDRAM,
+			MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
+			MCF_GPIO_SDRAM_SDWE |
+			MCF_GPIO_SDRAM_SCAS |
+			MCF_GPIO_SDRAM_SRAS |
+			MCF_GPIO_SDRAM_SCKE |
+			MCF_GPIO_SDRAM_SDCS_01);
+
+	/*
+	 * Wait 100us.  We run the bus at 50Mhz, one cycle is 20ns. So 5
+	 * iterations will do, but we do 10 just to be safe.
+	 */
+	for (i = 0; i < 10; ++i)
+		asm(" nop");
+
+
+	/* 1. Initialize DRAM Control Register: DCR */
+	mbar_writeShort(MCF_SDRAMC_DCR,
+			MCF_SDRAMC_DCR_RTIM(0x10) |	/* 65ns */
+			MCF_SDRAMC_DCR_RC(0x60));	/* 1562 cycles */
+
+
+	/*
+	 * 2. Initialize DACR0
+	 *
+	 * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
+	 * CBM: cmd at A20, bank select bits 21 and up
+	 * PS: 16 bit
+	 */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) |
+			MCF_SDRAMC_DACRn_BA(0x00) |
+			MCF_SDRAMC_DACRn_CASL(0x03) |
+			MCF_SDRAMC_DACRn_CBM(0x03) |
+			MCF_SDRAMC_DACRn_PS(0x03));
+
+	/* Initialize DMR0 */
+	mbar_writeLong(MCF_SDRAMC_DMR0,
+			MCF_SDRAMC_DMRn_BAM_16M |
+			MCF_SDRAMC_DMRn_V);
+
+
+	/* 3. Set IP bit in DACR to initiate PALL command */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			mbar_readLong(MCF_SDRAMC_DACR0) |
+			MCF_SDRAMC_DACRn_IP);
+
+	/* Write to this block to initiate precharge */
+	*(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5;
+
+	/*
+	 * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
+	 * wait a wee longer, just to be safe.
+	 */
+	for (i = 0; i < 5; ++i)
+		asm(" nop");
+
+
+	/* 4. Set RE bit in DACR */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			mbar_readLong(MCF_SDRAMC_DACR0) |
+			MCF_SDRAMC_DACRn_RE);
+
+	/*
+	 * Wait for at least 8 auto refresh cycles to occur, i.e. at least
+	 * 781 bus cycles.
+	 */
+	for (i = 0; i < 1000; ++i)
+		asm(" nop");
+
+	/* Finish the configuration by issuing the MRS */
+	mbar_writeLong(MCF_SDRAMC_DACR0,
+			mbar_readLong(MCF_SDRAMC_DACR0) |
+			MCF_SDRAMC_DACRn_MRS);
+
+	/*
+	 * Write to the SDRAM Mode Register A0-A11 = 0x400
+	 *
+	 * Write Burst Mode = Programmed Burst Length
+	 * Op Mode = Standard Op
+	 * CAS Latency = 3
+	 * Burst Type = Sequential
+	 * Burst Length = 1
+	 */
+	*(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
+
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+
+int testdram (void) {
+
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds
new file mode 100644
index 0000000..69f3179
--- /dev/null
+++ b/board/idmr/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+GROUP(libgcc.a)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile
new file mode 100644
index 0000000..aed3af0
--- /dev/null
+++ b/board/jupiter/Makefile
@@ -0,0 +1,51 @@
+
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/jupiter/config.mk b/board/jupiter/config.mk
new file mode 100644
index 0000000..5f4da96
--- /dev/null
+++ b/board/jupiter/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2007
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Jupiter board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0x00100000   boot from RAM (for testing only)
+#
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+#PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -DDEBUG -I$(TOPDIR)/board
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
new file mode 100644
index 0000000..04fda4a
--- /dev/null
+++ b/board/jupiter/jupiter.c
@@ -0,0 +1,317 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+
+#define SDRAM_DDR	0
+#if 1
+/* Settings Icecube */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+#else
+/*Settings Jupiter UB 1.0.0 */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0xD04F0000
+#define SDRAM_CONFIG1	0xf7277f00
+#define SDRAM_CONFIG2	0x88b70004
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Sauter (Jupiter)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+#if defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+#endif
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+int board_early_init_r (void)
+{
+	flash_preinit ();
+	return 0;
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x1000000) { /* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(CFG_BOOTCS_START | size);
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(CFG_BOOTCS_START | size, size);
+	}
+#if defined(CONFIG_MPC5200)
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+#endif
+}
+
+int update_flash_size (int flash_size)
+{
+	flash_afterinit (flash_size);
+	return 0;
+}
+
+int board_early_init_f (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+	/* Deassert reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
+	}
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif
diff --git a/board/jupiter/u-boot.lds b/board/jupiter/u-boot.lds
new file mode 100644
index 0000000..f23432e
--- /dev/null
+++ b/board/jupiter/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/lpc2292sodimm/Makefile b/board/lpc2292sodimm/Makefile
new file mode 100644
index 0000000..5a30198
--- /dev/null
+++ b/board/lpc2292sodimm/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= lpc2292sodimm.o flash.o mmc.o spi.o mmc_hw.o eth.o
+SOBJS	:= lowlevel_init.o iap_entry.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+# this MUST be compiled as thumb code!
+iap_entry.o:
+	arm-linux-gcc  -D__ASSEMBLY__ -g  -Os   -fno-strict-aliasing  \
+	-fno-common -ffixed-r8 -msoft-float  -D__KERNEL__ \
+	-DTEXT_BASE=0x81500000  -I/home/garyj/proj/LPC/u-boot/include \
+	-fno-builtin -ffreestanding -nostdinc -isystem \
+	/opt/eldk/arm/usr/bin/../lib/gcc/arm-linux/4.0.0/include -pipe  \
+	-DCONFIG_ARM -D__ARM__ -march=armv4t -mtune=arm7tdmi -mabi=apcs-gnu \
+	-c -o iap_entry.o iap_entry.S
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/lpc2292sodimm/config.mk b/board/lpc2292sodimm/config.mk
new file mode 100644
index 0000000..b28f418
--- /dev/null
+++ b/board/lpc2292sodimm/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#address where u-boot will be relocated
+#TEXT_BASE = 0x0
+TEXT_BASE = 0x81500000
diff --git a/board/lpc2292sodimm/eth.c b/board/lpc2292sodimm/eth.c
new file mode 100644
index 0000000..249ab04
--- /dev/null
+++ b/board/lpc2292sodimm/eth.c
@@ -0,0 +1,885 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+#include <asm/arch/hardware.h>
+#include "spi.h"
+
+/*
+ * Control Registers in Bank 0
+ */
+
+#define CTL_REG_ERDPTL	 0x00
+#define CTL_REG_ERDPTH	 0x01
+#define CTL_REG_EWRPTL	 0x02
+#define CTL_REG_EWRPTH	 0x03
+#define CTL_REG_ETXSTL	 0x04
+#define CTL_REG_ETXSTH	 0x05
+#define CTL_REG_ETXNDL	 0x06
+#define CTL_REG_ETXNDH	 0x07
+#define CTL_REG_ERXSTL	 0x08
+#define CTL_REG_ERXSTH	 0x09
+#define CTL_REG_ERXNDL	 0x0A
+#define CTL_REG_ERXNDA	 0x0B
+#define CTL_REG_ERXRDPTL 0x0C
+#define CTL_REG_ERXRDPTH 0x0D
+#define CTL_REG_ERXWRPTL 0x0E
+#define CTL_REG_ERXWRPTH 0x0F
+#define CTL_REG_EDMASTL  0x10
+#define CTL_REG_EDMASTH  0x11
+#define CTL_REG_EDMANDL  0x12
+#define CTL_REG_EDMANDH  0x13
+#define CTL_REG_EDMADSTL 0x14
+#define CTL_REG_EDMADSTH 0x15
+#define CTL_REG_EDMACSL  0x16
+#define CTL_REG_EDMACSH  0x17
+/* these are common in all banks */
+#define CTL_REG_EIE	 0x1B
+#define CTL_REG_EIR	 0x1C
+#define CTL_REG_ESTAT	 0x1D
+#define CTL_REG_ECON2	 0x1E
+#define CTL_REG_ECON1	 0x1F
+
+/*
+ * Control Registers in Bank 1
+ */
+
+#define CTL_REG_EHT0	0x00
+#define CTL_REG_EHT1	0x01
+#define CTL_REG_EHT2	0x02
+#define CTL_REG_EHT3	0x03
+#define CTL_REG_EHT4	0x04
+#define CTL_REG_EHT5	0x05
+#define CTL_REG_EHT6	0x06
+#define CTL_REG_EHT7	0x07
+#define CTL_REG_EPMM0	0x08
+#define CTL_REG_EPMM1	0x09
+#define CTL_REG_EPMM2	0x0A
+#define CTL_REG_EPMM3	0x0B
+#define CTL_REG_EPMM4	0x0C
+#define CTL_REG_EPMM5	0x0D
+#define CTL_REG_EPMM6	0x0E
+#define CTL_REG_EPMM7	0x0F
+#define CTL_REG_EPMCSL	0x10
+#define CTL_REG_EPMCSH	0x11
+#define CTL_REG_EPMOL	0x14
+#define CTL_REG_EPMOH	0x15
+#define CTL_REG_EWOLIE	0x16
+#define CTL_REG_EWOLIR	0x17
+#define CTL_REG_ERXFCON 0x18
+#define CTL_REG_EPKTCNT 0x19
+
+/*
+ * Control Registers in Bank 2
+ */
+
+#define CTL_REG_MACON1	 0x00
+#define CTL_REG_MACON2	 0x01
+#define CTL_REG_MACON3	 0x02
+#define CTL_REG_MACON4	 0x03
+#define CTL_REG_MABBIPG  0x04
+#define CTL_REG_MAIPGL	 0x06
+#define CTL_REG_MAIPGH	 0x07
+#define CTL_REG_MACLCON1 0x08
+#define CTL_REG_MACLCON2 0x09
+#define CTL_REG_MAMXFLL  0x0A
+#define CTL_REG_MAMXFLH  0x0B
+#define CTL_REG_MAPHSUP  0x0D
+#define CTL_REG_MICON	 0x11
+#define CTL_REG_MICMD	 0x12
+#define CTL_REG_MIREGADR 0x14
+#define CTL_REG_MIWRL	 0x16
+#define CTL_REG_MIWRH	 0x17
+#define CTL_REG_MIRDL	 0x18
+#define CTL_REG_MIRDH	 0x19
+
+/*
+ * Control Registers in Bank 3
+ */
+
+#define CTL_REG_MAADR1	0x00
+#define CTL_REG_MAADR0	0x01
+#define CTL_REG_MAADR3	0x02
+#define CTL_REG_MAADR2	0x03
+#define CTL_REG_MAADR5	0x04
+#define CTL_REG_MAADR4	0x05
+#define CTL_REG_EBSTSD	0x06
+#define CTL_REG_EBSTCON 0x07
+#define CTL_REG_EBSTCSL 0x08
+#define CTL_REG_EBSTCSH 0x09
+#define CTL_REG_MISTAT	0x0A
+#define CTL_REG_EREVID	0x12
+#define CTL_REG_ECOCON	0x15
+#define CTL_REG_EFLOCON 0x17
+#define CTL_REG_EPAUSL	0x18
+#define CTL_REG_EPAUSH	0x19
+
+
+/*
+ * PHY Register
+ */
+
+#define PHY_REG_PHID1 0x02
+#define PHY_REG_PHID2 0x03
+
+
+/*
+ * Receive Filter Register (ERXFCON) bits
+ */
+
+#define ENC_RFR_UCEN  0x80
+#define ENC_RFR_ANDOR 0x40
+#define ENC_RFR_CRCEN 0x20
+#define ENC_RFR_PMEN  0x10
+#define ENC_RFR_MPEN  0x08
+#define ENC_RFR_HTEN  0x04
+#define ENC_RFR_MCEN  0x02
+#define ENC_RFR_BCEN  0x01
+
+/*
+ * ECON1 Register Bits
+ */
+
+#define ENC_ECON1_TXRST  0x80
+#define ENC_ECON1_RXRST  0x40
+#define ENC_ECON1_DMAST  0x20
+#define ENC_ECON1_CSUMEN 0x10
+#define ENC_ECON1_TXRTS  0x08
+#define ENC_ECON1_RXEN	 0x04
+#define ENC_ECON1_BSEL1  0x02
+#define ENC_ECON1_BSEL0  0x01
+
+/*
+ * ECON2 Register Bits
+ */
+#define ENC_ECON2_AUTOINC 0x80
+#define ENC_ECON2_PKTDEC  0x40
+#define ENC_ECON2_PWRSV   0x20
+#define ENC_ECON2_VRPS	  0x08
+
+/*
+ * EIR Register Bits
+ */
+#define ENC_EIR_PKTIF  0x40
+#define ENC_EIR_DMAIF  0x20
+#define ENC_EIR_LINKIF 0x10
+#define ENC_EIR_TXIF   0x08
+#define ENC_EIR_WOLIF  0x04
+#define ENC_EIR_TXERIF 0x02
+#define ENC_EIR_RXERIF 0x01
+
+/*
+ * ESTAT Register Bits
+ */
+
+#define ENC_ESTAT_INT	  0x80
+#define ENC_ESTAT_LATECOL 0x10
+#define ENC_ESTAT_RXBUSY  0x04
+#define ENC_ESTAT_TXABRT  0x02
+#define ENC_ESTAT_CLKRDY  0x01
+
+/*
+ * EIE Register Bits
+ */
+
+#define ENC_EIE_INTIE  0x80
+#define ENC_EIE_PKTIE  0x40
+#define ENC_EIE_DMAIE  0x20
+#define ENC_EIE_LINKIE 0x10
+#define ENC_EIE_TXIE   0x08
+#define ENC_EIE_WOLIE  0x04
+#define ENC_EIE_TXERIE 0x02
+#define ENC_EIE_RXERIE 0x01
+
+/*
+ * MACON1 Register Bits
+ */
+#define ENC_MACON1_LOOPBK  0x10
+#define ENC_MACON1_TXPAUS  0x08
+#define ENC_MACON1_RXPAUS  0x04
+#define ENC_MACON1_PASSALL 0x02
+#define ENC_MACON1_MARXEN  0x01
+
+
+/*
+ * MACON2 Register Bits
+ */
+#define ENC_MACON2_MARST   0x80
+#define ENC_MACON2_RNDRST  0x40
+#define ENC_MACON2_MARXRST 0x08
+#define ENC_MACON2_RFUNRST 0x04
+#define ENC_MACON2_MATXRST 0x02
+#define ENC_MACON2_TFUNRST 0x01
+
+/*
+ * MACON3 Register Bits
+ */
+#define ENC_MACON3_PADCFG2 0x80
+#define ENC_MACON3_PADCFG1 0x40
+#define ENC_MACON3_PADCFG0 0x20
+#define ENC_MACON3_TXCRCEN 0x10
+#define ENC_MACON3_PHDRLEN 0x08
+#define ENC_MACON3_HFRMEN  0x04
+#define ENC_MACON3_FRMLNEN 0x02
+#define ENC_MACON3_FULDPX  0x01
+
+/*
+ * MICMD Register Bits
+ */
+#define ENC_MICMD_MIISCAN 0x02
+#define ENC_MICMD_MIIRD   0x01
+
+/*
+ * MISTAT Register Bits
+ */
+#define ENC_MISTAT_NVALID 0x04
+#define ENC_MISTAT_SCAN   0x02
+#define ENC_MISTAT_BUSY   0x01
+
+/*
+ * PHID1 and PHID2 values
+ */
+#define ENC_PHID1_VALUE 0x0083
+#define ENC_PHID2_VALUE 0x1400
+#define ENC_PHID2_MASK	0xFC00
+
+
+#define ENC_SPI_SLAVE_CS 0x00010000	/* pin P1.16 */
+#define ENC_RESET	 0x00020000	/* pin P1.17 */
+
+#define FAILSAFE_VALUE 5000
+
+/*
+ * Controller memory layout:
+ *
+ * 0x0000 - 0x17ff  6k bytes receive buffer
+ * 0x1800 - 0x1fff  2k bytes transmit buffer
+ */
+/* Use the lower memory for receiver buffer. See errata pt. 5 */
+#define ENC_RX_BUF_START 0x0000
+#define ENC_TX_BUF_START 0x1800
+
+/* maximum frame length */
+#define ENC_MAX_FRM_LEN 1518
+
+#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
+#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
+#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
+
+
+static unsigned char encReadReg (unsigned char regNo);
+static void encWriteReg (unsigned char regNo, unsigned char data);
+static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
+static void encReadBuff (unsigned short length, unsigned char *pBuff);
+static void encWriteBuff (unsigned short length, unsigned char *pBuff);
+static void encBitSet (unsigned char regNo, unsigned char data);
+static void encBitClr (unsigned char regNo, unsigned char data);
+static void encReset (void);
+static void encInit (unsigned char *pEthAddr);
+static unsigned short phyRead (unsigned char addr);
+static void encPoll (void);
+static void encRx (void);
+
+#define m_nic_read(reg) encReadReg(reg)
+#define m_nic_write(reg, data) encWriteReg(reg, data)
+#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
+#define m_nic_read_data(len, buf) encReadBuff((len), (buf))
+#define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
+
+/* bit field set */
+#define m_nic_bfs(reg, data) encBitSet(reg, data)
+
+/* bit field clear */
+#define m_nic_bfc(reg, data) encBitClr(reg, data)
+
+static unsigned char bank = 0;	/* current bank in enc28j60 */
+static unsigned char next_pointer_lsb;
+static unsigned char next_pointer_msb;
+
+static unsigned char buffer[ENC_MAX_FRM_LEN];
+static int rxResetCounter = 0;
+
+#define RX_RESET_COUNTER 1000;
+
+/*-----------------------------------------------------------------------------
+ * Returns 0 when failes otherwize 1
+ */
+int eth_init (bd_t * bis)
+{
+	/* configure GPIO */
+	(*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
+	(*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
+
+	/* CS and RESET active low */
+	PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
+	PUT32 (IO1SET, ENC_RESET);
+
+	spi_init ();
+
+	/* initialize controller */
+	encReset ();
+	encInit (bis->bi_enetaddr);
+
+	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN);	/* enable receive */
+
+	return 0;
+}
+
+int eth_send (volatile void *packet, int length)
+{
+	/* check frame length, etc. */
+	/* TODO: */
+
+	/* switch to bank 0 */
+	m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
+
+	/* set EWRPT */
+	m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
+	m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
+
+	/* set ETXST */
+	m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
+	m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
+
+	/* write packet */
+	m_nic_write_data (length, (unsigned char *) packet);
+
+	/* set ETXND */
+	m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
+	m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
+
+	/* set ECON1.TXRTS */
+	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
+
+	return 0;
+}
+
+
+/*****************************************************************************
+ * This function resets the receiver only. This function may be called from
+ * interrupt-context.
+ */
+static void encReceiverReset (void)
+{
+	unsigned char econ1;
+
+	econ1 = m_nic_read (CTL_REG_ECON1);
+	if ((econ1 & ENC_ECON1_RXRST) == 0) {
+		m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
+		rxResetCounter = RX_RESET_COUNTER;
+	}
+}
+
+/*****************************************************************************
+ * receiver reset timer
+ */
+static void encReceiverResetCallback (void)
+{
+	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
+	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN);	/* enable receive */
+}
+
+/*-----------------------------------------------------------------------------
+ * Check for received packets. Call NetReceive for each packet. The return
+ * value is ignored by the caller.
+ */
+int eth_rx (void)
+{
+	if (rxResetCounter > 0 && --rxResetCounter == 0) {
+		encReceiverResetCallback ();
+	}
+
+	encPoll ();
+
+	return 0;
+}
+
+void eth_halt (void)
+{
+	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN);	/* disable receive */
+}
+
+/*****************************************************************************/
+
+static void encPoll (void)
+{
+	unsigned char eir_reg;
+	volatile unsigned char estat_reg;
+	unsigned char pkt_cnt;
+
+	/* clear global interrupt enable bit in enc28j60 */
+	m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
+	estat_reg = m_nic_read (CTL_REG_ESTAT);
+
+	eir_reg = m_nic_read (CTL_REG_EIR);
+
+	if (eir_reg & ENC_EIR_TXIF) {
+		/* clear TXIF bit in EIR */
+		m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
+	}
+
+	/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
+
+	/* move to bank 1 */
+	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+
+	/* read pktcnt */
+	pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
+
+	if (pkt_cnt > 0) {
+		if ((eir_reg & ENC_EIR_PKTIF) == 0) {
+			/*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
+		}
+		encRx ();
+		/* clear PKTIF bit in EIR, this should not need to be done but it
+		   seems like we get problems if we do not */
+		m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
+	}
+
+	if (eir_reg & ENC_EIR_RXERIF) {
+		printf ("encPoll: rx error\n");
+		m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
+	}
+	if (eir_reg & ENC_EIR_TXERIF) {
+		printf ("encPoll: tx error\n");
+		m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
+	}
+
+	/* set global interrupt enable bit in enc28j60 */
+	m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
+}
+
+static void encRx (void)
+{
+	unsigned short pkt_len;
+	unsigned short copy_len;
+	unsigned short status;
+	unsigned char eir_reg;
+	unsigned char pkt_cnt = 0;
+
+	/* switch to bank 0 */
+	m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
+
+	m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
+	m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
+
+	do {
+		m_nic_read_data (6, buffer);
+		next_pointer_lsb = buffer[0];
+		next_pointer_msb = buffer[1];
+		pkt_len = buffer[2];
+		pkt_len |= (unsigned short) buffer[3] << 8;
+		status = buffer[4];
+		status |= (unsigned short) buffer[5] << 8;
+
+		if (pkt_len <= ENC_MAX_FRM_LEN) {
+			copy_len = pkt_len;
+		} else {
+			copy_len = 0;
+			/*      p_priv->stats.rx_dropped++; */
+			/* we will drop this packet */
+		}
+
+		if ((status & (1L << 7)) == 0) {	/* check Received Ok bit */
+			copy_len = 0;
+			/*      p_priv->stats.rx_errors++; */
+		}
+
+		if (copy_len > 0) {
+			m_nic_read_data (copy_len, buffer);
+		}
+
+		/* advance read pointer to next pointer */
+		m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
+		m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
+
+		/* decrease packet counter */
+		m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
+
+		/* move to bank 1 */
+		m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+		m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+
+		/* read pktcnt */
+		pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
+
+		/* switch to bank 0 */
+		m_nic_bfc (CTL_REG_ECON1,
+			   (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
+
+		if (copy_len == 0) {
+			eir_reg = m_nic_read (CTL_REG_EIR);
+			encReceiverReset ();
+			printf ("eth_rx: copy_len=0\n");
+			continue;
+		}
+
+		NetReceive ((unsigned char *) buffer, pkt_len);
+
+		eir_reg = m_nic_read (CTL_REG_EIR);
+	} while (pkt_cnt);	/* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
+	m_nic_write (CTL_REG_ERXRDPTL, next_pointer_lsb);
+	m_nic_write (CTL_REG_ERXRDPTH, next_pointer_msb);
+}
+
+static void encWriteReg (unsigned char regNo, unsigned char data)
+{
+	spi_lock ();
+	enc_cfg_spi ();
+	enc_enable ();
+
+	spi_write (0x40 | regNo);	/* write in regNo */
+	spi_write (data);
+
+	enc_disable ();
+	enc_enable ();
+
+	spi_write (0x1f);	/* write reg 0x1f */
+
+	enc_disable ();
+	spi_unlock ();
+}
+
+static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
+{
+	unsigned char readback;
+	int i;
+
+	spi_lock ();
+
+	for (i = 0; i < c; i++) {
+		enc_cfg_spi ();
+		enc_enable ();
+
+		spi_write (0x40 | regNo);	/* write in regNo */
+		spi_write (data);
+
+		enc_disable ();
+		enc_enable ();
+
+		spi_write (0x1f);	/* write reg 0x1f */
+
+		enc_disable ();
+
+		spi_unlock ();	/* we must unlock spi first */
+
+		readback = encReadReg (regNo);
+
+		spi_lock ();
+
+		if (readback == data)
+			break;
+	}
+	spi_unlock ();
+
+	if (i == c) {
+		printf ("enc28j60: write reg %d failed\n", regNo);
+	}
+}
+
+static unsigned char encReadReg (unsigned char regNo)
+{
+	unsigned char rxByte;
+
+	spi_lock ();
+	enc_cfg_spi ();
+	enc_enable ();
+
+	spi_write (0x1f);	/* read reg 0x1f */
+
+	bank = spi_read () & 0x3;
+
+	enc_disable ();
+	enc_enable ();
+
+	spi_write (regNo);
+	rxByte = spi_read ();
+
+	/* check if MAC or MII register */
+	if (((bank == 2) && (regNo <= 0x1a)) ||
+	    ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
+		/* ignore first byte and read another byte */
+		rxByte = spi_read ();
+	}
+
+	enc_disable ();
+	spi_unlock ();
+
+	return rxByte;
+}
+
+static void encReadBuff (unsigned short length, unsigned char *pBuff)
+{
+	spi_lock ();
+	enc_cfg_spi ();
+	enc_enable ();
+
+	spi_write (0x20 | 0x1a);	/* read buffer memory */
+
+	while (length--) {
+		if (pBuff != NULL)
+			*pBuff++ = spi_read ();
+		else
+			spi_write (0);
+	}
+
+	enc_disable ();
+	spi_unlock ();
+}
+
+static void encWriteBuff (unsigned short length, unsigned char *pBuff)
+{
+	spi_lock ();
+	enc_cfg_spi ();
+	enc_enable ();
+
+	spi_write (0x60 | 0x1a);	/* write buffer memory */
+
+	spi_write (0x00);	/* control byte */
+
+	while (length--)
+		spi_write (*pBuff++);
+
+	enc_disable ();
+	spi_unlock ();
+}
+
+static void encBitSet (unsigned char regNo, unsigned char data)
+{
+	spi_lock ();
+	enc_cfg_spi ();
+	enc_enable ();
+
+	spi_write (0x80 | regNo);	/* bit field set */
+	spi_write (data);
+
+	enc_disable ();
+	spi_unlock ();
+}
+
+static void encBitClr (unsigned char regNo, unsigned char data)
+{
+	spi_lock ();
+	enc_cfg_spi ();
+	enc_enable ();
+
+	spi_write (0xA0 | regNo);	/* bit field clear */
+	spi_write (data);
+
+	enc_disable ();
+	spi_unlock ();
+}
+
+static void encReset (void)
+{
+	spi_lock ();
+	enc_cfg_spi ();
+	enc_enable ();
+
+	spi_write (0xff);	/* soft reset */
+
+	enc_disable ();
+	spi_unlock ();
+
+	/* sleep 1 ms. See errata pt. 2 */
+	udelay (1000);
+
+#if 0
+	(*((volatile unsigned long *) IO1CLR)) &= ENC_RESET;
+	mdelay (5);
+	(*((volatile unsigned long *) IO1SET)) &= ENC_RESET;
+#endif
+}
+
+static void encInit (unsigned char *pEthAddr)
+{
+	unsigned short phid1 = 0;
+	unsigned short phid2 = 0;
+
+	/* switch to bank 0 */
+	m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
+
+	/*
+	 * Setup the buffer space. The reset values are valid for the
+	 * other pointers.
+	 */
+#if 0
+	/* We shall not write to ERXST, see errata pt. 5. Instead we
+	   have to make sure that ENC_RX_BUS_START is 0. */
+	m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
+	m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
+#endif
+	m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
+	m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
+
+	next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
+	next_pointer_msb = (ENC_RX_BUF_START >> 8);
+
+	/*
+	 * For tracking purposes, the ERXRDPT registers should be programmed with
+	 * the same value. This is the read pointer.
+	 */
+	m_nic_write (CTL_REG_ERXRDPTL, (ENC_RX_BUF_START & 0xFF));
+	m_nic_write_retry (CTL_REG_ERXRDPTH, (ENC_RX_BUF_START >> 8), 1);
+
+	/* Setup receive filters. */
+
+	/* move to bank 1 */
+	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+
+	/* OR-filtering, Unicast, CRC-check and broadcast */
+	m_nic_write_retry (CTL_REG_ERXFCON,
+			   (ENC_RFR_UCEN | ENC_RFR_CRCEN | ENC_RFR_BCEN), 1);
+
+	/* Wait for Oscillator Start-up Timer (OST). */
+	while ((m_nic_read (CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) == 0) {
+		static int cnt = 0;
+
+		if (cnt++ >= 1000) {
+			cnt = 0;
+		}
+	}
+
+	/* verify identification */
+	phid1 = phyRead (PHY_REG_PHID1);
+	phid2 = phyRead (PHY_REG_PHID2);
+
+	if (phid1 != ENC_PHID1_VALUE
+	    || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
+		printf ("ERROR: failed to identify controller\n");
+		printf ("phid1 = %x, phid2 = %x\n",
+			phid1, (phid2 & ENC_PHID2_MASK));
+		printf ("should be phid1 = %x, phid2 = %x\n",
+			ENC_PHID1_VALUE, ENC_PHID2_VALUE);
+	}
+
+	/*
+	 * --- MAC Initialization ---
+	 */
+
+	/* Pull MAC out of Reset */
+
+	/* switch to bank 2 */
+	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+	/* clear MAC reset bits */
+	m_nic_write_retry (CTL_REG_MACON2, 0, 1);
+
+	/* enable MAC to receive frames */
+	m_nic_write_retry (CTL_REG_MACON1, ENC_MACON1_MARXEN, 10);
+
+	/* configure pad, tx-crc and duplex */
+	/* TODO maybe enable FRMLNEN */
+	m_nic_write_retry (CTL_REG_MACON3,
+			   (ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN), 10);
+
+	/* set maximum frame length */
+	m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
+	m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
+
+	/*
+	 * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
+	 * and 0x15 for full duplex.
+	 */
+	m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
+
+	/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
+	m_nic_write_retry (CTL_REG_MAIPGL, 0x12, 10);
+
+	/*
+	 * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
+	 * 0x0c for half-duplex. Nothing for full-duplex
+	 */
+	m_nic_write_retry (CTL_REG_MAIPGH, 0x0C, 10);
+
+	/* set MAC address */
+
+	/* switch to bank 3 */
+	m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
+
+	m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
+	m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
+	m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
+	m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
+	m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
+	m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
+
+	/*
+	 * Receive settings
+	 */
+
+	/* auto-increment RX-pointer when reading a received packet */
+	m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_AUTOINC);
+
+	/* enable interrupts */
+	m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
+	m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
+	m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
+	m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
+	m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
+}
+
+/*****************************************************************************
+ *
+ * Description:
+ *    Read PHY registers.
+ *
+ *    NOTE! This function will change to Bank 2.
+ *
+ * Params:
+ *    [in] addr address of the register to read
+ *
+ * Returns:
+ *    The value in the register
+ */
+static unsigned short phyRead (unsigned char addr)
+{
+	unsigned short ret = 0;
+
+	/* move to bank 2 */
+	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+
+	/* write address to MIREGADR */
+	m_nic_write (CTL_REG_MIREGADR, addr);
+
+	/* set MICMD.MIIRD */
+	m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
+
+	/* poll MISTAT.BUSY bit until operation is complete */
+	while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
+		static int cnt = 0;
+
+		if (cnt++ >= 1000) {
+			/* GJ - this seems extremely dangerous! */
+			/* printf("#"); */
+			cnt = 0;
+		}
+	}
+
+	/* clear MICMD.MIIRD */
+	m_nic_write (CTL_REG_MICMD, 0);
+
+	ret = (m_nic_read (CTL_REG_MIRDH) << 8);
+	ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
+
+	return ret;
+}
diff --git a/board/lpc2292sodimm/flash.c b/board/lpc2292sodimm/flash.c
new file mode 100644
index 0000000..55aaabf
--- /dev/null
+++ b/board/lpc2292sodimm/flash.c
@@ -0,0 +1,476 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+/* IAP commands use 32 bytes at the top of CPU internal sram, we
+   use 512 bytes below that */
+#define COPY_BUFFER_LOCATION 0x40003de0
+
+#define IAP_LOCATION 0x7ffffff1
+#define IAP_CMD_PREPARE 50
+#define IAP_CMD_COPY 51
+#define IAP_CMD_ERASE 52
+#define IAP_CMD_CHECK 53
+#define IAP_CMD_ID 54
+#define IAP_CMD_VERSION 55
+#define IAP_CMD_COMPARE 56
+
+#define IAP_RET_CMD_SUCCESS 0
+
+#define SST_BASEADDR 0x80000000
+#define SST_ADDR1 ((volatile ushort*)(SST_BASEADDR + (0x5555 << 1)))
+#define SST_ADDR2 ((volatile ushort*)(SST_BASEADDR + (0x2AAA << 1)))
+
+
+static unsigned long command[5];
+static unsigned long result[2];
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+extern void iap_entry(unsigned long * command, unsigned long * result);
+
+/*-----------------------------------------------------------------------
+ *
+ */
+int get_flash_sector(flash_info_t * info, ulong flash_addr)
+{
+	int i;
+
+	for(i=1; i < (info->sector_count); i++) {
+		if (flash_addr < (info->start[i]))
+			break;
+	}
+
+	return (i-1);
+}
+
+/*-----------------------------------------------------------------------
+ * This function assumes that flash_addr is aligned on 512 bytes boundary
+ * in flash. This function also assumes that prepare have been called
+ * for the sector in question.
+ */
+int copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
+{
+	int first_sector;
+	int last_sector;
+
+	first_sector = get_flash_sector(info, flash_addr);
+	last_sector = get_flash_sector(info, flash_addr + 512 - 1);
+
+	/* prepare sectors for write */
+	command[0] = IAP_CMD_PREPARE;
+	command[1] = first_sector;
+	command[2] = last_sector;
+	iap_entry(command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf("IAP prepare failed\n");
+		return ERR_PROG_ERROR;
+	}
+
+	command[0] = IAP_CMD_COPY;
+	command[1] = flash_addr;
+	command[2] = COPY_BUFFER_LOCATION;
+	command[3] = 512;
+	command[4] = CFG_SYS_CLK_FREQ >> 10;
+	iap_entry(command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf("IAP copy failed\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ *
+ */
+void write_word_sst(ulong addr, ushort data)
+{
+	ushort tmp;
+
+	*SST_ADDR1 = 0x00AA;
+	*SST_ADDR2 = 0x0055;
+	*SST_ADDR1 = 0x00A0;
+	*((volatile ushort*)addr) = data;
+	/* do data polling */
+	do {
+		tmp = *((volatile ushort*)addr);
+	} while (tmp != data);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int j, k;
+	ulong size = 0;
+	ulong flashbase = 0;
+
+	flash_info[0].flash_id = (PHILIPS_LPC2292 & FLASH_VENDMASK);
+	flash_info[0].size = 0x003E000;	/* 256 - 8 KB */
+	flash_info[0].sector_count = 17;
+	memset (flash_info[0].protect, 0, 17);
+	flashbase = 0x00000000;
+	for (j = 0, k = 0; j < 8; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00002000;
+	}
+	for (j = 0; j < 2; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00010000;
+	}
+	for (j = 0; j < 7; j++, k++) {
+		flash_info[0].start[k] = flashbase;
+		flashbase += 0x00002000;
+	}
+	size += flash_info[0].size;
+
+	flash_info[1].flash_id = (SST_MANUFACT & FLASH_VENDMASK);
+	flash_info[1].size = 0x00200000; /* 2 MB */
+	flash_info[1].sector_count = 512;
+	memset (flash_info[1].protect, 0, 512);
+	flashbase = SST_BASEADDR;
+	for (j=0; j<512; j++) {
+		flash_info[1].start[j] = flashbase;
+		flashbase += 0x1000;	/* 4 KB sectors */
+	}
+	size += flash_info[1].size;
+
+	/* Protect monitor and environment sectors */
+	flash_protect (FLAG_PROTECT_SET,
+		 0x0,
+		 0x0 + monitor_flash_len - 1,
+		 &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		 CFG_ENV_ADDR,
+		 CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		 &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	int erased = 0;
+	unsigned long j;
+	unsigned long count;
+	unsigned char *p;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (SST_MANUFACT & FLASH_VENDMASK):
+		printf("SST: ");
+		break;
+	case (PHILIPS_LPC2292 & FLASH_VENDMASK):
+		printf("Philips: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+	  info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		if (i < (info->sector_count - 1)) {
+			count = info->start[i+1] - info->start[i];
+		}
+		else {
+			count = info->start[0] + info->size - info->start[i];
+		}
+		p = (unsigned char*)(info->start[i]);
+		erased = 1;
+		for (j = 0; j < count; j++) {
+			if (*p != 0xFF) {
+				erased = 0;
+				break;
+			}
+			p++;
+		}
+		printf (" %08lX%s%s", info->start[i], info->protect[i] ? " RO" : "   ",
+			erased ? " E" : "  ");
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase_philips (flash_info_t * info, int s_first, int s_last)
+{
+	int flag;
+	int prot;
+	int sect;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+
+	flag = disable_interrupts();
+
+	printf ("Erasing %d sectors starting at sector %2d.\n"
+	"This make take some time ... ",
+	s_last - s_first + 1, s_first);
+
+	command[0] = IAP_CMD_PREPARE;
+	command[1] = s_first;
+	command[2] = s_last;
+	iap_entry(command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf("IAP prepare failed\n");
+		return ERR_PROTECTED;
+	}
+
+	command[0] = IAP_CMD_ERASE;
+	command[1] = s_first;
+	command[2] = s_last;
+	command[3] = CFG_SYS_CLK_FREQ >> 10;
+	iap_entry(command, result);
+	if (result[0] != IAP_RET_CMD_SUCCESS) {
+		printf("IAP erase failed\n");
+		return ERR_PROTECTED;
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	return ERR_OK;
+}
+
+int flash_erase_sst (flash_info_t * info, int s_first, int s_last)
+{
+	int i;
+
+	for (i = s_first; i <= s_last; i++) {
+		*SST_ADDR1 = 0x00AA;
+		*SST_ADDR2 = 0x0055;
+		*SST_ADDR1 = 0x0080;
+		*SST_ADDR1 = 0x00AA;
+		*SST_ADDR2 = 0x0055;
+		*((volatile ushort*)(info->start[i])) = 0x0030;
+		/* wait for erase to finish */
+		udelay(25000);
+	}
+
+	return ERR_OK;
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case (SST_MANUFACT & FLASH_VENDMASK):
+			return flash_erase_sst(info, s_first, s_last);
+		case (PHILIPS_LPC2292 & FLASH_VENDMASK):
+			return flash_erase_philips(info, s_first, s_last);
+		default:
+			return ERR_PROTECTED;
+	}
+	return ERR_PROTECTED;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ *
+ * cnt is in bytes
+ */
+
+int write_buff_sst (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ushort tmp;
+	ulong i;
+	uchar* src_org;
+	uchar* dst_org;
+	ulong cnt_org = cnt;
+	int ret = ERR_OK;
+
+	src_org = src;
+	dst_org = (uchar*)addr;
+
+	if (addr & 1) {		/* if odd address */
+		tmp = *((uchar*)(addr - 1)); /* little endian */
+		tmp |= (*src << 8);
+		write_word_sst(addr - 1, tmp);
+		addr += 1;
+		cnt -= 1;
+		src++;
+	}
+	while (cnt > 1) {
+		tmp = ((*(src+1)) << 8) + (*src); /* little endian */
+		write_word_sst(addr, tmp);
+		addr += 2;
+		src += 2;
+		cnt -= 2;
+	}
+	if (cnt > 0) {
+		tmp = (*((uchar*)(addr + 1))) << 8;
+		tmp |= *src;
+		write_word_sst(addr, tmp);
+	}
+
+	for (i = 0; i < cnt_org; i++) {
+		if (*dst_org != *src_org) {
+			printf("Write failed. Byte %lX differs\n", i);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+		dst_org++;
+		src_org++;
+	}
+
+	return ret;
+}
+
+int write_buff_philips (flash_info_t * info,
+			uchar * src,
+			ulong addr,
+			ulong cnt)
+{
+	int first_copy_size;
+	int last_copy_size;
+	int first_block;
+	int last_block;
+	int nbr_mid_blocks;
+	uchar memmap_value;
+	ulong i;
+	uchar* src_org;
+	uchar* dst_org;
+	int ret = ERR_OK;
+
+	src_org = src;
+	dst_org = (uchar*)addr;
+
+	first_block = addr / 512;
+	last_block = (addr + cnt) / 512;
+	nbr_mid_blocks = last_block - first_block - 1;
+
+	first_copy_size = 512 - (addr % 512);
+	last_copy_size = (addr + cnt) % 512;
+
+#if 0
+	printf("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
+		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
+	(ulong)(first_block * 512),
+	(ulong)COPY_BUFFER_LOCATION,
+	(ulong)src,
+	(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
+	first_copy_size,
+	(ulong)COPY_BUFFER_LOCATION,
+	(ulong)(first_block * 512));
+#endif
+
+	/* copy first block */
+	memcpy((void*)COPY_BUFFER_LOCATION,
+		(void*)(first_block * 512), 512);
+	memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
+		src, first_copy_size);
+	copy_buffer_to_flash(info, first_block * 512);
+	src += first_copy_size;
+	addr += first_copy_size;
+
+	/* copy middle blocks */
+	for (i = 0; i < nbr_mid_blocks; i++) {
+#if 0
+		printf("copy middle block: %lX -> %lX 512 bytes, "
+		"%lX -> %lX 512 bytes\n",
+		(ulong)src,
+		(ulong)COPY_BUFFER_LOCATION,
+		(ulong)COPY_BUFFER_LOCATION,
+		(ulong)addr);
+#endif
+		memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
+		copy_buffer_to_flash(info, addr);
+		src += 512;
+		addr += 512;
+	}
+
+
+	if (last_copy_size > 0) {
+#if 0
+		printf("copy last block: (1) %lX -> %lX 0x200 bytes, "
+		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
+		(ulong)(last_block * 512),
+		(ulong)COPY_BUFFER_LOCATION,
+		(ulong)src,
+		(ulong)(COPY_BUFFER_LOCATION),
+		last_copy_size,
+		(ulong)COPY_BUFFER_LOCATION,
+		(ulong)addr);
+#endif
+		/* copy last block */
+		memcpy((void*)COPY_BUFFER_LOCATION,
+			(void*)(last_block * 512), 512);
+		memcpy((void*)COPY_BUFFER_LOCATION,
+			src, last_copy_size);
+		copy_buffer_to_flash(info, addr);
+	}
+
+	/* verify write */
+	memmap_value = GET8(MEMMAP);
+
+	disable_interrupts();
+
+	PUT8(MEMMAP, 01);		/* we must make sure that initial 64
+							   bytes are taken from flash when we
+							   do the compare */
+
+	for (i = 0; i < cnt; i++) {
+		if (*dst_org != *src_org){
+			printf("Write failed. Byte %lX differs\n", i);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+		dst_org++;
+		src_org++;
+	}
+
+	PUT8(MEMMAP, memmap_value);
+	enable_interrupts();
+
+	return ret;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case (SST_MANUFACT & FLASH_VENDMASK):
+			return write_buff_sst(info, src, addr, cnt);
+		case (PHILIPS_LPC2292 & FLASH_VENDMASK):
+			return write_buff_philips(info, src, addr, cnt);
+		default:
+			return ERR_PROG_ERROR;
+	}
+	return ERR_PROG_ERROR;
+}
diff --git a/board/lpc2292sodimm/iap_entry.S b/board/lpc2292sodimm/iap_entry.S
new file mode 100644
index 0000000..c31d519
--- /dev/null
+++ b/board/lpc2292sodimm/iap_entry.S
@@ -0,0 +1,7 @@
+IAP_ADDRESS:	.word	0x7FFFFFF1
+
+.globl iap_entry
+iap_entry:
+	ldr	r2, IAP_ADDRESS
+	bx	r2
+	mov	pc, lr
diff --git a/board/lpc2292sodimm/lowlevel_init.S b/board/lpc2292sodimm/lowlevel_init.S
new file mode 100644
index 0000000..a0e9747
--- /dev/null
+++ b/board/lpc2292sodimm/lowlevel_init.S
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/hardware.h>
+
+/* some parameters for the board */
+/* setting up the memory */
+#define 	SRAM_START 	0x40000000
+#define 	SRAM_SIZE	0x00004000
+#define   BCFG0_VALUE 0x1000ffef
+#define   BCFG1_VALUE 0x10001C61
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+MEMMAP_ADR:
+	.word	MEMMAP
+BCFG0_ADR:
+  .word BCFG0
+_BCFG0_VALUE:
+  .word BCFG0_VALUE
+BCFG1_ADR:
+	.word	BCFG1
+_BCFG1_VALUE:
+	.word	BCFG1_VALUE
+PINSEL2_ADR:
+	.word	PINSEL2
+PINSEL2_MASK:
+	.word	0x00000000
+PINSEL2_VALUE:
+	.word	0x0F800914
+
+.extern _start
+
+.globl lowlevel_init
+lowlevel_init:
+	/* set up memory control register for bank 0 */
+	ldr r0, _BCFG0_VALUE
+	ldr r1, BCFG0_ADR
+	str r0, [r1]
+
+	/* set up memory control register for bank 1 */
+	ldr	r0, _BCFG1_VALUE
+	ldr	r1, BCFG1_ADR
+	str	r0, [r1]
+
+	/* set up PINSEL2 for bus-pins */
+	ldr	r0, PINSEL2_ADR
+	ldr	r1, [r0]
+	ldr	r2, PINSEL2_MASK
+	ldr	r3, PINSEL2_VALUE
+	and	r1, r1, r2
+	orr	r1, r1, r3
+	str	r1, [r0]
+
+	/* move vectors to beginning of SRAM */
+	mov	r2, #SRAM_START
+	mov	r0, #0 /*_start*/
+	ldmneia r0!, {r3-r10}
+	stmneia r2!, {r3-r10}
+	ldmneia r0, {r3-r9}
+	stmneia r2, {r3-r9}
+
+	/* Set-up MEMMAP register, so vectors are taken from SRAM */
+	ldr	r0, MEMMAP_ADR
+	mov	r1, #0x02	/* vectors re-mapped to static RAM */
+	str	r1, [r0]
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/board/lpc2292sodimm/lpc2292sodimm.c b/board/lpc2292sodimm/lpc2292sodimm.c
new file mode 100644
index 0000000..d212c63
--- /dev/null
+++ b/board/lpc2292sodimm/lpc2292sodimm.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clps7111.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Activate LED flasher */
+	IO_LEDFLSH = 0x40;
+
+	/* arch number MACH_TYPE_ARMADILLO - not official*/
+	gd->bd->bi_arch_number = 83;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/board/lpc2292sodimm/mmc.c b/board/lpc2292sodimm/mmc.c
new file mode 100644
index 0000000..1c0922f
--- /dev/null
+++ b/board/lpc2292sodimm/mmc.c
@@ -0,0 +1,154 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <mmc.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include <part.h>
+#include <fat.h>
+#include "mmc_hw.h"
+#include "spi.h"
+
+#ifdef CONFIG_MMC
+
+#undef MMC_DEBUG
+
+static block_dev_desc_t mmc_dev;
+
+/* these are filled out by a call to mmc_hw_get_parameters */
+static int hw_size;		/* in kbytes */
+static int hw_nr_sects;
+static int hw_sect_size;	/* in bytes */
+
+block_dev_desc_t * mmc_get_dev(int dev)
+{
+	return (block_dev_desc_t *)(&mmc_dev);
+}
+
+unsigned long mmc_block_read(int dev,
+			     unsigned long start,
+			     lbaint_t blkcnt,
+			     unsigned long *buffer)
+{
+	unsigned long rc = 0;
+	unsigned char *p = (unsigned char *)buffer;
+	unsigned long i;
+	unsigned long addr = start;
+
+#ifdef MMC_DEBUG
+	printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
+		 (unsigned long)blkcnt);
+#endif
+
+	for(i = 0; i < (unsigned long)blkcnt; i++) {
+#ifdef MMC_DEBUG
+		printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
+#endif
+		(void)mmc_read_sector(addr, p);
+		rc++;
+		addr++;
+		p += hw_sect_size;
+	}
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------------
+ * Read hardware paramterers (sector size, size, number of sectors)
+ */
+static int mmc_hw_get_parameters(void)
+{
+	unsigned char csddata[16];
+	unsigned int sizemult;
+	unsigned int size;
+
+	mmc_read_csd(csddata);
+	hw_sect_size = 1<<(csddata[5] & 0x0f);
+	size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
+	sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
+	hw_nr_sects = (size+1)*(1<<(sizemult+2));
+	hw_size = hw_nr_sects*hw_sect_size/1024;
+
+#ifdef MMC_DEBUG
+	printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
+		 "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
+#endif
+
+	return 0;
+}
+
+int mmc_init(int verbose)
+{
+	int ret = -ENODEV;
+
+	if (verbose)
+		printf("mmc_init\n");
+
+	spi_init();
+	mmc_hw_init();
+
+	mmc_hw_get_parameters();
+
+	mmc_dev.if_type = IF_TYPE_MMC;
+	mmc_dev.part_type = PART_TYPE_DOS;
+	mmc_dev.dev = 0;
+	mmc_dev.lun = 0;
+	mmc_dev.type = 0;
+	mmc_dev.blksz = hw_sect_size;
+	mmc_dev.lba = hw_nr_sects;
+	sprintf((char*)mmc_dev.vendor, "Unknown vendor");
+	sprintf((char*)mmc_dev.product, "Unknown product");
+	sprintf((char*)mmc_dev.revision, "N/A");
+	mmc_dev.removable = 0;	/* should be true??? */
+	mmc_dev.block_read = mmc_block_read;
+
+	fat_register_device(&mmc_dev, 1);
+
+	ret = 0;
+
+	return ret;
+}
+
+int mmc_write(uchar * src, ulong dst, int size)
+{
+#ifdef MMC_DEBUG
+	printf("mmc_write: src=%p, dst=%lu, size=%u\n", src, dst, size);
+#endif
+	/* Since mmc2info always returns 0 this function will never be called */
+	return 0;
+}
+
+int mmc_read(ulong src, uchar * dst, int size)
+{
+#ifdef MMC_DEBUG
+	printf("mmc_read: src=%lu, dst=%p, size=%u\n", src, dst, size);
+#endif
+	/* Since mmc2info always returns 0 this function will never be called */
+	return 0;
+}
+
+int mmc2info(ulong addr)
+{
+	/* This function is used by cmd_cp to determine if source or destination
+	 address resides on MMC-card or not. We do not support copy to and from
+	 MMC-card so we always return 0. */
+	return 0;
+}
+
+#endif /* CONFIG_MMC */
diff --git a/board/lpc2292sodimm/mmc_hw.c b/board/lpc2292sodimm/mmc_hw.c
new file mode 100644
index 0000000..31f2a79
--- /dev/null
+++ b/board/lpc2292sodimm/mmc_hw.c
@@ -0,0 +1,233 @@
+/*
+    This code was original written by Ulrich Radig and modified by
+    Embedded Artists AB (www.embeddedartists.com).
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include "spi.h"
+
+#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
+#define MMC_Disable() PUT32(IO1SET, 1l << 22)
+#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
+
+static unsigned char Write_Command_MMC (unsigned char *CMD);
+static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
+		    unsigned short int Bytes);
+
+/* initialize the hardware */
+int mmc_hw_init(void)
+{
+	unsigned long a;
+	unsigned short int Timeout = 0;
+	unsigned char b;
+	unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
+
+	/* set-up GPIO and SPI */
+	(*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
+	(*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
+
+	MMC_Disable();
+
+	spi_lock();
+	spi_set_clock(248);
+	spi_set_cfg(0, 1, 0);
+	MMC_Enable();
+
+	/* waste some time */
+	for(a=0; a < 20000; a++)
+		asm("nop");
+
+	/* Put the MMC/SD-card into SPI-mode */
+	for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
+		spi_write(0xff);
+
+	/* Sends command CMD0 to MMC/SD-card */
+	while (Write_Command_MMC(CMD) != 1) {
+		if (Timeout++ > 200) {
+			MMC_Disable();
+			spi_unlock();
+			return(1); /* Abort with command 1 (return 1) */
+		}
+	}
+	/* Sends Command CMD1 an MMC/SD-card */
+	Timeout = 0;
+	CMD[0] = 0x41;/* Command 1 */
+	CMD[5] = 0xFF;
+
+	while (Write_Command_MMC(CMD) != 0) {
+		if (Timeout++ > 200) {
+			MMC_Disable();
+			spi_unlock();
+			return (2); /* Abort with command 2 (return 2) */
+		}
+	}
+
+	MMC_Disable();
+	spi_unlock();
+
+	return 0;
+}
+
+/* ############################################################################
+   Sends a command to the MMC/SD-card
+   ######################################################################### */
+static unsigned char Write_Command_MMC (unsigned char *CMD)
+{
+	unsigned char a, tmp = 0xff;
+	unsigned short int Timeout = 0;
+
+	MMC_Disable();
+	spi_write(0xFF);
+	MMC_Enable();
+
+	for (a = 0; a < 0x06; a++)
+		spi_write(*CMD++);
+
+	while (tmp == 0xff) {
+		tmp = spi_read();
+		if (Timeout++ > 5000)
+		  break;
+	}
+
+	return (tmp);
+}
+
+/* ############################################################################
+   Routine to read the CID register from the MMC/SD-card (16 bytes)
+   ######################################################################### */
+void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
+	int Bytes)
+{
+	unsigned short int a;
+
+	spi_lock();
+	mmc_spi_cfg();
+	MMC_Enable();
+
+	if (Write_Command_MMC(CMD) != 0) {
+		MMC_Disable();
+		spi_unlock();
+		return;
+	}
+
+	while (spi_read() != 0xfe) {};
+	for (a = 0; a < Bytes; a++)
+		*Buffer++ = spi_read();
+
+	/* Read the CRC-byte */
+	spi_read(); /* CRC - byte is discarded */
+	spi_read(); /* CRC - byte is discarded */
+	/* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
+	MMC_Disable();
+	spi_unlock();
+
+	return;
+}
+
+/* ############################################################################
+   Routine to read a block (512 bytes) from the MMC/SD-card
+   ######################################################################### */
+unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
+{
+	/* Command 16 to read aBlocks from the MMC/SD - caed */
+	unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
+
+	/* The addres on the MMC/SD-card is in bytes,
+	addr is transformed from blocks to bytes and the result is
+	placed into the command */
+
+	addr = addr << 9; /* addr = addr * 512 */
+
+	CMD[1] = ((addr & 0xFF000000) >> 24);
+	CMD[2] = ((addr & 0x00FF0000) >> 16);
+	CMD[3] = ((addr & 0x0000FF00) >> 8 );
+
+	MMC_Read_Block(CMD, Buffer, 512);
+
+	return (0);
+}
+
+/* ############################################################################
+   Routine to write a block (512 byte) to the MMC/SD-card
+   ######################################################################### */
+unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
+{
+	unsigned char tmp, a;
+	unsigned short int b;
+	/* Command 24 to write a block to the MMC/SD - card */
+	unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
+
+	/* The addres on the MMC/SD-card is in bytes,
+	addr is transformed from blocks to bytes and the result is
+	placed into the command */
+
+	addr = addr << 9; /* addr = addr * 512 */
+
+	CMD[1] = ((addr & 0xFF000000) >> 24);
+	CMD[2] = ((addr & 0x00FF0000) >> 16);
+	CMD[3] = ((addr & 0x0000FF00) >> 8 );
+
+	spi_lock();
+	mmc_spi_cfg();
+	MMC_Enable();
+
+	/* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
+	tmp = Write_Command_MMC(CMD);
+	if (tmp != 0) {
+		MMC_Disable();
+		spi_unlock();
+		return(tmp);
+	}
+
+	/* Do a short delay and send a clock-pulse to the MMC/SD-card */
+	for (a = 0; a < 100; a++)
+		spi_read();
+
+	/* Send a start byte to the MMC/SD-card */
+	spi_write(0xFE);
+
+	/* Write the block (512 bytes) to the MMC/SD-card */
+	for (b = 0; b < 512; b++)
+		spi_write(*Buffer++);
+
+	/* write the CRC-Byte */
+	spi_write(0xFF); /* write a dummy CRC */
+	spi_write(0xFF); /* CRC code is not used */
+
+	/* Wait for MMC/SD-card busy */
+	while (spi_read() != 0xff) {};
+
+	/* set MMC_Chip_Select to high (MMC/SD-card inactive) */
+	MMC_Disable();
+	spi_unlock();
+	return (0);
+}
+
+/* #########################################################################
+   Routine to read the CSD register from the MMC/SD-card (16 bytes)
+   ######################################################################### */
+unsigned char mmc_read_csd (unsigned char *Buffer)
+{
+	/* Command to read the CSD register */
+	unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
+
+	MMC_Read_Block(CMD, Buffer, 16);
+
+	return (0);
+}
diff --git a/board/lpc2292sodimm/mmc_hw.h b/board/lpc2292sodimm/mmc_hw.h
new file mode 100644
index 0000000..3687dbf
--- /dev/null
+++ b/board/lpc2292sodimm/mmc_hw.h
@@ -0,0 +1,29 @@
+/*
+    This module implements a linux character device driver for the 24c256 chip.
+    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef _MMC_HW_
+#define _MMC_HW_
+
+unsigned char mmc_read_csd(unsigned char *Buffer);
+unsigned char mmc_read_sector (unsigned long addr,
+			       unsigned char *Buffer);
+unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
+int mmc_hw_init(void);
+
+#endif /* _MMC_HW_ */
diff --git a/board/lpc2292sodimm/spi.c b/board/lpc2292sodimm/spi.c
new file mode 100644
index 0000000..4ba1468
--- /dev/null
+++ b/board/lpc2292sodimm/spi.c
@@ -0,0 +1,40 @@
+/*
+    This module implements an interface to the SPI on the lpc22xx.
+    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include "spi.h"
+
+unsigned long spi_flags;
+unsigned char spi_idle = 0x00;
+
+int spi_init(void)
+{
+	unsigned long pinsel0_value;
+
+	/* activate spi pins */
+	pinsel0_value = GET32(PINSEL0);
+	pinsel0_value &= ~(0xFFl << 8);
+	pinsel0_value |= (0x55l << 8);
+	PUT32(PINSEL0, pinsel0_value);
+
+	return 0;
+}
diff --git a/board/lpc2292sodimm/spi.h b/board/lpc2292sodimm/spi.h
new file mode 100644
index 0000000..6ae66e8
--- /dev/null
+++ b/board/lpc2292sodimm/spi.h
@@ -0,0 +1,82 @@
+/*
+    This file defines the interface to the lpc22xx SPI module.
+    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
+
+    This file may be included in software not adhering to the GPL.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef SPI_H
+#define SPI_H
+
+#include <config.h>
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+
+#define SPIF 0x80
+
+#define spi_lock() disable_interrupts();
+#define spi_unlock() enable_interrupts();
+
+extern unsigned long spi_flags;
+extern unsigned char spi_idle;
+
+int spi_init(void);
+
+static inline unsigned char spi_read(void)
+{
+	unsigned char b;
+
+	PUT8(S0SPDR, spi_idle);
+	while (!(GET8(S0SPSR) & SPIF));
+	b = GET8(S0SPDR);
+
+	return b;
+}
+
+static inline void spi_write(unsigned char b)
+{
+	PUT8(S0SPDR, b);
+	while (!(GET8(S0SPSR) & SPIF));
+	GET8(S0SPDR);		/* this will clear the SPIF bit */
+}
+
+static inline void spi_set_clock(unsigned char clk_value)
+{
+	PUT8(S0SPCCR, clk_value);
+}
+
+static inline void spi_set_cfg(unsigned char phase,
+			       unsigned char polarity,
+			       unsigned char lsbf)
+{
+	unsigned char v = 0x20;	/* master bit set */
+
+	if (phase)
+		v |= 0x08;			/* set phase bit */
+	if (polarity) {
+		v |= 0x10;			/* set polarity bit */
+		spi_idle = 0xFF;
+	} else {
+		spi_idle = 0x00;
+	}
+	if (lsbf)
+		v |= 0x40;			/* set lsbf bit */
+
+	PUT8(S0SPCR, v);
+}
+#endif /* SPI_H */
diff --git a/board/lpc2292sodimm/u-boot.lds b/board/lpc2292sodimm/u-boot.lds
new file mode 100644
index 0000000..64d946c
--- /dev/null
+++ b/board/lpc2292sodimm/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm720t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile
index 75808cb..5869119 100644
--- a/board/mcc200/Makefile
+++ b/board/mcc200/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o lcd.o
+COBJS	:= $(BOARD).o lcd.o auto_update.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c
new file mode 100644
index 0000000..90d03ec
--- /dev/null
+++ b/board/mcc200/auto_update.c
@@ -0,0 +1,522 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+#include <part.h>
+
+#ifdef CFG_HUSH_PARSER
+#include <hush.h>
+#endif
+
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#ifndef CONFIG_USB_OHCI
+#error "must define CONFIG_USB_OHCI"
+#endif
+
+#ifndef CONFIG_USB_STORAGE
+#error "must define CONFIG_USB_STORAGE"
+#endif
+
+#ifndef CFG_HUSH_PARSER
+#error "must define CFG_HUSH_PARSER"
+#endif
+
+#if !(CONFIG_COMMANDS & CFG_CMD_FAT)
+#error "must define CFG_CMD_FAT"
+#endif
+
+#undef AU_DEBUG
+
+#undef debug
+#ifdef	AU_DEBUG
+#define debug(fmt,args...)	printf (fmt ,##args)
+#else
+#define debug(fmt,args...)
+#endif	/* AU_DEBUG */
+
+/* possible names of files on the USB stick. */
+#define AU_FIRMWARE	"u-boot.img"
+#define AU_KERNEL	"kernel.img"
+#define AU_ROOTFS	"rootfs.img"
+
+struct flash_layout {
+	long start;
+	long end;
+};
+
+/* layout of the FLASH. ST = start address, ND = end address. */
+#define AU_FL_FIRMWARE_ST	0xfC000000
+#define AU_FL_FIRMWARE_ND	0xfC03FFFF
+#define AU_FL_KERNEL_ST		0xfC0C0000
+#define AU_FL_KERNEL_ND		0xfC1BFFFF
+#define AU_FL_ROOTFS_ST		0xFC1C0000
+#define AU_FL_ROOTFS_ND		0xFCFBFFFF
+
+static int au_usb_stor_curr_dev; /* current device */
+
+/* index of each file in the following arrays */
+#define IDX_FIRMWARE	0
+#define IDX_KERNEL	1
+#define IDX_ROOTFS	2
+
+/* max. number of files which could interest us */
+#define AU_MAXFILES 3
+
+/* pointers to file names */
+char *aufile[AU_MAXFILES] = {
+	AU_FIRMWARE,
+	AU_KERNEL,
+	AU_ROOTFS
+};
+
+/* sizes of flash areas for each file */
+long ausize[AU_MAXFILES] = {
+	(AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST,
+	(AU_FL_KERNEL_ND   + 1) - AU_FL_KERNEL_ST,
+	(AU_FL_ROOTFS_ND   + 1) - AU_FL_ROOTFS_ST,
+};
+
+/* array of flash areas start and end addresses */
+struct flash_layout aufl_layout[AU_MAXFILES] = {
+	{ AU_FL_FIRMWARE_ST,	AU_FL_FIRMWARE_ND, },
+	{ AU_FL_KERNEL_ST,	AU_FL_KERNEL_ND,   },
+	{ AU_FL_ROOTFS_ST,	AU_FL_ROOTFS_ND,   },
+};
+
+ulong totsize;
+
+/* where to load files into memory */
+#define LOAD_ADDR ((unsigned char *)0x00200000)
+
+/* the root file system is the largest image */
+#define MAX_LOADSZ ausize[IDX_ROOTFS]
+
+/*i2c address of the keypad status*/
+#define I2C_PSOC_KEYPAD_ADDR	0x53
+
+/* keypad mask */
+#define KEYPAD_ROW	2
+#define KEYPAD_COL	2
+#define KEYPAD_MASK_LO	((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF)
+#define KEYPAD_MASK_HI	((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8)
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
+extern int flash_sect_erase(ulong, ulong);
+extern int flash_sect_protect (int, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
+extern int u_boot_hush_start(void);
+#ifdef CONFIG_PROGRESSBAR
+extern void show_progress(int, int);
+extern void lcd_puts (char *);
+extern void lcd_enable(void);
+#endif
+
+int au_check_cksum_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) {
+		printf ("Image %s bad total SIZE\n", aufile[idx]);
+		return -1;
+	}
+	/* check the data CRC */
+	checksum = ntohl(hdr->ih_dcrc);
+
+	if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) != checksum) {
+		printf ("Image %s bad data checksum\n", aufile[idx]);
+		return -1;
+	}
+	return 0;
+}
+
+int au_check_header_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum, fsize;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+	/* check the easy ones first */
+#undef CHECK_VALID_DEBUG
+#ifdef CHECK_VALID_DEBUG
+	printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC);
+	printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_ARM);
+	printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes);
+	printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL);
+#endif
+	if (nbytes < sizeof(*hdr)) {
+		printf ("Image %s bad header SIZE\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC) {
+		printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	/* check the hdr CRC */
+	checksum = ntohl(hdr->ih_hcrc);
+	hdr->ih_hcrc = 0;
+
+	if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) {
+		printf ("Image %s bad header checksum\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	hdr->ih_hcrc = htonl(checksum);
+	/* check the type - could do this all in one gigantic if() */
+	if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	if ((idx == IDX_KERNEL) && (hdr->ih_type != IH_TYPE_KERNEL)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	if ((idx == IDX_ROOTFS) &&
+		( (hdr->ih_type != IH_TYPE_RAMDISK) && (hdr->ih_type != IH_TYPE_FILESYSTEM) )
+	   ) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	/* recycle checksum */
+	checksum = ntohl(hdr->ih_size);
+
+	fsize = checksum + sizeof(*hdr);
+	/* for kernel and ramdisk the image header must also fit into flash */
+	if (idx == IDX_KERNEL || hdr->ih_type == IH_TYPE_RAMDISK)
+		checksum += sizeof(*hdr);
+
+	/* check the size does not exceed space in flash. HUSH scripts */
+	if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
+		printf ("Image %s is bigger than FLASH\n", aufile[idx]);
+		ausize[idx] = 0;
+		return -1;
+	}
+	/* Update with the real filesize */
+	ausize[idx] = fsize;
+
+	return checksum; /* return size to be written to flash */
+}
+
+int au_do_update(int idx, long sz)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	int off, rc;
+	uint nbytes;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	/* execute a script */
+	if (hdr->ih_type == IH_TYPE_SCRIPT) {
+		addr = (char *)((char *)hdr + sizeof(*hdr));
+		/* stick a NULL at the end of the script, otherwise */
+		/* parse_string_outer() runs off the end. */
+		addr[ntohl(hdr->ih_size)] = 0;
+		addr += 8;
+		parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
+		return 0;
+	}
+
+	start = aufl_layout[idx].start;
+	end = aufl_layout[idx].end;
+
+	/* unprotect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE) {
+#undef AU_UPDATE_TEST
+#ifdef AU_UPDATE_TEST
+		/* erase it where Linux goes */
+		start = aufl_layout[1].start;
+		end = aufl_layout[1].end;
+#endif
+		flash_sect_protect(0, start, end);
+	}
+
+	/*
+	 * erase the address range.
+	 */
+	debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+	flash_sect_erase(start, end);
+	wait_ms(100);
+#ifdef CONFIG_PROGRESSBAR
+	show_progress(end - start, totsize);
+#endif
+
+	/* strip the header - except for the kernel and ramdisk */
+	if (hdr->ih_type == IH_TYPE_KERNEL || hdr->ih_type == IH_TYPE_RAMDISK) {
+		addr = (char *)hdr;
+		off = sizeof(*hdr);
+		nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
+	} else {
+		addr = (char *)((char *)hdr + sizeof(*hdr));
+#ifdef AU_UPDATE_TEST
+		/* copy it to where Linux goes */
+		if (idx == IDX_FIRMWARE)
+			start = aufl_layout[1].start;
+#endif
+		off = 0;
+		nbytes = ntohl(hdr->ih_size);
+	}
+
+	/* copy the data from RAM to FLASH */
+	debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
+	rc = flash_write(addr, start, nbytes);
+	if (rc != 0) {
+		printf("Flashing failed due to error %d\n", rc);
+		return -1;
+	}
+
+#ifdef CONFIG_PROGRESSBAR
+	show_progress(nbytes, totsize);
+#endif
+
+	/* check the data CRC of the copy */
+	if (crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) {
+		printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]);
+		return -1;
+	}
+
+	/* protect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE)
+		flash_sect_protect(1, start, end);
+	return 0;
+}
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev;
+	long sz;
+	int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc;
+	char *env;
+	long start, end;
+	uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0};
+
+	/*
+	 * Read keypad status
+	 */
+	i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2);
+	wait_ms(500);
+	i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2);
+
+	/*
+	 * Check keypad
+	 */
+	if ( !(keypad_status1[1] & KEYPAD_MASK_LO) ||
+	      (keypad_status1[1] != keypad_status2[1])) {
+		return 0;
+	}
+
+	au_usb_stor_curr_dev = -1;
+	/* start USB */
+	if (usb_stop() < 0) {
+		debug ("usb_stop failed\n");
+		return -1;
+	}
+	if (usb_init() < 0) {
+		debug ("usb_init failed\n");
+		return -1;
+	}
+	/*
+	 * check whether a storage device is attached (assume that it's
+	 * a USB memory stick, since nothing else should be attached).
+	 */
+	au_usb_stor_curr_dev = usb_stor_scan(0);
+	if (au_usb_stor_curr_dev == -1) {
+		debug ("No device found. Not initialized?\n");
+		return -1;
+	}
+	/* check whether it has a partition table */
+	stor_dev = get_dev("usb", 0);
+	if (stor_dev == NULL) {
+		debug ("uknown device type\n");
+		return -1;
+	}
+	if (fat_register_device(stor_dev, 1) != 0) {
+		debug ("Unable to use USB %d:%d for fatls\n",
+			au_usb_stor_curr_dev, 1);
+		return -1;
+	}
+	if (file_fat_detectfs() != 0) {
+		debug ("file_fat_detectfs failed\n");
+	}
+
+	/*
+	 * now check whether start and end are defined using environment
+	 * variables.
+	 */
+	start = -1;
+	end = 0;
+	env = getenv("firmware_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("firmware_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_FIRMWARE] = (end + 1) - start;
+		aufl_layout[IDX_FIRMWARE].start = start;
+		aufl_layout[IDX_FIRMWARE].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("kernel_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("kernel_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_KERNEL] = (end + 1) - start;
+		aufl_layout[IDX_KERNEL].start = start;
+		aufl_layout[IDX_KERNEL].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("rootfs_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("rootfs_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_ROOTFS] = (end + 1) - start;
+		aufl_layout[IDX_ROOTFS].start = start;
+		aufl_layout[IDX_ROOTFS].end = end;
+	}
+
+	/* make certain that HUSH is runnable */
+	u_boot_hush_start();
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc(0);
+
+	bitmap_first = 0;
+
+	/* validate the images first */
+	for (i = 0; i < AU_MAXFILES; i++) {
+		ulong imsize;
+		/* just read the header */
+		sz = file_fat_read(aufile[i], LOAD_ADDR, sizeof(image_header_t));
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, sizeof(image_header_t));
+		if (sz <= 0 || sz < sizeof(image_header_t)) {
+			debug ("%s not found\n", aufile[i]);
+			ausize[i] = 0;
+			continue;
+		}
+		/* au_check_header_valid() updates ausize[] */
+		if ((imsize = au_check_header_valid(i, sz)) < 0) {
+			debug ("%s header not valid\n", aufile[i]);
+			continue;
+		}
+		/* totsize accounts for image size and flash erase size */
+		totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start));
+	}
+
+#ifdef CONFIG_PROGRESSBAR
+	if (totsize) {
+		lcd_puts(" Update in progress\n");
+		lcd_enable();
+	}
+#endif
+
+	/* just loop thru all the possible files */
+	for (i = 0; i < AU_MAXFILES && totsize; i++) {
+		if (!ausize[i]) {
+			continue;
+		}
+		sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]);
+
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, sizeof(image_header_t));
+
+		if (sz != ausize[i]) {
+			printf ("%s: size %d read %d?\n", aufile[i], ausize[i], sz);
+			continue;
+		}
+
+		if (sz <= 0 || sz <= sizeof(image_header_t)) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_cksum_valid(i, sz) < 0) {
+			debug ("%s checksum not valid\n", aufile[i]);
+			continue;
+		}
+		/* this is really not a good idea, but it's what the */
+		/* customer wants. */
+		cnt = 0;
+		got_ctrlc = 0;
+		do {
+			res = au_do_update(i, sz);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc()) {
+				clear_ctrlc();
+				if (res < 0)
+					got_ctrlc = 1;
+				break;
+			}
+			cnt++;
+#ifdef AU_TEST_ONLY
+		} while (res < 0 && cnt < (AU_MAXFILES + 1));
+		if (cnt < (AU_MAXFILES + 1))
+#else
+		} while (res < 0);
+#endif
+	}
+	usb_stop();
+	/* restore the old state */
+	disable_ctrlc(old_ctrlc);
+#ifdef CONFIG_PROGRESSBAR
+	if (totsize) {
+		if (!res) {
+			lcd_puts("\n  Update completed\n");
+		} else {
+			lcd_puts("\n   Update error\n");
+		}
+		lcd_enable();
+	}
+#endif
+	return 0;
+}
+#endif /* CONFIG_AUTO_UPDATE */
diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c
index b262516..98b86d1 100644
--- a/board/mcc200/lcd.c
+++ b/board/mcc200/lcd.c
@@ -24,13 +24,13 @@
 
 #ifdef CONFIG_LCD
 
-#define SWAPPED_LCD
+#undef SWAPPED_LCD /* For the previous h/w version */
 /*
  *  The name of the device used for communication
  * with the PSoC.
  */
 #define PSOC_PSC	MPC5XXX_PSC2
-#define PSOC_BAUD	500000UL
+#define PSOC_BAUD	230400UL
 
 #define RTS_ASSERT	1
 #define RTS_NEGATE	0
@@ -181,10 +181,35 @@ void lcd_enable (void)
 		udelay (PSOC_WAIT_TIME);
 	}
 	if (!retries) {
-		printf ("%s Error: PSoC doesn't respond on "
+		printf ("%s Warning: PSoC doesn't respond on "
 			"RTS NEGATE\n",	__FUNCTION__);
 	}
 
 	return;
 }
+#ifdef CONFIG_PROGRESSBAR
+
+#define FONT_WIDTH      8 /* the same as VIDEO_FONT_WIDTH in video_font.h */
+void show_progress (int size, int tot)
+{
+	int cnt;
+	int i;
+	static int rc = 0;
+
+	rc += size;
+
+	cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot;
+
+	rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH);
+
+	for (i = 0; i < cnt; i++) {
+		lcd_putc(0xdc);
+	}
+
+	if (cnt) {
+		lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */
+	}
+}
+
+#endif
 #endif /* CONFIG_LCD */
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 5d74bde..af047e2 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -44,6 +44,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern flash_info_t flash_info[];	/* FLASH chips info */
 
+extern int do_auto_update(void);
 ulong flash_get_size (ulong base, int banknum);
 
 #ifndef CFG_RAMBOOT
@@ -91,8 +92,8 @@ static void sdram_start (int hi_addr)
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
- *            is something else than 0x00000000.
+ *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      is something else than 0x00000000.
  */
 
 long int initdram (int board_type)
@@ -289,6 +290,9 @@ int misc_init_r (void)
 		flash_info[0].sector_count = snum;
 	}
 
+#ifdef CONFIG_AUTO_UPDATE
+	do_auto_update();
+#endif
 	return (0);
 }
 
diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile
new file mode 100644
index 0000000..698ead1
--- /dev/null
+++ b/board/motionpro/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/motionpro/config.mk b/board/motionpro/config.mk
new file mode 100644
index 0000000..e7934d2
--- /dev/null
+++ b/board/motionpro/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2006-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Promess Motion-PRO
+#
+
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
new file mode 100644
index 0000000..d60d233
--- /dev/null
+++ b/board/motionpro/motionpro.c
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
+ * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
+ * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
+ * Also changed the refresh for 100Mhz operation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+
+/* Kollmorgen DPR initialization data */
+struct init_elem {
+	unsigned long addr;
+	unsigned len;
+	char *data;
+	} init_seq[] = {
+		{0x500003F2, 2, "\x86\x00"},		/* HW parameter */
+		{0x500003F0, 2, "\x00\x00"},
+		{0x500003EC, 4, "\x00\x80\xc1\x52"},	/* Magic word */
+	};
+
+/*
+ * Initialize Kollmorgen DPR
+ */
+static void kollmorgen_init(void)
+{
+	unsigned i, j;
+	vu_char *p;
+
+	for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
+		p = (vu_char *)init_seq[i].addr;
+		for (j = 0; j < init_seq[i].len; ++j)
+			*(p + j) = *(init_seq[i].data + j);
+	}
+
+	printf("DPR:   Kollmorgen DPR initialized\n");
+}
+
+
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+	/* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
+
+	/* Initialize Kollmorgen DPR */
+	kollmorgen_init();
+
+	return 0;
+}
+
+
+#ifndef CFG_RAMBOOT
+/*
+ * Helper function to initialize SDRAM controller.
+ */
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+						hi_addr_bit;
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+						hi_addr_bit;
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+						hi_addr_bit;
+
+	/* auto refresh, second time */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+						hi_addr_bit;
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+}
+#endif /* !CFG_RAMBOOT */
+
+
+/*
+ * Initalize SDRAM - configure SDRAM controller, detect memory size.
+ */
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* configure SDRAM start/end for detection */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	sdram_start(0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 and disable it */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
+
+#else /* !CFG_RAMBOOT */
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+#endif /* CFG_RAMBOOT */
+
+	/* return total ram size */
+	return dramsize;
+}
+
+
+int checkboard (void)
+{
+	puts("Board: Promess Motion-PRO board\n");
+	return 0;
+}
diff --git a/board/motionpro/u-boot.lds b/board/motionpro/u-boot.lds
new file mode 100644
index 0000000..8fa9c0f
--- /dev/null
+++ b/board/motionpro/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mpc832xemds/Makefile b/board/mpc832xemds/Makefile
new file mode 100644
index 0000000..5ec7a87
--- /dev/null
+++ b/board/mpc832xemds/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o pci.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/stamp/config.mk b/board/mpc832xemds/config.mk
index 0d00730..6c3eca7 100644
--- a/board/stamp/config.mk
+++ b/board/mpc832xemds/config.mk
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2001
+# (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -21,5 +21,8 @@
 # MA 02111-1307 USA
 #
 
-TEXT_BASE = 0x07FC0000
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+#
+# MPC832XEMDS
+#
+
+TEXT_BASE = 0xFE000000
diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c
new file mode 100644
index 0000000..772da67
--- /dev/null
+++ b/board/mpc832xemds/mpc832xemds.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <command.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#else
+#include <asm/mmu.h>
+#endif
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* ETH3 */
+	{1,  0, 1, 0, 1}, /* TxD0 */
+	{1,  1, 1, 0, 1}, /* TxD1 */
+	{1,  2, 1, 0, 1}, /* TxD2 */
+	{1,  3, 1, 0, 1}, /* TxD3 */
+	{1,  9, 1, 0, 1}, /* TxER */
+	{1, 12, 1, 0, 1}, /* TxEN */
+	{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
+
+	{1,  4, 2, 0, 1}, /* RxD0 */
+	{1,  5, 2, 0, 1}, /* RxD1 */
+	{1,  6, 2, 0, 1}, /* RxD2 */
+	{1,  7, 2, 0, 1}, /* RxD3 */
+	{1,  8, 2, 0, 1}, /* RxER */
+	{1, 10, 2, 0, 1}, /* RxDV */
+	{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
+	{1, 11, 2, 0, 1}, /* COL */
+	{1, 13, 2, 0, 1}, /* CRS */
+
+	/* ETH4 */
+	{1, 18, 1, 0, 1}, /* TxD0 */
+	{1, 19, 1, 0, 1}, /* TxD1 */
+	{1, 20, 1, 0, 1}, /* TxD2 */
+	{1, 21, 1, 0, 1}, /* TxD3 */
+	{1, 27, 1, 0, 1}, /* TxER */
+	{1, 30, 1, 0, 1}, /* TxEN */
+	{3,  6, 2, 0, 1}, /* TxCLK->CLK8 */
+
+	{1, 22, 2, 0, 1}, /* RxD0 */
+	{1, 23, 2, 0, 1}, /* RxD1 */
+	{1, 24, 2, 0, 1}, /* RxD2 */
+	{1, 25, 2, 0, 1}, /* RxD3 */
+	{1, 26, 1, 0, 1}, /* RxER */
+	{1, 28, 2, 0, 1}, /* Rx_DV */
+	{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
+	{1, 29, 2, 0, 1}, /* COL */
+	{1, 31, 2, 0, 1}, /* CRS */
+
+	{3,  4, 3, 0, 2}, /* MDIO */
+	{3,  5, 1, 0, 2}, /* MDC */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+int board_early_init_f(void)
+{
+	volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
+
+	/* Enable flash write */
+	bcsr[9] &= ~0x08;
+
+	return 0;
+}
+
+int fixed_sdram(void);
+
+long int initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+
+	msize = fixed_sdram();
+
+	puts("\n   DDR RAM: ");
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CFG_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CFG_DDR_SIZE != 128)
+#warning Currenly any ddr size other than 128 is not supported
+#endif
+	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CFG_DDR_MODE;
+	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
+	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	__asm__ __volatile__ ("sync");
+	udelay(200);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	__asm__ __volatile__ ("sync");
+	return msize;
+}
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC832XEMDS\n");
+	return 0;
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+}
+#endif
diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c
new file mode 100644
index 0000000..d0a407a
--- /dev/null
+++ b/board/mpc832xemds/pci.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/*
+ * PCI Configuration space access support for MPC83xx PCI Bridge
+ */
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <pci.h>
+#include <i2c.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PCI)
+#define PCI_FUNCTION_CONFIG   0x44
+#define PCI_FUNCTION_CFG_LOCK 0x20
+
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxemds_config_table[] = {
+	{
+		PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+		pci_cfgfunc_config_device,
+		{PCI_ENET0_IOADDR,
+		PCI_ENET0_MEMADDR,
+		PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+	},
+	{}
+}
+#endif
+static struct pci_controller hose[] = {
+	{
+#ifndef CONFIG_PCI_PNP
+		config_table:pci_mpc83xxemds_config_table,
+#endif
+	},
+};
+
+/**********************************************************************
+ * pci_init_board()
+ *********************************************************************/
+void pci_init_board(void)
+#ifdef CONFIG_PCISLAVE
+{
+	u16 reg16;
+	volatile immap_t *immr;
+	volatile law83xx_t *pci_law;
+	volatile pot83xx_t *pci_pot;
+	volatile pcictrl83xx_t *pci_ctrl;
+	volatile pciconf83xx_t *pci_conf;
+
+	immr = (immap_t *) CFG_IMMR;
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = immr->pci_ctrl;
+	pci_conf = immr->pci_conf;
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+	pci_ctrl[0].pitar0 = 0x0;
+	pci_ctrl[0].pibar0 = 0x0;
+	pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
+	    PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
+
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 &= ~PIWAR_EN;
+
+	pci_ctrl[0].pitar2 = 0x0;
+	pci_ctrl[0].pibar2 = 0x0;
+	pci_ctrl[0].piebar2 = 0x0;
+	pci_ctrl[0].piwar2 &= ~PIWAR_EN;
+
+	hose[0].first_busno = 0;
+	hose[0].last_busno = 0xff;
+	pci_setup_indirect(&hose[0],
+			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+	reg16 = 0xff;
+
+	pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
+				  PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
+				   PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
+				   PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
+				   PCI_LATENCY_TIMER, 0x80);
+
+	/*
+	 * Unlock configuration lock in PCI function configuration register.
+	 */
+	pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
+				  PCI_FUNCTION_CONFIG, &reg16);
+	reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
+	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
+				   PCI_FUNCTION_CONFIG, reg16);
+
+	printf("Enabled PCI 32bit Agent Mode\n");
+}
+#else
+{
+	volatile immap_t *immr;
+	volatile clk83xx_t *clk;
+	volatile law83xx_t *pci_law;
+	volatile pot83xx_t *pci_pot;
+	volatile pcictrl83xx_t *pci_ctrl;
+	volatile pciconf83xx_t *pci_conf;
+
+	u8 val8, orig_i2c_bus;
+	u16 reg16;
+	u32 val32;
+	u32 dev;
+
+	immr = (immap_t *) CFG_IMMR;
+	clk = (clk83xx_t *) & immr->clk;
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = immr->pci_ctrl;
+	pci_conf = immr->pci_conf;
+	/*
+	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+	 */
+	val32 = clk->occr;
+	udelay(2000);
+#if defined(PCI_66M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#elif defined(PCI_33M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
+	    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
+	printf("PCI clock is 33MHz\n");
+#else
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#endif
+	udelay(2000);
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI mem space - prefetch */
+	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].pocmr =
+	    POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/* PCI mmio - non-prefetch mem space */
+	pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/* PCI IO space */
+	pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+	pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
+	pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 =
+	    PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
+	    PIWAR_IWS_2G;
+
+	/*
+	 * Assign PIB PMC slot to desired PCI bus
+	 */
+
+	/* Switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	val8 = 0;
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+
+	val8 = 0xf9;		/* PMC2, PMC3 slot to PCI bus */
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+	asm("eieio");
+
+	/* Reset to original I2C bus */
+	i2c_set_bus_num(orig_i2c_bus);
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	udelay(2000);
+	pci_ctrl[0].gcr = 1;
+	udelay(2000);
+
+	hose[0].first_busno = 0;
+	hose[0].last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose[0].regions + 0,
+		       CFG_PCI_MEM_BASE,
+		       CFG_PCI_MEM_PHYS,
+		       CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose[0].regions + 1,
+		       CFG_PCI_MMIO_BASE,
+		       CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose[0].regions + 2,
+		       CFG_PCI_IO_BASE,
+		       CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose[0].regions + 3,
+		       CFG_PCI_SLV_MEM_LOCAL,
+		       CFG_PCI_SLV_MEM_BUS,
+		       CFG_PCI_SLV_MEM_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose[0].region_count = 4;
+
+	pci_setup_indirect(&hose[0],
+			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(0, 0, 0);
+	pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+	printf("PCI 32bit bus on PMC2 & PMC3\n");
+
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+}
+#endif				/* CONFIG_PCISLAVE */
+
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
+	if (p != NULL) {
+		p[0] = hose[0].first_busno;
+		p[1] = hose[0].last_busno;
+	}
+}
+#endif				/* CONFIG_OF_FLAT_TREE */
+#endif				/* CONFIG_PCI */
diff --git a/board/mpc832xemds/u-boot.lds b/board/mpc832xemds/u-boot.lds
new file mode 100644
index 0000000..937c87a
--- /dev/null
+++ b/board/mpc832xemds/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc83xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/mpc8349emds/Makefile b/board/mpc8349emds/Makefile
index acc9544..5ec7a87 100644
--- a/board/mpc8349emds/Makefile
+++ b/board/mpc8349emds/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o
+COBJS	:= $(BOARD).o pci.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c
index b5ccb53..071591e 100644
--- a/board/mpc8349emds/mpc8349emds.c
+++ b/board/mpc8349emds/mpc8349emds.c
@@ -33,6 +33,10 @@
 #if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
 #endif
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
 int fixed_sdram(void);
 void sdram_init(void);
 
@@ -59,7 +63,7 @@ int board_early_init_f (void)
 
 long int initdram (int board_type)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
@@ -96,7 +100,7 @@ long int initdram (int board_type)
  ************************************************************************/
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
@@ -115,6 +119,20 @@ int fixed_sdram(void)
 #if (CFG_DDR_SIZE != 256)
 #warning Currenly any ddr size other than 256 is not supported
 #endif
+#ifdef CONFIG_DDR_II
+	im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS;
+	im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG;
+	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CFG_DDR_MODE;
+	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
+	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+#else
 	im->ddr.csbnds[2].csbnds = 0x0000000f;
 	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
 
@@ -139,6 +157,7 @@ int fixed_sdram(void)
 	im->ddr.sdram_mode = CFG_DDR_MODE;
 
 	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+#endif
 	udelay(200);
 
 	/* enable DDR controller */
@@ -167,8 +186,8 @@ int checkboard (void)
 
 void sdram_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile lbus8349_t *lbc= &immap->lbus;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile lbus83xx_t *lbc= &immap->lbus;
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 
 	puts("\n   SDRAM on Local Bus: ");
@@ -235,7 +254,7 @@ void sdram_init(void)
 #else
 void sdram_init(void)
 {
-	put("SDRAM on Local Bus is NOT available!\n");
+	puts("   SDRAM on Local Bus is NOT available!\n");
 }
 #endif
 
@@ -245,8 +264,8 @@ void sdram_init(void)
  */
 void ecc_print_status(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile ddr8349_t *ddr = &immap->ddr;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
 
 	printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
 
@@ -320,8 +339,8 @@ void ecc_print_status(void)
 
 int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile ddr8349_t *ddr = &immap->ddr;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
 	volatile u32 val;
 	u64 *addr, count, val64;
 	register u64 *i;
@@ -564,3 +583,23 @@ U_BOOT_CMD(
 	"  - re-inits memory"
 );
 #endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+}
+#endif
diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c
index 63e4405..d6a12b8 100644
--- a/board/mpc8349emds/pci.c
+++ b/board/mpc8349emds/pci.c
@@ -68,12 +68,13 @@ static struct pci_controller pci_hose[] = {
 void
 pib_init(void)
 {
-	u8 val8;
+	u8 val8, orig_i2c_bus;
 	/*
 	 * Assign PIB PMC slot to desired PCI bus
 	 */
-	mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	/* Switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
 
 	val8 = 0;
 	i2c_write(0x23, 0x6, 1, &val8, 1);
@@ -118,6 +119,8 @@ pib_init(void)
 	printf("PCI1: 32-bit on PMC1, PMC2\n");
 	printf("PCI2: 32-bit on PMC3\n");
 #endif
+	/* Reset to original I2C bus */
+	i2c_set_bus_num(orig_i2c_bus);
 }
 
 /**************************************************************************
@@ -130,18 +133,18 @@ void
 pci_init_board(void)
 {
 	volatile immap_t *	immr;
-	volatile clk8349_t *	clk;
-	volatile law8349_t *	pci_law;
-	volatile pot8349_t *	pci_pot;
-	volatile pcictrl8349_t *	pci_ctrl;
-	volatile pciconf8349_t *	pci_conf;
+	volatile clk83xx_t *	clk;
+	volatile law83xx_t *	pci_law;
+	volatile pot83xx_t *	pci_pot;
+	volatile pcictrl83xx_t *	pci_ctrl;
+	volatile pciconf83xx_t *	pci_conf;
 	u16 reg16;
 	u32 reg32;
 	u32 dev;
 	struct	pci_controller * hose;
 
-	immr = (immap_t *)CFG_IMMRBAR;
-	clk = (clk8349_t *)&immr->clk;
+	immr = (immap_t *)CFG_IMMR;
+	clk = (clk83xx_t *)&immr->clk;
 	pci_law = immr->sysconf.pcilaw;
 	pci_pot = immr->ios.pot;
 	pci_ctrl = immr->pci_ctrl;
@@ -254,8 +257,8 @@ pci_init_board(void)
 	hose->region_count = 4;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMRBAR+0x8300),
-			   (CFG_IMMRBAR+0x8304));
+			   (CFG_IMMR+0x8300),
+			   (CFG_IMMR+0x8304));
 
 	pci_register_hose(hose);
 
@@ -350,8 +353,8 @@ pci_init_board(void)
 	hose->region_count = 4;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMRBAR+0x8380),
-			   (CFG_IMMRBAR+0x8384));
+			   (CFG_IMMR+0x8380),
+			   (CFG_IMMR+0x8384));
 
 	pci_register_hose(hose);
 
@@ -379,4 +382,26 @@ pci_init_board(void)
 
 }
 
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+       	u32 *p;
+       	int len;
+
+       	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
+       	if (p != NULL) {
+		p[0] = pci_hose[0].first_busno;
+		p[1] = pci_hose[0].last_busno;
+       	}
+
+#ifdef CONFIG_MPC83XX_PCI2
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
+	if (p != NULL) {
+		p[0] = pci_hose[1].first_busno;
+		p[1] = pci_hose[1].last_busno;
+	}
+#endif
+}
+#endif /* CONFIG_OF_FLAT_TREE */
 #endif /* CONFIG_PCI */
diff --git a/board/mpc8349itx/Makefile b/board/mpc8349itx/Makefile
new file mode 100644
index 0000000..31bcdb8
--- /dev/null
+++ b/board/mpc8349itx/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o pci.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mpc8349itx/config.mk b/board/mpc8349itx/config.mk
new file mode 100644
index 0000000..1901fdc
--- /dev/null
+++ b/board/mpc8349itx/config.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC8349E-mITX and MPC8349E-mITX-GP
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE  =   0xFEF00000
+endif
+
+ifneq ($(OBJTREE),$(SRCTREE))
+# We are building u-boot in a separate directory, use generated
+# .lds script from OBJTREE directory.
+LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds
+endif
diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c
new file mode 100644
index 0000000..2b3ded1
--- /dev/null
+++ b/board/mpc8349itx/mpc8349itx.c
@@ -0,0 +1,407 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+
+#ifdef CONFIG_PCI
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#endif
+
+#ifdef CONFIG_SPD_EEPROM
+#include <spd_sdram.h>
+#else
+#include <asm/mmu.h>
+#endif
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+#ifndef CONFIG_SPD_EEPROM
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	u32 ddr_size;		/* The size of RAM, in bytes */
+	u32 ddr_size_log2 = 0;
+
+	for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+		ddr_size_log2++;
+	}
+
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+	im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff;
+
+	/* Only one CS0 for DDR */
+	im->ddr.csbnds[0].csbnds = 0x0000000f;
+	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+
+	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
+	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
+
+	debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
+	debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
+
+	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
+	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR;
+	im->ddr.sdram_mode =
+	    (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
+	im->ddr.sdram_interval =
+	    (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
+						       SDRAM_INTERVAL_BSTOPRE_SHIFT);
+	im->ddr.sdram_clk_cntl =
+	    DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
+
+	udelay(200);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
+	debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
+	debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
+	debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
+	debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
+
+	return CFG_DDR_SIZE;
+}
+#endif
+
+#ifdef CONFIG_PCI
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
+	{
+	 PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 0x0f,
+	 PCI_ANY_ID,
+	 pci_cfgfunc_config_device,
+	 {
+	  PCI_ENET0_IOADDR,
+	  PCI_ENET0_MEMADDR,
+	  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
+	 },
+	{}
+}
+#endif
+
+volatile static struct pci_controller hose[] = {
+	{
+#ifndef CONFIG_PCI_PNP
+	      config_table:pci_mpc83xxmitx_config_table,
+#endif
+	 },
+	{
+#ifndef CONFIG_PCI_PNP
+	      config_table:pci_mpc83xxmitx_config_table,
+#endif
+	 }
+};
+#endif				/* CONFIG_PCI */
+
+long int initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	u32 msize = 0;
+#ifdef CONFIG_DDR_ECC
+	volatile ddr83xx_t *ddr = &im->ddr;
+#endif
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#ifdef CONFIG_SPD_EEPROM
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+
+#ifdef CONFIG_DDR_ECC
+	if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
+		/* Unlike every other board, on the 83xx spd_sdram() returns
+		   megabytes instead of just bytes.  That's why we need to
+		   multiple by 1MB when calling ddr_enable_ecc(). */
+		ddr_enable_ecc(msize * 1048576);
+#endif
+
+	puts("   DDR RAM: ");
+	/* return total bus RAM size(bytes) */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_MPC8349ITX
+	puts("Board: Freescale MPC8349E-mITX\n");
+#else
+	puts("Board: Freescale MPC8349E-mITX-GP\n");
+#endif
+
+	return 0;
+}
+
+/*
+ * Implement a work-around for a hardware problem with compact
+ * flash.
+ *
+ * Program the UPM if compact flash is enabled.
+ */
+int misc_init_f(void)
+{
+#ifdef CONFIG_VSC7385
+	volatile u32 *vsc7385_cpuctrl;
+
+	/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
+	   default of VSC7385 L1_IRQ and L2_IRQ requests are active high.  That
+	   means it is 0 when the IRQ is not active.  This makes the wire-AND
+	   logic always assert IRQ7 to CPU even if there is no request from the
+	   switch.  Since the compact flash and the switch share the same IRQ,
+	   the Linux kernel will think that the compact flash is requesting irq
+	   and get stuck when it tries to clear the IRQ.  Thus we need to set
+	   the L2_IRQ0 and L2_IRQ1 to active low.
+
+	   The following code sets the L1_IRQ and L2_IRQ polarity to active low.
+	   Without this code, compact flash will not work in Linux because
+	   unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
+	   don't enable compact flash for U-Boot.
+	 */
+
+	vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0);
+	*vsc7385_cpuctrl |= 0x0c;
+#endif
+
+#ifdef CONFIG_COMPACT_FLASH
+	/* UPM Table Configuration Code */
+	static uint UPMATable[] = {
+		0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
+		0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
+		0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
+	};
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile lbus83xx_t *lbus = &immap->lbus;
+
+	lbus->bank[3].br = CFG_BR3_PRELIM;
+	lbus->bank[3].or = CFG_OR3_PRELIM;
+
+	/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
+	   GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
+	 */
+	lbus->mamr = 0x08404440;
+
+	upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
+
+	puts("UPMA:  Configured for compact flash\n");
+#endif
+
+	return 0;
+}
+
+/*
+ * Make sure the EEPROM has the HRCW correctly programmed.
+ * Make sure the RTC is correctly programmed.
+ *
+ * The MPC8349E-mITX can be configured to load the HRCW from
+ * EEPROM instead of flash.  This is controlled via jumpers
+ * LGPL0, 1, and 3.  Normally, these jumpers are set to 000 (all
+ * jumpered), but if they're set to 001 or 010, then the HRCW is
+ * read from the "I2C EEPROM".
+ *
+ * This function makes sure that the I2C EEPROM is programmed
+ * correctly.
+ */
+int misc_init_r(void)
+{
+	int rc = 0;
+
+#ifdef CONFIG_HARD_I2C
+
+	unsigned int orig_bus = i2c_get_bus_num();
+	u8 i2c_data;
+
+#ifdef CFG_I2C_RTC_ADDR
+	u8 ds1339_data[17];
+#endif
+
+#ifdef CFG_I2C_EEPROM_ADDR
+	static u8 eeprom_data[] =	/* HRCW data */
+	{
+		0xAA, 0x55, 0xAA,       /* Preamble */
+		0x7C, 		        /* ACS=0, BYTE_EN=1111, CONT=1 */
+		0x02, 0x40, 	        /* RCWL ADDR=0x0_0900 */
+		(CFG_HRCW_LOW >> 24) & 0xFF,
+		(CFG_HRCW_LOW >> 16) & 0xFF,
+		(CFG_HRCW_LOW >> 8) & 0xFF,
+		CFG_HRCW_LOW & 0xFF,
+		0x7C, 		        /* ACS=0, BYTE_EN=1111, CONT=1 */
+		0x02, 0x41,	        /* RCWH ADDR=0x0_0904 */
+		(CFG_HRCW_HIGH >> 24) & 0xFF,
+		(CFG_HRCW_HIGH >> 16) & 0xFF,
+		(CFG_HRCW_HIGH >> 8) & 0xFF,
+		CFG_HRCW_HIGH & 0xFF
+	};
+
+	u8 data[sizeof(eeprom_data)];
+#endif
+
+	printf("Board revision: ");
+	i2c_set_bus_num(1);
+	if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+		printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
+	else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+		printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
+	else {
+		printf("Unknown\n");
+		rc = 1;
+	}
+
+#ifdef CFG_I2C_EEPROM_ADDR
+	i2c_set_bus_num(0);
+
+	if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
+		if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
+			if (i2c_write
+			    (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
+			     sizeof(eeprom_data)) != 0) {
+				puts("Failure writing the HRCW to EEPROM via I2C.\n");
+				rc = 1;
+			}
+		}
+	} else {
+		puts("Failure reading the HRCW from EEPROM via I2C.\n");
+		rc = 1;
+	}
+#endif
+
+#ifdef CFG_I2C_RTC_ADDR
+	i2c_set_bus_num(1);
+
+	if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
+	    == 0) {
+
+		/* Work-around for MPC8349E-mITX bug #13601.
+		   If the RTC does not contain valid register values, the DS1339
+		   Linux driver will not work.
+		 */
+
+		/* Make sure status register bits 6-2 are zero */
+		ds1339_data[0x0f] &= ~0x7c;
+
+		/* Check for a valid day register value */
+		ds1339_data[0x03] &= ~0xf8;
+		if (ds1339_data[0x03] == 0) {
+			ds1339_data[0x03] = 1;
+		}
+
+		/* Check for a valid date register value */
+		ds1339_data[0x04] &= ~0xc0;
+		if ((ds1339_data[0x04] == 0) ||
+		    ((ds1339_data[0x04] & 0x0f) > 9) ||
+		    (ds1339_data[0x04] >= 0x32)) {
+			ds1339_data[0x04] = 1;
+		}
+
+		/* Check for a valid month register value */
+		ds1339_data[0x05] &= ~0x60;
+
+		if ((ds1339_data[0x05] == 0) ||
+		    ((ds1339_data[0x05] & 0x0f) > 9) ||
+		    ((ds1339_data[0x05] >= 0x13)
+		     && (ds1339_data[0x05] <= 0x19))) {
+			ds1339_data[0x05] = 1;
+		}
+
+		/* Enable Oscillator and rate select */
+		ds1339_data[0x0e] = 0x1c;
+
+		/* Work-around for MPC8349E-mITX bug #13330.
+		   Ensure that the RTC control register contains the value 0x1c.
+		   This affects SATA performance.
+		 */
+
+		if (i2c_write
+		    (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data,
+		     sizeof(ds1339_data))) {
+			puts("Failure writing to the RTC via I2C.\n");
+			rc = 1;
+		}
+	} else {
+		puts("Failure reading from the RTC via I2C.\n");
+		rc = 1;
+	}
+#endif
+
+	i2c_set_bus_num(orig_bus);
+#endif
+
+	return rc;
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+}
+#endif
diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c
new file mode 100644
index 0000000..e81ad27
--- /dev/null
+++ b/board/mpc8349itx/pci.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_PCI
+
+#include <asm/mmu.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8349itx_config_table[] = {
+	{
+	 PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_IDSEL_NUMBER,
+	 PCI_ANY_ID,
+	 pci_cfgfunc_config_device,
+	 {
+	  PCI_ENET0_IOADDR,
+	  PCI_ENET0_MEMADDR,
+	  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
+	 },
+	{}
+};
+#endif
+
+static struct pci_controller pci_hose[] = {
+	{
+#ifndef CONFIG_PCI_PNP
+	      config_table:pci_mpc8349itx_config_table,
+#endif
+	 },
+	{
+#ifndef CONFIG_PCI_PNP
+	      config_table:pci_mpc8349itx_config_table,
+#endif
+	 }
+};
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not currently supported
+ *
+ */
+void pci_init_board(void)
+{
+	volatile immap_t *immr;
+	volatile clk83xx_t *clk;
+	volatile law83xx_t *pci_law;
+	volatile pot83xx_t *pci_pot;
+	volatile pcictrl83xx_t *pci_ctrl;
+	volatile pciconf83xx_t *pci_conf;
+	u8 reg8;
+	u16 reg16;
+	u32 reg32;
+	u32 dev;
+	struct pci_controller *hose;
+
+	immr = (immap_t *) CFG_IMMR;
+	clk = (clk83xx_t *) & immr->clk;
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = immr->pci_ctrl;
+	pci_conf = immr->pci_conf;
+
+	hose = &pci_hose[0];
+
+	/*
+	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+	 */
+
+	reg32 = clk->occr;
+	udelay(2000);
+
+#ifdef CONFIG_HARD_I2C
+	i2c_set_bus_num(1);
+	/* Read the PCI_M66EN jumper setting */
+	if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
+	    (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
+		if (reg8 & I2C_8574_PCI66)
+			clk->occr = 0xff000000;	/* 66 MHz PCI */
+		else
+			clk->occr = 0xff600001;	/* 33 MHz PCI */
+	} else {
+		clk->occr = 0xff600001;	/* 33 MHz PCI */
+	}
+#else
+	clk->occr = 0xff000000;	/* 66 MHz PCI */
+#endif
+
+	udelay(2000);
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	pci_ctrl[0].gcr = 0;
+	udelay(2000);
+	pci_ctrl[0].gcr = 1;
+
+#ifdef CONFIG_MPC83XX_PCI2
+	pci_ctrl[1].gcr = 0;
+	udelay(2000);
+	pci_ctrl[1].gcr = 1;
+#endif
+
+	/* We need to wait at least a 1sec based on PCI specs */
+	{
+		int i;
+
+		for (i = 0; i < 1000; i++)
+			udelay(1000);
+	}
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI1 mem space - prefetch */
+	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
+
+	/* PCI1 IO space */
+	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
+
+	/* PCI1 mmio - non-prefetch mem space */
+	pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+	    PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI1_MEM_BASE,
+		       CFG_PCI1_MEM_PHYS,
+		       CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI1_MMIO_BASE,
+		       CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CFG_PCI1_IO_BASE,
+		       CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 3,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	pci_setup_indirect(hose,
+			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+
+#ifdef CONFIG_MPC83XX_PCI2
+	hose = &pci_hose[1];
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI2 mem space - prefetch */
+	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;
+
+	/* PCI2 IO space */
+	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
+
+	/* PCI2 mmio - non-prefetch mem space */
+	pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	pci_ctrl[1].pitar1 = 0x0;
+	pci_ctrl[1].pibar1 = 0x0;
+	pci_ctrl[1].piebar1 = 0x0;
+	pci_ctrl[1].piwar1 =
+	    PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
+	    (__ilog2(gd->ram_size) - 1);
+
+	hose->first_busno = pci_hose[0].last_busno + 1;
+	hose->last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI2_MEM_BASE,
+		       CFG_PCI2_MEM_PHYS,
+		       CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI2_MMIO_BASE,
+		       CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CFG_PCI2_IO_BASE,
+		       CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 3,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	pci_setup_indirect(hose,
+			   (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+#endif
+}
+
+#endif				/* CONFIG_PCI */
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+       	u32 *p;
+       	int len;
+
+       	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
+       	if (p != NULL) {
+		p[0] = pci_hose[0].first_busno;
+		p[1] = pci_hose[0].last_busno;
+       	}
+
+#ifdef CONFIG_MPC83XX_PCI2
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
+	if (p != NULL) {
+		p[0] = pci_hose[1].first_busno;
+		p[1] = pci_hose[1].last_busno;
+	}
+#endif
+}
+#endif /* CONFIG_OF_FLAT_TREE */
diff --git a/board/mpc8349itx/u-boot.lds b/board/mpc8349itx/u-boot.lds
new file mode 100644
index 0000000..f044c0f
--- /dev/null
+++ b/board/mpc8349itx/u-boot.lds
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc83xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/mpc8360emds/Makefile b/board/mpc8360emds/Makefile
new file mode 100644
index 0000000..5ec7a87
--- /dev/null
+++ b/board/mpc8360emds/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o pci.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ezkit533/config.mk b/board/mpc8360emds/config.mk
index 36c9f99..9ace886 100644
--- a/board/ezkit533/config.mk
+++ b/board/mpc8360emds/config.mk
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2001
+# (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -21,5 +21,8 @@
 # MA 02111-1307 USA
 #
 
-TEXT_BASE = 0x01FC0000
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
+#
+# MPC8360EMDS
+#
+
+TEXT_BASE = 0xFE000000
diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c
new file mode 100644
index 0000000..535884c
--- /dev/null
+++ b/board/mpc8360emds/mpc8360emds.c
@@ -0,0 +1,679 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on board/mpc8349emds/mpc8349emds.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <command.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#else
+#include <asm/mmu.h>
+#endif
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+	/* GETH1 */
+	{0,  3, 1, 0, 1}, /* TxD0 */
+	{0,  4, 1, 0, 1}, /* TxD1 */
+	{0,  5, 1, 0, 1}, /* TxD2 */
+	{0,  6, 1, 0, 1}, /* TxD3 */
+	{1,  6, 1, 0, 3}, /* TxD4 */
+	{1,  7, 1, 0, 1}, /* TxD5 */
+	{1,  9, 1, 0, 2}, /* TxD6 */
+	{1, 10, 1, 0, 2}, /* TxD7 */
+	{0,  9, 2, 0, 1}, /* RxD0 */
+	{0, 10, 2, 0, 1}, /* RxD1 */
+	{0, 11, 2, 0, 1}, /* RxD2 */
+	{0, 12, 2, 0, 1}, /* RxD3 */
+	{0, 13, 2, 0, 1}, /* RxD4 */
+	{1,  1, 2, 0, 2}, /* RxD5 */
+	{1,  0, 2, 0, 2}, /* RxD6 */
+	{1,  4, 2, 0, 2}, /* RxD7 */
+	{0,  7, 1, 0, 1}, /* TX_EN */
+	{0,  8, 1, 0, 1}, /* TX_ER */
+	{0, 15, 2, 0, 1}, /* RX_DV */
+	{0, 16, 2, 0, 1}, /* RX_ER */
+	{0,  0, 2, 0, 1}, /* RX_CLK */
+	{2,  9, 1, 0, 3}, /* GTX_CLK - CLK10 */
+	{2,  8, 2, 0, 1}, /* GTX125 - CLK9 */
+	/* GETH2 */
+	{0, 17, 1, 0, 1}, /* TxD0 */
+	{0, 18, 1, 0, 1}, /* TxD1 */
+	{0, 19, 1, 0, 1}, /* TxD2 */
+	{0, 20, 1, 0, 1}, /* TxD3 */
+	{1,  2, 1, 0, 1}, /* TxD4 */
+	{1,  3, 1, 0, 2}, /* TxD5 */
+	{1,  5, 1, 0, 3}, /* TxD6 */
+	{1,  8, 1, 0, 3}, /* TxD7 */
+	{0, 23, 2, 0, 1}, /* RxD0 */
+	{0, 24, 2, 0, 1}, /* RxD1 */
+	{0, 25, 2, 0, 1}, /* RxD2 */
+	{0, 26, 2, 0, 1}, /* RxD3 */
+	{0, 27, 2, 0, 1}, /* RxD4 */
+	{1, 12, 2, 0, 2}, /* RxD5 */
+	{1, 13, 2, 0, 3}, /* RxD6 */
+	{1, 11, 2, 0, 2}, /* RxD7 */
+	{0, 21, 1, 0, 1}, /* TX_EN */
+	{0, 22, 1, 0, 1}, /* TX_ER */
+	{0, 29, 2, 0, 1}, /* RX_DV */
+	{0, 30, 2, 0, 1}, /* RX_ER */
+	{0, 31, 2, 0, 1}, /* RX_CLK */
+	{2,  2, 1, 0, 2}, /* GTX_CLK = CLK10 */
+	{2,  3, 2, 0, 1}, /* GTX125 - CLK4 */
+
+	{0,  1, 3, 0, 2}, /* MDIO */
+	{0,  2, 1, 0, 1}, /* MDC */
+
+	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+int board_early_init_f(void)
+{
+
+	u8 *bcsr = (u8 *)CFG_BCSR;
+	const immap_t *immr = (immap_t *)CFG_IMMR;
+
+	/* Enable flash write */
+	bcsr[0xa] &= ~0x04;
+
+	/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
+	if (immr->sysconf.spridr == SPR_8360_REV20 ||
+	    immr->sysconf.spridr == SPR_8360E_REV20)
+		bcsr[0xe] = 0x30;
+
+	return 0;
+}
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+void sdram_init(void);
+
+long int initdram(int board_type)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+	/*
+	 * Initialize DDR ECC byte
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+	/*
+	 * Initialize SDRAM if it is on local bus.
+	 */
+	sdram_init();
+	puts("   DDR RAM: ");
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CFG_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].ar =
+	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CFG_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+#ifdef CONFIG_DDR_II
+	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CFG_DDR_MODE;
+	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
+	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+#else
+	im->ddr.csbnds[0].csbnds = 0x00000007;
+	im->ddr.csbnds[1].csbnds = 0x0008000f;
+
+	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[1] = CFG_DDR_CONFIG;
+
+	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+	im->ddr.sdram_cfg = CFG_DDR_CONTROL;
+
+	im->ddr.sdram_mode = CFG_DDR_MODE;
+	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+#endif
+	udelay(200);
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	return msize;
+}
+#endif				/*!CFG_SPD_EEPROM */
+
+int checkboard(void)
+{
+	puts("Board: Freescale MPC8360EMDS\n");
+	return 0;
+}
+
+/*
+ * if MPC8360EMDS is soldered with SDRAM
+ */
+#if defined(CFG_BR2_PRELIM)  \
+	&& defined(CFG_OR2_PRELIM) \
+	&& defined(CFG_LBLAWBAR2_PRELIM) \
+	&& defined(CFG_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile lbus83xx_t *lbc = &immap->lbus;
+	uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
+
+	puts("\n   SDRAM on Local Bus: ");
+	print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+	/*
+	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+	 */
+	/*setup mtrpt, lsrt and lbcr for LB bus */
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller Machine Mode Register.
+	 */
+	lbc->lsdmr = CFG_LBC_LSDMR_5;	/* Normal Operation */
+	lbc->lsdmr = CFG_LBC_LSDMR_1;	/* Precharge All Banks */
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/*
+	 * We need do 8 times auto refresh operation.
+	 */
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	*sdram_addr = 0xff;	/* 1 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 2 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 3 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 4 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 5 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 6 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 7 times */
+	udelay(100);
+	*sdram_addr = 0xff;	/* 8 times */
+	udelay(100);
+
+	/* Mode register write operation */
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	*(sdram_addr + 0xcc) = 0xff;
+	udelay(100);
+
+	/* Normal operation */
+	lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+}
+#else
+void sdram_init(void)
+{
+	puts("SDRAM on Local Bus is NOT available!\n");
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
+/*
+ * ECC user commands
+ */
+void ecc_print_status(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
+
+	printf("\nECC mode: %s\n\n",
+	       (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
+
+	/* Interrupts */
+	printf("Memory Error Interrupt Enable:\n");
+	printf("  Multiple-Bit Error Interrupt Enable: %d\n",
+	       (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
+	printf("  Single-Bit Error Interrupt Enable: %d\n",
+	       (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
+	printf("  Memory Select Error Interrupt Enable: %d\n\n",
+	       (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
+
+	/* Error disable */
+	printf("Memory Error Disable:\n");
+	printf("  Multiple-Bit Error Disable: %d\n",
+	       (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
+	printf("  Sinle-Bit Error Disable: %d\n",
+	       (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
+	printf("  Memory Select Error Disable: %d\n\n",
+	       (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
+
+	/* Error injection */
+	printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
+	       ddr->data_err_inject_hi, ddr->data_err_inject_lo);
+
+	printf("Memory Data Path Error Injection Mask ECC:\n");
+	printf("  ECC Mirror Byte: %d\n",
+	       (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
+	printf("  ECC Injection Enable: %d\n",
+	       (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
+	printf("  ECC Error Injection Mask: 0x%02x\n\n",
+	       ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
+
+	/* SBE counter/threshold */
+	printf("Memory Single-Bit Error Management (0..255):\n");
+	printf("  Single-Bit Error Threshold: %d\n",
+	       (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
+	printf("  Single-Bit Error Counter: %d\n\n",
+	       (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
+
+	/* Error detect */
+	printf("Memory Error Detect:\n");
+	printf("  Multiple Memory Errors: %d\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
+	printf("  Multiple-Bit Error: %d\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
+	printf("  Single-Bit Error: %d\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
+	printf("  Memory Select Error: %d\n\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
+
+	/* Capture data */
+	printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
+	printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
+	       ddr->capture_data_hi, ddr->capture_data_lo);
+	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
+	       ddr->capture_ecc & CAPTURE_ECC_ECE);
+
+	printf("Memory Error Attributes Capture:\n");
+	printf(" Data Beat Number: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
+	       ECC_CAPT_ATTR_BNUM_SHIFT);
+	printf("  Transaction Size: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
+	       ECC_CAPT_ATTR_TSIZ_SHIFT);
+	printf("  Transaction Source: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
+	       ECC_CAPT_ATTR_TSRC_SHIFT);
+	printf("  Transaction Type: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
+	       ECC_CAPT_ATTR_TTYP_SHIFT);
+	printf("  Error Information Valid: %d\n\n",
+	       ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
+}
+
+int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
+	volatile u32 val;
+	u64 *addr;
+	u32 count;
+	register u64 *i;
+	u32 ret[2];
+	u32 pattern[2];
+	u32 writeback[2];
+
+	/* The pattern is written into memory to generate error */
+	pattern[0] = 0xfedcba98UL;
+	pattern[1] = 0x76543210UL;
+
+	/* After injecting error, re-initialize the memory with the value */
+	writeback[0] = 0x01234567UL;
+	writeback[1] = 0x89abcdefUL;
+
+	if (argc > 4) {
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (argc == 2) {
+		if (strcmp(argv[1], "status") == 0) {
+			ecc_print_status();
+			return 0;
+		} else if (strcmp(argv[1], "captureclear") == 0) {
+			ddr->capture_address = 0;
+			ddr->capture_data_hi = 0;
+			ddr->capture_data_lo = 0;
+			ddr->capture_ecc = 0;
+			ddr->capture_attributes = 0;
+			return 0;
+		}
+	}
+	if (argc == 3) {
+		if (strcmp(argv[1], "sbecnt") == 0) {
+			val = simple_strtoul(argv[2], NULL, 10);
+			if (val > 255) {
+				printf("Incorrect Counter value, "
+				       "should be 0..255\n");
+				return 1;
+			}
+
+			val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
+			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
+
+			ddr->err_sbe = val;
+			return 0;
+		} else if (strcmp(argv[1], "sbethr") == 0) {
+			val = simple_strtoul(argv[2], NULL, 10);
+			if (val > 255) {
+				printf("Incorrect Counter value, "
+				       "should be 0..255\n");
+				return 1;
+			}
+
+			val = (val << ECC_ERROR_MAN_SBET_SHIFT);
+			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
+
+			ddr->err_sbe = val;
+			return 0;
+		} else if (strcmp(argv[1], "errdisable") == 0) {
+			val = ddr->err_disable;
+
+			if (strcmp(argv[2], "+sbe") == 0) {
+				val |= ECC_ERROR_DISABLE_SBED;
+			} else if (strcmp(argv[2], "+mbe") == 0) {
+				val |= ECC_ERROR_DISABLE_MBED;
+			} else if (strcmp(argv[2], "+mse") == 0) {
+				val |= ECC_ERROR_DISABLE_MSED;
+			} else if (strcmp(argv[2], "+all") == 0) {
+				val |= (ECC_ERROR_DISABLE_SBED |
+					ECC_ERROR_DISABLE_MBED |
+					ECC_ERROR_DISABLE_MSED);
+			} else if (strcmp(argv[2], "-sbe") == 0) {
+				val &= ~ECC_ERROR_DISABLE_SBED;
+			} else if (strcmp(argv[2], "-mbe") == 0) {
+				val &= ~ECC_ERROR_DISABLE_MBED;
+			} else if (strcmp(argv[2], "-mse") == 0) {
+				val &= ~ECC_ERROR_DISABLE_MSED;
+			} else if (strcmp(argv[2], "-all") == 0) {
+				val &= ~(ECC_ERROR_DISABLE_SBED |
+					 ECC_ERROR_DISABLE_MBED |
+					 ECC_ERROR_DISABLE_MSED);
+			} else {
+				printf("Incorrect err_disable field\n");
+				return 1;
+			}
+
+			ddr->err_disable = val;
+			__asm__ __volatile__("sync");
+			__asm__ __volatile__("isync");
+			return 0;
+		} else if (strcmp(argv[1], "errdetectclr") == 0) {
+			val = ddr->err_detect;
+
+			if (strcmp(argv[2], "mme") == 0) {
+				val |= ECC_ERROR_DETECT_MME;
+			} else if (strcmp(argv[2], "sbe") == 0) {
+				val |= ECC_ERROR_DETECT_SBE;
+			} else if (strcmp(argv[2], "mbe") == 0) {
+				val |= ECC_ERROR_DETECT_MBE;
+			} else if (strcmp(argv[2], "mse") == 0) {
+				val |= ECC_ERROR_DETECT_MSE;
+			} else if (strcmp(argv[2], "all") == 0) {
+				val |= (ECC_ERROR_DETECT_MME |
+					ECC_ERROR_DETECT_MBE |
+					ECC_ERROR_DETECT_SBE |
+					ECC_ERROR_DETECT_MSE);
+			} else {
+				printf("Incorrect err_detect field\n");
+				return 1;
+			}
+
+			ddr->err_detect = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectdatahi") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+
+			ddr->data_err_inject_hi = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectdatalo") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+
+			ddr->data_err_inject_lo = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectecc") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+			if (val > 0xff) {
+				printf("Incorrect ECC inject mask, "
+				       "should be 0x00..0xff\n");
+				return 1;
+			}
+			val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
+
+			ddr->ecc_err_inject = val;
+			return 0;
+		} else if (strcmp(argv[1], "inject") == 0) {
+			val = ddr->ecc_err_inject;
+
+			if (strcmp(argv[2], "en") == 0)
+				val |= ECC_ERR_INJECT_EIEN;
+			else if (strcmp(argv[2], "dis") == 0)
+				val &= ~ECC_ERR_INJECT_EIEN;
+			else
+				printf("Incorrect command\n");
+
+			ddr->ecc_err_inject = val;
+			__asm__ __volatile__("sync");
+			__asm__ __volatile__("isync");
+			return 0;
+		} else if (strcmp(argv[1], "mirror") == 0) {
+			val = ddr->ecc_err_inject;
+
+			if (strcmp(argv[2], "en") == 0)
+				val |= ECC_ERR_INJECT_EMB;
+			else if (strcmp(argv[2], "dis") == 0)
+				val &= ~ECC_ERR_INJECT_EMB;
+			else
+				printf("Incorrect command\n");
+
+			ddr->ecc_err_inject = val;
+			return 0;
+		}
+	}
+	if (argc == 4) {
+		if (strcmp(argv[1], "testdw") == 0) {
+			addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
+			count = simple_strtoul(argv[3], NULL, 16);
+
+			if ((u32) addr % 8) {
+				printf("Address not alligned on "
+				       "double word boundary\n");
+				return 1;
+			}
+			disable_interrupts();
+
+			for (i = addr; i < addr + count; i++) {
+
+				/* enable injects */
+				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__("sync");
+				__asm__ __volatile__("isync");
+
+				/* write memory location injecting errors */
+				ppcDWstore((u32 *) i, pattern);
+				__asm__ __volatile__("sync");
+
+				/* disable injects */
+				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__("sync");
+				__asm__ __volatile__("isync");
+
+				/* read data, this generates ECC error */
+				ppcDWload((u32 *) i, ret);
+				__asm__ __volatile__("sync");
+
+				/* re-initialize memory, double word write the location again,
+				 * generates new ECC code this time */
+				ppcDWstore((u32 *) i, writeback);
+				__asm__ __volatile__("sync");
+			}
+			enable_interrupts();
+			return 0;
+		}
+		if (strcmp(argv[1], "testword") == 0) {
+			addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
+			count = simple_strtoul(argv[3], NULL, 16);
+
+			if ((u32) addr % 8) {
+				printf("Address not alligned on "
+				       "double word boundary\n");
+				return 1;
+			}
+			disable_interrupts();
+
+			for (i = addr; i < addr + count; i++) {
+
+				/* enable injects */
+				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__("sync");
+				__asm__ __volatile__("isync");
+
+				/* write memory location injecting errors */
+				*(u32 *) i = 0xfedcba98UL;
+				__asm__ __volatile__("sync");
+
+				/* sub double word write,
+				 * bus will read-modify-write,
+				 * generates ECC error */
+				*((u32 *) i + 1) = 0x76543210UL;
+				__asm__ __volatile__("sync");
+
+				/* disable injects */
+				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__("sync");
+				__asm__ __volatile__("isync");
+
+				/* re-initialize memory,
+				 * double word write the location again,
+				 * generates new ECC code this time */
+				ppcDWstore((u32 *) i, writeback);
+				__asm__ __volatile__("sync");
+			}
+			enable_interrupts();
+			return 0;
+		}
+	}
+	printf("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(ecc, 4, 0, do_ecc,
+	   "ecc     - support for DDR ECC features\n",
+	   "status              - print out status info\n"
+	   "ecc captureclear        - clear capture regs data\n"
+	   "ecc sbecnt <val>        - set Single-Bit Error counter\n"
+	   "ecc sbethr <val>        - set Single-Bit Threshold\n"
+	   "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
+	   "  [-|+]sbe - Single-Bit Error\n"
+	   "  [-|+]mbe - Multiple-Bit Error\n"
+	   "  [-|+]mse - Memory Select Error\n"
+	   "  [-|+]all - all errors\n"
+	   "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
+	   "  mme - Multiple Memory Errors\n"
+	   "  sbe - Single-Bit Error\n"
+	   "  mbe - Multiple-Bit Error\n"
+	   "  mse - Memory Select Error\n"
+	   "  all - all errors\n"
+	   "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
+	   "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
+	   "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
+	   "ecc inject <en|dis>    - enable/disable error injection\n"
+	   "ecc mirror <en|dis>    - enable/disable mirror byte\n"
+	   "ecc testdw <addr> <cnt>  - test mem region with double word access:\n"
+	   "  - enables injects\n"
+	   "  - writes pattern injecting errors with double word access\n"
+	   "  - disables injects\n"
+	   "  - reads pattern back with double word access, generates error\n"
+	   "  - re-inits memory\n"
+	   "ecc testword <addr> <cnt>  - test mem region with word access:\n"
+	   "  - enables injects\n"
+	   "  - writes pattern injecting errors with word access\n"
+	   "  - writes pattern with word access, generates error\n"
+	   "  - disables injects\n" "  - re-inits memory");
+#endif				/* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+}
+#endif
diff --git a/board/mpc8360emds/pci.c b/board/mpc8360emds/pci.c
new file mode 100644
index 0000000..67cd709
--- /dev/null
+++ b/board/mpc8360emds/pci.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/*
+ * PCI Configuration space access support for MPC83xx PCI Bridge
+ */
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <pci.h>
+#include <i2c.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PCI)
+#define PCI_FUNCTION_CONFIG   0x44
+#define PCI_FUNCTION_CFG_LOCK 0x20
+
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxemds_config_table[] = {
+	{
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 pci_cfgfunc_config_device,
+	 {PCI_ENET0_IOADDR,
+	  PCI_ENET0_MEMADDR,
+	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+	 },
+	{}
+}
+#endif
+static struct pci_controller hose[] = {
+	{
+#ifndef CONFIG_PCI_PNP
+	      config_table:pci_mpc83xxemds_config_table,
+#endif
+	 },
+};
+
+/**********************************************************************
+ * pci_init_board()
+ *********************************************************************/
+void pci_init_board(void)
+#ifdef CONFIG_PCISLAVE
+{
+	u16 reg16;
+	volatile immap_t *immr;
+	volatile law83xx_t *pci_law;
+	volatile pot83xx_t *pci_pot;
+	volatile pcictrl83xx_t *pci_ctrl;
+	volatile pciconf83xx_t *pci_conf;
+
+	immr = (immap_t *) CFG_IMMR;
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = immr->pci_ctrl;
+	pci_conf = immr->pci_conf;
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+	pci_ctrl[0].pitar0 = 0x0;
+	pci_ctrl[0].pibar0 = 0x0;
+	pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
+	    PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
+
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 &= ~PIWAR_EN;
+
+	pci_ctrl[0].pitar2 = 0x0;
+	pci_ctrl[0].pibar2 = 0x0;
+	pci_ctrl[0].piebar2 = 0x0;
+	pci_ctrl[0].piwar2 &= ~PIWAR_EN;
+
+	hose[0].first_busno = 0;
+	hose[0].last_busno = 0xff;
+	pci_setup_indirect(&hose[0],
+			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+	reg16 = 0xff;
+
+	pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
+				  PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
+				   PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
+				   PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
+				   PCI_LATENCY_TIMER, 0x80);
+
+	/*
+	 * Unlock configuration lock in PCI function configuration register.
+	 */
+	pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
+				  PCI_FUNCTION_CONFIG, &reg16);
+	reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
+	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
+				   PCI_FUNCTION_CONFIG, reg16);
+
+	printf("Enabled PCI 32bit Agent Mode\n");
+}
+#else
+{
+	volatile immap_t *immr;
+	volatile clk83xx_t *clk;
+	volatile law83xx_t *pci_law;
+	volatile pot83xx_t *pci_pot;
+	volatile pcictrl83xx_t *pci_ctrl;
+	volatile pciconf83xx_t *pci_conf;
+
+	u8 val8, orig_i2c_bus;
+	u16 reg16;
+	u32 val32;
+	u32 dev;
+
+	immr = (immap_t *) CFG_IMMR;
+	clk = (clk83xx_t *) & immr->clk;
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = immr->pci_ctrl;
+	pci_conf = immr->pci_conf;
+	/*
+	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+	 */
+	val32 = clk->occr;
+	udelay(2000);
+#if defined(PCI_66M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#elif defined(PCI_33M)
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
+	    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
+	printf("PCI clock is 33MHz\n");
+#else
+	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+	printf("PCI clock is 66MHz\n");
+#endif
+	udelay(2000);
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI mem space - prefetch */
+	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].pocmr =
+	    POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/* PCI mmio - non-prefetch mem space */
+	pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/* PCI IO space */
+	pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+	pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
+	pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 =
+	    PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
+	    PIWAR_IWS_2G;
+
+	/*
+	 * Assign PIB PMC slot to desired PCI bus
+	 */
+
+	/* Switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+ 	i2c_set_bus_num(1);
+
+	val8 = 0;
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+
+	val8 = 0xf3;		/*PMC1, PMC2, PMC3 slot to PCI bus */
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+	asm("eieio");
+
+	/* Reset to original I2C bus */
+	i2c_set_bus_num(orig_i2c_bus);
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	udelay(2000);
+	pci_ctrl[0].gcr = 1;
+	udelay(2000);
+
+	hose[0].first_busno = 0;
+	hose[0].last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose[0].regions + 0,
+		       CFG_PCI_MEM_BASE,
+		       CFG_PCI_MEM_PHYS,
+		       CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose[0].regions + 1,
+		       CFG_PCI_MMIO_BASE,
+		       CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose[0].regions + 2,
+		       CFG_PCI_IO_BASE,
+		       CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose[0].regions + 3,
+		       CFG_PCI_SLV_MEM_LOCAL,
+		       CFG_PCI_SLV_MEM_BUS,
+		       CFG_PCI_SLV_MEM_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose[0].region_count = 4;
+
+	pci_setup_indirect(&hose[0],
+			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(0, 0, 0);
+	pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+	printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n");
+
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+}
+#endif				/* CONFIG_PCISLAVE */
+
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+       	u32 *p;
+       	int len;
+
+       	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
+       	if (p != NULL) {
+		p[0] = hose[0].first_busno;
+		p[1] = hose[0].last_busno;
+       	}
+}
+#endif				/* CONFIG_OF_FLAT_TREE */
+#endif				/* CONFIG_PCI */
diff --git a/board/mpc8360emds/u-boot.lds b/board/mpc8360emds/u-boot.lds
new file mode 100644
index 0000000..937c87a
--- /dev/null
+++ b/board/mpc8360emds/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc83xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c
index ff1190a..1d28513 100644
--- a/board/mpl/common/memtst.c
+++ b/board/mpl/common/memtst.c
@@ -48,7 +48,7 @@ int testdram (void)
 
 #include <common.h>
 #include <asm/processor.h>
-#include <405gp_i2c.h>
+#include <4xx_i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index 34f3289..4b1c1c0 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -65,7 +65,7 @@
 #include <common.h>
 #include "mip405.h"
 #include <asm/processor.h>
-#include <405gp_i2c.h>
+#include <4xx_i2c.h>
 #include <miiphy.h>
 #include "../common/common_util.h"
 #include <i2c.h>
@@ -73,9 +73,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern block_dev_desc_t * scsi_get_dev(int dev);
-extern block_dev_desc_t * ide_get_dev(int dev);
-
 #undef SDRAM_DEBUG
 #define ENABLE_ECC /* for ecc boards */
 #define FALSE           0
diff --git a/board/nc650/nand.c b/board/nc650/nand.c
index de54386..6bb7c31 100644
--- a/board/nc650/nand.c
+++ b/board/nc650/nand.c
@@ -106,12 +106,13 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
  * Members with a "?" were not set in the merged testing-NAND branch,
  * so they are not set here either.
  */
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 
 	nand->hwcontrol = nc650_hwcontrol;
 	nand->eccmode = NAND_ECC_SOFT;
 	nand->chip_delay = 12;
 /*	nand->options = NAND_SAMSUNG_LP_OPTIONS;*/
+	return 0;
 }
 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
diff --git a/board/netstar/nand.c b/board/netstar/nand.c
index f470c1a..7852365 100644
--- a/board/netstar/nand.c
+++ b/board/netstar/nand.c
@@ -55,12 +55,13 @@ static int netstar_nand_ready(struct mtd_info *mtd)
 }
 ***/
 
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	nand->eccmode = NAND_ECC_SOFT;
 	nand->hwcontrol = netstar_nand_hwcontrol;
 /*	nand->dev_ready = netstar_nand_ready; */
 	nand->chip_delay = 18;
+	return 0;
 }
 #endif
diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile
new file mode 100644
index 0000000..00dc180
--- /dev/null
+++ b/board/prodrive/alpr/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o fpga.o nand.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
new file mode 100644
index 0000000..5abc87d
--- /dev/null
+++ b/board/prodrive/alpr/alpr.c
@@ -0,0 +1,317 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <ppc4xx_enet.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int alpr_fpga_init(void);
+
+int board_early_init_f (void)
+{
+	/*-------------------------------------------------------------------------
+	 * Initialize EBC CONFIG
+	 *-------------------------------------------------------------------------*/
+	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
+	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
+	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic0pr, 0xfffffe03);	/* per manual */
+	mtdcr (uic0tr, 0x01c00000);	/* per manual */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000); /* clear all */
+	mtdcr (uicb0er, 0x00000000); /* disable all */
+	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000); /* */
+	mtdcr (uicb0tr, 0x00000000); /* */
+	mtdcr (uicb0vr, 0x00000001); /* */
+
+	/* Setup shutdown/SSD empty interrupt as inputs */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
+
+	/* Setup GPIO/IRQ multiplexing */
+	mtsdr(sdr_pfc0, 0x01a33e00);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	unsigned short reg;
+
+	/*
+	 * Configure LED's of both Marvell 88E1111 PHY's
+	 *
+	 * This has to be done after the 4xx ethernet driver is loaded,
+	 * so "last_stage_init()" is the right place.
+	 */
+	miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, &reg);
+	reg |= 0x0001;
+	miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
+	miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, &reg);
+	reg |= 0x0001;
+	miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
+
+	return 0;
+}
+
+static int board_rev(void)
+{
+	/* Setup as input */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
+
+	return (in32(GPIO0_IR) >> 16) & 0x3;
+}
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	printf ("Board: ALPR");
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	printf(" (Rev. %d)\n", board_rev());
+
+	return (0);
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 *	The ocotea board is always configured as the host & requires the
+	 *	PCI arbiter to be enabled.
+	 *--------------------------------------------------------------------------*/
+	mfsdr(sdr_sdstp1, strap);
+	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
+		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+		return 0;
+	}
+
+	/* FPGA Init */
+	alpr_fpga_init ();
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+
+static void wait_for_pci_ready(void)
+{
+	/*
+	 * Configure EREADY as input
+	 */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
+	udelay(1000);
+
+	for (;;) {
+		if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
+			return;
+	}
+
+}
+
+int is_pci_host(struct pci_controller *hose)
+{
+	wait_for_pci_ready();
+	return 1;		/* return 1 for host controller */
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ *  pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	/*--------------------------------------------------------------------------+
+	  | PowerPC440 PCI Master configuration.
+	  | Map PLB/processor addresses to PCI memory space.
+	  |   PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
+	  |   Use byte reversed out routines to handle endianess.
+	  | Make this region non-prefetchable.
+	  +--------------------------------------------------------------------------*/
+	out32r( PCIX0_POM0SA, 0 ); /* disable */
+	out32r( PCIX0_POM1SA, 0 ); /* disable */
+	out32r( PCIX0_POM2SA, 0 ); /* disable */
+
+	out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_POM0LAH, 0x00000003);	/* PMM0 Local Address */
+	out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_POM0PCIAH, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
+
+	out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_POM1LAH, 0x00000003);	/* PMM0 Local Address */
+	out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_POM1PCIAH, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+	return (ctrlc());
+}
+#endif
diff --git a/board/amcc/yellowstone/config.mk b/board/prodrive/alpr/config.mk
index 4ab0ea0..9e18335 100644
--- a/board/amcc/yellowstone/config.mk
+++ b/board/prodrive/alpr/config.mk
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2002
+# (C) Copyright 2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -22,15 +22,15 @@
 #
 
 #
-# esd ADCIOP boards
+# AMCC 440GX Reference Platform (Ocotea) board
 #
 
-#TEXT_BASE = 0x00001000
+#TEXT_BASE = 0xFFFE0000
 
 ifeq ($(ramsym),1)
-TEXT_BASE = 0xFBD00000
+TEXT_BASE = 0x07FD0000
 else
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
 endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c
new file mode 100644
index 0000000..e94360f
--- /dev/null
+++ b/board/prodrive/alpr/fpga.c
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Altera FPGA configuration support for the ALPR computer from prodrive
+ */
+
+#include <common.h>
+#include <altera.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm-ppc/processor.h>
+#include <ppc440.h>
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+#ifdef FPGA_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define	PRINTF(fmt,args...)
+#endif
+
+static unsigned long regval;
+
+#define SET_GPIO_REG_0(reg, bit) {				\
+		regval = in32(reg);				\
+		regval &= ~(0x80000000 >> bit);			\
+		out32(reg, regval);				\
+	}
+
+#define SET_GPIO_REG_1(reg, bit) {				\
+		regval = in32(reg);				\
+		regval |= (0x80000000 >> bit);			\
+		out32(reg, regval);				\
+	}
+
+#define	SET_GPIO_0(bit)		SET_GPIO_REG_0(GPIO0_OR, bit)
+#define	SET_GPIO_1(bit)		SET_GPIO_REG_1(GPIO0_OR, bit)
+
+#define FPGA_PRG		(0x80000000 >> CFG_GPIO_PROG_EN)
+#define FPGA_CONFIG		(0x80000000 >> CFG_GPIO_CONFIG)
+#define FPGA_DATA		(0x80000000 >> CFG_GPIO_DATA)
+#define FPGA_CLK		(0x80000000 >> CFG_GPIO_CLK)
+#define OLD_VAL			(FPGA_PRG | FPGA_CONFIG)
+
+#define SET_FPGA(data)		out32(GPIO0_OR, data)
+
+#define FPGA_WRITE_1 {							\
+		SET_FPGA(OLD_VAL | 0        | FPGA_DATA);  /* set data to 1  */	\
+		SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#define FPGA_WRITE_0 {							\
+		SET_FPGA(OLD_VAL | 0        | 0        );   /* set data to 0  */ \
+		SET_FPGA(OLD_VAL | FPGA_CLK | 0        );}  /* set data to 1  */
+
+/* Plattforminitializations */
+/* Here we have to set the FPGA Chain */
+/* PROGRAM_PROG_EN	= HIGH */
+/* PROGRAM_SEL_DPR	= LOW */
+int fpga_pre_fn (int cookie)
+{
+	unsigned long	reg;
+
+	reg = in32(GPIO0_IR);
+	/* Enable the FPGA Chain */
+	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN);
+	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN);
+	SET_GPIO_1(CFG_GPIO_PROG_EN);
+	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR);
+	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR);
+	SET_GPIO_0((CFG_GPIO_SEL_DPR));
+
+	/* initialize the GPIO Pins */
+	/* output */
+	SET_GPIO_0(CFG_GPIO_CLK);
+	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK);
+	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK);
+
+	/* output */
+	SET_GPIO_0(CFG_GPIO_DATA);
+	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA);
+	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA);
+
+	/* First we set STATUS to 0 then as an input */
+	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS);
+	SET_GPIO_0(CFG_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS);
+
+	/* output */
+	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG);
+	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG);
+	SET_GPIO_0(CFG_GPIO_CONFIG);
+
+	/* input */
+	SET_GPIO_0(CFG_GPIO_CON_DON);
+	SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON);
+	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON);
+
+	/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
+	SET_GPIO_0(CFG_GPIO_CONFIG);
+	return FPGA_SUCCESS;
+}
+
+/* Set the state of CONFIG Pin */
+int fpga_config_fn (int assert_config, int flush, int cookie)
+{
+	if (assert_config) {
+		SET_GPIO_1(CFG_GPIO_CONFIG);
+	} else {
+		SET_GPIO_0(CFG_GPIO_CONFIG);
+	}
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of STATUS Pin */
+int fpga_status_fn (int cookie)
+{
+	unsigned long	reg;
+
+	reg = in32(GPIO0_IR);
+	if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) {
+		PRINTF("STATUS = HIGH\n");
+		return FPGA_FAIL;
+	}
+	PRINTF("STATUS = LOW\n");
+	return FPGA_SUCCESS;
+}
+
+/* Returns the state of CONF_DONE Pin */
+int fpga_done_fn (int cookie)
+{
+	unsigned long	reg;
+	reg = in32(GPIO0_IR);
+	if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) {
+		PRINTF("CONF_DON = HIGH\n");
+		return FPGA_FAIL;
+	}
+	PRINTF("CONF_DON = LOW\n");
+	return FPGA_SUCCESS;
+}
+
+/* writes the complete buffer to the FPGA
+   writing the complete buffer in one function is much faster,
+   then calling it for every bit */
+int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
+{
+	size_t bytecount = 0;
+	unsigned char *data = (unsigned char *) buf;
+	unsigned char val=0;
+	int		i;
+	int len_40 = len / 40;
+
+	while (bytecount < len) {
+		val = data[bytecount++];
+		i = 8;
+		do {
+			if (val & 0x01) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			val >>= 1;
+			i --;
+		} while (i > 0);
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		if (bytecount % len_40 == 0) {
+			putc ('.');		/* let them know we are alive */
+#ifdef CFG_FPGA_CHECK_CTRLC
+			if (ctrlc ())
+				return FPGA_FAIL;
+#endif
+		}
+#endif
+	}
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming is aborted */
+int fpga_abort_fn (int cookie)
+{
+	SET_GPIO_1((CFG_GPIO_SEL_DPR));
+	return FPGA_SUCCESS;
+}
+
+/* called, when programming was succesful */
+int fpga_post_fn (int cookie)
+{
+	return fpga_abort_fn (cookie);
+}
+
+/* Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ */
+Altera_CYC2_Passive_Serial_fns fpga_fns = {
+	fpga_pre_fn,
+	fpga_config_fn,
+	fpga_status_fn,
+	fpga_done_fn,
+	fpga_write_fn,
+	fpga_abort_fn,
+	fpga_post_fn
+};
+
+Altera_desc fpga[CONFIG_FPGA_COUNT] = {
+	{Altera_CYC2,
+	 passive_serial,
+	 Altera_EP2C35_SIZE,
+	 (void *) &fpga_fns,
+	 NULL,
+	 0}
+};
+
+/*
+ * Initialize the fpga.  Return 1 on success, 0 on failure.
+ */
+int alpr_fpga_init (void)
+{
+	int i;
+
+	PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
+	fpga_init (gd->reloc_off);
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
+		fpga_add (fpga_altera, &fpga[i]);
+	}
+	return 1;
+}
+
+#endif
diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
new file mode 100644
index 0000000..135674c
--- /dev/null
+++ b/board/prodrive/alpr/init.S
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)	( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+	tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+
+	/* PCI */
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
+
+	/* NAND */
+	tlbentry( CFG_NAND_BASE, SZ_4K, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbtab_end
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
new file mode 100644
index 0000000..d66b088
--- /dev/null
+++ b/board/prodrive/alpr/nand.c
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <asm/processor.h>
+#include <nand.h>
+
+struct alpr_ndfc_regs {
+	u8 cmd[4];
+	u8 addr_wait;
+	u8 term;
+	u8 dummy;
+	u8 dummy2;
+	u8 data;
+};
+
+static u8 hwctl;
+static struct alpr_ndfc_regs *alpr_ndfc = NULL;
+
+#define readb(addr)	(u8)(*(volatile u8 *)(addr))
+#define writeb(d,addr)	*(volatile u8 *)(addr) = ((u8)(d))
+
+/*
+ * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
+ * the NAND devices.  The NDFC has command, address and data registers that
+ * when accessed will set up the NAND flash pins appropriately.  We'll use the
+ * hwcontrol function to save the configuration in a global variable.
+ * We can then use this information in the read and write functions to
+ * determine which NDFC register to access.
+ *
+ * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
+ */
+static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		hwctl |= 0x1;
+		break;
+	case NAND_CTL_CLRCLE:
+		hwctl &= ~0x1;
+		break;
+	case NAND_CTL_SETALE:
+		hwctl |= 0x2;
+		break;
+	case NAND_CTL_CLRALE:
+		hwctl &= ~0x2;
+		break;
+	case NAND_CTL_SETNCE:
+		break;
+	case NAND_CTL_CLRNCE:
+		writeb(0x00, &(alpr_ndfc->term));
+		break;
+	}
+}
+
+static void alpr_nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+	struct nand_chip *nand = mtd->priv;
+
+	if (hwctl & 0x1)
+		/*
+		 * IO_ADDR_W used as CMD[i] reg to support multiple NAND
+		 * chips.
+		 */
+		writeb(byte, nand->IO_ADDR_W);
+	else if (hwctl & 0x2) {
+		writeb(byte, &(alpr_ndfc->addr_wait));
+	} else
+		writeb(byte, &(alpr_ndfc->data));
+}
+
+static u_char alpr_nand_read_byte(struct mtd_info *mtd)
+{
+	return readb(&(alpr_ndfc->data));
+}
+
+static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	struct nand_chip *nand = mtd->priv;
+	int i;
+
+	for (i = 0; i < len; i++) {
+		if (hwctl & 0x1)
+			 /*
+			  * IO_ADDR_W used as CMD[i] reg to support multiple NAND
+			  * chips.
+			  */
+			writeb(buf[i], nand->IO_ADDR_W);
+		else if (hwctl & 0x2)
+			writeb(buf[i], &(alpr_ndfc->addr_wait));
+		else
+			writeb(buf[i], &(alpr_ndfc->data));
+	}
+}
+
+static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		buf[i] = readb(&(alpr_ndfc->data));
+	}
+}
+
+static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		if (buf[i] != readb(&(alpr_ndfc->data)))
+			return i;
+
+	return 0;
+}
+
+static int alpr_nand_dev_ready(struct mtd_info *mtd)
+{
+	volatile u_char val;
+
+	/*
+	 * Blocking read to wait for NAND to be ready
+	 */
+	val = readb(&(alpr_ndfc->addr_wait));
+
+	/*
+	 * Return always true
+	 */
+	return 1;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
+
+	nand->eccmode = NAND_ECC_SOFT;
+
+	/* Reference hardware control function */
+	nand->hwcontrol  = alpr_nand_hwcontrol;
+	/* Set command delay time */
+	nand->write_byte = alpr_nand_write_byte;
+	nand->read_byte  = alpr_nand_read_byte;
+	nand->write_buf  = alpr_nand_write_buf;
+	nand->read_buf   = alpr_nand_read_buf;
+	nand->verify_buf = alpr_nand_verify_buf;
+	nand->dev_ready  = alpr_nand_dev_ready;
+
+	return 0;
+}
+#endif
diff --git a/board/prodrive/alpr/u-boot.lds b/board/prodrive/alpr/u-boot.lds
new file mode 100644
index 0000000..4f04089
--- /dev/null
+++ b/board/prodrive/alpr/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/prodrive/alpr/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c
index 8630cc1..363631f 100644
--- a/board/prodrive/common/flash.c
+++ b/board/prodrive/common/flash.c
@@ -48,6 +48,7 @@ void flash_print_info(flash_info_t *info)
 	case FLASH_MAN_AMD:	printf ("AMD ");		break;
 	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
 	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("ST ");			break;
 	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
 	default:		printf ("Unknown Vendor ");	break;
 	}
@@ -156,6 +157,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info)
 	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
+	case (CFG_FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
 	case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
 		info->flash_id = FLASH_MAN_EXCEL;
 		break;
diff --git a/board/prodrive/p3mx/64460.h b/board/prodrive/p3mx/64460.h
new file mode 100644
index 0000000..8bb0ebf
--- /dev/null
+++ b/board/prodrive/p3mx/64460.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the Galileo Eval board DB64460.
+ */
+
+#ifndef __64460_H__
+#define __64460_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64460_H__ */
diff --git a/board/prodrive/p3mx/Makefile b/board/prodrive/p3mx/Makefile
new file mode 100644
index 0000000..bf74a5a
--- /dev/null
+++ b/board/prodrive/p3mx/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../../Marvell/common)
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+SOBJS	= misc.o
+COBJS	= $(BOARD).o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
+		../../Marvell/common/i2c.o ../../Marvell/common/memory.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/prodrive/p3mx/config.mk b/board/prodrive/p3mx/config.mk
new file mode 100644
index 0000000..35bf1c1
--- /dev/null
+++ b/board/prodrive/p3mx/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# p3mx boards (P3M750 & P3M7448)
+#
+
+TEXT_BASE = 0xfff00000
diff --git a/board/prodrive/p3mx/eth.h b/board/prodrive/p3mx/eth.h
new file mode 100644
index 0000000..aab32d2
--- /dev/null
+++ b/board/prodrive/p3mx/eth.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64360_ETH_H__
+#define __EVB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+
+int db64360_eth0_poll(void);
+int db64360_eth0_transmit(unsigned int s, volatile char *p);
+void db64360_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+
+#endif /* __EVB64360_ETH_H__ */
diff --git a/board/prodrive/p3mx/misc.S b/board/prodrive/p3mx/misc.S
new file mode 100644
index 0000000..160b1d3
--- /dev/null
+++ b/board/prodrive/p3mx/misc.S
@@ -0,0 +1,245 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include "version.h"
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include "../../Marvell/include/mv_gen_reg.h"
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CFG_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CFG_MONITOR_LEN@h
+	ori	r8, r8, CFG_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11: gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CFG_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CFG_DFL_GT_REGS@h
+	ori	r3, r3, CFG_DFL_GT_REGS@l
+	lis	r4, CFG_GT_REGS@h
+	ori	r4, r4, CFG_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
+/*	rlwinm	r7, r4, 8, 16, 31
+	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
+	rlwinm	r7, r4, 16, 16, 31
+	/* -----------------------------------------------------*/
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	lis	r3, CFG_INT_SRAM_BASE@h
+	ori	r3, r3, CFG_INT_SRAM_BASE@l
+	rlwinm  r3, r3, 16, 16, 31
+	lis	r4, CFG_GT_REGS@h
+	ori	r4, r4, CFG_GT_REGS@l
+	li	r5, INTEGRATED_SRAM_BASE_ADDR
+	stwbrx  r3, r5, r4
+
+2:	lwbrx	r6, r5, r4
+	cmp	cr0, r3, r6
+	bne	2b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0_relocated
+led_on0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC80
+	ori	r18, r18, 0x8000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_off0_relocated
+led_off0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC81
+	ori	r18, r18, 0x4000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_on0
+led_on0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off0
+led_off0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x4000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off1
+led_off1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x0000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off2
+led_off2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
diff --git a/board/prodrive/p3mx/mpsc.c b/board/prodrive/p3mx/mpsc.c
new file mode 100644
index 0000000..da95cfa
--- /dev/null
+++ b/board/prodrive/p3mx/mpsc.c
@@ -0,0 +1,1013 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+#include "mv_regs.h"
+
+#include "../../Marvell/include/memory.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define this if you wish to use the MPSC as a register based UART.
+ * This will force the serial port to not use the SDMA engine at all.
+ */
+#undef CONFIG_MPSC_DEBUG_PORT
+
+
+int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
+char (*mpsc_getchar) (void) = mpsc_getchar_debug;
+int (*mpsc_test_char) (void) = mpsc_test_char_debug;
+
+
+static volatile unsigned int *rx_desc_base = NULL;
+static unsigned int rx_desc_index = 0;
+static volatile unsigned int *tx_desc_base = NULL;
+static unsigned int tx_desc_index = 0;
+
+/* local function declarations */
+static int galmpsc_connect (int channel, int connect);
+static int galmpsc_route_rx_clock (int channel, int brg);
+static int galmpsc_route_tx_clock (int channel, int brg);
+static int galmpsc_write_config_regs (int mpsc, int mode);
+static int galmpsc_config_channel_regs (int mpsc);
+static int galmpsc_set_char_length (int mpsc, int value);
+static int galmpsc_set_stop_bit_length (int mpsc, int value);
+static int galmpsc_set_parity (int mpsc, int value);
+static int galmpsc_enter_hunt (int mpsc);
+static int galmpsc_set_brkcnt (int mpsc, int value);
+static int galmpsc_set_tcschar (int mpsc, int value);
+static int galmpsc_set_snoop (int mpsc, int value);
+static int galmpsc_shutdown (int mpsc);
+
+static int galsdma_set_RFT (int channel);
+static int galsdma_set_SFM (int channel);
+static int galsdma_set_rxle (int channel);
+static int galsdma_set_txle (int channel);
+static int galsdma_set_burstsize (int channel, unsigned int value);
+static int galsdma_set_RC (int channel, unsigned int value);
+
+static int galbrg_set_CDV (int channel, int value);
+static int galbrg_enable (int channel);
+static int galbrg_disable (int channel);
+static int galbrg_set_clksrc (int channel, int value);
+static int galbrg_set_CUV (int channel, int value);
+
+static void galsdma_enable_rx (void);
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress,
+				  unsigned int size);
+
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+static void mpsc_debug_init (void)
+{
+
+	volatile unsigned int temp;
+
+	/* Clear the CFR  (CHR4) */
+	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
+	temp &= 0xffffff00;
+	temp |= BIT29;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
+	temp |= (BIT12 | BIT15);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set int mask */
+	temp = GTREGREAD (GALMPSC_0_INT_MASK);
+	temp |= BIT6;
+	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
+}
+#endif
+
+char mpsc_getchar_debug (void)
+{
+	volatile int temp;
+	volatile unsigned int cause;
+
+	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	while ((cause & BIT6) == 0) {
+		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	}
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
+			  (CHANNEL * GALMPSC_REG_GAP));
+	/* By writing 1's to the set bits, the register is cleared */
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
+	return (temp >> 16) & 0xff;
+}
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int mpsc_putchar_early (char ch)
+{
+	int mpsc = CHANNEL;
+	int temp =
+		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	galmpsc_set_tcschar (mpsc, ch);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
+		      temp | 0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay (MAGIC_FACTOR / gd->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int mpsc_putchar_sdma (char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset ((void *) p, 0, 8 * sizeof (unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;		/* x */
+	p[5] = (unsigned int) ch;	/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;	/* 0 */
+	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
+	p[2] = 0;		/* 8 */
+	p[3] = (unsigned int) &p[4];	/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int) &p[0];
+	p[11] = (unsigned int) &p[12];
+#endif
+
+	FLUSH_DCACHE (&p[0], &p[8]);
+
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	while (p[1] & DESC_OWNER_BIT) {
+		udelay (100);
+		INVALIDATE_DCACHE (&p[1], &p[2]);
+	}
+	return 0;
+}
+
+char mpsc_getchar_sdma (void)
+{
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
+
+	volatile unsigned int *p;
+
+
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER_BIT) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
+					  (CHANNEL * GALMPSC_REG_GAP));
+			temp |= (1 << 23);
+			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
+				      (CHANNEL * GALMPSC_REG_GAP), temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
+}
+
+
+int mpsc_test_char_debug (void)
+{
+	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
+		return 0;
+	else {
+		return 1;
+	}
+}
+
+
+int mpsc_test_char_sdma (void)
+{
+	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER_BIT)
+		return 0;
+	else
+		return 1;
+}
+
+int mpsc_init (int baud)
+{
+	/* BRG CONFIG */
+	galbrg_set_baudrate (CHANNEL, baud);
+	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
+	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
+	galbrg_enable (CHANNEL);	/* Enable BRG */
+
+	/* Set up clock routing */
+	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
+
+	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
+	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
+
+	/* reset MPSC state */
+	galmpsc_shutdown (CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle (CHANNEL);
+	galsdma_set_rxle (CHANNEL);
+	galsdma_set_RC (CHANNEL, 0xf);
+	galsdma_set_SFM (CHANNEL);
+	galsdma_set_RFT (CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs (CHANNEL);
+	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
+	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
+	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+	mpsc_debug_init ();
+#endif
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
+#else
+	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
+#endif
+
+	return 0;
+}
+
+
+void mpsc_sdma_init (void)
+{
+	/* Setup SDMA channel0 SDMA_CONFIG_REG*/
+	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
+
+	/*  Enable MPSC-Window0 for DRAM Bank 0 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT,
+				   MV64460_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress(0),
+				   memoryGetBankSize(0)) != true)
+		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+	/*  Enable MPSC-Window1 for DRAM Bank 1 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT,
+				   MV64460_SDMA_DRAM_CS_1_TARGET,
+				   0,
+				   memoryGetBankBaseAddress(1),
+				   memoryGetBankSize(1)) != true)
+		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+	/*  Disable MPSC-Window2 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT,
+				   MV64460_SDMA_DRAM_CS_2_TARGET,
+				   0,
+				   memoryGetBankBaseAddress(2),
+				   memoryGetBankSize(2)) != true)
+		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+	/*  Disable MPSC-Window3 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT,
+				   MV64460_SDMA_DRAM_CS_3_TARGET,
+				   0,
+				   memoryGetBankBaseAddress(3),
+				   memoryGetBankSize(3)) != true)
+		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
+			__FUNCTION__);
+
+	/*  Setup MPSC0 access mode Window0 full access */
+	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
+			 (MV64460_SDMA_WIN_ACCESS_FULL <<
+			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+	/*  Setup MPSC1 access mode Window1 full access */
+	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
+			 (MV64460_SDMA_WIN_ACCESS_FULL <<
+			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+	/* Setup MPSC internal address space base address 	*/
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+
+	/* no high address remap*/
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
+
+	/* clear interrupt cause register for MPSC (fault register)*/
+	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
+}
+
+
+void mpsc_init2 (void)
+{
+	int i;
+
+#ifndef CONFIG_MPSC_DEBUG_PORT
+	mpsc_putchar = mpsc_putchar_sdma;
+	mpsc_getchar = mpsc_getchar_sdma;
+	mpsc_test_char = mpsc_test_char_sdma;
+#endif
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset ((void *) rx_desc_base, 0,
+		(RX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
+		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
+		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
+		rx_desc_base[i * 8] = 0x00100000;
+	}
+	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
+
+	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset ((void *) tx_desc_base, 0,
+		(TX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 3] =
+			(unsigned int) &tx_desc_base[i * 8 + 4];
+		tx_desc_base[i * 8 + 2] =
+			(unsigned int) &tx_desc_base[(i + 1) * 8];
+		tx_desc_base[i * 8 + 1] =
+			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i * 8] = 0x00010001;
+	}
+	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
+
+	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
+
+	udelay (100);
+
+	galsdma_enable_rx ();
+
+	return;
+}
+
+int galbrg_set_baudrate (int channel, int rate)
+{
+	int clock;
+
+	galbrg_disable (channel);	/*ok */
+
+#ifdef ZUMA_NTL
+	/* from tclk */
+	clock = (CFG_TCLK / (16 * rate)) - 1;
+#else
+	clock = (CFG_TCLK / (16 * rate)) - 1;
+#endif
+
+	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
+
+	galbrg_enable (channel);
+
+	gd->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int galbrg_set_CDV (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_enable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x00010000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_disable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_set_clksrc (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
+	temp |= (value << 18);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+	return 0;
+}
+
+static int galbrg_set_CUV (int channel, int value)
+{
+	/* set CountUpValue */
+	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int galbrg_reset (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int galsdma_set_RFT (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_SFM (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_rxle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_txle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_RC (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_burstsize (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	case 8:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x3 << 12)));
+		break;
+
+	case 4:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x2 << 12)));
+		break;
+
+	case 2:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x1 << 12)));
+		break;
+
+	case 1:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x0 << 12)));
+		break;
+
+	default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int galmpsc_connect (int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_rx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_tx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_write_config_regs (int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
+			      0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
+			      0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int galmpsc_config_channel_regs (int mpsc)
+{
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt (mpsc, 0x3);
+	galmpsc_set_tcschar (mpsc, 0xab);
+
+	return 0;
+}
+
+static int galmpsc_set_brkcnt (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_tcschar (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_char_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_stop_bit_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFBFFF;
+	temp |= (value << 14);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_parity (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_enter_hunt (int mpsc)
+{
+	int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= 0x80000000;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
+	       MPSC_ENTER_HUNT) {
+		udelay (1);
+	}
+	return 0;
+}
+
+
+static int galmpsc_shutdown (int mpsc)
+{
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
+	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
+
+	udelay (100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
+
+	udelay (100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
+
+	udelay (100);
+
+	return 0;
+}
+
+static void galsdma_enable_rx (void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt (CHANNEL);
+}
+
+static int galmpsc_set_snoop (int mpsc, int value)
+{
+	int reg =
+		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
+		MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp = GTREGREAD (reg);
+
+	if (value)
+		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
+	else
+		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
+	GT_REG_WRITE (reg, temp);
+	return 0;
+}
+
+/*******************************************************************************
+* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map.
+*
+* DESCRIPTION:
+*       the MV64460 SDMA has its own address decoding map that is de-coupled
+*       from the CPU interface address decoding windows. The SDMA channels
+*       share four address windows. Each region can be individually configured
+*       by this function by associating it to a target interface and setting
+*       base and size values.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*       The size must be a series of 1s followed by a series of zeros
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       True for success, false otherwise.
+*
+*******************************************************************************/
+
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress, unsigned int size)
+{
+	unsigned int temp;
+
+	if (size == 0) {
+		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+		return true;
+	}
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size < 0x10000) {
+		return false;
+	}
+
+	/* Align size and base to 64K */
+	baseAddress &= 0xffff0000;
+	size &= 0xffff0000;
+	temp = size >> 16;
+
+	/* Checking that the size is a sequence of '1' followed by a
+	   sequence of '0' starting from LSB to MSB. */
+	while ((temp > 0) && (temp & 0x1)) {
+		temp = temp >> 1;
+	}
+
+	if (temp != 0) {
+		GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+	} else {
+		/* An invalid size was specified */
+		return false;
+	}
+	return true;
+}
diff --git a/board/prodrive/p3mx/mpsc.h b/board/prodrive/p3mx/mpsc.h
new file mode 100644
index 0000000..a03d1cc
--- /dev/null
+++ b/board/prodrive/p3mx/mpsc.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../../Marvell/include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT 		  (1 << 15)
+#define SDMA_TX_ABORT 		  (1 << 31)
+#define MPSC_TX_ABORT 		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c
new file mode 100644
index 0000000..8203b3c
--- /dev/null
+++ b/board/prodrive/p3mx/mv_eth.c
@@ -0,0 +1,3344 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ 3 the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.c - header file for the polled mode GT ethernet driver
+ */
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <miiphy.h>
+
+#include "mv_eth.h"
+
+/* enable Debug outputs */
+
+#undef DEBUG_MV_ETH
+
+#ifdef DEBUG_MV_ETH
+#define DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* PHY DFCDL Registers */
+#define ETH_PHY_DFCDL_CONFIG0_REG	0x2100
+#define ETH_PHY_DFCDL_CONFIG1_REG	0x2104
+#define ETH_PHY_DFCDL_ADDR_REG		0x2110
+#define ETH_PHY_DFCDL_DATA0_REG		0x2114
+
+#define PHY_AUTONEGOTIATE_TIMEOUT	4000	/* 4000 ms autonegotiate timeout */
+#define PHY_UPDATE_TIMEOUT		10000
+
+#undef MV64460_CHECKSUM_OFFLOAD
+/*************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+*************************************************************************/
+
+/* Definition for configuring driver */
+/* #define UPDATE_STATS_BY_SOFTWARE */
+#undef MV64460_RX_QUEUE_FILL_ON_TASK
+
+/* Constants */
+#define MAGIC_ETH_RUNNING		8031971
+#define MV64460_INTERNAL_SRAM_SIZE	_256K
+#define EXTRA_BYTES 32
+#define WRAP	   ETH_HLEN + 2 + 4 + 16
+#define BUFFER_MTU dev->mtu + WRAP
+#define INT_CAUSE_UNMASK_ALL		0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
+#ifdef MV64460_RX_FILL_ON_TASK
+#define INT_CAUSE_MASK_ALL		0x00000000
+#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
+#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
+#endif
+
+/* Read/Write to/from MV64460 internal registers */
+#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
+#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
+#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
+#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
+
+#define my_cpu_to_le32(x) my_le32_to_cpu((x))
+
+/* Static function declarations */
+static int mv64460_eth_real_open (struct eth_device *eth);
+static int mv64460_eth_real_stop (struct eth_device *eth);
+static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
+						       *dev);
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
+static void mv64460_eth_update_stat (struct eth_device *dev);
+bool db64460_eth_start (struct eth_device *eth);
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset);
+int mv64460_eth_receive (struct eth_device *dev);
+
+int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
+
+int mv_miiphy_read(char *devname, unsigned char phy_addr,
+		   unsigned char phy_reg, unsigned short *value);
+int mv_miiphy_write(char *devname, unsigned char phy_addr,
+		    unsigned char phy_reg, unsigned short value);
+
+int phy_setup_aneg (char *devname, unsigned char addr);
+
+#ifndef	 UPDATE_STATS_BY_SOFTWARE
+static void mv64460_eth_print_stat (struct eth_device *dev);
+#endif
+/* Processes a received packet */
+extern void NetReceive (volatile uchar *, int);
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+unsigned long my_le32_to_cpu (unsigned long x)
+{
+	return (((x & 0x000000ffU) << 24) |
+		((x & 0x0000ff00U) << 8) |
+		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
+}
+
+/*************************************************
+ *Helper functions - used inside the driver only *
+ *************************************************/
+#ifdef DEBUG_MV_ETH
+void print_globals (struct eth_device *dev)
+{
+	printf ("Ethernet PRINT_Globals-Debug function\n");
+	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
+		(unsigned int) dev->priv);
+	printf ("Base Address for mv64460_eth_priv:	%08x\n",
+		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
+				 port_private));
+
+	printf ("GT Internal Base Address:	%08x\n",
+		INTERNAL_REG_BASE_ADDR);
+	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
+	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
+	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_rx_buffer_base[0],
+		(MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
+	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_tx_buffer_base[0],
+		(MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
+}
+#endif
+
+/**********************************************************************
+ * mv64460_eth_print_phy_status
+ *
+ * Prints gigabit ethenret phy status
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+void mv64460_eth_print_phy_status (struct eth_device *dev)
+{
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	unsigned int port_status, phy_reg_data;
+
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		printf ("Ethernet port changed link status to DOWN\n");
+	} else {
+		port_status =
+			MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
+		printf ("Ethernet status port %d: Link up", port_num);
+		printf (", %s",
+			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
+		if (port_status & BIT4)
+			printf (", Speed 1 Gbps");
+		else
+			printf (", %s",
+				(port_status & BIT5) ? "Speed 100 Mbps" :
+				"Speed 10 Mbps");
+		printf ("\n");
+	}
+}
+
+/**********************************************************************
+ * u-boot entry functions for mv64460_eth
+ *
+ **********************************************************************/
+int db64460_eth_probe (struct eth_device *dev)
+{
+	return ((int) db64460_eth_start (dev));
+}
+
+int db64460_eth_poll (struct eth_device *dev)
+{
+	return mv64460_eth_receive (dev);
+}
+
+int db64460_eth_transmit (struct eth_device *dev, volatile void *packet,
+			  int length)
+{
+	mv64460_eth_xmit (dev, packet, length);
+	return 0;
+}
+
+void db64460_eth_disable (struct eth_device *dev)
+{
+	mv64460_eth_stop (dev);
+}
+
+#define DFCDL(write,read)   ((write << 6) | read)
+unsigned int  ethDfcdls[] = {
+	DFCDL(0,0),	DFCDL(1,1),	DFCDL(2,2),	DFCDL(3,3),
+	DFCDL(4,4),	DFCDL(5,5),	DFCDL(6,6),	DFCDL(7,7),
+	DFCDL(8,8),	DFCDL(9,9),	DFCDL(10,10),	DFCDL(11,11),
+	DFCDL(12,12),	DFCDL(13,13),	DFCDL(14,14),	DFCDL(15,15),
+	DFCDL(16,16),	DFCDL(17,17),	DFCDL(18,18),	DFCDL(19,19),
+	DFCDL(20,20),	DFCDL(21,21),	DFCDL(22,22),	DFCDL(23,23),
+	DFCDL(24,24),	DFCDL(25,25),	DFCDL(26,26),	DFCDL(27,27),
+	DFCDL(28,28),	DFCDL(29,29),	DFCDL(30,30),	DFCDL(31,31),
+	DFCDL(32,32),	DFCDL(33,33),	DFCDL(34,34),	DFCDL(35,35),
+	DFCDL(36,36),	DFCDL(37,37),	DFCDL(38,38),	DFCDL(39,39),
+	DFCDL(40,40),	DFCDL(41,41),	DFCDL(42,42),	DFCDL(43,43),
+	DFCDL(44,44),	DFCDL(45,45),	DFCDL(46,46),	DFCDL(47,47),
+	DFCDL(48,48),	DFCDL(49,49),	DFCDL(50,50),	DFCDL(51,51),
+	DFCDL(52,52),	DFCDL(53,53),	DFCDL(54,54),	DFCDL(55,55),
+	DFCDL(56,56),	DFCDL(57,57),	DFCDL(58,58),	DFCDL(59,59),
+	DFCDL(60,60),	DFCDL(61,61),	DFCDL(62,62),	DFCDL(63,63),
+};
+
+void mv_eth_phy_init (void)
+{
+	int i;
+
+	MV_REG_WRITE (ETH_PHY_DFCDL_ADDR_REG, 0);
+
+	for (i = 0; i < 64; i++) {
+		MV_REG_WRITE (ETH_PHY_DFCDL_DATA0_REG, ethDfcdls[i]);
+	}
+
+	MV_REG_WRITE (ETH_PHY_DFCDL_CONFIG0_REG, 0x300000);
+}
+
+void mv6446x_eth_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+	/* P3M750 only
+	 * Set RGMII clock drives strength
+	 */
+	temp = MV_REG_READ(0x20A0);
+	temp |= 0x04000080;
+	MV_REG_WRITE(0x20A0, temp);
+
+	mv_eth_phy_init();
+
+	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
+		dev = calloc (sizeof (*dev), 1);
+		if (!dev) {
+			printf ("%s: mv_enet%d allocation failure, %s\n",
+				__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than NAMESIZE (16) */
+		sprintf (dev->name, "mv_enet%d", devnum);
+
+#ifdef DEBUG
+		printf ("Initializing %s\n", dev->name);
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+		case 1:
+			s = "eth1addr";
+			break;
+		case 2:
+			s = "eth2addr";
+			break;
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_r (s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		/* ronen - set the MAC addr in the HW */
+		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
+
+		dev->init = (void *) db64460_eth_probe;
+		dev->halt = (void *) ethernet_phy_reset;
+		dev->send = (void *) db64460_eth_transmit;
+		dev->recv = (void *) db64460_eth_poll;
+
+		ethernet_private = calloc (sizeof (*ethernet_private), 1);
+		dev->priv = (void *)ethernet_private;
+		if (!ethernet_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Private Device Structure");
+			free (dev);
+			return;
+		}
+		/* start with an zeroed ETH_PORT_INFO */
+		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
+		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+		/* set pointer to memory for stats data structure etc... */
+		port_private = calloc (sizeof (*ethernet_private), 1);
+		ethernet_private->port_private = (void *)port_private;
+		if (!port_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Port Private Device Structure");
+
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+
+		port_private->stats =
+			calloc (sizeof (struct net_device_stats), 1);
+		if (!port_private->stats) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Net stat Structure");
+
+			free (port_private);
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+		memset (ethernet_private->port_private, 0,
+			sizeof (struct mv64460_eth_priv));
+		switch (devnum) {
+		case 0:
+			ethernet_private->port_num = ETH_0;
+			break;
+		case 1:
+			ethernet_private->port_num = ETH_1;
+			break;
+		case 2:
+			ethernet_private->port_num = ETH_2;
+			break;
+		default:
+			printf ("Invalid device number %d\n", devnum);
+			break;
+		};
+
+		port_private->port_num = devnum;
+		/*
+		 * Read MIB counter on the GT in order to reset them,
+		 * then zero all the stats fields in memory
+		 */
+		mv64460_eth_update_stat (dev);
+		memset (port_private->stats, 0,
+			sizeof (struct net_device_stats));
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+		case 1:
+			s = "eth1addr";
+			break;
+		case 2:
+			s = "eth2addr";
+			break;
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_r (s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+
+		DP (printf ("Allocating descriptor and buffer rings\n"));
+
+		ethernet_private->p_rx_desc_area_base[0] =
+			(ETH_RX_DESC *) memalign (16,
+						  RX_DESC_ALIGNED_SIZE *
+						  MV64460_RX_QUEUE_SIZE + 1);
+		ethernet_private->p_tx_desc_area_base[0] =
+			(ETH_TX_DESC *) memalign (16,
+						  TX_DESC_ALIGNED_SIZE *
+						  MV64460_TX_QUEUE_SIZE + 1);
+
+		ethernet_private->p_rx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64460_RX_QUEUE_SIZE *
+					   MV64460_TX_BUFFER_SIZE + 1);
+		ethernet_private->p_tx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64460_RX_QUEUE_SIZE *
+					   MV64460_TX_BUFFER_SIZE + 1);
+
+#ifdef DEBUG_MV_ETH
+		/* DEBUG OUTPUT prints adresses of globals */
+		print_globals (dev);
+#endif
+		eth_register (dev);
+
+		miiphy_register(dev->name, mv_miiphy_read, mv_miiphy_write);
+	}
+	DP (printf ("%s: exit\n", __FUNCTION__));
+
+}
+
+/**********************************************************************
+ * mv64460_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+ * Input : a pointer to the network device structure
+ * / / ronen - changed the output to match  net/eth.c needs
+ * Output : nonzero of success , zero if fails.
+ * under construction
+ **********************************************************************/
+
+int mv64460_eth_open (struct eth_device *dev)
+{
+	return (mv64460_eth_real_open (dev));
+}
+
+/* Helper function for mv64460_eth_open */
+static int mv64460_eth_real_open (struct eth_device *dev)
+{
+
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	u32 port_status;
+	ushort reg_short;
+	int speed;
+	int duplex;
+	int i;
+	int reg;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	/* ronen - when we update the MAC env params we only update dev->enetaddr
+	   see ./net/eth.c eth_set_enetaddr() */
+	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+	port_private = (struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), 0x0000ff00);
+
+	/* Clear the ethernet port interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+
+	/* Unmask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL);
+
+	/* Unmask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL_EXT);
+
+	/* Set phy address of the port */
+	ethernet_private->port_phy_addr = 0x1 + (port_num << 1);
+	reg = ethernet_private->port_phy_addr;
+
+	/* Activate the DMA channels etc */
+	eth_port_init (ethernet_private);
+
+	/* "Allocate" setup TX rings */
+
+	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
+		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
+		ethernet_private->tx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
+			0, ethernet_private->tx_desc_area_size[queue]);
+
+		/* initialize tx desc ring with low level driver */
+		if (ether_init_tx_desc_ring
+		    (ethernet_private, ETH_Q0,
+		     port_private->tx_ring_size[queue],
+		     MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		     (unsigned int) ethernet_private->
+		     p_tx_desc_area_base[queue],
+		     (unsigned int) ethernet_private->
+		     p_tx_buffer_base[queue]) == false)
+			printf ("### Error initializing TX Ring\n");
+	}
+
+	/* "Allocate" setup RX rings */
+	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		/* Meantime RX Ring are fixed - but must be configurable by user */
+		port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
+		size = (port_private->rx_ring_size[queue] *
+			RX_DESC_ALIGNED_SIZE);
+		ethernet_private->rx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
+			0, ethernet_private->rx_desc_area_size[queue]);
+		if ((ether_init_rx_desc_ring
+		     (ethernet_private, ETH_Q0,
+		      port_private->rx_ring_size[queue],
+		      MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		      (unsigned int) ethernet_private->
+		      p_rx_desc_area_base[queue],
+		      (unsigned int) ethernet_private->
+		      p_rx_buffer_base[queue])) == false)
+			printf ("### Error initializing RX Ring\n");
+	}
+
+	eth_port_start (ethernet_private);
+
+	/* Set maximum receive buffer to 9700 bytes */
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
+		      (0x5 << 17) |
+		      (MV_REG_READ
+		       (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
+		       & 0xfff1ffff));
+
+	/*
+	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+	 * disable the leaky bucket mechanism .
+	 */
+
+	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
+	port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
+
+#if defined(CONFIG_PHY_RESET)
+	/*
+	 * Reset the phy, only if its the first time through
+	 * otherwise, just check the speeds & feeds
+	 */
+	if (port_private->first_init == 0) {
+		port_private->first_init = 1;
+		ethernet_phy_reset (port_num);
+
+		/* Start/Restart autonegotiation */
+		phy_setup_aneg (dev->name, reg);
+		udelay (1000);
+	}
+#endif /* defined(CONFIG_PHY_RESET) */
+
+	miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
+
+	/*
+	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
+	 */
+	if ((reg_short & PHY_BMSR_AUTN_ABLE)
+	    && !(reg_short & PHY_BMSR_AUTN_COMP)) {
+		puts ("Waiting for PHY auto negotiation to complete");
+		i = 0;
+		while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
+			/*
+			 * Timeout reached ?
+			 */
+			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+				puts (" TIMEOUT !\n");
+				break;
+			}
+
+			if ((i++ % 1000) == 0) {
+				putc ('.');
+			}
+			udelay (1000);	/* 1 ms */
+			miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
+
+		}
+		puts (" done\n");
+		udelay (500000);	/* another 500 ms (results in faster booting) */
+	}
+
+	speed = miiphy_speed (dev->name, reg);
+	duplex = miiphy_duplex (dev->name, reg);
+
+	printf ("ENET Speed is %d Mbps - %s duplex connection\n",
+		(int) speed, (duplex == HALF) ? "HALF" : "FULL");
+
+	port_private->eth_running = MAGIC_ETH_RUNNING;
+	return 1;
+}
+
+static int mv64460_eth_free_tx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop Tx Queues */
+	MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free TX rings */
+	DP (printf ("Clearing previously allocated TX queues... "));
+	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
+		/* Free on TX rings */
+		for (p_tx_curr_desc =
+		     ethernet_private->p_tx_desc_area_base[queue];
+		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
+		      ethernet_private->p_tx_desc_area_base[queue] +
+		      ethernet_private->tx_desc_area_size[queue]);
+		     p_tx_curr_desc =
+		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
+				      TX_DESC_ALIGNED_SIZE)) {
+			/* this is inside for loop */
+			if (p_tx_curr_desc->return_info != 0) {
+				p_tx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+static int mv64460_eth_free_rx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free RX rings */
+	DP (printf ("Clearing previously allocated RX queues... "));
+	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
+		/* Free preallocated skb's on RX rings */
+		for (p_rx_curr_desc =
+		     ethernet_private->p_rx_desc_area_base[queue];
+		     (((unsigned int) p_rx_curr_desc <
+		       ((unsigned int) ethernet_private->
+			p_rx_desc_area_base[queue] +
+			ethernet_private->rx_desc_area_size[queue])));
+		     p_rx_curr_desc =
+		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
+				      RX_DESC_ALIGNED_SIZE)) {
+			if (p_rx_curr_desc->return_info != 0) {
+				p_rx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+/**********************************************************************
+ * mv64460_eth_stop
+ *
+ * This function is used when closing the network device.
+ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+ * Input : a pointer to the device structure
+ * Output : zero if success , nonzero if fails
+ *********************************************************************/
+
+int mv64460_eth_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Disable all gigE address decoder */
+	MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
+	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
+	mv64460_eth_real_stop (dev);
+
+	return 0;
+};
+
+/* Helper function for mv64460_eth_stop */
+
+static int mv64460_eth_real_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	mv64460_eth_free_tx_rings (dev);
+	mv64460_eth_free_rx_rings (dev);
+
+	eth_port_reset (ethernet_private->port_num);
+	/* Disable ethernet port interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+	/* Mask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
+	/* Mask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
+	MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
+			   BIT0 << port_num);
+	/* Print Network statistics */
+#ifndef	 UPDATE_STATS_BY_SOFTWARE
+	/*
+	 * Print statistics (only if ethernet is running),
+	 * then zero all the stats fields in memory
+	 */
+	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
+		port_private->eth_running = 0;
+		mv64460_eth_print_stat (dev);
+	}
+	memset (port_private->stats, 0, sizeof (struct net_device_stats));
+#endif
+	DP (printf ("\nEthernet stopped ... \n"));
+	return 0;
+}
+
+/**********************************************************************
+ * mv64460_eth_start_xmit
+ *
+ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+ * Input : skb - a pointer to socket buffer
+ *	   dev - a pointer to the required port
+ *
+ * Output : zero upon success
+ **********************************************************************/
+
+int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
+		      int dataSize)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	ETH_FUNC_RET_STATUS status;
+	struct net_device_stats *stats;
+	ETH_FUNC_RET_STATUS release_result;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	stats = port_private->stats;
+
+	/* Update packet info data structure */
+	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
+	pkt_info.byte_cnt = dataSize;
+	pkt_info.buf_ptr = (unsigned int) dataPtr;
+	pkt_info.return_info = 0;
+
+	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
+	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
+		printf ("Error on transmitting packet ..");
+		if (status == ETH_QUEUE_FULL)
+			printf ("ETH Queue is full. \n");
+		if (status == ETH_QUEUE_LAST_RESOURCE)
+			printf ("ETH Queue: using last available resource. \n");
+		return 1;
+	}
+
+	/* Update statistics and start of transmittion time */
+	stats->tx_bytes += dataSize;
+	stats->tx_packets++;
+
+	/* Check if packet(s) is(are) transmitted correctly (release everything) */
+	do {
+		release_result =
+			eth_tx_return_desc (ethernet_private, ETH_Q0,
+					    &pkt_info);
+		switch (release_result) {
+		case ETH_OK:
+			DP (printf ("descriptor released\n"));
+			if (pkt_info.cmd_sts & BIT0) {
+				printf ("Error in TX\n");
+				stats->tx_errors++;
+			}
+			break;
+		case ETH_RETRY:
+			DP (printf ("transmission still in process\n"));
+			break;
+
+		case ETH_ERROR:
+			printf ("routine can not access Tx desc ring\n");
+			break;
+
+		case ETH_END_OF_JOB:
+			DP (printf ("the routine has nothing to release\n"));
+			break;
+		default:	/* should not happen */
+			break;
+		}
+	} while (release_result == ETH_OK);
+
+	return 0;	/* success */
+}
+
+/**********************************************************************
+ * mv64460_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+ * Input : dev - a pointer to the required interface
+ *	   max - maximum number to receive (0 means unlimted)
+ *
+ * Output : number of served packets
+ **********************************************************************/
+
+int mv64460_eth_receive (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	struct net_device_stats *stats;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private = (struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == ETH_OK)) {
+#ifdef DEBUG_MV_ETH
+		if (pkt_info.byte_cnt != 0) {
+			printf ("%s: Received %d byte Packet @ 0x%x\n",
+				__FUNCTION__, pkt_info.byte_cnt,
+				pkt_info.buf_ptr);
+			if(pkt_info.buf_ptr != 0){
+				for(i=0; i < pkt_info.byte_cnt; i++){
+					if((i % 4) == 0){
+						printf("\n0x");
+					}
+					printf("%02x", ((char*)pkt_info.buf_ptr)[i]);
+				}
+				printf("\n");
+			}
+		}
+#endif
+		/* Update statistics. Note byte count includes 4 byte CRC count */
+		stats->rx_packets++;
+		stats->rx_bytes += pkt_info.byte_cnt;
+
+		/*
+		 * In case received a packet without first / last bits on OR the error
+		 * summary bit is on, the packets needs to be dropeed.
+		 */
+		if (((pkt_info.
+		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+			stats->rx_dropped++;
+
+			printf ("Received packet spread on multiple descriptors\n");
+
+			/* Is this caused by an error ? */
+			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
+				stats->rx_errors++;
+			}
+
+			/* free these descriptors again without forwarding them to the higher layers */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+			/* /free these descriptors again */
+		} else {
+
+/* !!! call higher layer processing */
+#ifdef DEBUG_MV_ETH
+			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
+#endif
+			/* let the upper layer handle the packet */
+			NetReceive ((uchar *) pkt_info.buf_ptr,
+				    (int) pkt_info.byte_cnt);
+
+/* **************************************************************** */
+/* free descriptor  */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+			DP (printf ("RX: pkt_info.buf_ptr =	%x\n", pkt_info.buf_ptr));
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX: Desc returned to Ring\n"));
+			}
+
+/* **************************************************************** */
+
+		}
+	}
+	mv64460_eth_get_stats (dev);	/* update statistics */
+	return 1;
+}
+
+/**********************************************************************
+ * mv64460_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : a pointer to the interface's statistics
+ **********************************************************************/
+
+static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	mv64460_eth_update_stat (dev);
+
+	return port_private->stats;
+}
+
+/**********************************************************************
+ * mv64460_eth_update_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64460_eth_update_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+	volatile unsigned int dummy;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	stats->rx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_RECEIVED);
+	stats->tx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_SENT);
+	stats->rx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
+	/*
+	 * Ideally this should be as follows -
+	 *
+	 *   stats->rx_bytes   += stats->rx_bytes +
+	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
+	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
+	 *
+	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
+	 * is just a dummy read for proper work of the GigE port
+	 */
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
+	stats->tx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
+	stats->rx_errors += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MAC_RECEIVE_ERROR);
+
+	/* Rx dropped is for received packet with CRC error */
+	stats->rx_dropped +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_BAD_CRC_EVENT);
+	stats->multicast += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
+	stats->collisions +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_COLLISION) +
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_LATE_COLLISION);
+	/* detailed rx errors */
+	stats->rx_length_errors +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_UNDERSIZE_RECEIVED)
+		+
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_OVERSIZE_RECEIVED);
+	/* detailed tx errors */
+}
+
+#ifndef	 UPDATE_STATS_BY_SOFTWARE
+/**********************************************************************
+ * mv64460_eth_print_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64460_eth_print_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	printf ("\n### Network statistics: ###\n");
+	printf ("--------------------------\n");
+	printf (" Packets received:		%ld\n", stats->rx_packets);
+	printf (" Packets send:			%ld\n", stats->tx_packets);
+	printf (" Received bytes:		%ld\n", stats->rx_bytes);
+	printf (" Send bytes:			%ld\n", stats->tx_bytes);
+	if (stats->rx_errors != 0)
+		printf (" Rx Errors:			%ld\n",
+			stats->rx_errors);
+	if (stats->rx_dropped != 0)
+		printf (" Rx dropped (CRC Errors):	%ld\n",
+			stats->rx_dropped);
+	if (stats->multicast != 0)
+		printf (" Rx mulicast frames:		%ld\n",
+			stats->multicast);
+	if (stats->collisions != 0)
+		printf (" No. of collisions:		%ld\n",
+			stats->collisions);
+	if (stats->rx_length_errors != 0)
+		printf (" Rx length errors:		%ld\n",
+			stats->rx_length_errors);
+}
+#endif
+
+/**************************************************************************
+ *network_start - Network Kick Off Routine UBoot
+ *Inputs :
+ *Outputs :
+ **************************************************************************/
+
+bool db64460_eth_start (struct eth_device *dev)
+{
+	return (mv64460_eth_open (dev));	/* calls real open */
+}
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+/*
+ * based on Linux code
+ * arch/ppc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ */
+
+/********************************************************************************
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+ *	 This file introduce low level API to Marvell's Gigabit Ethernet
+ *		controller. This Gigabit Ethernet Controller driver API controls
+ *		1) Operations (i.e. port init, start, reset etc').
+ *		2) Data flow (i.e. port send, receive etc').
+ *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
+ *		struct.
+ *		This struct includes user configuration information as well as
+ *		driver internal data needed for its operations.
+ *
+ *		Supported Features:
+ *		- This low level driver is OS independent. Allocating memory for
+ *		  the descriptor rings and buffers are not within the scope of
+ *		  this driver.
+ *		- The user is free from Rx/Tx queue managing.
+ *		- This low level driver introduce functionality API that enable
+ *		  the to operate Marvell's Gigabit Ethernet Controller in a
+ *		  convenient way.
+ *		- Simple Gigabit Ethernet port operation API.
+ *		- Simple Gigabit Ethernet port data flow API.
+ *		- Data flow and operation API support per queue functionality.
+ *		- Support cached descriptors for better performance.
+ *		- Enable access to all four DRAM banks and internal SRAM memory
+ *		  spaces.
+ *		- PHY access and control API.
+ *		- Port control register configuration API.
+ *		- Full control over Unicast and Multicast MAC configurations.
+ *
+ *		Operation flow:
+ *
+ *		Initialization phase
+ *		This phase complete the initialization of the ETH_PORT_INFO
+ *		struct.
+ *		User information regarding port configuration has to be set
+ *		prior to calling the port initialization routine. For example,
+ *		the user has to assign the port_phy_addr field which is board
+ *		depended parameter.
+ *		In this phase any port Tx/Rx activity is halted, MIB counters
+ *		are cleared, PHY address is set according to user parameter and
+ *		access to DRAM and internal SRAM memory spaces.
+ *
+ *		Driver ring initialization
+ *		Allocating memory for the descriptor rings and buffers is not
+ *		within the scope of this driver. Thus, the user is required to
+ *		allocate memory for the descriptors ring and buffers. Those
+ *		memory parameters are used by the Rx and Tx ring initialization
+ *		routines in order to curve the descriptor linked list in a form
+ *		of a ring.
+ *		Note: Pay special attention to alignment issues when using
+ *		cached descriptors/buffers. In this phase the driver store
+ *		information in the ETH_PORT_INFO struct regarding each queue
+ *		ring.
+ *
+ *		Driver start
+ *		This phase prepares the Ethernet port for Rx and Tx activity.
+ *		It uses the information stored in the ETH_PORT_INFO struct to
+ *		initialize the various port registers.
+ *
+ *		Data flow:
+ *		All packet references to/from the driver are done using PKT_INFO
+ *		struct.
+ *		This struct is a unified struct used with Rx and Tx operations.
+ *		This way the user is not required to be familiar with neither
+ *		Tx nor Rx descriptors structures.
+ *		The driver's descriptors rings are management by indexes.
+ *		Those indexes controls the ring resources and used to indicate
+ *		a SW resource error:
+ *		'current'
+ *		This index points to the current available resource for use. For
+ *		example in Rx process this index will point to the descriptor
+ *		that will be passed to the user upon calling the receive routine.
+ *		In Tx process, this index will point to the descriptor
+ *		that will be assigned with the user packet info and transmitted.
+ *		'used'
+ *		This index points to the descriptor that need to restore its
+ *		resources. For example in Rx process, using the Rx buffer return
+ *		API will attach the buffer returned in packet info to the
+ *		descriptor pointed by 'used'. In Tx process, using the Tx
+ *		descriptor return will merely return the user packet info with
+ *		the command status of  the transmitted buffer pointed by the
+ *		'used' index. Nevertheless, it is essential to use this routine
+ *		to update the 'used' index.
+ *		'first'
+ *		This index supports Tx Scatter-Gather. It points to the first
+ *		descriptor of a packet assembled of multiple buffers. For example
+ *		when in middle of Such packet we have a Tx resource error the
+ *		'curr' index get the value of 'first' to indicate that the ring
+ *		returned to its state before trying to transmit this packet.
+ *
+ *		Receive operation:
+ *		The eth_port_receive API set the packet information struct,
+ *		passed by the caller, with received information from the
+ *		'current' SDMA descriptor.
+ *		It is the user responsibility to return this resource back
+ *		to the Rx descriptor ring to enable the reuse of this source.
+ *		Return Rx resource is done using the eth_rx_return_buff API.
+ *
+ *		Transmit operation:
+ *		The eth_port_send API supports Scatter-Gather which enables to
+ *		send a packet spanned over multiple buffers. This means that
+ *		for each packet info structure given by the user and put into
+ *		the Tx descriptors ring, will be transmitted only if the 'LAST'
+ *		bit will be set in the packet info command status field. This
+ *		API also consider restriction regarding buffer alignments and
+ *		sizes.
+ *		The user must return a Tx resource after ensuring the buffer
+ *		has been transmitted to enable the Tx ring indexes to update.
+ *
+ *		BOARD LAYOUT
+ *		This device is on-board.  No jumper diagram is necessary.
+ *
+ *		EXTERNAL INTERFACE
+ *
+ *	 Prior to calling the initialization routine eth_port_init() the user
+ *	 must set the following fields under ETH_PORT_INFO struct:
+ *	 port_num	      User Ethernet port number.
+ *	 port_phy_addr		    User PHY address of Ethernet port.
+ *	 port_mac_addr[6]	    User defined port MAC address.
+ *	 port_config	      User port configuration value.
+ *	 port_config_extend    User port config extend value.
+ *	 port_sdma_config      User port SDMA config value.
+ *	 port_serial_control   User port serial control value.
+ *	 *port_virt_to_phys ()	User function to cast virtual addr to CPU bus addr.
+ *	 *port_private	      User scratch pad for user specific data structures.
+ *
+ *	 This driver introduce a set of default values:
+ *	 PORT_CONFIG_VALUE	     Default port configuration value
+ *	 PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
+ *	 PORT_SDMA_CONFIG_VALUE	     Default sdma control value
+ *	 PORT_SERIAL_CONTROL_VALUE   Default port serial control value
+ *
+ *		This driver data flow is done using the PKT_INFO struct which is
+ *		a unified struct for Rx and Tx operations:
+ *		byte_cnt	Tx/Rx descriptor buffer byte count.
+ *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
+ *		cmd_sts		Tx/Rx descriptor command status.
+ *		buf_ptr		Tx/Rx descriptor buffer pointer.
+ *		return_info	Tx/Rx user resource return information.
+ *
+ *
+ *		EXTERNAL SUPPORT REQUIREMENTS
+ *
+ *		This driver requires the following external support:
+ *
+ *		D_CACHE_FLUSH_LINE (address, address offset)
+ *
+ *		This macro applies assembly code to flush and invalidate cache
+ *		line.
+ *		address	       - address base.
+ *		address offset - address offset
+ *
+ *
+ *		CPU_PIPE_FLUSH
+ *
+ *		This macro applies assembly code to flush the CPU pipeline.
+ *
+ *******************************************************************************/
+/* includes */
+
+/* defines */
+/* SDMA command macros */
+#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
+
+#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
+ (1 << (8 + tx_queue)))
+
+#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
+
+#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
+
+#define CURR_RFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
+
+#define CURR_RFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_RFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
+
+#define USED_RFD_SET(p_used_desc, queue)\
+(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
+
+
+#define CURR_TFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
+
+#define CURR_TFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_TFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
+
+#define USED_TFD_SET(p_used_desc, queue) \
+ (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
+
+#define FIRST_TFD_GET(p_first_desc, queue) \
+ ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
+
+#define FIRST_TFD_SET(p_first_desc, queue) \
+ (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
+
+
+/* Macros that save access to desc in order to find next desc pointer  */
+#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
+
+#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
+
+#define LINK_UP_TIMEOUT		100000
+#define PHY_BUSY_TIMEOUT    10000000
+
+/* locals */
+
+/* PHY routines */
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
+static int ethernet_phy_get (ETH_PORT eth_port_num);
+
+/* Ethernet Port routines */
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param);
+static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option);
+#if 0				/* FIXME */
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option);
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option);
+#endif
+
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count);
+
+void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
+
+
+typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
+u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_dram_bank_size (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64460_CS_0_SIZE);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64460_CS_1_SIZE);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64460_CS_2_SIZE);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64460_CS_3_SIZE);
+	result += 1;
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_internal_sram_base (void)
+{
+	u32 result;
+
+	result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+/*******************************************************************************
+* eth_port_init - Initialize the Ethernet port driver
+*
+* DESCRIPTION:
+*	This function prepares the ethernet port to start its activity:
+*	1) Completes the ethernet port driver struct initialization toward port
+*	    start routine.
+*	2) Resets the device to a quiescent state in case of warm reboot.
+*	3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+*	4) Clean MAC tables. The reset status of those tables is unknown.
+*	5) Set PHY address.
+*	Note: Call this routine prior to eth_port_start routine and after setting
+*	user values in the user fields of Ethernet port control struct (i.e.
+*	port_phy_addr).
+*
+* INPUT:
+*	ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	None.
+*
+*******************************************************************************/
+static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	ETH_WIN_PARAM win_param;
+
+	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
+	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+
+	p_eth_port_ctrl->port_rx_queue_command = 0;
+	p_eth_port_ctrl->port_tx_queue_command = 0;
+
+	/* Zero out SW structs */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->rx_resource_err[queue] = false;
+	}
+
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->tx_resource_err[queue] = false;
+	}
+
+	eth_port_reset (p_eth_port_ctrl->port_num);
+
+	/* Set access parameters for DRAM bank 0 */
+	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR	*/
+	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
+	win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 1 */
+	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
+	win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 2 */
+	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
+	win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 3 */
+	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
+	win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for Internal SRAM */
+	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
+	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
+	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
+	win_param.high_addr = 0;
+	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
+	win_param.size = MV64460_INTERNAL_SRAM_SIZE;	/* Get bank size */
+	win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
+
+	ethernet_phy_set (p_eth_port_ctrl->port_num,
+			  p_eth_port_ctrl->port_phy_addr);
+
+	return;
+
+}
+
+/*******************************************************************************
+* eth_port_start - Start the Ethernet port activity.
+*
+* DESCRIPTION:
+*	This routine prepares the Ethernet port for Rx and Tx activity:
+*	1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+*	    has been initialized a descriptor's ring (using ether_init_tx_desc_ring
+*	    for Tx and ether_init_rx_desc_ring for Rx)
+*	2. Initialize and enable the Ethernet configuration port by writing to
+*	    the port's configuration and command registers.
+*	3. Initialize and enable the SDMA by writing to the SDMA's
+*    configuration and command registers.
+*	After completing these steps, the ethernet port SDMA can starts to
+*	perform Rx and Tx activities.
+*
+*	Note: Each Rx and Tx queue descriptor's list must be initialized prior
+*	to calling this function (use ether_init_tx_desc_ring for Tx queues and
+*	ether_init_rx_desc_ring for Rx queues).
+*
+* INPUT:
+*	ETH_PORT_INFO	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*	Ethernet port is ready to receive and transmit.
+*
+* RETURN:
+*	false if the port PHY is not up.
+*	true otherwise.
+*
+*******************************************************************************/
+static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	unsigned int phy_reg_data;
+	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
+
+	/* Assignment of Tx CTRP of given queue */
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_GET (p_tx_curr_desc, queue);
+		MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_tx_curr_desc));
+
+	}
+
+	/* Assignment of Rx CRDP of given queue */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_GET (p_rx_curr_desc, queue);
+		MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_rx_curr_desc));
+
+		if (p_rx_curr_desc != NULL)
+			/* Add the assigned Ethernet address to the port's address table */
+			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
+					      p_eth_port_ctrl->port_mac_addr,
+					      queue);
+	}
+
+	/* Assign port configuration and command. */
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config);
+
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config_extend);
+
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      p_eth_port_ctrl->port_serial_control);
+
+	MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+			 ETH_SERIAL_PORT_ENABLE);
+
+	/* Assign port SDMA configuration */
+	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_sdma_config);
+
+	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
+		      (eth_port_num), 0x3fffffff);
+	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
+		      (eth_port_num), 0x03fffcff);
+	/* Turn off the port/queue bandwidth limitation */
+	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
+
+	/* Enable port Rx. */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_rx_queue_command);
+
+	/* Check if link is up */
+	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+	if (!(phy_reg_data & 0x20))
+		return false;
+
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr_set - This function Set the port Unicast address.
+*
+* DESCRIPTION:
+*		This function Set the port Ethernet MAC address.
+*
+* INPUT:
+*	ETH_PORT eth_port_num	  Port number.
+*	char *	      p_addr		Address to be set
+*	ETH_QUEUE	  queue		Rx queue number for this MAC address.
+*
+* OUTPUT:
+*	Set MAC address low and high registers. also calls eth_port_uc_addr()
+*	To set the unicast table with the proper information.
+*
+* RETURN:
+*	N/A.
+*
+*******************************************************************************/
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr, ETH_QUEUE queue)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+
+	mac_l = (p_addr[4] << 8) | (p_addr[5]);
+	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+		(p_addr[2] << 8) | (p_addr[3] << 0);
+
+	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
+	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
+
+	/* Accept frames of this address */
+	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
+
+	return;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr - This function Set the port unicast address table
+*
+* DESCRIPTION:
+*	This function locates the proper entry in the Unicast table for the
+*	specified MAC nibble and sets its properties according to function
+*	parameters.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num	  Port number.
+*	unsigned char uc_nibble		Unicast MAC Address last nibble.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option	    0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	This function add/removes MAC addresses from the port unicast address
+*	table.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_uc_addr (ETH_PORT eth_port_num,
+			      unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int unicast_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the Unicast table entry */
+	uc_nibble = (0xf & uc_nibble);
+	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
+	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified unicast DA table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at unicast DA filter table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+#if 0				/* FIXME */
+/*******************************************************************************
+* eth_port_mc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This API controls the MV device MAC multicast support.
+*	The MV device supports multicast using two tables:
+*	1) Special Multicast Table for MAC addresses of the form
+*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	   Table entries in the DA-Filter table.
+*	   In this case, the function calls eth_port_smc_addr() routine to set the
+*	   Special Multicast Table.
+*	2) Other Multicast Table for multicast of another type. A CRC-8bit
+*	   is used as an index to the Other Multicast Table entries in the
+*	   DA-Filter table.
+*	   In this case, the function calculates the CRC-8bit value and calls
+*	   eth_port_omc_addr() routine to set the Other Multicast Table.
+* INPUT:
+*	ETH_PORT	eth_port_num	  Port number.
+*	unsigned char	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option	    0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if add_address_table_entry( ) failed.
+*
+*******************************************************************************/
+static void eth_port_mc_addr (ETH_PORT eth_port_num,
+			      unsigned char *p_addr,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+	unsigned char crc_result = 0;
+	int mac_array[48];
+	int crc[8];
+	int i;
+
+	if ((p_addr[0] == 0x01) &&
+	    (p_addr[1] == 0x00) &&
+	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
+
+		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
+	} else {
+		/* Calculate CRC-8 out of the given address */
+		mac_h = (p_addr[0] << 8) | (p_addr[1]);
+		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
+			(p_addr[4] << 8) | (p_addr[5] << 0);
+
+		for (i = 0; i < 32; i++)
+			mac_array[i] = (mac_l >> i) & 0x1;
+		for (i = 32; i < 48; i++)
+			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
+
+		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
+			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
+			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
+			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
+			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
+			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[0];
+
+		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
+			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
+			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
+			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
+			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
+			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
+			mac_array[0];
+
+		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
+			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
+			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
+			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
+			mac_array[2] ^ mac_array[1] ^ mac_array[0];
+
+		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
+			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
+			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
+			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
+			mac_array[2] ^ mac_array[1];
+
+		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
+			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
+			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
+			mac_array[2];
+
+		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
+			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
+			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
+			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
+			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
+			mac_array[3];
+
+		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
+			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
+			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
+			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[6] ^ mac_array[5] ^ mac_array[4];
+
+		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
+			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
+			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
+			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
+			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[5];
+
+		for (i = 0; i < 8; i++)
+			crc_result = crc_result | (crc[i] << i);
+
+		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
+	}
+	return;
+}
+
+/*******************************************************************************
+* eth_port_smc_addr - Special Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device special MAC multicast support.
+*	The Special Multicast Table for MAC addresses supports MAC of the form
+*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	Table entries in the DA-Filter table.
+*	This function set the Special Multicast Table appropriate entry
+*	according to the argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num	  Port number.
+*	unsigned char	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option	    0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int smc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the SMC table entry */
+	tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
+	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_omc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device Other MAC multicast support.
+*	The Other Multicast Table is used for multicast of another type.
+*	A CRC-8bit is used as an index to the Other Multicast Table entries
+*	in the DA-Filter table.
+*	The function gets the CRC-8bit value from the calling routine and
+*      set the Other Multicast Table appropriate entry according to the
+*	CRC-8 argument given.
+*
+* INPUT:
+*	ETH_PORT	eth_port_num	  Port number.
+*	unsigned char	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE		 queue		Rx queue number for this MAC address.
+*	int			option	    0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int omc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the OMC table entry */
+	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
+	reg_offset = crc8 % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+#endif
+
+/*******************************************************************************
+* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+*
+* DESCRIPTION:
+*	Go through all the DA filter tables (Unicast, Special Multicast & Other
+*	Multicast) and set each entry to 0.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*	Multicast and Unicast packets are rejected.
+*
+* RETURN:
+*	None.
+*
+*******************************************************************************/
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
+{
+	int table_index;
+
+	/* Clear DA filter unicast table (Ex_dFUT) */
+	for (table_index = 0; table_index <= 0xC; table_index += 4)
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num) + table_index), 0);
+
+	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+		/* Clear DA filter special multicast table (Ex_dFSMT) */
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+		/* Clear DA filter other multicast table (Ex_dFOMT) */
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+	}
+}
+
+/*******************************************************************************
+* eth_clear_mib_counters - Clear all MIB counters
+*
+* DESCRIPTION:
+*	This function clears all MIB counters of a specific ethernet port.
+*	A read from the MIB counter will reset the counter.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*	After reading all MIB counters, the counters resets.
+*
+* RETURN:
+*	MIB counter value.
+*
+*******************************************************************************/
+static void eth_clear_mib_counters (ETH_PORT eth_port_num)
+{
+	int i;
+	unsigned int dummy;
+
+	/* Perform dummy reads from MIB counters */
+	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
+	     i += 4)
+		dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
+				      (eth_port_num) + i));
+
+	return;
+}
+
+/*******************************************************************************
+* eth_read_mib_counter - Read a MIB counter
+*
+* DESCRIPTION:
+*	This function reads a MIB counter of a specific ethernet port.
+*	NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
+*	following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
+*	register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
+*	ETH_MIB_GOOD_OCTETS_SENT_HIGH
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*	unsigned int mib_offset	  MIB counter offset (use ETH_MIB_... macros).
+*
+* OUTPUT:
+*	After reading the MIB counter, the counter resets.
+*
+* RETURN:
+*	MIB counter value.
+*
+*******************************************************************************/
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset)
+{
+	return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
+			     + mib_offset));
+}
+
+/*******************************************************************************
+* ethernet_phy_set - Set the ethernet port PHY address.
+*
+* DESCRIPTION:
+*	This routine set the ethernet port PHY address according to given
+*	parameter.
+*
+* INPUT:
+*		ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*	Set PHY Address Register with given PHY address parameter.
+*
+* RETURN:
+*	None.
+*
+*******************************************************************************/
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
+
+	reg_data &= ~(0x1F << (5 * eth_port_num));
+	reg_data |= (phy_addr << (5 * eth_port_num));
+
+	MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
+
+	return;
+}
+
+/*******************************************************************************
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+ *	 This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+ *		ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *	 None.
+ *
+ * RETURN:
+ *	 PHY address.
+ *
+ *******************************************************************************/
+static int ethernet_phy_get (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
+
+	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+}
+
+/***********************************************************/
+/* (Re)start autonegotiation				   */
+/***********************************************************/
+int phy_setup_aneg (char *devname, unsigned char addr)
+{
+	unsigned short ctl, adv;
+
+	/* Setup standard advertise */
+	miiphy_read (devname, addr, PHY_ANAR, &adv);
+	adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
+		PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
+		PHY_ANLPAR_10);
+	miiphy_write (devname, addr, PHY_ANAR, adv);
+
+	miiphy_read (devname, addr, PHY_1000BTCR, &adv);
+	adv |= (0x0300);
+	miiphy_write (devname, addr, PHY_1000BTCR, adv);
+
+	/* Start/Restart aneg */
+	miiphy_read (devname, addr, PHY_BMCR, &ctl);
+	ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	miiphy_write (devname, addr, PHY_BMCR, ctl);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+ *	 This routine utilize the SMI interface to reset the ethernet port PHY.
+ *	 The routine waits until the link is up again or link up is timeout.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *	 The ethernet port PHY renew its link.
+ *
+ * RETURN:
+ *	 None.
+ *
+ *******************************************************************************/
+static bool ethernet_phy_reset (ETH_PORT eth_port_num)
+{
+	unsigned int time_out = 50;
+	unsigned int phy_reg_data;
+
+	eth_port_read_smi_reg (eth_port_num, 20, &phy_reg_data);
+	phy_reg_data |= 0x0083; /* Set bit 7 to 1 for different RGMII timing */
+	eth_port_write_smi_reg (eth_port_num, 20, phy_reg_data);
+
+	/* Reset the PHY */
+	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
+	phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
+	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
+
+	/* Poll on the PHY LINK */
+	do {
+		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+		if (time_out-- == 0)
+			return false;
+	}
+	while (!(phy_reg_data & 0x20));
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_reset - Reset Ethernet port
+ *
+ * DESCRIPTION:
+ *	This routine resets the chip by aborting any SDMA engine activity and
+ *	clearing the MIB counters. The Receiver and the Transmit unit are in
+ *	idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *	 Channel activity is halted.
+ *
+ * RETURN:
+ *	 None.
+ *
+ *******************************************************************************/
+static void eth_port_reset (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	/* Stop Tx port activity. Check port Tx activity. */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Tx activity to terminate. */
+		do {
+			/* Check port cause register that all Tx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Rx activity to terminate. */
+		do {
+			/* Check port cause register that all Rx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Clear all MIB counters */
+	eth_clear_mib_counters (eth_port_num);
+
+	/* Reset the Enable bit in the Configuration Register */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
+			     (eth_port_num));
+	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      reg_data);
+
+	return;
+}
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *	 This function sets specified bits in the given ethernet
+ *	 configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *	unsigned int	value	32 bit value.
+ *
+ * OUTPUT:
+ *	The set bits in the value parameter are set in the configuration
+ *	register.
+ *
+ * RETURN:
+ *	None.
+ *
+ *******************************************************************************/
+static void ethernet_set_config_reg (ETH_PORT eth_port_num,
+				     unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg =
+		MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
+	eth_config_reg |= value;
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* FIXME */
+/*******************************************************************************
+ * ethernet_reset_config_reg - Reset specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *	 This function resets specified bits in the given Ethernet
+ *	 configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *	unsigned int	value	32 bit value.
+ *
+ * OUTPUT:
+ *	The set bits in the value parameter are reset in the configuration
+ *	register.
+ *
+ * RETURN:
+ *	None.
+ *
+ *******************************************************************************/
+static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
+				       unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	eth_config_reg &= ~value;
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+ *	 This function returns the configuration register value of the given
+ *	 ethernet port.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *	 None.
+ *
+ * RETURN:
+ *	 Port configuration register value.
+ *
+ *******************************************************************************/
+static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	return eth_config_reg;
+}
+
+#endif
+
+/*******************************************************************************
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+ *	 This routine utilize the SMI interface to interact with the PHY in
+ *	 order to perform PHY register read.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *	 unsigned int	phy_reg	  PHY register address offset.
+ *	 unsigned int	*value	 Register value buffer.
+ *
+ * OUTPUT:
+ *	 Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+ *	 false if the PHY is busy or read data is not in valid state.
+ *	 true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
+				   unsigned int phy_reg, unsigned int *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+#define PHY_UPDATE_TIMEOUT	10000
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return true;
+}
+
+int mv_miiphy_read(char *devname, unsigned char phy_addr,
+		   unsigned char phy_reg, unsigned short *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return 0;
+}
+
+/*******************************************************************************
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+ *	 This routine utilize the SMI interface to interact with the PHY in
+ *	 order to perform writes to PHY registers.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *	unsigned int   phy_reg	 PHY register address offset.
+ *	unsigned int	value	Register value.
+ *
+ * OUTPUT:
+ *	Write the given value to the specified PHY register.
+ *
+ * RETURN:
+ *	false if the PHY is busy.
+ *	true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
+				    unsigned int phy_reg, unsigned int value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return true;
+}
+
+int mv_miiphy_write(char *devname, unsigned char phy_addr,
+		    unsigned char phy_reg, unsigned short value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return 0;
+}
+
+/*******************************************************************************
+ * eth_set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * DESCRIPTION:
+ *	 This function configures the address decode parameters for the Gigabit
+ *	 Ethernet Controller according the given parameters struct.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num	  Ethernet Port number. See ETH_PORT enum.
+ *	 ETH_WIN_PARAM	*param	 Address decode parameter struct.
+ *
+ * OUTPUT:
+ *	 An access window is opened using the given access parameters.
+ *
+ * RETURN:
+ *	 None.
+ *
+ *******************************************************************************/
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param)
+{
+	unsigned int access_prot_reg;
+
+	/* Set access control register */
+	access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
+				       (eth_port_num));
+	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
+	access_prot_reg |= (param->access_ctrl << (param->win * 2));
+	MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
+		      access_prot_reg);
+
+	/* Set window Size reg (SR) */
+	MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
+		       (ETH_SIZE_REG_GAP * param->win)),
+		      (((param->size / 0x10000) - 1) << 16));
+
+	/* Set window Base address reg (BA) */
+	MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
+		      (param->target | param->attributes | param->base_addr));
+	/* High address remap reg (HARR) */
+	if (param->win < 4)
+		MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
+			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
+			      param->high_addr);
+
+	/* Base address enable reg (BARER) */
+	if (param->enable == 1)
+		MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
+				   (1 << param->win));
+	else
+		MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
+				 (1 << param->win));
+}
+
+/*******************************************************************************
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *	 This function prepares a Rx chained list of descriptors and packet
+ *	 buffers in a form of a ring. The routine must be called after port
+ *	 initialization routine and before port start routine.
+ *	 The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *	 devices in the system (i.e. DRAM). This function uses the ethernet
+ *	 struct 'virtual to physical' routine (set by the user) to set the ring
+ *	 with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue	 Number of Rx queue.
+ *	int			rx_desc_num	  Number of Rx descriptors
+ *	int			rx_buff_size	  Size of Rx buffer
+ *	unsigned int	rx_desc_base_addr  Rx descriptors memory area base addr.
+ *	unsigned int	rx_buff_base_addr  Rx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *	The routine updates the Ethernet port control struct with information
+ *	regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+ *	false if the given descriptors memory area is not aligned according to
+ *	Ethernet SDMA specifications.
+ *	true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE rx_queue,
+				     int rx_desc_num,
+				     int rx_buff_size,
+				     unsigned int rx_desc_base_addr,
+				     unsigned int rx_buff_base_addr)
+{
+	ETH_RX_DESC *p_rx_desc;
+	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
+	p_rx_prev_desc = p_rx_desc;
+	buffer_addr = rx_buff_base_addr;
+
+	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (rx_buff_base_addr & 0xF)
+		return false;
+
+	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+		return false;
+
+	/* Rx buffers must be 64-bit aligned.	    */
+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+		return false;
+
+	/* initialize the Rx descriptors ring */
+	for (ix = 0; ix < rx_desc_num; ix++) {
+		p_rx_desc->buf_size = rx_buff_size;
+		p_rx_desc->byte_cnt = 0x0000;
+		p_rx_desc->cmd_sts =
+			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+		p_rx_desc->next_desc_ptr =
+			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
+		p_rx_desc->buf_ptr = buffer_addr;
+		p_rx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
+		buffer_addr += rx_buff_size;
+		p_rx_prev_desc = p_rx_desc;
+		p_rx_desc = (ETH_RX_DESC *)
+			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
+	}
+
+	/* Closing Rx descriptors ring */
+	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
+	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
+
+	/* Save Rx desc pointer to driver struct. */
+	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+
+	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
+		(ETH_RX_DESC *) rx_desc_base_addr;
+	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
+		rx_desc_num * RX_DESC_ALIGNED_SIZE;
+
+	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *	 This function prepares a Tx chained list of descriptors and packet
+ *	 buffers in a form of a ring. The routine must be called after port
+ *	 initialization routine and before port start routine.
+ *	 The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *	 devices in the system (i.e. DRAM). This function uses the ethernet
+ *	 struct 'virtual to physical' routine (set by the user) to set the ring
+ *	 with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue	 Number of Tx queue.
+ *	int			tx_desc_num	  Number of Tx descriptors
+ *	int			tx_buff_size	  Size of Tx buffer
+ *	unsigned int	tx_desc_base_addr  Tx descriptors memory area base addr.
+ *	unsigned int	tx_buff_base_addr  Tx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *	The routine updates the Ethernet port control struct with information
+ *	regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+ *	false if the given descriptors memory area is not aligned according to
+ *	Ethernet SDMA specifications.
+ *	true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE tx_queue,
+				     int tx_desc_num,
+				     int tx_buff_size,
+				     unsigned int tx_desc_base_addr,
+				     unsigned int tx_buff_base_addr)
+{
+
+	ETH_TX_DESC *p_tx_desc;
+	ETH_TX_DESC *p_tx_prev_desc;
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+	/* save the first desc pointer to link with the last descriptor */
+	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
+	p_tx_prev_desc = p_tx_desc;
+	buffer_addr = tx_buff_base_addr;
+
+	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (tx_buff_base_addr & 0xF)
+		return false;
+
+	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
+	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
+		return false;
+
+	/* Initialize the Tx descriptors ring */
+	for (ix = 0; ix < tx_desc_num; ix++) {
+		p_tx_desc->byte_cnt = 0x0000;
+		p_tx_desc->l4i_chk = 0x0000;
+		p_tx_desc->cmd_sts = 0x00000000;
+		p_tx_desc->next_desc_ptr =
+			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
+
+		p_tx_desc->buf_ptr = buffer_addr;
+		p_tx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
+		buffer_addr += tx_buff_size;
+		p_tx_prev_desc = p_tx_desc;
+		p_tx_desc = (ETH_TX_DESC *)
+			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
+
+	}
+	/* Closing Tx descriptors ring */
+	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
+	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
+	/* Set Tx desc pointer in driver struct. */
+	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+
+	/* Init Tx ring base and size parameters */
+	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
+		(ETH_TX_DESC *) tx_desc_base_addr;
+	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
+		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
+
+	/* Add the queue to the list of Tx queues of this port */
+	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+ *	This routine send a given packet described by p_pktinfo parameter. It
+ *	supports transmitting of a packet spaned over multiple buffers. The
+ *	routine updates 'curr' and 'first' indexes according to the packet
+ *	segment passed to the routine. In case the packet segment is first,
+ *	the 'first' index is update. In any case, the 'curr' index is updated.
+ *	If the routine get into Tx resource error it assigns 'curr' index as
+ *	'first'. This way the function can abort Tx process of multiple
+ *	descriptors per packet.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue	 Number of Tx queue.
+ *	PKT_INFO	*p_pkt_info	  User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_QUEUE_FULL in case of Tx resource error.
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+ *	ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
+					  ETH_QUEUE tx_queue,
+					  PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_first;
+	volatile ETH_TX_DESC *p_tx_desc_curr;
+	volatile ETH_TX_DESC *p_tx_next_desc_curr;
+	volatile ETH_TX_DESC *p_tx_desc_used;
+	unsigned int command_status;
+
+	/* Do not process Tx ring in case of Tx ring resource error */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		return ETH_QUEUE_FULL;
+
+	/* Get the Tx Desc ring indexes */
+	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+
+	if (p_tx_desc_curr == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
+	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+	if (command_status & (ETH_TX_FIRST_DESC)) {
+		/* Update first desc */
+		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
+		p_tx_desc_first = p_tx_desc_curr;
+	} else {
+		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+		command_status |= ETH_BUFFER_OWNED_BY_DMA;
+	}
+
+	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
+	/* boundary. We use the memory allocated for Tx descriptor. This memory	 */
+	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
+	if (p_pkt_info->byte_cnt <= 8) {
+		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
+		return ETH_ERROR;
+
+		p_tx_desc_curr->buf_ptr =
+			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
+		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
+			    p_pkt_info->byte_cnt);
+	} else
+		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
+
+	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
+	p_tx_desc_curr->return_info = p_pkt_info->return_info;
+
+	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
+		/* Set last desc with DMA ownership and interrupt enable. */
+		p_tx_desc_curr->cmd_sts = command_status |
+			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+		if (p_tx_desc_curr != p_tx_desc_first)
+			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+
+		/* Flush CPU pipe */
+
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
+		CPU_PIPE_FLUSH;
+
+		/* Apply send command */
+		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
+
+		/* Finish Tx packet. Update first desc in case of Tx resource error */
+		p_tx_desc_first = p_tx_next_desc_curr;
+		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
+
+	} else {
+		p_tx_desc_curr->cmd_sts = command_status;
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+	}
+
+	/* Check for ring index overlap in the Tx desc ring */
+	if (p_tx_next_desc_curr == p_tx_desc_used) {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_desc_first, tx_queue);
+
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
+		return ETH_QUEUE_LAST_RESOURCE;
+	} else {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
+		return ETH_OK;
+	}
+}
+
+/*******************************************************************************
+ * eth_tx_return_desc - Free all used Tx descriptors
+ *
+ * DESCRIPTION:
+ *	This routine returns the transmitted packet information to the caller.
+ *	It uses the 'first' index to support Tx desc return in case a transmit
+ *	of a packet spanned over multiple buffer still in process.
+ *	In case the Tx queue was in "resource error" condition, where there are
+ *	no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	tx_queue	 Number of Tx queue.
+ *	PKT_INFO	*p_pkt_info	  User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_RETRY in case there is transmission in process.
+ *	ETH_END_OF_JOB if the routine has nothing to release.
+ *	ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE tx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
+	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
+	unsigned int command_status;
+
+	/* Get the Tx Desc ring indexes */
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+
+	/* Sanity check */
+	if (p_tx_desc_used == NULL)
+		return ETH_ERROR;
+
+	command_status = p_tx_desc_used->cmd_sts;
+
+	/* Still transmitting... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_RETRY;
+	}
+
+	/* Stop release. About to overlap the current available Tx descriptor */
+	if ((p_tx_desc_used == p_tx_desc_first) &&
+	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_END_OF_JOB;
+	}
+
+	/* Pass the packet information to the caller */
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->return_info = p_tx_desc_used->return_info;
+	p_tx_desc_used->return_info = 0;
+
+	/* Update the next descriptor to release. */
+	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
+
+	/* Any Tx return cancels the Tx resource error status */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+
+	return ETH_OK;
+
+}
+
+/*******************************************************************************
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns the received data to the caller. There is no
+ *	data copying during routine operation. All information is returned
+ *	using pointer to packet information struct passed from the caller.
+ *	If the routine exhausts Rx ring resources then the resource error flag
+ *	is set.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue	 Number of Rx queue.
+ *	PKT_INFO	*p_pkt_info	  User packet buffer.
+ *
+ * OUTPUT:
+ *	Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ *	ETH_END_OF_JOB if there is no received data.
+ *	ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_next_curr_desc;
+	volatile ETH_RX_DESC *p_rx_used_desc;
+	unsigned int command_status;
+
+	/* Do not process Rx ring in case of Rx ring resource error */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
+		printf ("\nRx Queue is full ...\n");
+		return ETH_QUEUE_FULL;
+	}
+
+	/* Get the Rx Desc ring 'curr and 'used' indexes */
+	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
+	USED_RFD_GET (p_rx_used_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_rx_curr_desc == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
+	command_status = p_rx_curr_desc->cmd_sts;
+
+	/* Nothing to receive... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+/*	DP(printf("Rx: command_status: %08x\n", command_status)); */
+		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
+		return ETH_END_OF_JOB;
+	}
+
+	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
+	p_pkt_info->return_info = p_rx_curr_desc->return_info;
+	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
+
+	/* Clean the return info field to indicate that the packet has been */
+	/* moved to the upper layers					    */
+	p_rx_curr_desc->return_info = 0;
+
+	/* Update 'curr' in data structure */
+	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
+
+	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
+	if (p_rx_next_curr_desc == p_rx_used_desc)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
+ *	next 'used' descriptor and attached the returned buffer to it.
+ *	In case the Rx ring was in "resource error" condition, where there are
+ *	no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO	*p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE	rx_queue	 Number of Rx queue.
+ *	PKT_INFO	*p_pkt_info	  Information on the returned buffer.
+ *
+ * OUTPUT:
+ *	New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE rx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
+
+	/* Get 'used' Rx descriptor */
+	USED_RFD_GET (p_used_rx_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_used_rx_desc == NULL)
+		return ETH_ERROR;
+
+	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
+	p_used_rx_desc->return_info = p_pkt_info->return_info;
+	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
+	p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE;	/* Reset Buffer size */
+
+	/* Flush the write pipe */
+	CPU_PIPE_FLUSH;
+
+	/* Return the descriptor to DMA ownership */
+	p_used_rx_desc->cmd_sts =
+		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+
+	/* Flush descriptor and CPU pipe */
+	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	/* Move the used descriptor pointer to the next descriptor */
+	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
+
+	/* Any Rx return cancels the Rx resource error status */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the RX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the tClk of the MV-643xx chip
+ *	, and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num	   Ethernet port number
+ *	unsigned int t_clk	  t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay	 Delay in usec
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set RX Coalescing mechanism */
+	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      ((coal & 0x3fff) << 8) |
+		      (MV_REG_READ
+		       (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
+		       & 0xffc000ff));
+	return coal;
+}
+
+#endif
+/*******************************************************************************
+ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the TX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the t_cLK frequency of the
+ *	MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num	   Ethernet port number
+ *	unsigned int t_clk	  t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay	 Delay in uSeconds
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set TX Coalescing mechanism */
+	MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
+		      coal << 4);
+	return coal;
+}
+#endif
+
+/*******************************************************************************
+ * eth_b_copy - Copy bytes from source to destination
+ *
+ * DESCRIPTION:
+ *	 This function supports the eight bytes limitation on Tx buffer size.
+ *	 The routine will zero eight bytes starting from the destination address
+ *	 followed by copying bytes from the source address to the destination.
+ *
+ * INPUT:
+ *	 unsigned int src_addr	  32 bit source address.
+ *	 unsigned int dst_addr	  32 bit destination address.
+ *	 int	    byte_count	  Number of bytes to copy.
+ *
+ * OUTPUT:
+ *	 See description.
+ *
+ * RETURN:
+ *	 None.
+ *
+ *******************************************************************************/
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count)
+{
+	/* Zero the dst_addr area */
+	*(unsigned int *) dst_addr = 0x0;
+
+	while (byte_count != 0) {
+		*(char *) dst_addr = *(char *) src_addr;
+		dst_addr++;
+		src_addr++;
+		byte_count--;
+	}
+}
diff --git a/board/prodrive/p3mx/mv_eth.h b/board/prodrive/p3mx/mv_eth.h
new file mode 100644
index 0000000..334b049
--- /dev/null
+++ b/board/prodrive/p3mx/mv_eth.h
@@ -0,0 +1,840 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64460_ETH_H__
+#define __DB64460_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include "ppc_error_no.h"
+#include "../../Marvell/include/core.h"
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64460_TX_QUEUE_NUM 1
+#define MV64460_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
+#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
+#else
+#define MV64460_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64460_ETH_RXQUEUE_SIZE
+#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
+#else
+#define MV64460_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64460_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64460_TX_BUFFER_SIZE 1600
+#endif
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64460_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+    /* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+    int first_init;
+};
+
+int mv64460_eth_init (struct eth_device *dev);
+int mv64460_eth_stop (struct eth_device *dev);
+int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
+/*	return db64460_eth0_poll(); */
+
+int mv64460_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64460_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64460_ETH_ */
diff --git a/board/prodrive/p3mx/mv_regs.h b/board/prodrive/p3mx/mv_regs.h
new file mode 100644
index 0000000..068590f
--- /dev/null
+++ b/board/prodrive/p3mx/mv_regs.h
@@ -0,0 +1,1125 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/********************************************************************************
+* gt64460r.h - GT-64460 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_regsh
+#define __INCmv_regsh
+
+#define MV64460
+
+/* Supported by the Atlantis */
+#define MV64460_INCLUDE_PCI_1
+#define MV64460_INCLUDE_PCI_0_ARBITER
+#define MV64460_INCLUDE_PCI_1_ARBITER
+#define MV64460_INCLUDE_SNOOP_SUPPORT
+#define MV64460_INCLUDE_P2P
+#define MV64460_INCLUDE_ETH_PORT_2
+#define MV64460_INCLUDE_CPU_MAPPING
+#define MV64460_INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+/****************************************/
+/* Processor Address Space		*/
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64460_CS_0_BASE_ADDR					    0x008
+#define MV64460_CS_0_SIZE					    0x010
+#define MV64460_CS_1_BASE_ADDR					    0x208
+#define MV64460_CS_1_SIZE					    0x210
+#define MV64460_CS_2_BASE_ADDR					    0x018
+#define MV64460_CS_2_SIZE					    0x020
+#define MV64460_CS_3_BASE_ADDR					    0x218
+#define MV64460_CS_3_SIZE					    0x220
+
+/* Devices BAR and size registers */
+
+#define MV64460_DEV_CS0_BASE_ADDR				    0x028
+#define MV64460_DEV_CS0_SIZE					    0x030
+#define MV64460_DEV_CS1_BASE_ADDR				    0x228
+#define MV64460_DEV_CS1_SIZE					    0x230
+#define MV64460_DEV_CS2_BASE_ADDR				    0x248
+#define MV64460_DEV_CS2_SIZE					    0x250
+#define MV64460_DEV_CS3_BASE_ADDR				    0x038
+#define MV64460_DEV_CS3_SIZE					    0x040
+#define MV64460_BOOTCS_BASE_ADDR				    0x238
+#define MV64460_BOOTCS_SIZE					    0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64460_PCI_0_IO_BASE_ADDR				    0x048
+#define MV64460_PCI_0_IO_SIZE					    0x050
+#define MV64460_PCI_0_MEMORY0_BASE_ADDR				    0x058
+#define MV64460_PCI_0_MEMORY0_SIZE				    0x060
+#define MV64460_PCI_0_MEMORY1_BASE_ADDR				    0x080
+#define MV64460_PCI_0_MEMORY1_SIZE				    0x088
+#define MV64460_PCI_0_MEMORY2_BASE_ADDR				    0x258
+#define MV64460_PCI_0_MEMORY2_SIZE				    0x260
+#define MV64460_PCI_0_MEMORY3_BASE_ADDR				    0x280
+#define MV64460_PCI_0_MEMORY3_SIZE				    0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64460_PCI_1_IO_BASE_ADDR				    0x090
+#define MV64460_PCI_1_IO_SIZE					    0x098
+#define MV64460_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
+#define MV64460_PCI_1_MEMORY0_SIZE				    0x0a8
+#define MV64460_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
+#define MV64460_PCI_1_MEMORY1_SIZE				    0x0b8
+#define MV64460_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
+#define MV64460_PCI_1_MEMORY2_SIZE				    0x2a8
+#define MV64460_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
+#define MV64460_PCI_1_MEMORY3_SIZE				    0x2b8
+
+/* SRAM base address */
+#define MV64460_INTEGRATED_SRAM_BASE_ADDR			    0x268
+
+/* internal registers space base address */
+#define MV64460_INTERNAL_SPACE_BASE_ADDR			    0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define MV64460_BASE_ADDR_ENABLE				    0x278
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+      /* PCI 0 */
+#define MV64460_PCI_0_IO_ADDR_REMAP				    0x0f0
+#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
+#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
+#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
+#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
+#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
+#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
+#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
+#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
+      /* PCI 1 */
+#define MV64460_PCI_1_IO_ADDR_REMAP				    0x108
+#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
+#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
+#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
+#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
+#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
+#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
+#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
+#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
+
+#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
+#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
+#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
+#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
+#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
+#define MV64460_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
+#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
+#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+
+#define MV64460_CPU_CONFIG					    0x000
+#define MV64460_CPU_MODE					    0x120
+#define MV64460_CPU_MASTER_CONTROL				    0x160
+#define MV64460_CPU_CROSS_BAR_CONTROL_LOW			    0x150
+#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
+#define MV64460_CPU_CROSS_BAR_TIMEOUT				    0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define MV64460_SMP_WHO_AM_I					    0x200
+#define MV64460_SMP_CPU0_DOORBELL				    0x214
+#define MV64460_SMP_CPU0_DOORBELL_CLEAR				    0x21C
+#define MV64460_SMP_CPU1_DOORBELL				    0x224
+#define MV64460_SMP_CPU1_DOORBELL_CLEAR				    0x22C
+#define MV64460_SMP_CPU0_DOORBELL_MASK				    0x234
+#define MV64460_SMP_CPU1_DOORBELL_MASK				    0x23C
+#define MV64460_SMP_SEMAPHOR0					    0x244
+#define MV64460_SMP_SEMAPHOR1					    0x24c
+#define MV64460_SMP_SEMAPHOR2					    0x254
+#define MV64460_SMP_SEMAPHOR3					    0x25c
+#define MV64460_SMP_SEMAPHOR4					    0x264
+#define MV64460_SMP_SEMAPHOR5					    0x26c
+#define MV64460_SMP_SEMAPHOR6					    0x274
+#define MV64460_SMP_SEMAPHOR7					    0x27c
+
+/****************************************/
+/*  CPU Sync Barrier Register		*/
+/****************************************/
+
+#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
+#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
+#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
+#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
+#define MV64460_CPU_PROTECT_WINDOW_0_SIZE			    0x188
+#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
+#define MV64460_CPU_PROTECT_WINDOW_1_SIZE			    0x198
+#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
+#define MV64460_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
+#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
+#define MV64460_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
+
+
+/****************************************/
+/*	    CPU Error Report		*/
+/****************************************/
+
+#define MV64460_CPU_ERROR_ADDR_LOW				    0x070
+#define MV64460_CPU_ERROR_ADDR_HIGH				    0x078
+#define MV64460_CPU_ERROR_DATA_LOW				    0x128
+#define MV64460_CPU_ERROR_DATA_HIGH				    0x130
+#define MV64460_CPU_ERROR_PARITY				    0x138
+#define MV64460_CPU_ERROR_CAUSE					    0x140
+#define MV64460_CPU_ERROR_MASK					    0x148
+
+/****************************************/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define MV64460_PUNIT_SLAVE_DEBUG_LOW				    0x360
+#define MV64460_PUNIT_SLAVE_DEBUG_HIGH				    0x368
+#define MV64460_PUNIT_MASTER_DEBUG_LOW				    0x370
+#define MV64460_PUNIT_MASTER_DEBUG_HIGH				    0x378
+#define MV64460_PUNIT_MMASK					    0x3e4
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define MV64460_SRAM_CONFIG					    0x380
+#define MV64460_SRAM_TEST_MODE					    0X3F4
+#define MV64460_SRAM_ERROR_CAUSE				    0x388
+#define MV64460_SRAM_ERROR_ADDR					    0x390
+#define MV64460_SRAM_ERROR_ADDR_HIGH				    0X3F8
+#define MV64460_SRAM_ERROR_DATA_LOW				    0x398
+#define MV64460_SRAM_ERROR_DATA_HIGH				    0x3a0
+#define MV64460_SRAM_ERROR_DATA_PARITY				    0x3a8
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+#define MV64460_SDRAM_CONFIG					    0x1400
+#define MV64460_D_UNIT_CONTROL_LOW				    0x1404
+#define MV64460_D_UNIT_CONTROL_HIGH				    0x1424
+#define MV64460_D_UNIT_MMASK					    0x14B0
+#define MV64460_SDRAM_TIMING_CONTROL_LOW			    0x1408
+#define MV64460_SDRAM_TIMING_CONTROL_HIGH			    0x140c
+#define MV64460_SDRAM_ADDR_CONTROL				    0x1410
+#define MV64460_SDRAM_OPEN_PAGES_CONTROL			    0x1414
+#define MV64460_SDRAM_OPERATION					    0x1418
+#define MV64460_SDRAM_MODE					    0x141c
+#define MV64460_EXTENDED_DRAM_MODE				    0x1420
+#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
+#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
+#define MV64460_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
+#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
+#define MV64460_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+
+#define MV64460_SDRAM_ERROR_DATA_LOW				    0x1444
+#define MV64460_SDRAM_ERROR_DATA_HIGH				    0x1440
+#define MV64460_SDRAM_ERROR_ADDR				    0x1450
+#define MV64460_SDRAM_RECEIVED_ECC				    0x1448
+#define MV64460_SDRAM_CALCULATED_ECC				    0x144c
+#define MV64460_SDRAM_ECC_CONTROL				    0x1454
+#define MV64460_SDRAM_ECC_ERROR_COUNTER				    0x1458
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64460_DFCDL_CONFIG0					    0x1480
+#define MV64460_DFCDL_CONFIG1					    0x1484
+#define MV64460_DLL_WRITE					    0x1488
+#define MV64460_DLL_READ					    0x148c
+#define MV64460_SRAM_ADDR					    0x1490
+#define MV64460_SRAM_DATA0					    0x1494
+#define MV64460_SRAM_DATA1					    0x1498
+#define MV64460_SRAM_DATA2					    0x149c
+#define MV64460_DFCL_PROBE					    0x14a0
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define MV64460_DUNIT_DEBUG_LOW					    0x1460
+#define MV64460_DUNIT_DEBUG_HIGH				    0x1464
+#define MV64460_DUNIT_MMASK					    0X1b40
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define MV64460_DEVICE_BANK0_PARAMETERS				    0x45c
+#define MV64460_DEVICE_BANK1_PARAMETERS				    0x460
+#define MV64460_DEVICE_BANK2_PARAMETERS				    0x464
+#define MV64460_DEVICE_BANK3_PARAMETERS				    0x468
+#define MV64460_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
+#define MV64460_DEVICE_INTERFACE_CONTROL			    0x4c0
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
+
+/****************************************/
+/* Device interrupt registers		*/
+/****************************************/
+
+#define MV64460_DEVICE_INTERRUPT_CAUSE				    0x4d0
+#define MV64460_DEVICE_INTERRUPT_MASK				    0x4d4
+#define MV64460_DEVICE_ERROR_ADDR				    0x4d8
+#define MV64460_DEVICE_ERROR_DATA				    0x4dc
+#define MV64460_DEVICE_ERROR_PARITY				    0x4e0
+
+/****************************************/
+/* Device debug registers		*/
+/****************************************/
+
+#define MV64460_DEVICE_DEBUG_LOW				    0x4e4
+#define MV64460_DEVICE_DEBUG_HIGH				    0x4e8
+#define MV64460_RUNIT_MMASK					    0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64460_PCI_0_CS_0_BANK_SIZE				    0xc08
+#define MV64460_PCI_1_CS_0_BANK_SIZE				    0xc88
+#define MV64460_PCI_0_CS_1_BANK_SIZE				    0xd08
+#define MV64460_PCI_1_CS_1_BANK_SIZE				    0xd88
+#define MV64460_PCI_0_CS_2_BANK_SIZE				    0xc0c
+#define MV64460_PCI_1_CS_2_BANK_SIZE				    0xc8c
+#define MV64460_PCI_0_CS_3_BANK_SIZE				    0xd0c
+#define MV64460_PCI_1_CS_3_BANK_SIZE				    0xd8c
+#define MV64460_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
+#define MV64460_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
+#define MV64460_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
+#define MV64460_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
+#define MV64460_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
+#define MV64460_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
+#define MV64460_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
+#define MV64460_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
+#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
+#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
+#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
+#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
+#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
+#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
+#define MV64460_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
+#define MV64460_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
+#define MV64460_PCI_0_CPU_BAR_SIZE				    0xd28
+#define MV64460_PCI_1_CPU_BAR_SIZE				    0xda8
+#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
+#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
+#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
+#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
+#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
+#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
+#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
+#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
+#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
+#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
+#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
+#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
+#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
+#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
+#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
+#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
+#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
+#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
+#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
+#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
+#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
+#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
+#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
+#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
+#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
+#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
+#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
+#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
+#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
+#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
+#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
+#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
+#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
+#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
+#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
+#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
+#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
+#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
+#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
+#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
+#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
+#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
+#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
+#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
+#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
+#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
+#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
+#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
+#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
+#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
+#define MV64460_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
+#define MV64460_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
+#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
+#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
+#define MV64460_PCI_0_HEADERS_RETARGET_BASE			    0xF44
+#define MV64460_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
+#define MV64460_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
+#define MV64460_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
+
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
+#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
+#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
+#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
+#define MV64460_PCI_0_COMMAND					    0xc00
+#define MV64460_PCI_1_COMMAND					    0xc80
+#define MV64460_PCI_0_MODE					    0xd00
+#define MV64460_PCI_1_MODE					    0xd80
+#define MV64460_PCI_0_RETRY					    0xc04
+#define MV64460_PCI_1_RETRY					    0xc84
+#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
+#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MV64460_PCI_0_MSI_TRIGGER_TIMER				    0xc38
+#define MV64460_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
+#define MV64460_PCI_0_ARBITER_CONTROL				    0x1d00
+#define MV64460_PCI_1_ARBITER_CONTROL				    0x1d80
+#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
+#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
+#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
+#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
+#define MV64460_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
+#define MV64460_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
+#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
+#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
+#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
+#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
+#define MV64460_PCI_0_P2P_CONFIG				    0x1d14
+#define MV64460_PCI_1_P2P_CONFIG				    0x1d94
+
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
+
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64460_PCI_0_CONFIG_ADDR				    0xcf8
+#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
+#define MV64460_PCI_1_CONFIG_ADDR				    0xc78
+#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
+#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
+#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define MV64460_PCI_0_SERR_MASK					    0xc28
+#define MV64460_PCI_1_SERR_MASK					    0xca8
+#define MV64460_PCI_0_ERROR_ADDR_LOW				    0x1d40
+#define MV64460_PCI_1_ERROR_ADDR_LOW				    0x1dc0
+#define MV64460_PCI_0_ERROR_ADDR_HIGH				    0x1d44
+#define MV64460_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
+#define MV64460_PCI_0_ERROR_ATTRIBUTE				    0x1d48
+#define MV64460_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
+#define MV64460_PCI_0_ERROR_COMMAND				    0x1d50
+#define MV64460_PCI_1_ERROR_COMMAND				    0x1dd0
+#define MV64460_PCI_0_ERROR_CAUSE				    0x1d58
+#define MV64460_PCI_1_ERROR_CAUSE				    0x1dd8
+#define MV64460_PCI_0_ERROR_MASK				    0x1d5c
+#define MV64460_PCI_1_ERROR_MASK				    0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define MV64460_PCI_0_MMASK					    0X1D24
+#define MV64460_PCI_1_MMASK					    0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define MV64460_PCI_DEVICE_AND_VENDOR_ID			    0x000
+#define MV64460_PCI_STATUS_AND_COMMAND				    0x004
+#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
+#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
+
+#define MV64460_PCI_SCS_0_BASE_ADDR_LOW				    0x010
+#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
+#define MV64460_PCI_SCS_1_BASE_ADDR_LOW				    0x018
+#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
+#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
+#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
+#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
+#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
+#define MV64460_PCI_CAPABILTY_LIST_POINTER			    0x034
+#define MV64460_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
+       /* capability list */
+#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define MV64460_PCI_VPD_ADDR					    0x048
+#define MV64460_PCI_VPD_DATA					    0x04c
+#define MV64460_PCI_MSI_MESSAGE_CONTROL				    0x050
+#define MV64460_PCI_MSI_MESSAGE_ADDR				    0x054
+#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
+#define MV64460_PCI_MSI_MESSAGE_DATA				    0x05c
+#define MV64460_PCI_X_COMMAND					    0x060
+#define MV64460_PCI_X_STATUS					    0x064
+#define MV64460_PCI_COMPACT_PCI_HOT_SWAP			    0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define MV64460_PCI_SCS_2_BASE_ADDR_LOW				    0x110
+#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
+#define MV64460_PCI_SCS_3_BASE_ADDR_LOW				    0x118
+#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
+#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
+#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
+#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
+#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
+#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
+#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
+#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
+#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
+#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
+#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
+#define MV64460_PCI_CPU_BASE_ADDR_LOW				    0x220
+#define MV64460_PCI_CPU_BASE_ADDR_HIGH				    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
+#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
+#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
+#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
+#define MV64460_PCI_P2P_I_O_BASE_ADDR				    0x420
+#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
+#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
+#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
+#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
+#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define MV64460_ETH_PHY_ADDR_REG				    0x2000
+#define MV64460_ETH_SMI_REG					    0x2004
+#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
+#define MV64460_ETH_UNIT_DEFAULTID_REG				    0x200c
+#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
+#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
+#define MV64460_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
+#define MV64460_ETH_UNIT_ERROR_ADDR_REG				    0x2094
+#define MV64460_ETH_BAR_0					    0x2200
+#define MV64460_ETH_BAR_1					    0x2208
+#define MV64460_ETH_BAR_2					    0x2210
+#define MV64460_ETH_BAR_3					    0x2218
+#define MV64460_ETH_BAR_4					    0x2220
+#define MV64460_ETH_BAR_5					    0x2228
+#define MV64460_ETH_SIZE_REG_0					    0x2204
+#define MV64460_ETH_SIZE_REG_1					    0x220c
+#define MV64460_ETH_SIZE_REG_2					    0x2214
+#define MV64460_ETH_SIZE_REG_3					    0x221c
+#define MV64460_ETH_SIZE_REG_4					    0x2224
+#define MV64460_ETH_SIZE_REG_5					    0x222c
+#define MV64460_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
+#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
+#define MV64460_ETH_BASE_ADDR_ENABLE_REG			    0x2290
+#define MV64460_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
+#define MV64460_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
+#define MV64460_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
+#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
+#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
+#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
+#define MV64460_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
+#define MV64460_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
+#define MV64460_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
+#define MV64460_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
+#define MV64460_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
+#define MV64460_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
+#define MV64460_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
+#define MV64460_ETH_DSCP_3(port)				   (0x242c + (port<<10))
+#define MV64460_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
+#define MV64460_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
+#define MV64460_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
+#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
+#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
+#define MV64460_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
+#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
+#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
+#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define MV64460_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
+#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
+#define MV64460_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
+#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
+#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
+#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
+#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
+#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
+#define MV64460_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
+#define MV64460_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
+#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
+#define MV64460_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
+#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
+#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
+#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
+#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define MV64460_CUNIT_BASE_ADDR_REG0				    0xf200
+#define MV64460_CUNIT_BASE_ADDR_REG1				    0xf208
+#define MV64460_CUNIT_BASE_ADDR_REG2				    0xf210
+#define MV64460_CUNIT_BASE_ADDR_REG3				    0xf218
+#define MV64460_CUNIT_SIZE0					    0xf204
+#define MV64460_CUNIT_SIZE1					    0xf20c
+#define MV64460_CUNIT_SIZE2					    0xf214
+#define MV64460_CUNIT_SIZE3					    0xf21c
+#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
+#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
+#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
+#define MV64460_MPSC0_ACCESS_PROTECTION_REG			    0xf254
+#define MV64460_MPSC1_ACCESS_PROTECTION_REG			    0xf258
+#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
+
+	/*  Error Report Registers  */
+
+#define MV64460_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
+#define MV64460_CUNIT_INTERRUPT_MASK_REG			    0xf314
+#define MV64460_CUNIT_ERROR_ADDR				    0xf318
+
+	/*  Cunit Control Registers */
+
+#define MV64460_CUNIT_ARBITER_CONTROL_REG			    0xf300
+#define MV64460_CUNIT_CONFIG_REG				    0xb40c
+#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define MV64460_CUNIT_DEBUG_LOW					    0xf340
+#define MV64460_CUNIT_DEBUG_HIGH				    0xf344
+#define MV64460_CUNIT_MMASK					    0xf380
+
+	/*  Cunit Base Address Enable Window Bits*/
+#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
+#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
+#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
+#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MV64460_MPSC_ROUTING_REG				    0xb400
+#define MV64460_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
+#define MV64460_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MV64460_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
+#define MV64460_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
+
+#define MV64460_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
+#define MV64460_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
+#define MV64460_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
+
+	/*  MPSC0 Registers	 */
+
+
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define MV64460_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
+#define MV64460_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
+#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
+#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define MV64460_SDMA_CAUSE_REG					    0xb800
+#define MV64460_SDMA_MASK_REG					    0xb880
+
+
+/****************************************/
+/* SDMA Address Space Targets		*/
+/****************************************/
+
+#define MV64460_SDMA_DRAM_CS_0_TARGET				    0x0e00
+#define MV64460_SDMA_DRAM_CS_1_TARGET				    0x0d00
+#define MV64460_SDMA_DRAM_CS_2_TARGET				    0x0b00
+#define MV64460_SDMA_DRAM_CS_3_TARGET				    0x0700
+
+#define MV64460_SDMA_DEV_CS_0_TARGET				    0x1e01
+#define MV64460_SDMA_DEV_CS_1_TARGET				    0x1d01
+#define MV64460_SDMA_DEV_CS_2_TARGET				    0x1b01
+#define MV64460_SDMA_DEV_CS_3_TARGET				    0x1701
+
+#define MV64460_SDMA_BOOT_CS_TARGET				    0x0f00
+
+#define MV64460_SDMA_SRAM_TARGET				    0x0003
+#define MV64460_SDMA_60X_BUS_TARGET				    0x4003
+
+#define MV64460_PCI_0_TARGET					    0x0003
+#define MV64460_PCI_1_TARGET					    0x0004
+
+
+/* Devices BAR and size registers */
+
+#define MV64460_DEV_CS0_BASE_ADDR				    0x028
+#define MV64460_DEV_CS0_SIZE					    0x030
+#define MV64460_DEV_CS1_BASE_ADDR				    0x228
+#define MV64460_DEV_CS1_SIZE					    0x230
+#define MV64460_DEV_CS2_BASE_ADDR				    0x248
+#define MV64460_DEV_CS2_SIZE					    0x250
+#define MV64460_DEV_CS3_BASE_ADDR				    0x038
+#define MV64460_DEV_CS3_SIZE					    0x040
+#define MV64460_BOOTCS_BASE_ADDR				    0x238
+#define MV64460_BOOTCS_SIZE					    0x240
+
+/* SDMA Window access protection */
+#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0
+#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1
+#define MV64460_SDMA_WIN_ACCESS_FULL 2
+
+/* BRG Interrupts */
+
+#define MV64460_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
+#define MV64460_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
+#define MV64460_BRG_CAUSE_REG					    0xb834
+#define MV64460_BRG_MASK_REG					    0xb8b4
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define MV64460_DMA_CHANNEL0_CONTROL				    0x840
+#define MV64460_DMA_CHANNEL0_CONTROL_HIGH			    0x880
+#define MV64460_DMA_CHANNEL1_CONTROL				    0x844
+#define MV64460_DMA_CHANNEL1_CONTROL_HIGH			    0x884
+#define MV64460_DMA_CHANNEL2_CONTROL				    0x848
+#define MV64460_DMA_CHANNEL2_CONTROL_HIGH			    0x888
+#define MV64460_DMA_CHANNEL3_CONTROL				    0x84C
+#define MV64460_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
+
+
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define MV64460_DMA_CHANNEL0_BYTE_COUNT				    0x800
+#define MV64460_DMA_CHANNEL1_BYTE_COUNT				    0x804
+#define MV64460_DMA_CHANNEL2_BYTE_COUNT				    0x808
+#define MV64460_DMA_CHANNEL3_BYTE_COUNT				    0x80C
+#define MV64460_DMA_CHANNEL0_SOURCE_ADDR			    0x810
+#define MV64460_DMA_CHANNEL1_SOURCE_ADDR			    0x814
+#define MV64460_DMA_CHANNEL2_SOURCE_ADDR			    0x818
+#define MV64460_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
+#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
+#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
+#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
+#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
+#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
+#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
+#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
+#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
+#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
+#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
+#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
+#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define MV64460_DMA_BASE_ADDR_REG0				    0xa00
+#define MV64460_DMA_BASE_ADDR_REG1				    0xa08
+#define MV64460_DMA_BASE_ADDR_REG2				    0xa10
+#define MV64460_DMA_BASE_ADDR_REG3				    0xa18
+#define MV64460_DMA_BASE_ADDR_REG4				    0xa20
+#define MV64460_DMA_BASE_ADDR_REG5				    0xa28
+#define MV64460_DMA_BASE_ADDR_REG6				    0xa30
+#define MV64460_DMA_BASE_ADDR_REG7				    0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define MV64460_DMA_SIZE_REG0					    0xa04
+#define MV64460_DMA_SIZE_REG1					    0xa0c
+#define MV64460_DMA_SIZE_REG2					    0xa14
+#define MV64460_DMA_SIZE_REG3					    0xa1c
+#define MV64460_DMA_SIZE_REG4					    0xa24
+#define MV64460_DMA_SIZE_REG5					    0xa2c
+#define MV64460_DMA_SIZE_REG6					    0xa34
+#define MV64460_DMA_SIZE_REG7					    0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
+#define MV64460_DMA_BASE_ADDR_ENABLE_REG			    0xa80
+#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
+#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
+#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
+#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
+#define MV64460_DMA_ARBITER_CONTROL				    0x860
+#define MV64460_DMA_CROSS_BAR_TIMEOUT				    0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+#define MV64460_DMA_HEADERS_RETARGET_CONTROL			    0xa84
+#define MV64460_DMA_HEADERS_RETARGET_BASE			    0xa88
+
+ /*  IDMA Interrupt Register  */
+
+#define MV64460_DMA_INTERRUPT_CAUSE_REG				    0x8c0
+#define MV64460_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
+#define MV64460_DMA_ERROR_ADDR					    0x8c8
+#define MV64460_DMA_ERROR_SELECT				    0x8cc
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define MV64460_DMA_DEBUG_LOW					    0x8e0
+#define MV64460_DMA_DEBUG_HIGH					    0x8e4
+#define MV64460_DMA_SPARE					    0xA8C
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define MV64460_TIMER_COUNTER0					    0x850
+#define MV64460_TIMER_COUNTER1					    0x854
+#define MV64460_TIMER_COUNTER2					    0x858
+#define MV64460_TIMER_COUNTER3					    0x85C
+#define MV64460_TIMER_COUNTER_0_3_CONTROL			    0x864
+#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
+#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
+
+/****************************************/
+/*	   Watchdog registers		*/
+/****************************************/
+
+#define MV64460_WATCHDOG_CONFIG_REG				    0xb410
+#define MV64460_WATCHDOG_VALUE_REG				    0xb414
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define MV64460_I2C_SLAVE_ADDR					    0xc000
+#define MV64460_I2C_EXTENDED_SLAVE_ADDR				    0xc010
+#define MV64460_I2C_DATA					    0xc004
+#define MV64460_I2C_CONTROL					    0xc008
+#define MV64460_I2C_STATUS_BAUDE_RATE				    0xc00C
+#define MV64460_I2C_SOFT_RESET					    0xc01c
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define MV64460_GPP_IO_CONTROL					    0xf100
+#define MV64460_GPP_LEVEL_CONTROL				    0xf110
+#define MV64460_GPP_VALUE					    0xf104
+#define MV64460_GPP_INTERRUPT_CAUSE				    0xf108
+#define MV64460_GPP_INTERRUPT_MASK0				    0xf10c
+#define MV64460_GPP_INTERRUPT_MASK1				    0xf114
+#define MV64460_GPP_VALUE_SET					    0xf118
+#define MV64460_GPP_VALUE_CLEAR					    0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define MV64460_MAIN_INTERRUPT_CAUSE_LOW			    0x004
+#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
+#define MV64460_CPU_INTERRUPT0_MASK_LOW				    0x014
+#define MV64460_CPU_INTERRUPT0_MASK_HIGH			    0x01c
+#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
+#define MV64460_CPU_INTERRUPT1_MASK_LOW				    0x034
+#define MV64460_CPU_INTERRUPT1_MASK_HIGH			    0x03c
+#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
+#define MV64460_INTERRUPT0_MASK_0_LOW				    0x054
+#define MV64460_INTERRUPT0_MASK_0_HIGH				    0x05c
+#define MV64460_INTERRUPT0_SELECT_CAUSE				    0x064
+#define MV64460_INTERRUPT1_MASK_0_LOW				    0x074
+#define MV64460_INTERRUPT1_MASK_0_HIGH				    0x07c
+#define MV64460_INTERRUPT1_SELECT_CAUSE				    0x084
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+
+#define MV64460_MPP_CONTROL0					    0xf000
+#define MV64460_MPP_CONTROL1					    0xf004
+#define MV64460_MPP_CONTROL2					    0xf008
+#define MV64460_MPP_CONTROL3					    0xf00c
+
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+#define MV64460_SERIAL_INIT_LAST_DATA				    0xf324
+#define MV64460_SERIAL_INIT_CONTROL				    0xf328
+#define MV64460_SERIAL_INIT_STATUS				    0xf32c
+
+
+#endif /* __INCgt64460rh */
diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c
new file mode 100644
index 0000000..d54ddaf
--- /dev/null
+++ b/board/prodrive/p3mx/p3mx.c
@@ -0,0 +1,864 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Based on original work by
+ *	Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
+ *	Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
+ * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
+ * modifications for the P3M750 by roel.loeffen@prodrive.nl
+ */
+
+/*
+ * p3m750.c - main board support/init for the Prodrive p3m750/p3m7448.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+#include <i2c.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "64460.h"
+#include "mv_regs.h"
+#include "p3mx.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#ifdef CONFIG_PCI
+#define	MAP_PCI
+#endif /* of CONFIG_PCI */
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+extern void flush_data_cache (void);
+extern void invalidate_l1_instruction_cache (void);
+extern flash_info_t flash_info[];
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+int display_mem_map (void);
+void set_led(int);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, */
+					/* FuncNum 10:8, RegNum 7:2 */
+
+	/*
+	 * In PCIX mode devices provide their own bus and device numbers.
+	 * We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the
+	 * bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/* if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/* if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) |
+		(1 << 18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen:
+	 * add write to pci remap registers for 64460.
+	 * in 64360 when writing to pci base go and overide remap automaticaly,
+	 * in 64460 it doesn't
+	 */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+	/* ronen:
+	 * update the pci internal registers base address.
+	 */
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++)
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, CFG_GT_REGS);
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+	/* set the SINGLE_CPU bit  see MV64460 */
+#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+	tmp |= CPU_CONF_PIPELINE;
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+	/* set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in >MV6436x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+
+	/* Device and Boot bus settings
+	 */
+	memoryMapDeviceSpace(DEVICE0, 0, 0);
+	GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0);
+	memoryMapDeviceSpace(DEVICE1, 0, 0);
+	GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0);
+	memoryMapDeviceSpace(DEVICE2, 0, 0);
+	GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0);
+	memoryMapDeviceSpace(DEVICE3, 0, 0);
+	GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
+
+	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_BOOT_PAR);
+
+	gt_cpu_config();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+
+	set_led(LED_RED);
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	u8 val;
+
+	icache_enable ();
+#ifdef CFG_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+	/*
+	 * Enable trickle changing in RTC upon powerup
+	 * No diode, 250 ohm series resistor
+	 */
+	val = 0xa5;
+	i2c_write(CFG_I2C_RTC_ADDR, 8, 1, &val, 1);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	/* now relocate the debug serial driver */
+	mpsc_putchar += gd->reloc_off;
+	mpsc_getchar += gd->reloc_off;
+	mpsc_test_char += gd->reloc_off;
+
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+	memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
+
+/*	display_mem_map(); */
+
+	/* now, jump to the main U-Boot board init code */
+	set_led(LED_GREEN);
+	board_init_r (gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/*
+ * Check Board Identity:
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: %s", CFG_BOARD_NAME);
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+void set_led(int col)
+{
+	int tmp;
+	int on_pin;
+	int off_pin;
+
+	/* Program Mpp[22] as Gpp[22]
+	 * Program Mpp[23] as Gpp[23]
+	 */
+	tmp = GTREGREAD(MPP_CONTROL2);
+	tmp &= 0x00ffffff;
+	GT_REG_WRITE(MPP_CONTROL2,tmp);
+
+	/* Program Gpp[22] and Gpp[23] as output
+	 */
+	tmp = GTREGREAD(GPP_IO_CONTROL);
+	tmp |= 0x00C00000;
+	GT_REG_WRITE(GPP_IO_CONTROL, tmp);
+
+	/* Program Gpp[22] and Gpp[23] as active high
+	 */
+	tmp = GTREGREAD(GPP_LEVEL_CONTROL);
+	tmp &= 0xff3fffff;
+	GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);
+
+	switch(col) {
+	default:
+	case LED_OFF :
+		on_pin  = 0;
+		off_pin = ((1 << 23) | (1 << 22));
+		break;
+	case LED_RED :
+		on_pin  = (1 << 23);
+		off_pin = (1 << 22);
+		break;
+	case LED_GREEN :
+		on_pin  = (1 << 22);
+		off_pin = (1 << 23);
+		break;
+	case LED_ORANGE :
+		on_pin  = ((1 << 23) | (1 << 22));
+		off_pin = 0;
+		break;
+	}
+
+	/* Set output Gpp[22] and Gpp[23]
+	 */
+	tmp = GTREGREAD(GPP_VALUE);
+	tmp |= on_pin;
+	tmp &= ~off_pin;
+	GT_REG_WRITE(GPP_VALUE, tmp);
+}
+
+int display_mem_map (void)
+{
+	int i;
+	unsigned int base, size, width;
+#ifdef CONFIG_PCI
+	int j;
+#endif
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0)
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+	}
+#ifdef CONFIG_PCI
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		/* ronen currently only first PCI MEM is used 3 */
+		for (j = 0; j <= PCI_REGION0; j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",
+				j, base, size >> 20);
+		}
+	}
+#endif /* of CONFIG_PCI */
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\t- FLASH\n",
+		base, size >> 20, width);
+
+	return (0);
+}
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CFG_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+	     : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CFG_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_DATA */
+
+#if defined (CFG_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CFG_MEMTEST_START;
+	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++)
+		pmem[i] = i;
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_ADDRESS */
+
+#if defined (CFG_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CFG_MEMTEST_START;
+	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata    = 0;
+	int runaddress = 0;
+	int runwalk    = 0;
+
+#ifdef CFG_DRAM_TEST_DATA
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+#endif
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  "
+			"(don't panic... that will take a moment !!!!)\n",
+			CFG_MEMTEST_START, CFG_MEMTEST_END);
+#ifdef CFG_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
+		printf ("passed\n");
+	return 0;
+
+}
+#endif /* CFG_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function           */
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.                                            */
+/*  - we diable and invalidate the icache and dcache.                   */
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
diff --git a/board/prodrive/p3mx/p3mx.h b/board/prodrive/p3mx/p3mx.h
new file mode 100644
index 0000000..1caae6b
--- /dev/null
+++ b/board/prodrive/p3mx/p3mx.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2005
+ *
+ * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. roel.loeffen@prodrive.nl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __P3MX_H__
+#define __P3MX_H__
+
+#define LED_OFF		1
+#define LED_GREEN	2
+#define LED_RED		3
+#define LED_ORANGE	4
+
+#endif /* __P3MX_H__ */
diff --git a/board/prodrive/p3mx/pci.c b/board/prodrive/p3mx/pci.c
new file mode 100644
index 0000000..137739b
--- /dev/null
+++ b/board/prodrive/p3mx/pci.c
@@ -0,0 +1,1025 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+
+#ifdef CONFIG_PCI_PNP
+void pciauto_config_init(struct pci_controller *hose);
+int  pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
+#endif
+
+#include "../../Marvell/include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+#ifdef CONFIG_USE_CPCIDVI
+typedef struct {
+	unsigned int base;
+	unsigned int init;
+} GT_CPCIDVI_ROM_T;
+
+static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
+#endif
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*		    - Make sure the GT is configured as a master before writing
+*		      to another device on the PCI.
+*		    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*		   (or any other PCI device spec)
+*	    pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*		    - Make sure the GT is configured as a master before reading
+*		      from another device on the PCI.
+*		    - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*			spec)
+*	    pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*		  cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*				the agent is placed on another Bus. For more
+*				information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*	    GT spec (or any other PCI device spec).
+*	    unsigned int pciDevNum - The device number needs to be addressed.
+*	    unsigned int busNum - On which bus does the Target agent connect
+*				  to.
+*	    unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*				the agent target locate on another PCI bus.
+*			      - Make sure the GT is configured as a master
+*				before reading from another device on the PCI.
+*			      - The function takes care of Big/Little endian
+*				conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*			 spec). (configuration register offset.)
+*	    pciDevNum: The device number needs to be addressed.
+*	    busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*		  cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*	31 30	 24 23	16 15  11 10	 8 7	  2  0	   <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|	   |Number|Number| Number | Number |  |	   <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*	    - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*			  feature bits given as an input.
+*			- Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*	  unsigned int features - See file: pci.h there are defintion for those
+*				  region features.
+*	  unsigned int baseAddress - The region base Address.
+*	  unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*			    to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*	    PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*	    PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*	    PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*	    PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*	    PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*	    PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*		       disable the park on last mechanism for each agent.
+*		       disabling this option for all agents results parking
+*		       on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*	  PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*	  PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*	  PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*	  PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*	  PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*	  PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*			respond to grant assertion within a window specified in
+*			the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*			grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*			    Detection mechanism.
+*			    NOTE: This operation may cause a dead lock on the
+*			    pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*		  For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*				       Boundry.
+*	   unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*				       Boundry.
+*	   unsigned int busNum - The CPI bus number to which the PCI interface
+*				       is connected.
+*	   unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*			   supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*	  snoopType - There is four optional Types:
+*			 1. No Snoop.
+*			 2. Snoop to WT region.
+*			 3. Snoop to WB region.
+*			 4. Snoop & Invalidate to WB region.
+*	  baseAddress - Base Address of this region.
+*	  regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+					     0x0);
+		pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+					    &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					     bar_value);
+	}
+}
+
+#ifdef CONFIG_USE_CPCIDVI
+static void gt_setup_cpcidvi (struct pci_controller *hose,
+			      pci_dev_t dev, struct pci_config_table *entry)
+{
+	u32		  bar_value, pci_response;
+
+	pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
+	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
+	pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
+	pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
+	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
+	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
+	pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
+	pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
+	gt_cpcidvi_rom.base = bar_value & 0xffffff00;
+	gt_cpcidvi_rom.init = 1;
+}
+
+unsigned char gt_cpcidvi_in8(unsigned int offset)
+{
+	unsigned char	  data;
+
+	if (gt_cpcidvi_rom.init == 0) {
+		return(0);
+		}
+	data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
+	return(data);
+}
+
+void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
+{
+	unsigned int	  off;
+
+	if (gt_cpcidvi_rom.init == 0) {
+		return;
+	}
+	off = data;
+	off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
+	in8(off);
+	return;
+}
+#endif
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260	*/
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+#ifdef CONFIG_USE_CPCIDVI
+	{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
+#endif
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+#ifdef CONFIG_PCI_PNP
+	unsigned int bar;
+#endif
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+#ifdef CONFIG_USE_CPCIDVI
+	gt_cpcidvi_rom.init = 0;
+	gt_cpcidvi_rom.base = 0;
+#endif
+
+	pci0_hose.config_table = gt_config_table;
+	pci1_hose.config_table = gt_config_table;
+
+#ifdef CONFIG_USE_CPCIDVI
+	gt_config_table[0].config_device =  gt_setup_cpcidvi;
+#endif
+	gt_config_table[1].config_device =  gt_setup_ide;
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CFG_PCI0_IO_SPACE_PCI,
+			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+#ifdef CONFIG_PCI_PNP
+	pciauto_config_init(&pci0_hose);
+	pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
+#endif
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CFG_PCI1_IO_SPACE_PCI,
+			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+#ifdef CONFIG_PCI_PNP
+	pciauto_config_init(&pci1_hose);
+	pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
+#endif
+	pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}
+#endif /* of CONFIG_PCI */
diff --git a/board/prodrive/p3mx/ppc_error_no.h b/board/prodrive/p3mx/ppc_error_no.h
new file mode 100644
index 0000000..53687c8
--- /dev/null
+++ b/board/prodrive/p3mx/ppc_error_no.h
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
+ */
+#ifndef _MV_PPC_ERRNO_H
+#define _MV_PPC_ERRNO_H
+
+#define	EPERM		 1	/* Operation not permitted */
+#define	ENOENT		 2	/* No such file or directory */
+#define	ESRCH		 3	/* No such process */
+#define	EINTR		 4	/* Interrupted system call */
+#define	EIO		 5	/* I/O error */
+#define	ENXIO		 6	/* No such device or address */
+#define	E2BIG		 7	/* Arg list too long */
+#define	ENOEXEC		 8	/* Exec format error */
+#define	EBADF		 9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+#define	EDEADLOCK	58	/* File locking deadlock error */
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+/* Should never be seen by user programs */
+#define ERESTARTSYS	512
+#define ERESTARTNOINTR	513
+#define ERESTARTNOHAND	514	/* restart if no handler.. */
+#define ENOIOCTLCMD	515	/* No ioctl command */
+
+#define _LAST_ERRNO	515
+
+#endif
diff --git a/board/prodrive/p3mx/sdram_init.c b/board/prodrive/p3mx/sdram_init.c
new file mode 100644
index 0000000..0464860
--- /dev/null
+++ b/board/prodrive/p3mx/sdram_init.c
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * adaption for the Marvell DB64460 Board
+ * Ingo Assmus (ingo.assmus@keymile.com)
+ *************************************************************************/
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "../../Marvell/common/i2c.h"
+#include "64460.h"
+#include "mv_regs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef	DEBUG
+#define MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+int set_dfcdlInit (void);	/* setup delay line of Mv64460 */
+int mvDmaIsChannelActive (int);
+int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
+int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
+
+#define D_CACHE_FLUSH_LINE(addr, offset)				\
+	{								\
+		__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+	}
+
+int memory_map_bank (unsigned int bankNo,
+		     unsigned int bankBase, unsigned int bankLength)
+{
+#if defined (MAP_PCI) && defined (CONFIG_PCI)
+	PCI_HOST host;
+#endif
+
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf ("mapping bank %d at %08x - %08x\n",
+			bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf ("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank (bankNo, bankBase, bankLength);
+
+#if defined (MAP_PCI) && defined (CONFIG_PCI)
+	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+		const int features =
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 | PCI_NO_SWAP;
+
+		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+				       bankLength);
+
+		pciSetRegionFeatures (host, bankNo, features, bankBase,
+				      bankLength);
+	}
+#endif
+
+	return 0;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+long int dram_size (long int *base, long int maxsize)
+{
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */
+
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */
+
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */
+		val = *addr;	/* read *addr */
+
+		*addr = save1;
+		*b = save2;
+
+		if (val != cnt) {
+			DP (printf
+			    ("Found %08x  at Address %08x (failure)\n",
+			     (unsigned int) val, (unsigned int) addr));
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+
+	return maxsize;
+}
+
+#define SDRAM_NORMAL			0x0
+#define SDRAM_PRECHARGE_ALL		0x1
+#define SDRAM_REFRESH_ALL		0x2
+#define SDRAM_MODE_REG_SETUP		0x3
+#define SDRAM_XTEN_MODE_REG_SETUP	0x4
+#define SDRAM_NOP			0x5
+#define SDRAM_SELF_REFRESH		0x7
+
+long int initdram (int board_type)
+{
+	int tmp;
+	int start;
+	ulong size;
+	ulong memSpaceAttr;
+	ulong dest;
+
+	/* first disable all banks */
+	memory_map_bank(0, 0, 0);
+	memory_map_bank(1, 0, 0);
+	memory_map_bank(2, 0, 0);
+	memory_map_bank(3, 0, 0);
+
+	/* calibrate delay lines */
+	set_dfcdlInit();
+
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_NOP);		/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* SDRAM controller configuration */
+#ifdef CONFIG_MV64460_ECC
+	GT_REG_WRITE(MV64460_SDRAM_CONFIG,		0x58201400);	/* 0x1400 */
+#else
+	GT_REG_WRITE(MV64460_SDRAM_CONFIG,		0x58200400);	/* 0x1400 */
+#endif
+	GT_REG_WRITE(MV64460_D_UNIT_CONTROL_LOW,	0xC3000540);	/* 0x1404  */
+	GT_REG_WRITE(MV64460_D_UNIT_CONTROL_HIGH,	0x0300F777);	/* 0x1424 */
+	GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_LOW,	0x01712220);	/* 0x1408 */
+	GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_HIGH, 0x0000005D);	/* 0x140C */
+	GT_REG_WRITE(MV64460_SDRAM_ADDR_CONTROL,	0x00000012);	/* 0x1410 */
+	GT_REG_WRITE(MV64460_SDRAM_OPEN_PAGES_CONTROL,	0x00000001);	/* 0x1414 */
+
+	/* SDRAM drive strength */
+	GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000000); /* 0x14C0 */
+	GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000008); /* 0x14C0 */
+	GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000000);	    /* 0x14C4 */
+	GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000008);	    /* 0x14C4 */
+
+	/* setup SDRAM device registers */
+
+	/* precharge all */
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL);	/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* enable DLL */
+	GT_REG_WRITE(MV64460_EXTENDED_DRAM_MODE, 0x00000000);			/* 0x1420 */
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_XTEN_MODE_REG_SETUP);	/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* reset DLL */
+	GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000132);	/* 0x141C */
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP);	/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* precharge all */
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL);	/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* wait for 2 auto refresh commands */
+	udelay(20);
+
+	/* un-reset DLL */
+	GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000032);	/* 0x141C */
+	GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP);	/* 0x1418 */
+	do {
+		tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
+	} while(tmp != 0x0);
+
+	/* wait 200 cycles */
+	udelay(2);  /* FIXME  make this dynamic for the system clock */
+
+	/* SDRAM init done */
+	memory_map_bank(0, CFG_SDRAM_BASE,  (256 << 20));
+#ifdef CFG_SDRAM1_BASE
+	memory_map_bank(1, CFG_SDRAM1_BASE, (256 << 20));
+#endif
+
+	/* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4
+	 */
+	tmp = GTREGREAD(MV64460_D_UNIT_MMASK);				/* 0x14B0 */
+	GT_REG_WRITE(MV64460_D_UNIT_MMASK, tmp | 0x2);
+
+	start = (0 << 20);
+#ifdef CONFIG_P3M750
+	size = (512 << 20);
+#elif defined (CONFIG_P3M7448)
+	size = (128 << 20);
+#endif
+
+#ifdef CONFIG_MV64460_ECC
+	memSpaceAttr = ((~(BIT0 << 0)) & 0xf) << 8;
+	mvDmaSetMemorySpace (0, 0, memSpaceAttr, start, size);
+	for (dest = start; dest < start + size; dest += _8M) {
+		mvDmaTransfer (0, start, dest, _8M,
+			       BIT8 /*DMA_DTL_128BYTES */  |
+			       BIT3 /*DMA_HOLD_SOURCE_ADDR */ |
+			       BIT11 /*DMA_BLOCK_TRANSFER_MODE */ );
+		while (mvDmaIsChannelActive (0));
+	}
+#endif
+
+	return (size);
+}
+
+void board_add_ram_info(int use_default)
+{
+	u32 val;
+
+	puts(" (CL=");
+	switch ((GTREGREAD(MV64460_SDRAM_MODE) >> 4) & 0x7) {
+	case 0x2:
+		puts("2");
+		break;
+	case 0x3:
+		puts("3");
+		break;
+	case 0x5:
+		puts("1.5");
+		break;
+	case 0x6:
+		puts("2.5");
+		break;
+	}
+
+	val = GTREGREAD(MV64460_SDRAM_CONFIG);
+
+	puts(", ECC ");
+	if (val & 0x00001000)
+		puts("enabled)");
+	else
+		puts("not enabled)");
+}
+
+/*
+ * mvDmaIsChannelActive - Check if IDMA channel is active
+ *
+ * channel	= IDMA channel number from 0 to 7
+ */
+int mvDmaIsChannelActive (int channel)
+{
+	ulong data;
+
+	data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * channel);
+	if (data & BIT14)	/* activity status */
+		return 1;
+
+	return 0;
+}
+
+/*
+ * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
+ *			 map.
+ *
+ * memSpace	= IDMA memory window number from 0 to 7
+ * trg_if	= Target interface:
+ *		  0x0 DRAM
+ *		  0x1 Device Bus
+ *		  0x2 Integrated SDRAM (or CPU bus 60x only)
+ *		  0x3 PCI0
+ *		  0x4 PCI1
+ * attr		= IDMA attributes (see MV datasheet)
+ * base_addr	= Sets up memory window for transfers
+ *
+ */
+int mvDmaSetMemorySpace (ulong memSpace,
+			 ulong trg_if,
+			 ulong attr, ulong base_addr, ulong size)
+{
+	ulong temp;
+
+	/* The base address must be aligned to the size.  */
+	if (base_addr % size != 0)
+		return 0;
+
+	if (size >= 0x10000) {	 /* 64K */
+		size &= 0xffff0000;
+		base_addr = (base_addr & 0xffff0000);
+		/* Set the new attributes */
+		GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
+			      (base_addr | trg_if | attr));
+		GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
+		GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
+			      (temp & ~(BIT0 << memSpace)));
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * mvDmaTransfer - Transfer data from src_addr to dst_addr on one of the 4
+ *		   DMA channels.
+ *
+ * channel	= IDMA channel number from 0 to 3
+ * destAddr	= Destination address
+ * sourceAddr	= Source address
+ * size		= Size in bytes
+ * command	= See MV datasheet
+ *
+ */
+int mvDmaTransfer (int channel, ulong sourceAddr,
+		   ulong destAddr, ulong size, ulong command)
+{
+	ulong engOffReg = 0;	/* Engine Offset Register */
+
+	if (size > 0xffff)
+		command = command | BIT31;	/* DMA_16M_DESCRIPTOR_MODE */
+	command = command | ((command >> 6) & 0x7);
+	engOffReg = channel * 4;
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, size);
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, sourceAddr);
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, destAddr);
+	command = command |
+		BIT12	|			/* DMA_CHANNEL_ENABLE */
+		BIT9;				/* DMA_NON_CHAIN_MODE */
+	/* Activate DMA channel By writting to mvDmaControlRegister */
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
+	return 1;
+}
+
+/****************************************************************************************
+ *			       SDRAM INIT						*
+ *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
+ *		 This procedure fits only the Atlantis					*
+ *											*
+ ***************************************************************************************/
+
+/****************************************************************************************
+ *			       DFCDL initialize MV643xx Design Considerations		*
+ *											*
+ ***************************************************************************************/
+int set_dfcdlInit (void)
+{
+	int i;
+
+	/* Values from MV64460 User Manual */
+	unsigned int dfcdl_tbl[] = { 0x00000000, 0x00000001, 0x00000042, 0x00000083,
+				     0x000000c4, 0x00000105, 0x00000146, 0x00000187,
+				     0x000001c8, 0x00000209, 0x0000024a, 0x0000028b,
+				     0x000002cc, 0x0000030d, 0x0000034e, 0x0000038f,
+				     0x000003d0, 0x00000411, 0x00000452, 0x00000493,
+				     0x000004d4, 0x00000515, 0x00000556, 0x00000597,
+				     0x000005d8, 0x00000619, 0x0000065a, 0x0000069b,
+				     0x000006dc, 0x0000071d, 0x0000075e, 0x0000079f,
+				     0x000007e0, 0x00000821, 0x00000862, 0x000008a3,
+				     0x000008e4, 0x00000925, 0x00000966, 0x000009a7,
+				     0x000009e8, 0x00000a29, 0x00000a6a, 0x00000aab,
+				     0x00000aec, 0x00000b2d, 0x00000b6e, 0x00000baf,
+				     0x00000bf0, 0x00000c31, 0x00000c72, 0x00000cb3,
+				     0x00000cf4, 0x00000d35, 0x00000d76, 0x00000db7,
+				     0x00000df8, 0x00000e39, 0x00000e7a, 0x00000ebb,
+				     0x00000efc, 0x00000f3d, 0x00000f7e, 0x00000fbf };
+
+	for (i = 0; i < 64; i++)
+		GT_REG_WRITE (SRAM_DATA0, dfcdl_tbl[i]);
+	GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);	/* enable dynamic delay line updating */
+
+	return (0);
+}
diff --git a/board/prodrive/p3mx/serial.c b/board/prodrive/p3mx/serial.c
new file mode 100644
index 0000000..ba32ac1
--- /dev/null
+++ b/board/prodrive/p3mx/serial.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * modified for cpci750 board by
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * serial.c - serial support for esd cpci750 board
+ */
+
+/* supports the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include "../../Marvell/include/memory.h"
+#include "serial.h"
+
+#include "mpsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int serial_init (void)
+{
+	mpsc_init (gd->baudrate);
+
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		mpsc_putchar ('\r');
+
+	mpsc_putchar (c);
+}
+
+int serial_getc (void)
+{
+	return mpsc_getchar ();
+}
+
+int serial_tstc (void)
+{
+	return mpsc_test_char ();
+}
+
+void serial_setbrg (void)
+{
+	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif /* CFG_CMD_KGDB */
diff --git a/board/prodrive/p3mx/serial.h b/board/prodrive/p3mx/serial.h
new file mode 100644
index 0000000..c7fc8c1
--- /dev/null
+++ b/board/prodrive/p3mx/serial.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* serial.h - mostly useful for DUART serial_init in serial.c */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#if 0
+
+#define B230400         1
+#define B115200         2
+#define B57600          4
+#define B38400          82
+#define B19200          163
+#define B9600           24
+#define B4800           651
+#define B2400           1302
+#define B1200           2604
+#define B600            5208
+#define B300            10417
+#define B150            20833
+#define B110            28409
+#define BDEFAULT        B115200
+
+				/* this stuff is important to initialize
+				the DUART channels */
+
+#define	Scale		0x01L		/* distance between port addresses */
+#define	COM1		0x000003f8		/* Keyboard */
+#define COM2		0x000002f8		/* Host */
+
+
+/* Port Definitions relative to base COM port addresses */
+#define DataIn	(0x00*Scale)	/* data input port */
+#define DataOut	(0x00*Scale)	/* data output port */
+#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
+#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
+#define	Ier	(0x01*Scale)	/* interrupt enable register */
+#define	Iir	(0x02*Scale)	/* interrupt identification register */
+#define	Lcr	(0x03*Scale)	/* line control register */
+#define	Mcr	(0x04*Scale)	/* modem control register */
+#define	Lsr	(0x05*Scale)	/* line status register */
+#define	Msr	(0x06*Scale)	/* modem status register */
+
+/* Bit Definitions for above ports */
+#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
+#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
+
+#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
+#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
+#define	McrDflt	(McrRts|McrDtr)
+
+#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
+			/* b6: transmitter empty */
+#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
+
+#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
+#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
+#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
+
+#define IerRda	0xf	/* b0: Enable received data available interrupt */
+
+#endif
+
+#endif /* __SERIAL_H__ */
diff --git a/board/prodrive/p3mx/u-boot.lds b/board/prodrive/p3mx/u-boot.lds
new file mode 100644
index 0000000..d89eb6c
--- /dev/null
+++ b/board/prodrive/p3mx/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c
index d0e5fe7..518ea9c 100644
--- a/board/prodrive/pdnb3/flash.c
+++ b/board/prodrive/pdnb3/flash.c
@@ -24,6 +24,8 @@
 #include <common.h>
 #include <asm/arch/ixp425.h>
 
+#if !defined(CFG_FLASH_CFI_DRIVER)
+
 /*
  * include common flash code (for esd boards)
  */
@@ -83,3 +85,5 @@ unsigned long flash_init(void)
 
 	return size;
 }
+
+#endif /* CFG_FLASH_CFI_DRIVER */
diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c
index 1931d64..92f9c01 100644
--- a/board/prodrive/pdnb3/nand.c
+++ b/board/prodrive/pdnb3/nand.c
@@ -148,7 +148,7 @@ static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
 	return 1;
 }
 
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE;
 
@@ -167,5 +167,6 @@ void board_nand_init(struct nand_chip *nand)
 	nand->read_buf   = pdnb3_nand_read_buf;
 	nand->verify_buf = pdnb3_nand_verify_buf;
 	nand->dev_ready  = pdnb3_nand_dev_ready;
+	return 0;
 }
 #endif
diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c
index 859dd7a..1e3dffb 100644
--- a/board/sandburst/common/ppc440gx_i2c.c
+++ b/board/sandburst/common/ppc440gx_i2c.c
@@ -27,13 +27,8 @@
  */
 #include <common.h>
 #include <ppc4xx.h>
-#if defined(CONFIG_440)
-#   include <440_i2c.h>
-#else
-#   include <405gp_i2c.h>
-#endif
+#include <4xx_i2c.h>
 #include <i2c.h>
-#include <440_i2c.h>
 #include <command.h>
 #include "ppc440gx_i2c.h"
 
diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h
index cd4fc86..10000f5 100644
--- a/board/sandburst/common/ppc440gx_i2c.h
+++ b/board/sandburst/common/ppc440gx_i2c.h
@@ -27,11 +27,7 @@
  */
 #include <common.h>
 #include <ppc4xx.h>
-#if defined(CONFIG_440)
-#   include <440_i2c.h>
-#else
-#   include <405gp_i2c.h>
-#endif
+#include <4xx_i2c.h>
 #include <i2c.h>
 
 #ifdef CONFIG_HARD_I2C
diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile
new file mode 100644
index 0000000..02cf569
--- /dev/null
+++ b/board/sbc8349/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (c) 2006 Wind River Systems, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o pci.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/sbc8349/config.mk b/board/sbc8349/config.mk
new file mode 100644
index 0000000..05fa5a0
--- /dev/null
+++ b/board/sbc8349/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2006 Wind River Systems, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# SBC8349E
+#
+
+TEXT_BASE  =   0xFFF00000
diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c
new file mode 100644
index 0000000..eadf230
--- /dev/null
+++ b/board/sbc8349/pci.c
@@ -0,0 +1,348 @@
+/*
+ * pci.c -- WindRiver SBC8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <common.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_PCI
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8349emds_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+		}
+	},
+	{}
+};
+#endif
+
+static struct pci_controller pci_hose[] = {
+       {
+#ifndef CONFIG_PCI_PNP
+       config_table:pci_mpc8349emds_config_table,
+#endif
+       },
+       {
+#ifndef CONFIG_PCI_PNP
+       config_table:pci_mpc8349emds_config_table,
+#endif
+       }
+};
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *	immr;
+	volatile clk83xx_t *	clk;
+	volatile law83xx_t *	pci_law;
+	volatile pot83xx_t *	pci_pot;
+	volatile pcictrl83xx_t *	pci_ctrl;
+	volatile pciconf83xx_t *	pci_conf;
+	u16 reg16;
+	u32 reg32;
+	u32 dev;
+	struct	pci_controller * hose;
+
+	immr = (immap_t *)CFG_IMMR;
+	clk = (clk83xx_t *)&immr->clk;
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = immr->pci_ctrl;
+	pci_conf = immr->pci_conf;
+
+	hose = &pci_hose[0];
+
+	/*
+	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
+	 */
+
+	reg32 = clk->occr;
+	udelay(2000);
+	clk->occr = 0xff000000;
+	udelay(2000);
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	pci_ctrl[0].gcr = 0;
+	udelay(2000);
+	pci_ctrl[0].gcr = 1;
+
+#ifdef CONFIG_MPC83XX_PCI2
+	pci_ctrl[1].gcr = 0;
+	udelay(2000);
+	pci_ctrl[1].gcr = 1;
+#endif
+
+	/* We need to wait at least a 1sec based on PCI specs */
+	{
+		int i;
+
+		for (i = 0; i < 1000; ++i)
+			udelay (1000);
+	}
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI1 mem space - prefetch */
+	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/* PCI1 IO space */
+	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+	/* PCI1 mmio - non-prefetch mem space */
+	pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI1_MEM_BASE,
+		       CFG_PCI1_MEM_PHYS,
+		       CFG_PCI1_MEM_SIZE,
+		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI1_MMIO_BASE,
+		       CFG_PCI1_MMIO_PHYS,
+		       CFG_PCI1_MMIO_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CFG_PCI1_IO_BASE,
+		       CFG_PCI1_IO_PHYS,
+		       CFG_PCI1_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 3,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	pci_setup_indirect(hose,
+			   (CFG_IMMR+0x8300),
+			   (CFG_IMMR+0x8304));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+
+#ifdef CONFIG_MPC83XX_PCI2
+	hose = &pci_hose[1];
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI2 mem space - prefetch */
+	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/* PCI2 IO space */
+	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
+
+	/* PCI2 mmio - non-prefetch mem space */
+	pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	pci_ctrl[1].pitar1 = 0x0;
+	pci_ctrl[1].pibar1 = 0x0;
+	pci_ctrl[1].piebar1 = 0x0;
+	pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+	hose->first_busno = pci_hose[0].last_busno + 1;
+	hose->last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI2_MEM_BASE,
+		       CFG_PCI2_MEM_PHYS,
+		       CFG_PCI2_MEM_SIZE,
+		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI2_MMIO_BASE,
+		       CFG_PCI2_MMIO_PHYS,
+		       CFG_PCI2_MMIO_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CFG_PCI2_IO_BASE,
+		       CFG_PCI2_IO_PHYS,
+		       CFG_PCI2_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 3,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	pci_setup_indirect(hose,
+			   (CFG_IMMR+0x8380),
+			   (CFG_IMMR+0x8384));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+#endif
+
+}
+
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+		u32 *p;
+		int len;
+
+		p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
+		if (p != NULL) {
+			p[0] = pci_hose[0].first_busno;
+			p[1] = pci_hose[0].last_busno;
+		}
+
+#ifdef CONFIG_MPC83XX_PCI2
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
+	if (p != NULL) {
+		p[0] = pci_hose[1].first_busno;
+		p[1] = pci_hose[1].last_busno;
+	}
+#endif
+}
+#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_PCI */
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
new file mode 100644
index 0000000..4cd447e
--- /dev/null
+++ b/board/sbc8349/sbc8349.c
@@ -0,0 +1,585 @@
+/*
+ * sbc8349.c -- WindRiver SBC8349 board support.
+ * Copyright (c) 2006-2007 Wind River Systems, Inc.
+ *
+ * Paul Gortmaker <paul.gortmaker@windriver.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <command.h>
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#endif
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
+int fixed_sdram(void);
+void sdram_init(void);
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f (void)
+{
+	return 0;
+}
+#endif
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	puts("Initializing\n");
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram();
+#else
+	msize = fixed_sdram();
+#endif
+	/*
+	 * Initialize SDRAM if it is on local bus.
+	 */
+	sdram_init();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+	puts("   DDR RAM: ");
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CFG_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1);
+	     ddr_size = ddr_size>>1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+#if (CFG_DDR_SIZE != 256)
+#warning Currently any ddr size other than 256 is not supported
+#endif
+	im->ddr.csbnds[2].csbnds = 0x0000000f;
+	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+
+	/* currently we use only one CS, so disable the other banks */
+	im->ddr.cs_config[0] = 0;
+	im->ddr.cs_config[1] = 0;
+	im->ddr.cs_config[3] = 0;
+
+	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+		| SDRAM_CFG_2T_EN
+#endif
+		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+#if defined (CONFIG_DDR_32BIT)
+	/* for 32-bit mode burst length is 8 */
+	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+	im->ddr.sdram_mode = CFG_DDR_MODE;
+
+	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+	return msize;
+}
+#endif/*!CFG_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+	puts("Board: Wind River SBC834x\n");
+	return 0;
+}
+
+/*
+ * if board is fitted with SDRAM
+ */
+#if defined(CFG_BR2_PRELIM)  \
+	&& defined(CFG_OR2_PRELIM) \
+	&& defined(CFG_LBLAWBAR2_PRELIM) \
+	&& defined(CFG_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile lbus83xx_t *lbc= &immap->lbus;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+	puts("\n   SDRAM on Local Bus: ");
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+	 */
+
+	/* setup mtrpt, lsrt and lbcr for LB bus */
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller Machine Mode Register.
+	 */
+	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+
+	lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+	asm("sync");
+	/*1 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*2 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*3 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*4 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*5 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*6 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*7 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*8 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x58636733; mode register write operation */
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+}
+#else
+void sdram_init(void)
+{
+	puts("   SDRAM on Local Bus: Disabled in config\n");
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
+/*
+ * ECC user commands
+ */
+void ecc_print_status(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
+
+	printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
+
+	/* Interrupts */
+	printf("Memory Error Interrupt Enable:\n");
+	printf("  Multiple-Bit Error Interrupt Enable: %d\n",
+			(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
+	printf("  Single-Bit Error Interrupt Enable: %d\n",
+			(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
+	printf("  Memory Select Error Interrupt Enable: %d\n\n",
+			(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
+
+	/* Error disable */
+	printf("Memory Error Disable:\n");
+	printf("  Multiple-Bit Error Disable: %d\n",
+			(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
+	printf("  Sinle-Bit Error Disable: %d\n",
+			(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
+	printf("  Memory Select Error Disable: %d\n\n",
+			(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
+
+	/* Error injection */
+	printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
+			ddr->data_err_inject_hi, ddr->data_err_inject_lo);
+
+	printf("Memory Data Path Error Injection Mask ECC:\n");
+	printf("  ECC Mirror Byte: %d\n",
+			(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
+	printf("  ECC Injection Enable: %d\n",
+			(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
+	printf("  ECC Error Injection Mask: 0x%02x\n\n",
+			ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
+
+	/* SBE counter/threshold */
+	printf("Memory Single-Bit Error Management (0..255):\n");
+	printf("  Single-Bit Error Threshold: %d\n",
+			(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
+	printf("  Single-Bit Error Counter: %d\n\n",
+			(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
+
+	/* Error detect */
+	printf("Memory Error Detect:\n");
+	printf("  Multiple Memory Errors: %d\n",
+			(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
+	printf("  Multiple-Bit Error: %d\n",
+			(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
+	printf("  Single-Bit Error: %d\n",
+			(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
+	printf("  Memory Select Error: %d\n\n",
+			(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
+
+	/* Capture data */
+	printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
+	printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
+			ddr->capture_data_hi, ddr->capture_data_lo);
+	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
+		ddr->capture_ecc & CAPTURE_ECC_ECE);
+
+	printf("Memory Error Attributes Capture:\n");
+	printf("  Data Beat Number: %d\n",
+			(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
+	printf("  Transaction Size: %d\n",
+			(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
+	printf("  Transaction Source: %d\n",
+			(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
+	printf("  Transaction Type: %d\n",
+			(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
+	printf("  Error Information Valid: %d\n\n",
+			ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
+}
+
+int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
+	volatile u32 val;
+	u64 *addr, count, val64;
+	register u64 *i;
+
+	if (argc > 4) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (argc == 2) {
+		if (strcmp(argv[1], "status") == 0) {
+			ecc_print_status();
+			return 0;
+		} else if (strcmp(argv[1], "captureclear") == 0) {
+			ddr->capture_address = 0;
+			ddr->capture_data_hi = 0;
+			ddr->capture_data_lo = 0;
+			ddr->capture_ecc = 0;
+			ddr->capture_attributes = 0;
+			return 0;
+		}
+	}
+
+	if (argc == 3) {
+		if (strcmp(argv[1], "sbecnt") == 0) {
+			val = simple_strtoul(argv[2], NULL, 10);
+			if (val > 255) {
+				printf("Incorrect Counter value, should be 0..255\n");
+				return 1;
+			}
+
+			val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
+			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
+
+			ddr->err_sbe = val;
+			return 0;
+		} else if (strcmp(argv[1], "sbethr") == 0) {
+			val = simple_strtoul(argv[2], NULL, 10);
+			if (val > 255) {
+				printf("Incorrect Counter value, should be 0..255\n");
+				return 1;
+			}
+
+			val = (val << ECC_ERROR_MAN_SBET_SHIFT);
+			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
+
+			ddr->err_sbe = val;
+			return 0;
+		} else if (strcmp(argv[1], "errdisable") == 0) {
+			val = ddr->err_disable;
+
+			if (strcmp(argv[2], "+sbe") == 0) {
+				val |= ECC_ERROR_DISABLE_SBED;
+			} else if (strcmp(argv[2], "+mbe") == 0) {
+				val |= ECC_ERROR_DISABLE_MBED;
+			} else if (strcmp(argv[2], "+mse") == 0) {
+				val |= ECC_ERROR_DISABLE_MSED;
+			} else if (strcmp(argv[2], "+all") == 0) {
+				val |= (ECC_ERROR_DISABLE_SBED |
+					ECC_ERROR_DISABLE_MBED |
+					ECC_ERROR_DISABLE_MSED);
+			} else if (strcmp(argv[2], "-sbe") == 0) {
+				val &= ~ECC_ERROR_DISABLE_SBED;
+			} else if (strcmp(argv[2], "-mbe") == 0) {
+				val &= ~ECC_ERROR_DISABLE_MBED;
+			} else if (strcmp(argv[2], "-mse") == 0) {
+				val &= ~ECC_ERROR_DISABLE_MSED;
+			} else if (strcmp(argv[2], "-all") == 0) {
+				val &= ~(ECC_ERROR_DISABLE_SBED |
+					ECC_ERROR_DISABLE_MBED |
+					ECC_ERROR_DISABLE_MSED);
+			} else {
+				printf("Incorrect err_disable field\n");
+				return 1;
+			}
+
+			ddr->err_disable = val;
+			__asm__ __volatile__ ("sync");
+			__asm__ __volatile__ ("isync");
+			return 0;
+		} else if (strcmp(argv[1], "errdetectclr") == 0) {
+			val = ddr->err_detect;
+
+			if (strcmp(argv[2], "mme") == 0) {
+				val |= ECC_ERROR_DETECT_MME;
+			} else if (strcmp(argv[2], "sbe") == 0) {
+				val |= ECC_ERROR_DETECT_SBE;
+			} else if (strcmp(argv[2], "mbe") == 0) {
+				val |= ECC_ERROR_DETECT_MBE;
+			} else if (strcmp(argv[2], "mse") == 0) {
+				val |= ECC_ERROR_DETECT_MSE;
+			} else if (strcmp(argv[2], "all") == 0) {
+				val |= (ECC_ERROR_DETECT_MME |
+					ECC_ERROR_DETECT_MBE |
+					ECC_ERROR_DETECT_SBE |
+					ECC_ERROR_DETECT_MSE);
+			} else {
+				printf("Incorrect err_detect field\n");
+				return 1;
+			}
+
+			ddr->err_detect = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectdatahi") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+
+			ddr->data_err_inject_hi = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectdatalo") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+
+			ddr->data_err_inject_lo = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectecc") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+			if (val > 0xff) {
+				printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
+				return 1;
+			}
+			val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
+
+			ddr->ecc_err_inject = val;
+			return 0;
+		} else if (strcmp(argv[1], "inject") == 0) {
+			val = ddr->ecc_err_inject;
+
+			if (strcmp(argv[2], "en") == 0)
+				val |= ECC_ERR_INJECT_EIEN;
+			else if (strcmp(argv[2], "dis") == 0)
+				val &= ~ECC_ERR_INJECT_EIEN;
+			else
+				printf("Incorrect command\n");
+
+			ddr->ecc_err_inject = val;
+			__asm__ __volatile__ ("sync");
+			__asm__ __volatile__ ("isync");
+			return 0;
+		} else if (strcmp(argv[1], "mirror") == 0) {
+			val = ddr->ecc_err_inject;
+
+			if (strcmp(argv[2], "en") == 0)
+				val |= ECC_ERR_INJECT_EMB;
+			else if (strcmp(argv[2], "dis") == 0)
+				val &= ~ECC_ERR_INJECT_EMB;
+			else
+				printf("Incorrect command\n");
+
+			ddr->ecc_err_inject = val;
+			return 0;
+		}
+	}
+
+	if (argc == 4) {
+		if (strcmp(argv[1], "test") == 0) {
+			addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
+			count = simple_strtoul(argv[3], NULL, 16);
+
+			if ((u32)addr % 8) {
+				printf("Address not alligned on double word boundary\n");
+				return 1;
+			}
+
+			disable_interrupts();
+			icache_disable();
+
+			for (i = addr; i < addr + count; i++) {
+				/* enable injects */
+				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__ ("sync");
+				__asm__ __volatile__ ("isync");
+
+				/* write memory location injecting errors */
+				*i = 0x1122334455667788ULL;
+				__asm__ __volatile__ ("sync");
+
+				/* disable injects */
+				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__ ("sync");
+				__asm__ __volatile__ ("isync");
+
+				/* read data, this generates ECC error */
+				val64 = *i;
+				__asm__ __volatile__ ("sync");
+
+				/* disable errors for ECC */
+				ddr->err_disable |= ~ECC_ERROR_ENABLE;
+				__asm__ __volatile__ ("sync");
+				__asm__ __volatile__ ("isync");
+
+				/* re-initialize memory, write the location again
+				 * NOT injecting errors this time */
+				*i = 0xcafecafecafecafeULL;
+				__asm__ __volatile__ ("sync");
+
+				/* enable errors for ECC */
+				ddr->err_disable &= ECC_ERROR_ENABLE;
+				__asm__ __volatile__ ("sync");
+				__asm__ __volatile__ ("isync");
+			}
+
+			icache_enable();
+			enable_interrupts();
+
+			return 0;
+		}
+	}
+
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	ecc,     4,     0,      do_ecc,
+	"ecc     - support for DDR ECC features\n",
+	"status              - print out status info\n"
+	"ecc captureclear        - clear capture regs data\n"
+	"ecc sbecnt <val>        - set Single-Bit Error counter\n"
+	"ecc sbethr <val>        - set Single-Bit Threshold\n"
+	"ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
+	"  [-|+]sbe - Single-Bit Error\n"
+	"  [-|+]mbe - Multiple-Bit Error\n"
+	"  [-|+]mse - Memory Select Error\n"
+	"  [-|+]all - all errors\n"
+	"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
+	"  mme - Multiple Memory Errors\n"
+	"  sbe - Single-Bit Error\n"
+	"  mbe - Multiple-Bit Error\n"
+	"  mse - Memory Select Error\n"
+	"  all - all errors\n"
+	"ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
+	"ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
+	"ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
+	"ecc inject <en|dis>    - enable/disable error injection\n"
+	"ecc mirror <en|dis>    - enable/disable mirror byte\n"
+	"ecc test <addr> <cnt>  - test mem region:\n"
+	"  - enables injects\n"
+	"  - writes pattern injecting errors\n"
+	"  - disables injects\n"
+	"  - reads pattern back, generates error\n"
+	"  - re-inits memory"
+);
+#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+	ft_cpu_setup(blob, bd);
+
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+}
+#endif
diff --git a/board/sbc8349/u-boot.lds b/board/sbc8349/u-boot.lds
new file mode 100644
index 0000000..e32c075
--- /dev/null
+++ b/board/sbc8349/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * u-boot.lds for WindRiver SBC8349.
+ *
+ * Based on the MPC8349 u-boot.lds
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc83xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/sc3/Makefile b/board/sc3/Makefile
new file mode 100644
index 0000000..4cc2b41
--- /dev/null
+++ b/board/sc3/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o sc3nand.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/sc3/config.mk b/board/sc3/config.mk
new file mode 100644
index 0000000..1bdf5e4
--- /dev/null
+++ b/board/sc3/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/sc3/init.S b/board/sc3/init.S
new file mode 100644
index 0000000..e7b3c83
--- /dev/null
+++ b/board/sc3/init.S
@@ -0,0 +1,382 @@
+/*------------------------------------------------------------------------------+
+ *
+ *	 This souce code has been made available to you by EuroDesign
+ *	 (www.eurodsn.de). It's based on the original IBM source code, so
+ *	 this follows:
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.  Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.  No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *------------------------------------------------------------------------------- */
+
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/**
+ * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
+ *
+ * IMPORTANT: For pass1 this code must run from cache since you can not
+ * reliably change a peripheral banks timing register (pbxap) while running
+ * code from that bank. For ex., since we are running from ROM on bank 0, we
+ * can NOT execute the code that modifies bank 0 timings from ROM, so
+ * we run it from cache.
+ *
+ * Bank 0 - Boot-Flash
+ * Bank 1 - NAND-Flash
+ * Bank 2 - ISA bus
+ * Bank 3 - Second Flash
+ * Bank 4 - USB controller
+ */
+	.globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+/*
+ * We need the current boot up configuration to set correct
+ * timings into internal flash and external flash
+ */
+		mfdcr r24,strap			/* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
+						   0 0 -> 8 bit external ROM
+						   0 1 -> 16 bit internal ROM */
+		addi r4,0,2
+		srw r24,r24,r4				/* shift right r24 two positions */
+		andi. r24,r24,0x06000
+/*
+ * All calculations are based on 33MHz EBC clock.
+ *
+ * First, create a "very slow" timing (~250ns) with burst mode enabled
+ * This is need for the external flash access
+ */
+		lis r25,0x0800
+		ori r25,r25,0x0280			/* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
+/*
+ * Second, create a fast timing:
+ * 90ns first cycle - 3 clock access
+ * and 90ns burst cycle, plus 1 clock after the last access
+ * This is used for the internal access
+ */
+		lis r26,0x8900
+		ori r26,r26,0x0280			/* 1000 1001 0xxx 0000 0000 0010 100x xxxx
+/*
+ * We can't change settings on CS# if we currently use them.
+ * -> load a few instructions into cache and run this code from cache
+ */
+		mflr r4					/* save link register */
+		bl ..getAddr
+..getAddr:
+		mflr r3					/* get address of ..getAddr */
+		mtlr r4					/* restore link register */
+		addi r4,0,14				/* set ctr to 10; used to prefetch */
+		mtctr r4				/* 10 cache lines to fit this function
+							in cache (gives us 8x10=80 instructions) */
+..ebcloop:
+		icbt r0,r3				/* prefetch cache line for addr in r3 */
+		addi r3,r3,32				/* move to next cache line */
+		bdnz ..ebcloop				/* continue for 10 cache lines */
+/*
+ * Delay to ensure all accesses to ROM are complete before changing
+ * bank 0 timings. 200usec should be enough.
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+ */
+		lis r3,0x0
+		ori r3,r3,0xA000			/* ensure 200usec have passed since reset */
+		mtctr r3
+..spinlp:
+		bdnz ..spinlp				/* spin loop */
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 0 (BOOT-ROM) initialization
+ * 0xFFEF00000....0xFFFFFFF
+ * We only have to change the timing. Mapping is ok by boot-strapping
+ *----------------------------------------------------------------------- */
+
+		li r4,pb0ap				/* PB0AP=Peripheral Bank 0 Access Parameters */
+		mtdcr ebccfga,r4
+
+		mr r4,r26				/* assume internal fast flash is boot flash */
+		cmpwi r24,0x2000			/* assumption true? ... */
+		beq 1f					/* ...yes! */
+		mr r4,r25				/* ...no, use the slow variant */
+		mr r25,r26				/* use this for the other flash */
+1:
+		mtdcr ebccfgd,r4			/* change timing now */
+
+		li r4,pb0cr				/* PB0CR=Peripheral Bank 0 Control Register */
+		mtdcr ebccfga,r4
+		mfdcr r4,ebccfgd
+		lis r3,0x0001
+		ori r3,r3,0x8000			/* allow reads and writes */
+		or r4,r4,r3
+		mtdcr ebccfgd,r4
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 3 (Second-Flash) initialization
+ * 0xF0000000...0xF01FFFFF -> 2MB
+ *----------------------------------------------------------------------- */
+
+		li r4,pb3ap				/* Peripheral Bank 1 Access Parameter */
+		mtdcr ebccfga,r4
+		mtdcr ebccfgd,r2			/* change timing */
+
+		li r4,pb3cr				/* Peripheral Bank 1 Configuration Registers */
+		mtdcr ebccfga,r4
+
+		lis r4,0xF003
+		ori r4,r4,0x8000
+/*
+ * Consider boot configuration
+ */
+		xori r24,r24,0x2000			/* invert current bus width */
+		or r4,r4,r24
+		mtdcr ebccfgd,r4
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 1 (NAND-Flash) initialization
+ * 0x77D00000...0x77DFFFFF -> 1MB
+ * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
+ * - the setup time is 0ns
+ * - the hold time is 15ns
+ * ->
+ *   - TWT = 0
+ *   - CSN = 0
+ *   - OEN = 0
+ *   - WBN = 0
+ *   - WBF = 0
+ *   - TH  = 1
+ * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
+ *----------------------------------------------------------------------- */
+
+		li r4,pb1ap				/* Peripheral Bank 1 Access Parameter */
+		mtdcr ebccfga,r4
+
+		lis r4,0x0000
+		ori r4,r4,0x0200
+		mtdcr ebccfgd,r4
+
+		li r4,pb1cr				/* Peripheral Bank 1 Configuration Registers */
+		mtdcr ebccfga,r4
+
+		lis r4,0x77D1
+		ori r4,r4,0x8000
+		mtdcr ebccfgd,r4
+
+
+/* USB init (without acceleration) */
+#ifndef CONFIG_ISP1161_PRESENT
+		li r4,pb4ap				/* PB4AP=Peripheral Bank 4 Access Parameters */
+		mtdcr ebccfga,r4
+		lis r4,0x0180
+		ori r4,r4,0x5940
+		mtdcr ebccfgd,r4
+#endif
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
+ * 0x78000000...0x7BFFFFFF -> 64 MB
+ * Wir arbeiten bei 33 MHz -> 30ns
+ *-----------------------------------------------------------------------
+
+ A7 (ppc notation) or A24 (standard notation) decides about
+ the type of access:
+ A7/A24=0 -> memory cycle
+ A7/ /A24=1 -> I/O cycle
+*/
+		li r4,pb2ap				/* PB2AP=Peripheral Bank 2 Access Parameters */
+		mtdcr ebccfga,r4
+/*
+ We emulate an ISA access
+
+ 1. Address active
+ 2. wait 0 EBC clocks -> CSN=0
+ 3. set CS#
+ 4. wait 0 EBC clock -> OEN/WBN=0
+ 5. set OE#/WE#
+ 6. wait 4 clocks (ca. 90ns) and for Ready signal
+ 7. hold for 4 clocks -> TH=4
+*/
+
+#if 1
+/* faster access to isa-bus */
+		lis r4,0x0180
+		ori r4,r4,0x5940
+#else
+		lis r4,0x0100
+		ori r4,r4,0x0340
+#endif
+		mtdcr ebccfgd,r4
+
+#ifdef IDE_USES_ISA_EMULATION
+		li r25,pb5ap				/* PB5AP=Peripheral Bank 5 Access Parameters */
+		mtdcr ebccfga,r25
+		mtdcr ebccfgd,r4
+#endif
+
+		li r25,pb6ap				/* PB6AP=Peripheral Bank 6 Access Parameters */
+		mtdcr ebccfga,r25
+		mtdcr ebccfgd,r4
+		li r25,pb7ap				/* PB7AP=Peripheral Bank 7 Access Parameters */
+		mtdcr ebccfga,r25
+		mtdcr ebccfgd,r4
+
+		li r25,pb2cr				/* PB2CR=Peripheral Bank 2 Configuration Register */
+		mtdcr ebccfga,r25
+
+		lis r4,0x780B
+		ori r4,r4,0xA000
+		mtdcr ebccfgd,r4
+/*
+ * the other areas are only 1MiB in size
+ */
+		lis r4,0x7401
+		ori r4,r4,0xA000
+
+		li r25,pb6cr				/* PB6CR=Peripheral Bank 6 Configuration Register */
+		mtdcr ebccfga,r25
+		lis r4,0x7401
+		ori r4,r4,0xA000
+		mtdcr ebccfgd,r4
+
+		li r25,pb7cr				/* PB7CR=Peripheral Bank 7 Configuration Register */
+		mtdcr ebccfga,r25
+		lis r4,0x7411
+		ori r4,r4,0xA000
+		mtdcr ebccfgd,r4
+
+#ifndef CONFIG_ISP1161_PRESENT
+		li r25,pb4cr				/* PB4CR=Peripheral Bank 4 Configuration Register */
+		mtdcr ebccfga,r25
+		lis r4,0x7421
+		ori r4,r4,0xA000
+		mtdcr ebccfgd,r4
+#endif
+#ifdef IDE_USES_ISA_EMULATION
+		li r25,pb5cr				/* PB5CR=Peripheral Bank 5 Configuration Register */
+		mtdcr ebccfga,r25
+		lis r4,0x0000
+		ori r4,r4,0x0000
+		mtdcr ebccfgd,r4
+#endif
+
+/*-----------------------------------------------------------------------
+ * Memory bank 4: USB controller Philips ISP6111
+ * 0x77C00000 ... 0x77CFFFFF
+ *
+ * The chip is connected to:
+ * - CPU CS#4
+ * - CPU IRQ#2
+ * - CPU DMA 3
+ *
+ * Timing:
+ * - command to first data: 300ns. Software must ensure this timing!
+ * - Write pulse: 26ns
+ * - Read pulse: 33ns
+ * - read cycle time: 150ns
+ * - write cycle time: 140ns
+ *
+ * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
+ *
+ *			  |- 300ns --|
+ *		  |---- 420ns ---|---- 420ns ---| cycle
+ * CS ############:###____#######:###____#######
+ * OE ############:####___#######:####___#######
+ * WE ############:####__########:####__########
+ *
+ * ----> 2 clocks RD/WR pulses: 60ns
+ * ----> CSN: 3 clock, 90ns
+ * ----> OEN: 1 clocks (read cycle)
+ * ----> WBN: 1 clocks (write cycle)
+ * ----> WBE: 2 clocks
+ * ----> TH: 7 clock, 210ns
+ * ----> TWT: 7 clocks
+ *----------------------------------------------------------------------- */
+
+#ifdef CONFIG_ISP1161_PRESENT
+
+		li r4,pb4ap				/* PB4AP=Peripheral Bank 4 Access Parameters */
+		mtdcr ebccfga,r4
+
+		lis r4,0x030D
+		ori r4,r4,0x5E80
+		mtdcr ebccfgd,r4
+
+		li r4,pb4cr				/* PB2CR=Peripheral Bank 4 Configuration Register */
+		mtdcr ebccfga,r4
+
+		lis r4,0x77C1
+		ori r4,r4,0xA000
+		mtdcr ebccfgd,r4
+
+#endif
+
+#ifndef IDE_USES_ISA_EMULATION
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 5 used for IDE access
+ *
+ * Timings for IDE Interface
+ *
+ * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
+ *  70		165		30		PIO-Mode 0, [ns]
+ *   3		  6		 1		[Cycles] ----> AP=0x040C0200
+ *  50		125		20	   PIO-Mode 1, [ns]
+ *   2		  5		 1		[Cycles] ----> AP=0x03080200
+ *  30		100		15	   PIO-Mode 2, [ns]
+ *   1		  4		 1		[Cycles] ----> AP=0x02040200
+ *  30		 80		10	   PIO-Mode 3, [ns]
+ *   1		  3		 1		[Cycles] ----> AP=0x01840200
+ *  25		 70		10	   PIO-Mode 4, [ns]
+ *   1		  3		 1		[Cycles] ----> AP=0x01840200
+ *
+ *----------------------------------------------------------------------- */
+
+		li r4,pb5ap
+		mtdcr ebccfga,r4
+		lis r4,0x040C
+		ori r4,r4,0x0200
+		mtdcr ebccfgd,r4
+
+		li r4,pb5cr			/* PB2CR=Peripheral Bank 2 Configuration Register */
+		mtdcr ebccfga,r4
+
+		lis r4,0x7A01
+		ori r4,r4,0xA000
+		mtdcr ebccfgd,r4
+#endif
+/*
+ * External Peripheral Control Register
+ */
+		li r4,epcr
+		mtdcr ebccfga,r4
+
+		lis r4,0xB84E
+		ori r4,r4,0xF000
+		mtdcr ebccfgd,r4
+/*
+ * drive POST code
+ */
+		lis r4,0x7900
+		ori r4,r4,0x0080
+		li r3,0x0001
+		stb r3,0(r4)			/* 01 -> external bus controller is initialized */
+		nop				/* pass2 DCR errata #8 */
+		blr
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
new file mode 100644
index 0000000..363a77d
--- /dev/null
+++ b/board/sc3/sc3.c
@@ -0,0 +1,781 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
+ *
+ * (C) Copyright 2003
+ * Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
+ * Derived from walnut.c
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * $Log:$
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "sc3.h"
+#include <pci.h>
+#include <i2c.h>
+#include <malloc.h>
+
+#undef writel
+#undef writeb
+#define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+
+/* write only register to configure things in our CPLD */
+#define CPLD_CONTROL_1	0x79000102
+#define CPLD_VERSION	0x79000103
+
+#define	IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
+
+static struct pci_controller hose={0,};
+
+/************************************************************
+ * Standard definition
+ ************************************************************/
+
+/* CPC0_CR0        Function                                 ISA bus
+	-  GPIO0
+	-  GPIO1      -> Output: NAND-Command Latch Enable
+	-  GPIO2      -> Output: NAND Address Latch Enable
+	-  GPIO3      -> IRQ input                               ISA-IRQ #5 (through CPLD)
+	-  GPIO4      -> Output: NAND-Chip Enable
+	-  GPIO5      -> IRQ input                               ISA-IRQ#7 (through CPLD)
+	-  GPIO6      -> IRQ input                               ISA-IRQ#9 (through CPLD)
+	-  GPIO7      -> IRQ input                               ISA-IRQ#10 (through CPLD)
+	-  GPIO8      -> IRQ input                               ISA-IRQ#11 (through CPLD)
+	-  GPIO9      -> IRQ input                               ISA-IRQ#12 (through CPLD)
+	- GPIO10/CS1# -> CS1# NAND                               ISA-CS#0
+	- GPIO11/CS2# -> CS2# ISA emulation                      ISA-CS#1
+	- GPIO12/CS3# -> CS3# 2nd Flash-Bank                     ISA-CS#2 or ISA-CS#7
+	- GPIO13/CS4# -> CS4# USB HC or ISA emulation            ISA-CS#3
+	- GPIO14/CS5# -> CS5# Boosted IDE access                 ISA-CS#4
+	- GPIO15/CS6# -> CS6# ISA emulation                      ISA-CS#5
+	- GPIO16/CS7# -> CS7# ISA emulation                      ISA-CS#6
+	- GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line         ISA-IRQ#3
+	- GPIO18/IRQ1 -> IRQ input                               ISA-IRQ#14
+	- GPIO19/IRQ2 -> IRQ input or USB                        ISA-IRQ#4
+	- GPIO20/IRQ3 -> IRQ input                               PCI-IRQ#D
+	- GPIO21/IRQ4 -> IRQ input                               PCI-IRQ#C
+	- GPIO22/IRQ5 -> IRQ input                               PCI-IRQ#B
+	- GPIO23/IRQ6 -> IRQ input                               PCI-IRQ#A
+	- GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
+*/
+/*
+| CPLD register: io-space at offset 0x102 (write only)
+| 0
+| 1
+| 2 0=CS#4 USB CS#, 1=ISA or GP bus
+| 3
+| 4
+| 5
+| 6 1=enable faster IDE access
+| 7
+*/
+#define USB_CHIP_ENABLE 0x04
+#define IDE_BOOSTING 0x40
+
+/* --------------- USB stuff ------------------------------------- */
+#ifdef CONFIG_ISP1161_PRESENT
+/**
+ * initUsbHost- Initialize the Philips isp1161 HC part if present
+ * @cpldConfig: Pointer to value in write only CPLD register
+ *
+ * Initialize the USB host controller if present and fills the
+ * scratch register to inform the driver about used resources
+ */
+
+static void initUsbHost (unsigned char *cpldConfig)
+{
+	int i;
+	unsigned long usbBase;
+	/*
+	 * Read back where init.S has located the USB chip
+	 */
+	mtdcr (0x012, 0x04);
+	usbBase = mfdcr (0x013);
+	if (!(usbBase & 0x18000))	/* enabled? */
+		return;
+	usbBase &= 0xFFF00000;
+
+	/*
+	 * to test for the USB controller enable using of CS#4 and DMA 3 for USB access
+	 */
+	writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
+
+	/*
+	 * first check: is the controller assembled?
+	 */
+	hcWriteWord (usbBase, 0x5555, HcScratch);
+	if (hcReadWord (usbBase, HcScratch) == 0x5555) {
+		hcWriteWord (usbBase, 0xAAAA, HcScratch);
+		if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
+			if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
+				return;	/* this is not our controller */
+		/*
+		 * try a software reset. This needs up to 10 seconds (see datasheet)
+		 */
+			hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
+			for (i = 1000; i > 0; i--) {	/* loop up to 10 seconds */
+				udelay (10);
+				if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
+					break;
+			}
+
+			if (!i)
+				return;  /* the controller doesn't responding. Broken? */
+		/*
+		 * OK. USB controller is ready. Initialize it in such way the later driver
+		 * can us it (without any knowing about specific implementation)
+		 */
+			hcWriteDWord (usbBase, 0x00000000, HcControl);
+		/*
+		 * disable all interrupt sources. Because we
+		 * don't know where we come from (hard reset, cold start, soft reset...)
+		 */
+			hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
+		/*
+		 * our current setup hardware configuration
+		 * - every port power supply can switched indepently
+		 * - every port can signal overcurrent
+		 * - every port is "outside" and the devices are removeable
+		 */
+			hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
+			hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
+		/*
+		 * don't forget to switch off power supply of each port
+		 * The later running driver can reenable them to find and use
+		 * the (maybe) connected devices.
+		 *
+		 */
+			hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
+			hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
+			hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
+			hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
+			hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
+			hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
+		/*
+		 * controller is present and usable
+		 */
+			*cpldConfig |= USB_CHIP_ENABLE;
+		}
+	}
+}
+#endif
+
+#if defined(CONFIG_START_IDE)
+int board_start_ide(void)
+{
+	if (IS_CAMERON) {
+		puts ("no IDE on cameron board.\n");
+		return 0;
+	}
+	return 1;
+}
+#endif
+
+static int sc3_cameron_init (void)
+{
+	/* Set up the Memory Controller for the CAMERON version */
+	mtebc (pb4ap, 0x01805940);
+	mtebc (pb4cr, 0x7401a000);
+	mtebc (pb5ap, 0x01805940);
+	mtebc (pb5cr, 0x7401a000);
+	mtebc (pb6ap, 0x0);
+	mtebc (pb6cr, 0x0);
+	mtebc (pb7ap, 0x0);
+	mtebc (pb7cr, 0x0);
+	return 0;
+}
+
+void sc3_read_eeprom (void)
+{
+	uchar i2c_buffer[18];
+
+	i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
+	i2c_buffer[9] = 0;
+	setenv ("serial#", (char *)i2c_buffer);
+
+	/* read mac-address from eeprom */
+	i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
+	i2c_buffer[17] = 0;
+	i2c_buffer[16] = i2c_buffer[14];
+	i2c_buffer[15] = i2c_buffer[13];
+	i2c_buffer[14] = ':';
+	i2c_buffer[13] = i2c_buffer[12];
+	i2c_buffer[12] = i2c_buffer[11];
+	i2c_buffer[11] = ':';
+	i2c_buffer[8] = ':';
+	i2c_buffer[5] = ':';
+	i2c_buffer[2] = ':';
+	setenv ("ethaddr", (char *)i2c_buffer);
+}
+
+int board_early_init_f (void)
+{
+	/* write only register to configure things in our CPLD */
+	unsigned char cpldConfig_1=0x00;
+
+/*-------------------------------------------------------------------------+
+| Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
+|
+| Note: IRQ 0  UART 0, active high; level sensitive
+|       IRQ 1  UART 1, active high; level sensitive
+|       IRQ 2  IIC, active high; level sensitive
+|       IRQ 3  Ext. master, rising edge, edge sensitive
+|       IRQ 4  PCI, active high; level sensitive
+|       IRQ 5  DMA Channel 0, active high; level sensitive
+|       IRQ 6  DMA Channel 1, active high; level sensitive
+|       IRQ 7  DMA Channel 2, active high; level sensitive
+|       IRQ 8  DMA Channel 3, active high; level sensitive
+|       IRQ 9  Ethernet Wakeup, active high; level sensitive
+|       IRQ 10 MAL System Error (SERR), active high; level sensitive
+|       IRQ 11 MAL Tx End of Buffer, active high; level sensitive
+|       IRQ 12 MAL Rx End of Buffer, active high; level sensitive
+|       IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
+|       IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
+|       IRQ 15 Ethernet, active high; level sensitive
+|       IRQ 16 External PCI SERR, active high; level sensitive
+|       IRQ 17 ECC Correctable Error, active high; level sensitive
+|       IRQ 18 PCI Power Management, active high; level sensitive
+|
+|       IRQ 19 (EXT IRQ7 405GPr only)
+|       IRQ 20 (EXT IRQ8 405GPr only)
+|       IRQ 21 (EXT IRQ9 405GPr only)
+|       IRQ 22 (EXT IRQ10 405GPr only)
+|       IRQ 23 (EXT IRQ11 405GPr only)
+|       IRQ 24 (EXT IRQ12 405GPr only)
+|
+|       IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
+|       IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
+|       IRQ 27 (EXT IRQ 2) USB controller
+|       IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
+|       IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
+|       IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
+|       IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
+|
+| Direct Memory Access Controller Signal Polarities
+|       DRQ0 active high (like ISA)
+|       ACK0 active low (like ISA)
+|       EOT0 active high (like ISA)
+|       DRQ1 active high (like ISA)
+|       ACK1 active low (like ISA)
+|       EOT1 active high (like ISA)
+|       DRQ2 active high (like ISA)
+|       ACK2 active low (like ISA)
+|       EOT2 active high (like ISA)
+|       DRQ3 active high (like ISA)
+|       ACK3 active low (like ISA)
+|       EOT3 active high (like ISA)
+|
++-------------------------------------------------------------------------*/
+
+	writeb (cpldConfig_1, CPLD_CONTROL_1);	/* disable everything in CPLD */
+
+	mtdcr (uicsr, 0xFFFFFFFF);    /* clear all ints */
+	mtdcr (uicer, 0x00000000);    /* disable all ints */
+	mtdcr (uiccr, 0x00000000);    /* set all to be non-critical */
+
+	if (IS_CAMERON) {
+		sc3_cameron_init();
+		mtdcr (0x0B6, 0x18000000);
+		mtdcr (uicpr, 0xFFFFFFF0);
+		mtdcr (uictr, 0x10001030);
+	} else {
+		mtdcr (0x0B6, 0x0000000);
+		mtdcr (uicpr, 0xFFFFFFE0);
+		mtdcr (uictr, 0x10000020);
+	}
+	mtdcr (uicvcr, 0x00000001);   /* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);    /* clear all ints */
+
+	/* setup other implementation specific details */
+	mtdcr (ecr, 0x60606000);
+
+	mtdcr (cntrl1, 0x000042C0);
+
+	if (IS_CAMERON) {
+		mtdcr (cntrl0, 0x01380000);
+		/* Setup the GPIOs */
+		writel (0x08008000, 0xEF600700);	/* Output states */
+		writel (0x00000000, 0xEF600718);	/* Open Drain control */
+		writel (0x68098000, 0xEF600704);	/* Output control */
+	} else {
+		mtdcr (cntrl0,0x00080000);
+		/* Setup the GPIOs */
+		writel (0x08000000, 0xEF600700);	/* Output states */
+		writel (0x14000000, 0xEF600718);	/* Open Drain control */
+		writel (0x7C000000, 0xEF600704);	/* Output control */
+	}
+
+	/* Code decompression disabled */
+	mtdcr (kiar, kconf);
+	mtdcr (kidr, 0x2B);
+
+	/* CPC0_ER: enable sleep mode of (currently) unused components */
+	/* CPC0_FR: force unused components into sleep mode */
+	mtdcr (cpmer, 0x3F800000);
+	mtdcr (cpmfr, 0x14000000);
+
+	/* set PLB priority */
+	mtdcr (0x87, 0x08000000);
+
+	/* --------------- DMA stuff ------------------------------------- */
+	mtdcr (0x126, 0x49200000);
+
+#ifndef IDE_USES_ISA_EMULATION
+	cpldConfig_1 |= IDE_BOOSTING;	/* enable faster IDE */
+	/* cpldConfig |= 0x01; */	/* enable 8.33MHz output, if *not* present on your baseboard */
+	writeb (cpldConfig_1, CPLD_CONTROL_1);
+#endif
+
+#ifdef CONFIG_ISP1161_PRESENT
+	initUsbHost (&cpldConfig_1);
+	writeb (cpldConfig_1, CPLD_CONTROL_1);
+#endif
+	/* FIXME: for what must we do this */
+	*(unsigned long *)0x79000080 = 0x0001;
+	return(0);
+}
+
+int misc_init_r (void)
+{
+	char *s1;
+	int i, xilinx_val;
+	volatile char *xilinx_adr;
+	xilinx_adr = (char *)0x79000102;
+
+	*xilinx_adr = 0x00;
+
+/* customer settings ***************************************** */
+/*
+	s1 = getenv ("function");
+	if (s1) {
+		if (!strcmp (s1, "Rosho")) {
+			printf ("function 'Rosho' activated\n");
+			*xilinx_adr = 0x40;
+		}
+		else {
+			printf (">>>>>>>>>> function %s not recognized\n",s1);
+		}
+	}
+*/
+
+/* individual settings ***************************************** */
+	if ((s1 = getenv ("xilinx"))) {
+		i=0;
+		xilinx_val = 0;
+		while (i < 3 && s1[i]) {
+			if (s1[i] >= '0' && s1[i] <= '9')
+				xilinx_val = (xilinx_val << 4) + s1[i] - '0';
+			else
+				if (s1[i] >= 'A' && s1[i] <= 'F')
+					xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
+				else
+					if (s1[i] >= 'a' && s1[i] <= 'f')
+						xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
+					else {
+						xilinx_val = -1;
+						break;
+					}
+			i++;
+		}
+		if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
+			printf ("Xilinx: set to %s\n", s1);
+			*xilinx_adr = (unsigned char) xilinx_val;
+		} else
+			printf ("Xilinx: rejected value %s\n", s1);
+	}
+	return 0;
+}
+
+/* -------------------------------------------------------------------------
+ * printCSConfig
+ *
+ * Print some informations about chips select configurations
+ * Only used while debugging.
+ *
+ * Params:
+ * - No. of CS pin
+ * - AP of this CS
+ * - CR of this CS
+ *
+ * Returns
+ * nothing
+   ------------------------------------------------------------------------- */
+
+#ifdef SC3_DEBUGOUT
+static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
+{
+	const char *bsize[4] = {"8","16","32","?"};
+	const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
+	const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
+
+#define CYCLE 30  /* time of one clock (based on 33MHz) */
+
+	printf("\nCS#%d",reg);
+	if (!(cr & 0x00018000))
+		puts(" unused");
+	else {
+		if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
+			puts(" Address is not multiple of bank size!");
+
+		printf("\n -%s bit device",
+			bsize[(cr & 0x00006000) >> 13]);
+		printf(" at 0x%08lX", cr & 0xFFF00000U);
+		printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
+		printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
+   	   	if (ap & 0x80000000) {
+			printf("\n -Burst device (%luns/%luns)",
+				(((ap & 0x7C000000) >> 26) + 1) * CYCLE,
+				(((ap & 0x03800000) >> 23) + 1) * CYCLE);
+		} else {
+			printf("\n -Non burst device, active cycle %luns",
+				(((ap & 0x7F800000) >> 23) + 1) * CYCLE);
+			printf("\n -Address setup %luns",
+				((ap & 0xC0000) >> 18) * CYCLE);
+			printf("\n -CS active to RD %luns/WR %luns",
+				((ap & 0x30000) >> 16) * CYCLE,
+				((ap & 0xC000) >> 14) * CYCLE);
+			printf("\n -WR to CS inactive %luns",
+				((ap & 0x3000) >> 12) * CYCLE);
+			printf("\n -Hold after access %luns",
+				((ap & 0xE00) >> 9) * CYCLE);
+			printf("\n -Ready is %sabled",
+				ap & 0x100 ? "en" : "dis");
+		}
+	}
+}
+#endif
+
+#ifdef SC3_DEBUGOUT
+
+static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap,
+				pb5ap, pb6ap, pb7ap};
+static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr,
+				pb5cr, pb6cr, pb7cr};
+
+static int show_reg (int nr)
+{
+	unsigned long ul1, ul2;
+
+	mtdcr (ebccfga, ap[nr]);
+	ul1 = mfdcr (ebccfgd);
+	mtdcr (ebccfga, cr[nr]);
+	ul2 = mfdcr(ebccfgd);
+	printCSConfig(nr, ul1, ul2);
+	return 0;
+}
+#endif
+
+int checkboard (void)
+{
+#ifdef SC3_DEBUGOUT
+	unsigned long ul1;
+	int	i;
+
+	for (i = 0; i < 8; i++) {
+		show_reg (i);
+	}
+
+	mtdcr (ebccfga, epcr);
+	ul1 = mfdcr (ebccfgd);
+
+	puts ("\nGeneral configuration:\n");
+
+	if (ul1 & 0x80000000)
+		printf(" -External Bus is always driven\n");
+
+	if (ul1 & 0x400000)
+		printf(" -CS signals are always driven\n");
+
+	if (ul1 & 0x20000)
+		printf(" -PowerDown after %lu clocks\n",
+			(ul1 & 0x1F000) >> 7);
+
+	switch (ul1 & 0xC0000)
+	{
+	case 0xC0000:
+		printf(" -No external master present\n");
+		break;
+	case 0x00000:
+		printf(" -8 bit external master present\n");
+		break;
+	case 0x40000:
+		printf(" -16 bit external master present\n");
+		break;
+	case 0x80000:
+		printf(" -32 bit external master present\n");
+		break;
+	}
+
+	switch (ul1 & 0x300000)
+	{
+	case 0x300000:
+		printf(" -Prefetch: Illegal setting!\n");
+		break;
+	case 0x000000:
+		printf(" -1 doubleword prefetch\n");
+		break;
+	case 0x100000:
+		printf(" -2 doublewords prefetch\n");
+		break;
+	case 0x200000:
+		printf(" -4 doublewords prefetch\n");
+		break;
+	}
+	putc ('\n');
+#endif
+	printf("Board: SolidCard III %s %s version.\n",
+		(IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
+	return 0;
+}
+
+static int printSDRAMConfig(char reg, unsigned long cr)
+{
+	const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
+#ifdef SC3_DEBUGOUT
+	const char *basize[8]=
+		{"4", "8", "16", "32", "64", "128", "256", "Reserved"};
+
+	printf("SDRAM bank %d",reg);
+
+	if (!(cr & 0x01))
+		puts(" disabled\n");
+	else {
+		printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
+		printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
+	}
+#endif
+
+	if (cr & 0x01)
+		return(bisize[(cr & 0xE0000) >> 17]);
+
+	return 0;
+}
+
+#ifdef SC3_DEBUGOUT
+static unsigned int mbcf[] = {mem_mb0cf, mem_mb1cf, mem_mb2cf, mem_mb3cf};
+#endif
+
+long int initdram (int board_type)
+{
+	unsigned int mems=0;
+	unsigned long ul1;
+
+#ifdef SC3_DEBUGOUT
+	unsigned long ul2;
+	int	i;
+
+	puts("\nSDRAM configuration:\n");
+
+	mtdcr (memcfga, mem_mcopt1);
+	ul1 = mfdcr(memcfgd);
+
+	if (!(ul1 & 0x80000000)) {
+		puts(" Controller disabled\n");
+		return 0;
+	}
+	for (i = 0; i < 4; i++) {
+		mtdcr (memcfga, mbcf[i]);
+		ul1 = mfdcr (memcfgd);
+		mems += printSDRAMConfig (i, ul1);
+	}
+
+	mtdcr (memcfga, mem_sdtr1);
+	ul1 = mfdcr(memcfgd);
+
+	printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
+	printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
+	printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
+	printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
+	printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
+	printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
+	puts ("Misc:\n");
+	mtdcr (memcfga, mem_rtr);
+	ul1 = mfdcr(memcfgd);
+	printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
+
+	mtdcr(memcfga,mem_pmit);
+	ul2=mfdcr(memcfgd);
+
+	mtdcr(memcfga,mem_mcopt1);
+	ul1=mfdcr(memcfgd);
+
+	if (ul1 & 0x20000000)
+		printf(" -Power Down after: %luns\n",
+			((ul2 & 0xFFC00000) >> 22) * 7);
+	else
+		puts(" -Power Down disabled\n");
+
+	if (ul1 & 0x40000000)
+		printf(" -Self refresh feature active\n");
+	else
+		puts(" -Self refresh disabled\n");
+
+	if (ul1 & 0x10000000)
+		puts(" -ECC enabled\n");
+	else
+		puts(" -ECC disabled\n");
+
+	if (ul1 & 0x8000000)
+		puts(" -Using registered SDRAM\n");
+
+	if (!(ul1 & 0x6000000))
+		puts(" -Using 32 bit data width\n");
+	else
+		puts(" -Illegal data width!\n");
+
+	if (ul1 & 0x400000)
+		puts(" -ECC drivers inactive\n");
+	else
+		puts(" -ECC drivers active\n");
+
+	if (ul1 & 0x200000)
+		puts(" -Memory lines always active outputs\n");
+	else
+		puts(" -Memory lines only at write cycles active outputs\n");
+
+	mtdcr (memcfga, mem_status);
+	ul1 = mfdcr (memcfgd);
+	if (ul1 & 0x80000000)
+		puts(" -SDRAM Controller ready\n");
+	else
+		puts(" -SDRAM Controller not ready\n");
+
+	if (ul1 & 0x4000000)
+		puts(" -SDRAM in self refresh mode!\n");
+
+	return (mems * 1024 * 1024);
+#else
+	mtdcr (memcfga, mem_mb0cf);
+	ul1 = mfdcr (memcfgd);
+	mems = printSDRAMConfig (0, ul1);
+
+	mtdcr (memcfga, mem_mb1cf);
+	ul1 = mfdcr (memcfgd);
+	mems += printSDRAMConfig (1, ul1);
+
+	mtdcr (memcfga, mem_mb2cf);
+	ul1 = mfdcr(memcfgd);
+	mems += printSDRAMConfig (2, ul1);
+
+	mtdcr (memcfga, mem_mb3cf);
+	ul1 = mfdcr(memcfgd);
+	mems += printSDRAMConfig (3, ul1);
+
+	return (mems * 1024 * 1024);
+#endif
+}
+
+static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+/*-------------------------------------------------------------------------+
+ |             ,-.     ,-.        ,-.        ,-.        ,-.
+ |   INTD# ----|B|-----|P|-.    ,-|P|-.    ,-| |-.    ,-|G|
+ |             |R|     |C|  \  /  |C|  \  /  |E|  \  /  |r|
+ |   INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
+ |             |D|     |0|  \/    |0|  \/    |h|  \/    |f|
+ |   INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
+ |             |E|     |+| /\     |+| /\     |r| /\     |k|
+ |   INTA# ----| |-----| |-  `----| |-  `----| |-  `----| |
+ |             `-'     `-'        `-'        `-'        `-'
+ |   Slot      0       10         11         12         13
+ |   REQ#              0          1          2          *
+ |   GNT#              0          1          2          *
+ +-------------------------------------------------------------------------*/
+	unsigned char int_line = 0xff;
+
+	switch (PCI_DEV(dev)) {
+	case 10:
+		int_line = 31; /* INT A */
+		POST_OUT(0x42);
+		break;
+
+	case 11:
+		int_line = 30; /* INT B */
+		POST_OUT(0x43);
+		break;
+
+	case 12:
+		int_line = 29; /* INT C */
+		POST_OUT(0x44);
+		break;
+
+	case 13:
+		int_line = 28; /* INT D */
+		POST_OUT(0x45);
+		break;
+	}
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+extern void pci_405gp_init(struct pci_controller *hose);
+extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
+extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
+/*
+ * The following table is used when there is a special need to setup a PCI device.
+ * For every PCI device found in this table is called the given init function with given
+ * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
+ * parameters!
+ *
+*/
+static struct pci_config_table pci_solidcard3_config_table[] =
+{
+/* Host to PCI Bridge device (405GP) */
+	{
+		vendor: 0x1014,
+		device: 0x0156,
+		class: PCI_CLASS_BRIDGE_HOST,
+		bus: 0,
+		dev: 0,
+		func: 0,
+		config_device: pci_405gp_setup_bridge
+	},
+	{ }
+};
+
+/*-------------------------------------------------------------------------+
+ | pci_init_board (Called from pci_init() in drivers/pci.c)
+ |
+ | Init the PCI part of the SolidCard III
+ |
+ | Params:
+ * - Pointer to current PCI hose
+ * - Current Device
+ *
+ * Returns
+ * nothing
+ +-------------------------------------------------------------------------*/
+
+void pci_init_board(void)
+{
+	POST_OUT(0x41);
+/*
+ * we want the ptrs to RAM not flash (ie don't use init list)
+ */
+	hose.fixup_irq    = pci_solidcard3_fixup_irq;
+	hose.config_table = pci_solidcard3_config_table;
+	pci_405gp_init(&hose);
+}
diff --git a/board/sc3/sc3.h b/board/sc3/sc3.h
new file mode 100644
index 0000000..cf920f9
--- /dev/null
+++ b/board/sc3/sc3.h
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**
+ * hcWriteWord - write a 16 bit value into the USB controller
+ * @base: base address to access the chip registers
+ * @value: 16 bit value to write into register @offset
+ * @offset: register to write the @value into
+ *
+ */
+static void inline hcWriteWord (unsigned long base, unsigned int value,
+				unsigned int offset)
+{
+	out_le16 ((volatile u16*)(base + 2), offset | 0x80);
+	out_le16 ((volatile u16*)base, value);
+}
+
+/**
+ * hcWriteDWord - write a 32 bit value into the USB controller
+ * @base: base address to access the chip registers
+ * @value: 32 bit value to write into register @offset
+ * @offset: register to write the @value into
+ *
+ */
+
+static void inline hcWriteDWord (unsigned long base, unsigned long value,
+				unsigned int offset)
+{
+	out_le16 ((volatile u16*)(base + 2), offset | 0x80);
+	out_le16 ((volatile u16*)base, value);
+	out_le16 ((volatile u16*)base, value >> 16);
+}
+
+/**
+ * hcReadWord - read a 16 bit value from the USB controller
+ * @base: base address to access the chip registers
+ * @offset: register to read from
+ *
+ * Returns the readed register value
+ */
+
+static unsigned int inline hcReadWord (unsigned long base, unsigned int offset)
+{
+	out_le16 ((volatile u16*)(base + 2), offset);
+	return (in_le16 ((volatile u16*)base));
+}
+
+/**
+ * hcReadDWord - read a 32 bit value from the USB controller
+ * @base: base address to access the chip registers
+ * @offset: register to read from
+ *
+ * Returns the readed register value
+ */
+
+static unsigned long inline hcReadDWord (unsigned long base, unsigned int offset)
+{
+	unsigned long val, val16;
+
+	out_le16 ((volatile u16*)(base + 2), offset);
+	val = in_le16((volatile u16*)base);
+	val16 = in_le16((volatile u16*)base);
+	return (val | (val16 << 16));
+}
+
+/* control and status registers isp1161 */
+#define HcRevision		0x00
+#define HcControl 		0x01
+#define HcCommandStatus		0x02
+#define HcInterruptStatus	0x03
+#define HcInterruptEnable	0x04
+#define HcInterruptDisable	0x05
+#define HcFmInterval		0x0D
+#define HcFmRemaining		0x0E
+#define HcFmNumber		0x0F
+#define HcLSThreshold		0x11
+#define HcRhDescriptorA		0x12
+#define HcRhDescriptorB		0x13
+#define HcRhStatus		0x14
+#define HcRhPortStatus1		0x15
+#define HcRhPortStatus2		0x16
+
+#define HcHardwareConfiguration 0x20
+#define HcDMAConfiguration	0x21
+#define HcTransferCounter	0x22
+#define HcuPInterrupt		0x24
+#define HcuPInterruptEnable	0x25
+#define HcChipID		0x27
+#define HcScratch		0x28
+#define HcSoftwareReset		0x29
+#define HcITLBufferLength	0x2A
+#define HcATLBufferLength	0x2B
+#define HcBufferStatus		0x2C
+#define HcReadBackITL0Length	0x2D
+#define HcReadBackITL1Length	0x2E
+#define HcITLBufferPort		0x40
+#define HcATLBufferPort		0x41
diff --git a/board/sc3/sc3nand.c b/board/sc3/sc3nand.c
new file mode 100644
index 0000000..7daa877
--- /dev/null
+++ b/board/sc3/sc3nand.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/processor.h>
+
+#define readb(addr)	*(volatile u_char *)(addr)
+#define readl(addr)	*(volatile u_long *)(addr)
+#define writeb(d,addr)	*(volatile u_char *)(addr) = (d)
+
+#define SC3_NAND_ALE 29 /* GPIO PIN 3 */
+#define SC3_NAND_CLE 30	/* GPIO PIN 2 */
+#define SC3_NAND_CE  27 /* GPIO PIN 5 */
+
+static void *sc3_io_base;
+static void *sc3_control_base = (void *)0xEF600700;
+
+static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		set_bit (SC3_NAND_CLE, sc3_control_base);
+		break;
+	case NAND_CTL_CLRCLE:
+		clear_bit (SC3_NAND_CLE, sc3_control_base);
+		break;
+
+	case NAND_CTL_SETALE:
+		set_bit (SC3_NAND_ALE, sc3_control_base);
+		break;
+	case NAND_CTL_CLRALE:
+		clear_bit (SC3_NAND_ALE, sc3_control_base);
+		break;
+
+	case NAND_CTL_SETNCE:
+		set_bit (SC3_NAND_CE, sc3_control_base);
+		break;
+	case NAND_CTL_CLRNCE:
+		clear_bit (SC3_NAND_CE, sc3_control_base);
+		break;
+	}
+}
+
+static int sc3_nand_dev_ready(struct mtd_info *mtd)
+{
+	if (!(readl(sc3_control_base + 0x1C) & 0x4000))
+		return 0;
+	return 1;
+}
+
+static void sc3_select_chip(struct mtd_info *mtd, int chip)
+{
+	clear_bit (SC3_NAND_CE, sc3_control_base);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->eccmode = NAND_ECC_SOFT;
+
+	sc3_io_base = (void *) CFG_NAND_BASE;
+	/* Set address of NAND IO lines (Using Linear Data Access Region) */
+	nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
+	nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
+	/* Reference hardware control function */
+	nand->hwcontrol  = sc3_nand_hwcontrol;
+	nand->dev_ready  = sc3_nand_dev_ready;
+	nand->select_chip = sc3_select_chip;
+	return 0;
+}
+#endif
diff --git a/board/sc3/u-boot.lds b/board/sc3/u-boot.lds
new file mode 100644
index 0000000..dc255d2
--- /dev/null
+++ b/board/sc3/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/sc3/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/spc1920/Makefile b/board/spc1920/Makefile
index 424ab1c..0c48c3a 100644
--- a/board/spc1920/Makefile
+++ b/board/spc1920/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o
+COBJS	= $(BOARD).o hpi.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c
new file mode 100644
index 0000000..3c36f79
--- /dev/null
+++ b/board/spc1920/hpi.c
@@ -0,0 +1,603 @@
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Host Port Interface (HPI)
+ */
+
+/* debug levels:
+ *  0 : errors
+ *  1 : usefull info
+ *  2 : lots of info
+ *  3 : noisy
+ */
+
+#define DEBUG 0
+
+#include <config.h>
+#include <common.h>
+#include <mpc8xx.h>
+
+#include "pld.h"
+#include "hpi.h"
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/* original table:
+ * - inserted loops to achieve long CS low and high Periods (~217ns)
+ * - move cs high 2/4 to the right
+ */
+const uint dsp_table_slow[] =
+{
+	/* single read   (offset  0x00 in upm ram) */
+	0x8fffdc04, 0x0fffdc84, 0x0fffdc84, 0x0fffdc00,
+	0x3fffdc04, 0xffffdc84, 0xffffdc84, 0xffffdc05,
+
+	/* burst read    (offset 0x08 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* single write  (offset 0x18 in upm ram) */
+	0x8fffd004, 0x0fffd084, 0x0fffd084, 0x3fffd000,
+	0xffffd084, 0xffffd084, 0xffffd005, _NOT_USED_,
+
+	/* burst write   (offset 0x20 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* refresh       (offset 0x30 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* exception     (offset 0x3C in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* dsp hpi upm ram table
+ * works fine for noninc access, failes on incremental.
+ * - removed first word
+ */
+const uint dsp_table_fast[] =
+{
+	/* single read   (offset  0x00 in upm ram) */
+	0x8fffdc04, 0x0fffdc04, 0x0fffdc00, 0x3fffdc04,
+	0xffffdc05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* burst read    (offset 0x08 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* single write  (offset 0x18 in upm ram) */
+	0x8fffd004, 0x0fffd004, 0x3fffd000, 0xffffd005,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* burst write   (offset 0x20 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* refresh       (offset 0x30 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* exception     (offset 0x3C in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+#ifdef CONFIG_SPC1920_HPI_TEST
+#undef HPI_TEST_OSZI
+
+#define HPI_TEST_CHUNKSIZE	0x1000
+#define HPI_TEST_PATTERN	0x00000000
+#define HPI_TEST_START		0x0
+#define HPI_TEST_END		0x30000
+
+#define TINY_AUTOINC_DATA_SIZE 16 /* 32bit words */
+#define TINY_AUTOINC_BASE_ADDR 0x0
+
+static int hpi_activate(void);
+static void hpi_inactivate(void);
+static void dsp_reset(void);
+
+static int hpi_write_inc(u32 addr, u32 *data, u32 count);
+static int hpi_read_inc(u32 addr, u32 *buf, u32 count);
+static int hpi_write_noinc(u32 addr, u32 data);
+static u32 hpi_read_noinc(u32 addr);
+
+int hpi_test(void);
+static int hpi_write_addr_test(u32 addr);
+static int hpi_read_write_test(u32 addr, u32 data);
+static int hpi_tiny_autoinc_test(void);
+#endif /* CONFIG_SPC1920_HPI_TEST */
+
+
+/* init the host port interface on UPMA */
+int hpi_init(void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
+
+	upmconfig(UPMA, (uint *)dsp_table_slow, sizeof(dsp_table_slow)/sizeof(uint));
+	udelay(100);
+
+	memctl->memc_mamr = CFG_MAMR;
+	memctl->memc_or3 = CFG_OR3;
+	memctl->memc_br3 = CFG_BR3;
+
+	/* reset dsp */
+	dsp_reset();
+
+	/* activate hpi switch*/
+	pld->dsp_hpi_on = 0x1;
+
+	udelay(100);
+
+	return 0;
+}
+
+#ifdef CONFIG_SPC1920_HPI_TEST
+/* activate the Host Port interface */
+static int hpi_activate(void)
+{
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
+
+	/* turn on hpi */
+	pld->dsp_hpi_on = 0x1;
+
+	udelay(5);
+
+	/* turn on the power EN_DSP_POWER high*/
+	/* currently always on TBD */
+
+	/* setup hpi control register */
+	HPI_HPIC_1 = (u16) 0x0008;
+	HPI_HPIC_2 = (u16) 0x0008;
+
+	udelay(100);
+
+	return 0;
+}
+
+/* turn off the host port interface */
+static void hpi_inactivate(void)
+{
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
+
+	/* deactivate hpi */
+	pld->dsp_hpi_on = 0x0;
+
+	/* reset the dsp */
+	/* pld->dsp_reset = 0x0; */
+
+	/* turn off the power EN_DSP_POWER# high*/
+	/* currently always on TBD */
+
+}
+
+/* reset the DSP */
+static void dsp_reset(void)
+{
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
+	pld->dsp_reset = 0x1;
+	pld->dsp_hpi_on = 0x0;
+
+	udelay(300000);
+
+	pld->dsp_reset = 0x0;
+	pld->dsp_hpi_on = 0x1;
+}
+
+
+/* write using autoinc (count is number of 32bit words) */
+static int hpi_write_inc(u32 addr, u32 *data, u32 count)
+{
+	int i;
+	u16 addr1, addr2;
+
+	addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
+	addr2 = (u16) (addr & 0xffff);
+
+	/* write address */
+	HPI_HPIA_1 = addr1;
+	HPI_HPIA_2 = addr2;
+
+	debugX(4, "writing from data=0x%x to 0x%x\n", data, (data+count));
+
+	for(i=0; i<count; i++) {
+		HPI_HPID_INC_1 = (u16) ((data[i] >> 16) & 0xffff);
+		HPI_HPID_INC_2 = (u16) (data[i] & 0xffff);
+		debugX(4, "hpi_write_inc: data1=0x%x, data2=0x%x\n",
+		       (u16) ((data[i] >> 16) & 0xffff),
+		       (u16) (data[i] & 0xffff));
+	}
+#if 0
+	while(data_ptr < (u16*) (data + count)) {
+		HPI_HPID_INC_1 = *(data_ptr++);
+		HPI_HPID_INC_2 = *(data_ptr++);
+	}
+#endif
+
+	/* return number of bytes written */
+	return count;
+}
+
+/*
+ * read using autoinc (count is number of 32bit words)
+ */
+static int hpi_read_inc(u32 addr, u32 *buf, u32 count)
+{
+	int i;
+	u16 addr1, addr2, data1, data2;
+
+	addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
+	addr2 = (u16) (addr & 0xffff);
+
+	/* write address */
+	HPI_HPIA_1 = addr1;
+	HPI_HPIA_2 = addr2;
+
+	for(i=0; i<count; i++) {
+		data1 = HPI_HPID_INC_1;
+		data2 = HPI_HPID_INC_2;
+		debugX(4, "hpi_read_inc: data1=0x%x, data2=0x%x\n", data1, data2);
+		buf[i] = (((u32) data1) << 16) | (data2 & 0xffff);
+	}
+
+#if 0
+	while(buf_ptr < (u16*) (buf + count)) {
+		*(buf_ptr++) = HPI_HPID_INC_1;
+		*(buf_ptr++) = HPI_HPID_INC_2;
+	}
+#endif
+
+	/* return number of bytes read */
+	return count;
+}
+
+
+/* write to non- auto inc regs */
+static int hpi_write_noinc(u32 addr, u32 data)
+{
+
+	u16 addr1, addr2, data1, data2;
+
+	addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
+	addr2 = (u16) (addr & 0xffff);
+
+	/* printf("hpi_write_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */
+
+	HPI_HPIA_1 = addr1;
+	HPI_HPIA_2 = addr2;
+
+	data1 = (u16) ((data >> 16) & 0xffff);
+	data2 = (u16) (data & 0xffff);
+
+	/* printf("hpi_write_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */
+
+	HPI_HPID_NOINC_1 = data1;
+	HPI_HPID_NOINC_2 = data2;
+
+	return 0;
+}
+
+/* read from non- auto inc regs */
+static u32 hpi_read_noinc(u32 addr)
+{
+	u16 addr1, addr2, data1, data2;
+	u32 ret;
+
+	addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */
+	addr2 = (u16) (addr & 0xffff);
+
+	HPI_HPIA_1 = addr1;
+	HPI_HPIA_2 = addr2;
+
+	/* printf("hpi_read_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */
+
+	data1 = HPI_HPID_NOINC_1;
+	data2 = HPI_HPID_NOINC_2;
+
+	/* printf("hpi_read_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */
+
+	ret = (((u32) data1) << 16) | (data2 & 0xffff);
+	return ret;
+
+}
+
+/*
+ * Host Port Interface Tests
+ */
+
+#ifndef HPI_TEST_OSZI
+/* main test function */
+int hpi_test(void)
+{
+	int err = 0;
+	u32 i, ii, pattern, tmp;
+
+	pattern = HPI_TEST_PATTERN;
+
+	u32 test_data[HPI_TEST_CHUNKSIZE];
+	u32 read_data[HPI_TEST_CHUNKSIZE];
+
+	debugX(2, "hpi_test: activating hpi...");
+	hpi_activate();
+	debugX(2, "OK.\n");
+
+#if 0
+	/* Dump the first 1024 bytes
+	 *
+	 */
+	for(i=0; i<1024; i+=4) {
+		if(i%16==0)
+			printf("\n0x%08x: ", i);
+		printf("0x%08x ", hpi_read_noinc(i));
+	}
+#endif
+
+	/* HPIA read-write test
+	 *
+	 */
+	debugX(1, "hpi_test: starting HPIA read-write tests...\n");
+	err |= hpi_write_addr_test(0xdeadc0de);
+	err |= hpi_write_addr_test(0xbeefd00d);
+	err |= hpi_write_addr_test(0xabcd1234);
+	err |= hpi_write_addr_test(0xaaaaaaaa);
+	if(err) {
+		debugX(1, "hpi_test: HPIA read-write tests: *** FAILED ***\n");
+		return -1;
+	}
+	debugX(1, "hpi_test: HPIA read-write tests: OK\n");
+
+
+	/* read write test using nonincremental data regs
+	 *
+	 */
+	debugX(1, "hpi_test: starting nonincremental tests...\n");
+	for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
+		err |= hpi_read_write_test(i, pattern);
+
+		/* stolen from cmd_mem.c */
+		if(pattern & 0x80000000) {
+			pattern = -pattern;	/* complement & increment */
+		} else {
+			pattern = ~pattern;
+		}
+		err |= hpi_read_write_test(i, pattern);
+
+		if(err) {
+			debugX(1, "hpi_test: nonincremental tests *** FAILED ***\n");
+			return -1;
+		}
+	}
+	debugX(1, "hpi_test: nonincremental test OK\n");
+
+	/* read write a chunk of data using nonincremental data regs
+	 *
+	 */
+	debugX(1, "hpi_test: starting nonincremental chunk tests...\n");
+	pattern = HPI_TEST_PATTERN;
+	for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
+		hpi_write_noinc(i, pattern);
+
+		/* stolen from cmd_mem.c */
+		if(pattern & 0x80000000) {
+			pattern = -pattern;	/* complement & increment */
+		} else {
+			pattern = ~pattern;
+		}
+	}
+	pattern = HPI_TEST_PATTERN;
+	for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) {
+		tmp = hpi_read_noinc(i);
+
+		if(tmp != pattern) {
+			debugX(1, "hpi_test: noninc chunk test *** FAILED *** @ 0x%x, written=0x%x, read=0x%x\n", i, pattern, tmp);
+			err = -1;
+		}
+		/* stolen from cmd_mem.c */
+		if(pattern & 0x80000000) {
+			pattern = -pattern;	/* complement & increment */
+		} else {
+			pattern = ~pattern;
+		}
+	}
+	if(err)
+		return -1;
+	debugX(1, "hpi_test: nonincremental chunk test OK\n");
+
+
+#ifdef DO_TINY_TEST
+	/* small verbose test using autoinc and nonautoinc to compare
+	 *
+	 */
+	debugX(1, "hpi_test: tiny_autoinc_test...\n");
+	hpi_tiny_autoinc_test();
+	debugX(1, "hpi_test: tiny_autoinc_test done\n");
+#endif /* DO_TINY_TEST */
+
+
+	/* $%& write a chunk of data using the autoincremental regs
+	 *
+	 */
+	debugX(1, "hpi_test: starting autoinc test %d chunks with 0x%x bytes...\n",
+	       ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE),
+	       HPI_TEST_CHUNKSIZE);
+
+	for(i=HPI_TEST_START;
+	    i < ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE);
+	    i++) {
+		/* generate the pattern data */
+		debugX(3, "generating pattern data: ");
+		for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) {
+			debugX(3, "0x%x ", pattern);
+
+			test_data[ii] = pattern;
+			read_data[ii] = 0x0; /* zero to be sure */
+
+			/* stolen from cmd_mem.c */
+			if(pattern & 0x80000000) {
+				pattern = -pattern;	/* complement & increment */
+			} else {
+				pattern = ~pattern;
+			}
+		}
+		debugX(3, "done\n");
+
+		debugX(2, "Writing autoinc data @ 0x%x\n", i);
+		hpi_write_inc(i, test_data, HPI_TEST_CHUNKSIZE);
+
+		debugX(2, "Reading autoinc data @ 0x%x\n", i);
+		hpi_read_inc(i, read_data, HPI_TEST_CHUNKSIZE);
+
+		/* compare */
+		for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) {
+			debugX(3, "hpi_test_autoinc: @ 0x%x, written=0x%x, read=0x%x", i+ii, test_data[ii], read_data[ii]);
+			if(read_data[ii] != test_data[ii]) {
+				debugX(0, "hpi_test: autoinc test @ 0x%x, written=0x%x, read=0x%x *** FAILED ***\n", i+ii, test_data[ii], read_data[ii]);
+				return -1;
+			}
+		}
+	}
+	debugX(1, "hpi_test: autoinc test OK\n");
+
+	return 0;
+}
+#else /* HPI_TEST_OSZI */
+int hpi_test(void)
+{
+	int i;
+	u32 read_data[TINY_AUTOINC_DATA_SIZE];
+
+	unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = {
+		0x11112222, 0x33334444, 0x55556666, 0x77778888,
+		0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111,
+		0x00010002, 0x00030004, 0x00050006, 0x00070008,
+		0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001
+	};
+
+	debugX(0, "hpi_test: activating hpi...");
+	hpi_activate();
+	debugX(0, "OK.\n");
+
+	while(1) {
+		led9(1);
+		debugX(0, " writing to autoinc...\n");
+		hpi_write_inc(TINY_AUTOINC_BASE_ADDR,
+			      dummy_data, TINY_AUTOINC_DATA_SIZE);
+
+		debugX(0, " reading from autoinc...\n");
+		hpi_read_inc(TINY_AUTOINC_BASE_ADDR,
+			     read_data, TINY_AUTOINC_DATA_SIZE);
+
+		for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) {
+			debugX(0, " written=0x%x, read(inc)=0x%x\n",
+			       dummy_data[i], read_data[i]);
+		}
+		led9(0);
+		udelay(2000000);
+	}
+	return 0;
+}
+#endif
+
+/* test if Host Port Address Register can be written correctly */
+static int hpi_write_addr_test(u32 addr)
+{
+	u32 read_back;
+	/* write address */
+	HPI_HPIA_1 = ((u16) (addr >> 16)); /* First HW is most significant */
+	HPI_HPIA_2 = ((u16) addr);
+
+	read_back = (((u32) HPI_HPIA_1)<<16) | ((u32) HPI_HPIA_2);
+
+	if(read_back == addr) {
+		debugX(2, " hpi_write_addr_test OK: written=0x%x, read=0x%x\n",
+		       addr, read_back);
+		return 0;
+	} else {
+		debugX(0, " hpi_write_addr_test *** FAILED ***: written=0x%x, read=0x%x\n",
+		      addr, read_back);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* test if a simple read/write sequence succeeds */
+static int hpi_read_write_test(u32 addr, u32 data)
+{
+	u32 read_back;
+
+	hpi_write_noinc(addr, data);
+	read_back = hpi_read_noinc(addr);
+
+	if(read_back == data) {
+		debugX(2, " hpi_read_write_test: OK, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
+		return 0;
+	} else {
+		debugX(0, " hpi_read_write_test: *** FAILED ***, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int hpi_tiny_autoinc_test(void)
+{
+	int i;
+	u32 read_data[TINY_AUTOINC_DATA_SIZE];
+	u32 read_data_noinc[TINY_AUTOINC_DATA_SIZE];
+
+	unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = {
+		0x11112222, 0x33334444, 0x55556666, 0x77778888,
+		0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111,
+		0x00010002, 0x00030004, 0x00050006, 0x00070008,
+		0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001
+	};
+
+	printf(" writing to autoinc...\n");
+	hpi_write_inc(TINY_AUTOINC_BASE_ADDR, dummy_data, TINY_AUTOINC_DATA_SIZE);
+
+	printf(" reading from autoinc...\n");
+	hpi_read_inc(TINY_AUTOINC_BASE_ADDR, read_data, TINY_AUTOINC_DATA_SIZE);
+
+	printf(" reading from noinc for comparison...\n");
+	for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++)
+		read_data_noinc[i] = hpi_read_noinc(TINY_AUTOINC_BASE_ADDR+i*4);
+
+	for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) {
+		printf(" written=0x%x, read(inc)=0x%x, read(noinc)=0x%x\n",
+		       dummy_data[i], read_data[i], read_data_noinc[i]);
+	}
+	return 0;
+}
+
+#endif /* CONFIG_SPC1920_HPI_TEST */
diff --git a/board/spc1920/hpi.h b/board/spc1920/hpi.h
new file mode 100644
index 0000000..4503873
--- /dev/null
+++ b/board/spc1920/hpi.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+int hpi_init(void);
+
+#ifdef CONFIG_SPC1920_HPI_TEST
+int hpi_test(void);
+#endif
diff --git a/board/spc1920/pld.h b/board/spc1920/pld.h
index 3254f82..5beb71b 100644
--- a/board/spc1920/pld.h
+++ b/board/spc1920/pld.h
@@ -5,8 +5,8 @@ typedef struct spc1920_pld {
 	uchar com1_en;
 	uchar dsp_reset;
 	uchar dsp_hpi_on;
+	uchar superv_mode;
 	uchar codec_dsp_power_en;
-	uchar clk2_en;
 	uchar clk3_select;
 	uchar clk4_select;
 } spc1920_pld_t;
diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c
index 028f4c6..1f5dcb5 100644
--- a/board/spc1920/spc1920.c
+++ b/board/spc1920/spc1920.c
@@ -27,9 +27,9 @@
 #include <common.h>
 #include <mpc8xx.h>
 #include "pld.h"
+#include "hpi.h"
 
 #define	_NOT_USED_	0xFFFFFFFF
-/* #define debug(fmt,args...)     printf (fmt ,##args) */
 
 static long int dram_size (long int, long int *, long int);
 
@@ -172,10 +172,12 @@ long int initdram (int board_type)
 	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
 	udelay (1000);
 
+	/* initalize the DSP Host Port Interface */
+	hpi_init();
 
-	/* PLD Setup */
-	memctl->memc_or5 = CFG_OR5_PRELIM;
-	memctl->memc_br5 = CFG_BR5_PRELIM;
+	/* FRAM Setup */
+	memctl->memc_or4 = CFG_OR4;
+	memctl->memc_br4 = CFG_BR4;
 	udelay(1000);
 
 	return (size_b0);
@@ -207,13 +209,31 @@ int board_early_init_f(void)
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
+	/* Set Go/NoGo led (PA15) to color red */
+	immap->im_ioport.iop_papar &= ~0x1;
+	immap->im_ioport.iop_paodr &= ~0x1;
+	immap->im_ioport.iop_padir |= 0x1;
+	immap->im_ioport.iop_padat |= 0x1;
 
+#if 0
 	/* Turn on LED PD9 */
 	immap->im_ioport.iop_pdpar &= ~(0x0040);
 	immap->im_ioport.iop_pddir |= 0x0040;
 	immap->im_ioport.iop_pddat |= 0x0040;
+#endif
+
+	/*
+	 * Enable console on SMC1. This requires turning on
+	 * the com2_en signal and SMC1_DISABLE
+	 */
+
+	/* SMC1_DISABLE: PB17 */
+	immap->im_cpm.cp_pbodr &= ~0x4000;
+	immap->im_cpm.cp_pbpar &= ~0x4000;
+	immap->im_cpm.cp_pbdir |= 0x4000;
+	immap->im_cpm.cp_pbdat &= ~0x4000;
 
-	/* Enable PD10 (COM2_EN) */
+	/* COM2_EN: PD10 */
 	immap->im_ioport.iop_pdpar &= ~0x0020;
 	immap->im_ioport.iop_pddir &= ~0x4000;
 	immap->im_ioport.iop_pddir |= 0x0020;
@@ -228,6 +248,14 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int last_stage_init(void)
+{
+#ifdef CONFIG_SPC1920_HPI_TEST
+	printf("CMB1920 Host Port Interface Test: %s\n",
+	       hpi_test() ? "Failed!" : "OK");
+#endif
+	return 0;
+}
 
 int checkboard (void)
 {
diff --git a/board/tqm5200/cam5200_flash.c b/board/tqm5200/cam5200_flash.c
index 8c3f62e..b3f095d 100644
--- a/board/tqm5200/cam5200_flash.c
+++ b/board/tqm5200/cam5200_flash.c
@@ -25,7 +25,7 @@
 #include <mpc5xxx.h>
 #include <asm/processor.h>
 
-#ifdef CONFIG_CAM5200
+#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
 
 #if 0
 #define DEBUGF(x...) printf(x)
@@ -783,4 +783,4 @@ unsigned long flash_init(void)
 
 	return total_b;
 }
-#endif /* ifdef CONFIG_CAM5200 */
+#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */
diff --git a/board/tqm8272/Makefile b/board/tqm8272/Makefile
new file mode 100644
index 0000000..3dbf913
--- /dev/null
+++ b/board/tqm8272/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/tqm8272/config.mk b/board/tqm8272/config.mk
new file mode 100644
index 0000000..af7a81e
--- /dev/null
+++ b/board/tqm8272/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8272 boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/tqm8272/tqm8272.c b/board/tqm8272/tqm8272.c
new file mode 100644
index 0000000..70d1bb8
--- /dev/null
+++ b/board/tqm8272/tqm8272.c
@@ -0,0 +1,1234 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+#include <command.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/m8260_pci.h>
+#endif
+#if CONFIG_OF_FLAT_TREE
+#include <ft_build.h>
+#include <image.h>
+#endif
+
+#if 0
+#define deb_printf(fmt,arg...) \
+	printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
+#else
+#define deb_printf(fmt,arg...) \
+	do { } while (0)
+#endif
+
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+unsigned long board_get_cpu_clk_f (void);
+#endif
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTCA	*/
+	/* PA29 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTSOC	*/
+	/* PA28 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC1 ATMRXD[0] */
+	/* PA9	*/ {   1,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
+	/* PA8	*/ {   1,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
+	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
+	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
+	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
+	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
+	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
+	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
+	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
+	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
+	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
+	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
+	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
+	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
+	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
+	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
+	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
+	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
+	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
+	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
+	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
+	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
+	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
+	/* PC30 */ {   0,   0,	 0,   0,   0,	0   }, /* PC30 */
+	/* PC29 */ {   1,   1,	 1,   0,   0,	0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,	 0,   1,   0,	0   }, /* PC28 */
+	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
+	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
+	/* PC25 */ {   0,   0,	 0,   1,   0,	0   }, /* PC25 */
+	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
+	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   1,   0,	 0,   1,   0,	0   }, /* PC17 MDC */
+	/* PC16 */ {   1,   0,	 0,   0,   0,	0   }, /* PC16 MDIO*/
+	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
+	/* PC14 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
+	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
+	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
+	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* PC10 */
+	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC9 */
+	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
+	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
+	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
+	/* PC5	*/ {   1,   1,	 0,   1,   0,	0   }, /* PC5 SMC1 TXD */
+	/* PC4	*/ {   1,   1,	 0,   0,   0,	0   }, /* PC4 SMC1 RXD */
+	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
+	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
+	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
+	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
+	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
+	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
+	/* PD25 */ {   0,   0,	 0,   1,   0,	0   }, /* PD25 */
+	/* PD24 */ {   0,   0,	 0,   1,   0,	0   }, /* PD24 */
+	/* PD23 */ {   0,   0,	 0,   1,   0,	0   }, /* PD23 */
+	/* PD22 */ {   0,   0,	 0,   1,   0,	0   }, /* PD22 */
+	/* PD21 */ {   0,   0,	 0,   1,   0,	0   }, /* PD21 */
+	/* PD20 */ {   0,   0,	 0,   1,   0,	0   }, /* PD20 */
+	/* PD19 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
+	/* PD18 */ {   0,   0,	 0,   1,   0,	0   }, /* PD19 */
+	/* PD17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 ATMTXPRTY */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
+	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
+	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
+	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
+	/* PD9	*/ {   1,   1,	 0,   1,   0,	0   }, /* SMC1 TXD */
+	/* PD8	*/ {   1,   1,	 0,   0,   0,	0   }, /* SMC1 RXD */
+	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD7 */
+	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
+	/* PD5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PD5 */
+	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/* UPM pattern for bus clock = 66.7 MHz */
+static const uint upmTable67[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000,
+    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00,
+    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 100 MHz */
+static const uint upmTable100[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
+    /* 0x04 */	0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00,
+    /* 0x1C */	0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for bus clock = 133.3 MHz */
+static const uint upmTable133[] =
+{
+    /* Offset	UPM Read Single RAM array entry -> NAND Read Data */
+    /* 0x00 */	0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000,
+    /* 0x04 */	0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */
+    /* 0x18 */	0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00,
+    /* 0x1C */	0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unsused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+static int	chipsel = 0;
+
+/* UPM pattern for slow init */
+static const uint upmTableSlow[] =
+{
+    /* Offset	UPM Read Single RAM array entry */
+    /* 0x00 */	0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00,
+    /* 0x04 */	0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry */
+    /* 0x18 */	0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80,
+    /* 0x1C */	0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+/* UPM pattern for fast init */
+static const uint upmTableFast[] =
+{
+    /* Offset	UPM Read Single RAM array entry */
+    /* 0x00 */	0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00,
+    /* 0x04 */	0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x08 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x0C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Read Burst RAM array entry -> unused */
+    /* 0x10 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x14 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+
+		/* UPM Write Single RAM array entry */
+    /* 0x18 */	0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00,
+    /* 0x1C */	0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05,
+
+		/* UPM Write Burst RAM array entry -> unused */
+    /* 0x20 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x24 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x28 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x2C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Refresh Timer RAM array entry -> unused */
+    /* 0x30 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x34 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+    /* 0x38 */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+
+		/* UPM Exception RAM array entry -> unused */
+    /* 0x3C */	0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+};
+
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	char *p = (char *) HWIB_INFO_START_ADDR;
+
+	puts ("Board: ");
+	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
+		puts (p);
+	} else {
+		puts ("No HWIB assuming TQM8272");
+	}
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+static int get_cas_latency (void)
+{
+	/* get it from the option -ts in CIB */
+	/* default is 3 */
+	int	ret = 3;
+	int	pos = 0;
+	char	*p = (char *) CIB_INFO_START_ADDR;
+
+	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return ret;
+		}
+		if (*p == '-') {
+			if ((p[1] == 't') && (p[2] == 's')) {
+				return (p[4] - '0');
+			}
+		}
+		p++;
+		pos++;
+	}
+	return ret;
+}
+#endif
+
+static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col)
+{
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+	int	clk = board_get_cpu_clk_f ();
+	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	int	busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
+	int	cas;
+
+	sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \
+			 PSDMR_BUFCMD);
+	if (busmode) {
+		switch (clk) {
+			case 66666666:
+				sdmr |= (PSDMR_RFRC_66MHZ_60X | \
+					PSDMR_PRETOACT_66MHZ_60X | \
+					PSDMR_WRC_66MHZ_60X | \
+					PSDMR_BUFCMD_66MHZ_60X);
+				break;
+			case 100000000:
+				sdmr |= (PSDMR_RFRC_100MHZ_60X | \
+					PSDMR_PRETOACT_100MHZ_60X | \
+					PSDMR_WRC_100MHZ_60X | \
+					PSDMR_BUFCMD_100MHZ_60X);
+				break;
+
+		}
+	} else {
+		switch (clk) {
+			case 66666666:
+				sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \
+					PSDMR_PRETOACT_66MHZ_SINGLE | \
+					PSDMR_WRC_66MHZ_SINGLE | \
+					PSDMR_BUFCMD_66MHZ_SINGLE);
+				break;
+			case 100000000:
+				sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \
+					PSDMR_PRETOACT_100MHZ_SINGLE | \
+					PSDMR_WRC_100MHZ_SINGLE | \
+					PSDMR_BUFCMD_100MHZ_SINGLE);
+				break;
+			case 133333333:
+				sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \
+					PSDMR_PRETOACT_133MHZ_SINGLE | \
+					PSDMR_WRC_133MHZ_SINGLE | \
+					PSDMR_BUFCMD_133MHZ_SINGLE);
+				break;
+		}
+	}
+	cas = get_cas_latency();
+	sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK);
+	sdmr |= cas;
+	sdmr |= ((cas - 1) << 6);
+	return sdmr;
+#else
+	return sdmr;
+#endif
+}
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base, int col)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
+	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
+
+	*orx_ptr = orx;
+	sdmr = set_sdram_timing (sdmr_ptr, sdmr, col);
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	long size8, size9;
+#endif
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+					  (uchar *) CFG_SDRAM_BASE, 8);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
+					  (uchar *) CFG_SDRAM_BASE, 9);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL - %ld MB, ", psize >> 20);
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+						  (uchar *) CFG_SDRAM_BASE, 8);
+		printf ("(60x:8COL - %ld MB, ", psize >> 20);
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+
+static inline int scanChar (char *p, int len, unsigned long *number)
+{
+	int	akt = 0;
+
+	*number = 0;
+	while (akt < len) {
+		if ((*p >= '0') && (*p <= '9')) {
+			*number *= 10;
+			*number += *p - '0';
+			p += 1;
+		} else {
+			if (*p == '-')	return akt;
+			return -1;
+		}
+		akt ++;
+	}
+	return akt;
+}
+
+typedef struct{
+	int	Bus;
+	int	flash;
+	int	flash_nr;
+	int	ram;
+	int	ram_cs;
+	int	nand;
+	int	nand_cs;
+	int	eeprom;
+	int	can;
+	unsigned long	cpunr;
+	unsigned long	option;
+	int	SecEng;
+	int	cpucl;
+	int	cpmcl;
+	int	buscl;
+	int	busclk_real_ok;
+	int	busclk_real;
+	unsigned char	OK;
+	unsigned char  ethaddr[20];
+} HWIB_INFO;
+
+HWIB_INFO	hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0,
+			 0, 0, 0, 0, 0, 0};
+
+static int dump_hwib(void)
+{
+	HWIB_INFO	*hw = &hwinf;
+	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	char *s = getenv("serial#");
+
+	if (hw->OK) {
+		printf ("HWIB on %x\n", HWIB_INFO_START_ADDR);
+		printf ("serial : %s\n", s);
+		printf ("ethaddr: %s\n", hw->ethaddr);
+		printf ("FLASH	: %x nr:%d\n", hw->flash, hw->flash_nr);
+		printf ("RAM	: %x cs:%d\n", hw->ram, hw->ram_cs);
+		printf ("CPU	: %d\n", hw->cpunr);
+		printf ("CAN	: %d\n", hw->can);
+		if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom);
+		else printf ("No EEprom\n");
+		if (hw->nand) {
+			printf ("NAND	: %x\n", hw->nand);
+			printf ("NAND CS: %d\n", hw->nand_cs);
+		} else { printf ("No NAND\n");}
+		printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII"));
+		printf ("  real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \
+				 "60x" : "Single PQII"));
+		printf ("Option : %x\n", hw->option);
+		printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no"));
+		printf ("CPM Clk: %d\n", hw->cpmcl);
+		printf ("CPU Clk: %d\n", hw->cpucl);
+		printf ("Bus Clk: %d\n", hw->buscl);
+		if (hw->busclk_real_ok) {
+			printf ("  real Clk: %d\n", hw->busclk_real);
+		}
+		printf ("CAS	: %d\n", get_cas_latency());
+	} else {
+		printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR);
+	}
+	return 0;
+}
+
+static inline int search_real_busclk (int *clk)
+{
+	int	part = 0, pos = 0;
+	char *p = (char *) CIB_INFO_START_ADDR;
+	int	ok = 0;
+
+	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return 0;
+		}
+		switch (part) {
+		default:
+			if (*p == '-') {
+				++part;
+			}
+			break;
+		case 3:
+			if (*p == '-') {
+				++part;
+				break;
+			}
+			if (*p == 'b') {
+				ok = 1;
+				p++;
+				break;
+			}
+			if (ok) {
+				switch (*p) {
+				case '6':
+					*clk = 66666666;
+					return 1;
+					break;
+				case '1':
+					if (p[1] == '3') {
+						*clk = 133333333;
+					} else {
+						*clk = 100000000;
+					}
+					return 1;
+					break;
+				}
+			}
+			break;
+		}
+		p++;
+	}
+	return 0;
+}
+
+int analyse_hwib (void)
+{
+	char	*p = (char *) HWIB_INFO_START_ADDR;
+	int	anz;
+	int	part = 1, i = 0, pos = 0;
+	HWIB_INFO	*hw = &hwinf;
+
+	deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
+	/* Head = TQM */
+	if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) {
+		deb_printf("No HWIB\n");
+		return -1;
+	}
+	p += 3;
+	if (scanChar (p, 4, &hw->cpunr) < 0) {
+		deb_printf("No CPU\n");
+		return -2;
+	}
+	p +=4;
+
+	hw->flash = 0x200000 << (*p - 'A');
+	p++;
+	hw->flash_nr = *p - '0';
+	p++;
+
+	hw->ram = 0x2000000 << (*p - 'A');
+	p++;
+	if (*p == '2') {
+		hw->ram_cs = 2;
+		p++;
+	}
+
+	if (*p == 'A') hw->can = 1;
+	if (*p == 'B') hw->can = 2;
+	p +=1;
+	p +=1;	/* connector */
+	if (*p != '0') {
+		hw->eeprom = 0x1000 << (*p - 'A');
+	}
+	p++;
+
+	if ((*p < '0') || (*p > '9')) {
+		/* NAND before z-option */
+		hw->nand = 0x8000000 << (*p - 'A');
+		p++;
+		hw->nand_cs = *p - '0';
+		p += 2;
+	}
+	/* z-option */
+	anz = scanChar (p, 4, &hw->option);
+	if (anz < 0) {
+		deb_printf("No option\n");
+		return -3;
+	}
+	if (hw->option & 0x8) hw->Bus = 1;
+	p += anz;
+	if (*p != '-') {
+		deb_printf("No -\n");
+		return -4;
+	}
+	p++;
+	/* C option */
+	if (*p == 'E') {
+		hw->SecEng = 1;
+		p++;
+	}
+	switch (*p) {
+		case 'M': hw->cpucl = 266666666;
+			break;
+		case 'P': hw->cpucl = 300000000;
+			break;
+		case 'T': hw->cpucl = 400000000;
+			break;
+		default:
+			deb_printf("No CPU Clk: %c\n", *p);
+			return -5;
+			break;
+	}
+	p++;
+	switch (*p) {
+		case 'I': hw->cpmcl = 200000000;
+			break;
+		case 'M': hw->cpmcl = 300000000;
+			break;
+		default:
+			deb_printf("No CPM Clk\n");
+			return -6;
+			break;
+	}
+	p++;
+	switch (*p) {
+		case 'B': hw->buscl = 66666666;
+			break;
+		case 'E': hw->buscl = 100000000;
+			break;
+		case 'F': hw->buscl = 133333333;
+			break;
+		default:
+			deb_printf("No BUS Clk\n");
+			return -7;
+			break;
+	}
+	p++;
+
+	hw->OK = 1;
+	/* search MAC Address */
+	while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return 0;
+		}
+		switch (part) {
+		default:
+			if (*p == ' ') {
+				++part;
+				i = 0;
+			}
+			break;
+		case 3:			/* Copy MAC address */
+			if (*p == ' ') {
+				++part;
+				i = 0;
+				break;
+			}
+			hw->ethaddr[i++] = *p;
+			if ((i % 3) == 2)
+				hw->ethaddr[i++] = ':';
+			break;
+
+		}
+		p++;
+	}
+
+	hw->busclk_real_ok = search_real_busclk (&hw->busclk_real);
+	return 0;
+}
+
+#if defined(CONFIG_GET_CPU_STR_F)
+/* !! This routine runs from Flash */
+char get_cpu_str_f (char *buf)
+{
+	char *p = (char *) HWIB_INFO_START_ADDR;
+	int	i = 0;
+
+	buf[i++] = 'M';
+	buf[i++] = 'P';
+	buf[i++] = 'C';
+	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
+		buf[i++] = *&p[3];
+		buf[i++] = *&p[4];
+		buf[i++] = *&p[5];
+		buf[i++] = *&p[6];
+	} else {
+		buf[i++] = '8';
+		buf[i++] = '2';
+		buf[i++] = '7';
+		buf[i++] = 'x';
+	}
+	buf[i++] = 0;
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+/* !! This routine runs from Flash */
+unsigned long board_get_cpu_clk_f (void)
+{
+	char *p = (char *) HWIB_INFO_START_ADDR;
+	int i = 0;
+
+	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
+		if (search_real_busclk (&i))
+			return i;
+	}
+	return CONFIG_8260_CLKIN;
+}
+#endif
+
+#if CONFIG_BOARD_EARLY_INIT_R
+
+static int can_test (unsigned long off)
+{
+	volatile unsigned char	*base	= (unsigned char *) (CFG_CAN_BASE + off);
+
+	*(base + 0x17) = 'T';
+	*(base + 0x18) = 'Q';
+	*(base + 0x19) = 'M';
+	if ((*(base + 0x17) != 'T') ||
+	    (*(base + 0x18) != 'Q') ||
+	    (*(base + 0x19) != 'M')) {
+		return 0;
+	}
+	return 1;
+}
+
+static int can_config_one (unsigned long off)
+{
+	volatile unsigned char	*ctrl	= (unsigned char *) (CFG_CAN_BASE + off);
+	volatile unsigned char	*cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02);
+	volatile unsigned char	*clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f);
+	unsigned char temp;
+
+	*cpu_if = 0x45;
+	temp = *ctrl;
+	temp |= 0x40;
+	*ctrl	= temp;
+	*clkout = 0x20;
+	temp = *ctrl;
+	temp &= ~0x40;
+	*ctrl	= temp;
+	return 0;
+}
+
+static int can_config (void)
+{
+	int	ret = 0;
+	can_config_one (0);
+	if (hwinf.can == 2) {
+		can_config_one (0x100);
+	}
+	/* make Test if they really there */
+	ret += can_test (0);
+	ret += can_test (0x100);
+	return ret;
+}
+
+static int init_can (void)
+{
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+	int	count = 0;
+
+	if ((hwinf.OK) && (hwinf.can)) {
+		memctl->memc_or4 = CFG_CAN_OR;
+		memctl->memc_br4 = CFG_CAN_BR;
+		/* upm Init */
+		upmconfig (UPMC, (uint *) upmTableFast,
+			   sizeof (upmTableFast) / sizeof (uint));
+		memctl->memc_mcmr =	(MxMR_DSx_3_CYCL |
+					MxMR_GPL_x4DIS |
+					MxMR_RLFx_2X |
+					MxMR_WLFx_2X |
+					MxMR_OP_NORM);
+		/* can configure */
+		count = can_config ();
+		printf ("CAN:	%d @ %x\n", count, CFG_CAN_BASE);
+		if (hwinf.can != count) printf("!!! difference to HWIB\n");
+	} else {
+		printf ("CAN:	No\n");
+	}
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	analyse_hwib ();
+	init_can ();
+	return 0;
+}
+#endif
+
+int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	dump_hwib ();
+	return 0;
+}
+
+U_BOOT_CMD(
+	  hwib, 1,	1,	do_hwib_dump,
+	  "hwib	   - dump HWIB'\n",
+	  "\n"
+);
+
+#ifdef CFG_UPDATE_FLASH_SIZE
+static int get_flash_timing (void)
+{
+	/* get it from the option -tf in CIB */
+	/* default is 0x00000c84 */
+	int	ret = 0x00000c84;
+	int	pos = 0;
+	int	nr = 0;
+	char	*p = (char *) CIB_INFO_START_ADDR;
+
+	while ((*p != '\0') && (pos < CIB_INFO_LEN)) {
+		if (*p < ' ' || *p > '~') { /* ASCII strings! */
+			return ret;
+		}
+		if (*p == '-') {
+			if ((p[1] == 't') && (p[2] == 'f')) {
+				p += 6;
+				ret = 0;
+				while (nr < 8) {
+				if ((*p >= '0') && (*p <= '9')) {
+					ret *= 0x10;
+					ret += *p - '0';
+					p += 1;
+					nr ++;
+				} else if ((*p >= 'A') && (*p <= 'F')) {
+					ret *= 10;
+					ret += *p - '7';
+					p += 1;
+					nr ++;
+				} else {
+					if (nr < 8) return 0x00000c84;
+					return ret;
+				}
+				}
+			}
+		}
+		p++;
+		pos++;
+	}
+	return ret;
+}
+
+/* Update the Flash_Size and the Flash Timing */
+int update_flash_size (int flash_size)
+{
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+	unsigned long reg;
+	unsigned long tim;
+
+	/* I must use reg, otherwise the board hang */
+	reg = memctl->memc_or0;
+	reg &= ~ORxU_AM_MSK;
+	reg |= MEG_TO_AM(flash_size >> 20);
+	tim = get_flash_timing ();
+	reg &= ~0xfff;
+	reg |= (tim & 0xfff);
+	memctl->memc_or0 = reg;
+	return 0;
+}
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+static u8 hwctl = 0;
+
+static void upmnand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		hwctl |= 0x1;
+		break;
+	case NAND_CTL_CLRCLE:
+		hwctl &= ~0x1;
+		break;
+
+	case NAND_CTL_SETALE:
+		hwctl |= 0x2;
+		break;
+
+	case NAND_CTL_CLRALE:
+		hwctl &= ~0x2;
+		break;
+	}
+}
+
+static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+
+	if (hwctl & 0x1) {
+		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
+	} else if (hwctl & 0x2) {
+		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
+	} else {
+		WRITE_NAND(byte, base);
+	}
+}
+
+static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+
+	return READ_NAND(base);
+}
+
+static int tqm8272_dev_ready(struct mtd_info *mtdinfo)
+{
+	/* constant delay (see also tR in the datasheet) */
+	udelay(12); \
+	return 1;
+}
+
+#ifndef CONFIG_NAND_SPL
+static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i< len; i++)
+		buf[i] = *base;
+}
+
+static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i< len; i++)
+		*base = buf[i];
+}
+
+static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+	struct nand_chip *this = mtdinfo->priv;
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	int	i;
+
+	for (i = 0; i < len; i++)
+		if (buf[i] != *base)
+			return -1;
+	return 0;
+}
+#endif /* #ifndef CONFIG_NAND_SPL */
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+	chipsel = chip;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	static	int	UpmInit = 0;
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+
+	if (hwinf.nand == 0) return -1;
+
+	/* Setup the UPM */
+	if (UpmInit == 0) {
+		switch (hwinf.busclk_real) {
+		case 100000000:
+			upmconfig (UPMB, (uint *) upmTable100,
+			   sizeof (upmTable100) / sizeof (uint));
+			break;
+		case 133333333:
+			upmconfig (UPMB, (uint *) upmTable133,
+			   sizeof (upmTable133) / sizeof (uint));
+			break;
+		default:
+			upmconfig (UPMB, (uint *) upmTable67,
+			   sizeof (upmTable67) / sizeof (uint));
+			break;
+		}
+		UpmInit = 1;
+	}
+
+	/* Setup the memctrl */
+	memctl->memc_or3 = CFG_NAND_OR;
+	memctl->memc_br3 = CFG_NAND_BR;
+	memctl->memc_mbmr = (MxMR_OP_NORM);
+
+	nand->eccmode = NAND_ECC_SOFT;
+
+	nand->hwcontrol	 = upmnand_hwcontrol;
+	nand->read_byte	 = upmnand_read_byte;
+	nand->write_byte = upmnand_write_byte;
+	nand->dev_ready	 = tqm8272_dev_ready;
+
+#ifndef CONFIG_NAND_SPL
+	nand->write_buf	 = tqm8272_write_buf;
+	nand->read_buf	 = tqm8272_read_buf;
+	nand->verify_buf = tqm8272_verify_buf;
+#endif
+
+	/*
+	 * Select required NAND chip
+	 */
+	board_nand_select_device(nand, 0);
+	return 0;
+}
+
+#endif	/* CFG_CMD_NAND */
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+int board_early_init_f (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+	return 0;
+}
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/board/tqm8272/u-boot.lds b/board/tqm8272/u-boot.lds
new file mode 100644
index 0000000..05f29c6
--- /dev/null
+++ b/board/tqm8272/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c
index 5a23e6c..d896f17 100644
--- a/board/tqm834x/pci.c
+++ b/board/tqm834x/pci.c
@@ -69,17 +69,17 @@ void
 pci_init_board(void)
 {
 	volatile immap_t *	immr;
-	volatile clk8349_t *	clk;
-	volatile law8349_t *	pci_law;
-	volatile pot8349_t *	pci_pot;
-	volatile pcictrl8349_t *	pci_ctrl;
-	volatile pciconf8349_t *	pci_conf;
+	volatile clk83xx_t *	clk;
+	volatile law83xx_t *	pci_law;
+	volatile pot83xx_t *	pci_pot;
+	volatile pcictrl83xx_t *	pci_ctrl;
+	volatile pciconf83xx_t *	pci_conf;
 	u16 reg16;
 	u32 reg32;
 	struct	pci_controller * hose;
 
-	immr = (immap_t *)CFG_IMMRBAR;
-	clk = (clk8349_t *)&immr->clk;
+	immr = (immap_t *)CFG_IMMR;
+	clk = (clk83xx_t *)&immr->clk;
 	pci_law = immr->sysconf.pcilaw;
 	pci_pot = immr->ios.pot;
 	pci_ctrl = immr->pci_ctrl;
@@ -186,8 +186,8 @@ pci_init_board(void)
 	hose->region_count = 3;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMRBAR+0x8300),
-			   (CFG_IMMRBAR+0x8304));
+			   (CFG_IMMR+0x8300),
+			   (CFG_IMMR+0x8304));
 
 	pci_register_hose(hose);
 
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index 41b34cc..9c35e22 100644
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -69,7 +69,7 @@ static void set_cs_config(short cs, long config);
 static void set_ddr_config(void);
 
 /* Local variable */
-static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+static volatile immap_t *im = (immap_t *)CFG_IMMR;
 
 /**************************************************************************
  * Board initialzation after relocation to RAM. Used to detect the number
@@ -147,15 +147,15 @@ int checkboard (void)
 	volatile immap_t * immr;
 	u32 w, f;
 
-	immr = (immap_t *)CFG_IMMRBAR;
-	if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
+	immr = (immap_t *)CFG_IMMR;
+	if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
 		printf("PCI:   NOT in host mode..?!\n");
 		return 0;
 	}
 
 	/* get bus width */
 	w = 32;
-	if (immr->reset.rcwh & RCWH_PCI64)
+	if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
 		w = 64;
 
 	/* get clock */
diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c
index 7684499..6f903d2 100644
--- a/board/trab/auto_update.c
+++ b/board/trab/auto_update.c
@@ -203,7 +203,6 @@ extern int flash_write (char *, ulong, ulong);
 /* change char* to void* to shutup the compiler */
 extern int i2c_write_multiple (uchar, uint, int, void *, int);
 extern int i2c_read_multiple (uchar, uint, int, void *, int);
-extern block_dev_desc_t *get_dev (char*, int);
 extern int u_boot_hush_start(void);
 
 int
diff --git a/board/uc101/Makefile b/board/uc101/Makefile
new file mode 100644
index 0000000..ddfd2ef
--- /dev/null
+++ b/board/uc101/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/uc101/config.mk b/board/uc101/config.mk
new file mode 100644
index 0000000..51e8e84c
--- /dev/null
+++ b/board/uc101/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# INKA 4X0 board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFE00000   boot high
+#
+#	0x00100000   boot from RAM (for testing only)
+#
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+#TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/uc101/u-boot.lds b/board/uc101/u-boot.lds
new file mode 100644
index 0000000..123a14c
--- /dev/null
+++ b/board/uc101/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within  */
+    /* the sector layout of our flash chips!    XXX FIXME XXX   */
+
+    cpu/mpc5xxx/start.o          (.text)
+    cpu/mpc5xxx/traps.o          (.text)
+    lib_generic/crc32.o         (.text)
+    lib_ppc/cache.o             (.text)
+    lib_ppc/time.o              (.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o        (.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/uc101/uc101.c b/board/uc101/uc101.c
new file mode 100644
index 0000000..7a6b3be
--- /dev/null
+++ b/board/uc101/uc101.c
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <malloc.h>
+
+/* some SIMPLE GPIO Pins */
+#define GPIO_USB_8	(31-12)
+#define GPIO_USB_7	(31-13)
+#define GPIO_USB_6	(31-14)
+#define GPIO_USB_0	(31-15)
+#define GPIO_PSC3_7	(31-18)
+#define GPIO_PSC3_6	(31-19)
+#define GPIO_PSC3_1	(31-22)
+#define GPIO_PSC3_0	(31-23)
+
+/* some simple Interrupt GPIO Pins */
+#define GPIO_PSC3_8	2
+#define GPIO_USB1_9	3
+
+#define GPT_OUT_0	0x00000027
+#define GPT_OUT_1	0x00000037
+#define	GPT_DISABLE	0x00000000	/* GPT pin disabled */
+
+#define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \
+				pgpio->simple_ddr |= (1 << n); \
+				pgpio->simple_gpioe |= (1 << n); \
+				}
+
+#define GP_SIMP_ENABLE_I(n) {	pgpio->simple_ddr |= ~(1 << n); \
+				pgpio->simple_gpioe |= (1 << n); \
+				}
+
+#define GP_SIMP_SET_O(n, v)  (pgpio->simple_dvo = v ? \
+				(pgpio->simple_dvo | (1 << n)) : \
+				(pgpio->simple_dvo & ~(1 << n)) )
+
+#define GP_SIMP_GET_O(n)  ((pgpio->simple_dvo >> n) & 1)
+#define GP_SIMP_GET_I(n)  ((pgpio->simple_ival >> n) & 1)
+
+#define GP_SINT_SET_O(n, v)  (pgpio->sint_dvo = v ? \
+				(pgpio->sint_dvo | (1 << n)) : \
+				(pgpio->sint_dvo & ~(1 << n)) )
+
+#define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \
+				pgpio->sint_ddr |= (1 << n); \
+				GP_SINT_SET_O(n, v); \
+				pgpio->sint_gpioe |= (1 << n); \
+				}
+
+#define GP_SINT_ENABLE_I(n) {	pgpio->sint_ddr |= ~(1 << n); \
+				pgpio->sint_gpioe |= (1 << n); \
+				}
+
+#define GP_SINT_GET_O(n)  ((pgpio->sint_ival >> n) & 1)
+#define GP_SINT_GET_I(n)  ((pgpio-ntt_ival >> n) & 1)
+
+#define GP_TIMER_ENABLE_O(n, v) ( \
+	((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \
+				GPT_OUT_1 : \
+				GPT_OUT_0 )
+
+#define GP_TIMER_SET_O(n, v)	GP_TIMER_ENABLE_O(n, v)
+
+#define GP_TIMER_GET_O(n, v) ( \
+	(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4)
+
+#define GP_TIMER_GET_I(n, v) ( \
+	(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8)
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+/*	return dramsize + dramsize2; */
+	return dramsize;
+}
+
+int checkboard (void)
+{
+	puts ("Board: MAN UC101\n");
+	return 0;
+}
+
+static void init_ports (void)
+{
+	volatile struct mpc5xxx_gpio *pgpio =
+		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	GP_SIMP_ENABLE_I(GPIO_USB_8);	/* HEX Bit 3 */
+	GP_SIMP_ENABLE_I(GPIO_USB_7);	/* HEX Bit 2 */
+	GP_SIMP_ENABLE_I(GPIO_USB_6);	/* HEX Bit 1 */
+	GP_SIMP_ENABLE_I(GPIO_USB_0);	/* HEX Bit 0 */
+	GP_SIMP_ENABLE_I(GPIO_PSC3_0);	/* Switch Menue A */
+	GP_SIMP_ENABLE_I(GPIO_PSC3_1);	/* Switch Menue B */
+	GP_SIMP_ENABLE_I(GPIO_PSC3_6);	/* Switch Cold_Warm */
+	GP_SIMP_ENABLE_I(GPIO_PSC3_7);	/* Switch Restart */
+	GP_SINT_ENABLE_O(GPIO_PSC3_8, 0);	/* LED H2 */
+	GP_SINT_ENABLE_O(GPIO_USB1_9, 0);	/* LED H3 */
+	GP_TIMER_ENABLE_O(4, 0);	/* LED H4 */
+	GP_TIMER_ENABLE_O(5, 0);	/* LED H5 */
+	GP_TIMER_ENABLE_O(3, 0);	/* LED HB */
+	GP_TIMER_ENABLE_O(1, 0);	/* RES_COLDSTART */
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[]		= "key_magic";
+static uchar kbd_command_prefix[]	= "key_cmd";
+
+struct kbd_data_t {
+	char s1;
+};
+
+struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
+{
+	volatile struct mpc5xxx_gpio *pgpio =
+		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \
+			GP_SIMP_GET_I(GPIO_USB_7) << 2 | \
+			GP_SIMP_GET_I(GPIO_USB_6) << 1 | \
+			GP_SIMP_GET_I(GPIO_USB_0) << 0;
+	return kbd_data;
+}
+
+static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
+{
+	char s1 = str[0];
+
+	if (s1 >= '0' && s1 <= '9')
+		s1 -= '0';
+	else if (s1 >= 'a' && s1 <= 'f')
+		s1 = s1 - 'a' + 10;
+	else if (s1 >= 'A' && s1 <= 'F')
+		s1 = s1 - 'A' + 10;
+	else
+		return -1;
+
+	if (s1 != kbd_data->s1) return -1;
+	return 0;
+}
+
+static char *key_match (const struct kbd_data_t *kbd_data)
+{
+	char magic[sizeof (kbd_magic_prefix) + 1];
+	char *suffix;
+	char *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can be appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix = kbd_magic_keys; *suffix ||
+		     suffix == kbd_magic_keys; ++suffix) {
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+
+		if (compare_magic(kbd_data, getenv(magic)) == 0) {
+			char cmd_name[sizeof (kbd_command_prefix) + 1];
+			char *cmd;
+
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			cmd = getenv (cmd_name);
+
+			return (cmd);
+		}
+	}
+
+	return (NULL);
+}
+
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r (void)
+{
+	/* Init the I/O ports */
+	init_ports ();
+
+#ifdef CONFIG_PREBOOT
+	struct kbd_data_t kbd_data;
+	/* Decode keys */
+	char *str = strdup (key_match (get_keys (&kbd_data)));
+	/* Set or delete definition */
+	setenv ("preboot", str);
+	free (str);
+#endif /* CONFIG_PREBOOT */
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	/* Interbus enable it here ?? */
+	*(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1;
+	return 0;
+}
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+	/* Trigger HW Watchdog with TIMER_0 */
+	*(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1;
+	*(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0;
+}
+#endif
diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
index dede996..ace4aa2 100644
--- a/board/v38b/v38b.c
+++ b/board/v38b/v38b.c
@@ -191,16 +191,8 @@ int checkboard (void)
 	return 0;
 }
 
-
-int board_early_init_r(void)
+int board_early_init_f(void)
 {
-	/*
-	 * Now, when we are in RAM, enable flash write access for the
-	 * detection process.  Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-
 #ifdef CONFIG_HW_WATCHDOG
 	/*
 	 * Enable and configure the direction (output) of PSC3_9 - watchdog
@@ -210,6 +202,17 @@ int board_early_init_r(void)
 	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
 	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
 #endif /* CONFIG_HW_WATCHDOG */
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write access for the
+	 * detection process.  Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 
 	/*
 	 * Enable GPIO_WKUP_7 to "read the status of the actual power
diff --git a/board/xilinx/ml300/Makefile b/board/xilinx/ml300/Makefile
index 02c22fb..05ad235 100644
--- a/board/xilinx/ml300/Makefile
+++ b/board/xilinx/ml300/Makefile
@@ -28,7 +28,7 @@ $(shell mkdir -p $(obj)../xilinx_enet)
 $(shell mkdir -p $(obj)../xilinx_iic)
 endif
 
-INCS		:= -I../ml300 -I../common -I../xilinx_enet -I../xilinx_iic
+INCS		:= -I../common -I../xilinx_enet -I../xilinx_iic
 CFLAGS		+= $(INCS)
 HOST_CFLAGS	+= $(INCS)
 
diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c
index dad562f..60f0bc2 100644
--- a/board/xilinx/ml300/ml300.c
+++ b/board/xilinx/ml300/ml300.c
@@ -38,9 +38,9 @@
  *
  */
 
+#include <config.h>
 #include <common.h>
 #include <asm/processor.h>
-#include "xparameters.h"
 
 #ifdef CFG_ENV_IS_IN_EEPROM
 extern void convert_env(void);
diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c
index c204b88..9b03f89 100644
--- a/board/xilinx/ml300/serial.c
+++ b/board/xilinx/ml300/serial.c
@@ -40,8 +40,7 @@
 #include <asm/processor.h>
 #include <common.h>
 #include <command.h>
-#include <configs/ml300.h>
-#include "xparameters.h"
+#include <config.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c
index b30e897..f159cb6 100644
--- a/board/xilinx/xilinx_enet/emac_adapter.c
+++ b/board/xilinx/xilinx_enet/emac_adapter.c
@@ -37,9 +37,9 @@
 *
 ******************************************************************************/
 
+#include <config.h>
 #include <common.h>
 #include <net.h>
-#include "xparameters.h"
 #include "xemac.h"
 
 #if defined(XPAR_EMAC_0_DEVICE_ID)
diff --git a/board/xilinx/xilinx_enet/xemac.h b/board/xilinx/xilinx_enet/xemac.h
index ed704bf..584cb7a 100644
--- a/board/xilinx/xilinx_enet/xemac.h
+++ b/board/xilinx/xilinx_enet/xemac.h
@@ -257,9 +257,9 @@
 
 /***************************** Include Files *********************************/
 
+#include <config.h>
 #include "xbasic_types.h"
 #include "xstatus.h"
-#include "xparameters.h"
 #include "xpacket_fifo_v1_00_b.h"	/* Uses v1.00b of Packet Fifo */
 #include "xdma_channel.h"
 
diff --git a/board/xilinx/xilinx_enet/xemac_g.c b/board/xilinx/xilinx_enet/xemac_g.c
index 9340f91..d985157 100644
--- a/board/xilinx/xilinx_enet/xemac_g.c
+++ b/board/xilinx/xilinx_enet/xemac_g.c
@@ -43,7 +43,7 @@
 *
 *******************************************************************/
 
-#include "xparameters.h"
+#include <config.h>
 #include "xemac.h"
 
 /*
diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c
index 163fe15..37dce03 100644
--- a/board/xilinx/xilinx_iic/iic_adapter.c
+++ b/board/xilinx/xilinx_iic/iic_adapter.c
@@ -37,10 +37,10 @@
 *
 ******************************************************************************/
 
+#include <config.h>
 #include <common.h>
 #include <environment.h>
 #include <net.h>
-#include "xparameters.h"
 
 #ifdef CFG_ENV_IS_IN_EEPROM
 #include <i2c.h>
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index 5d2cd65..a417143 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -448,7 +448,7 @@ static void dfc_gpio_init(void)
  * Members with a "?" were not set in the merged testing-NAND branch,
  * so they are not set here either.
  */
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
 
@@ -576,6 +576,7 @@ void board_nand_init(struct nand_chip *nand)
 	nand->cmdfunc = dfc_cmdfunc;
 	nand->autooob = &delta_oob;
 	nand->badblock_pattern = &delta_bbt_descr;
+	return 0;
 }
 
 #else
diff --git a/common/Makefile b/common/Makefile
index 07ddc95..6f81c4a 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -27,8 +27,7 @@ LIB	= $(obj)libcommon.a
 
 AOBJS	=
 
-COBJS	= main.o ACEX1K.o altera.o bedbug.o circbuf.o \
-	  cmd_ace.o cmd_autoscript.o \
+COBJS	= main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
 	  cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \
 	  cmd_cache.o cmd_console.o \
 	  cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \
@@ -41,7 +40,7 @@ COBJS	= main.o ACEX1K.o altera.o bedbug.o circbuf.o \
 	  cmd_pci.o cmd_pcmcia.o cmd_portio.o \
 	  cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \
 	  cmd_usb.o cmd_vfd.o \
-	  command.o console.o devices.o dlmalloc.o docecc.o \
+	  command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
 	  environment.o env_common.o \
 	  env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
 	  env_nvram.o env_nowhere.o \
diff --git a/common/altera.c b/common/altera.c
index ebd5038..06e8a95 100644
--- a/common/altera.c
+++ b/common/altera.c
@@ -50,15 +50,20 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize )
 {
 	int ret_val = FPGA_FAIL;	/* assume a failure */
 
-	if (!altera_validate (desc, __FUNCTION__)) {
+	if (!altera_validate (desc, (char *)__FUNCTION__)) {
 		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
 	} else {
 		switch (desc->family) {
 		case Altera_ACEX1K:
+		case Altera_CYC2:
 #if (CONFIG_FPGA & CFG_ACEX1K)
 			PRINTF ("%s: Launching the ACEX1K Loader...\n",
 					__FUNCTION__);
 			ret_val = ACEX1K_load (desc, buf, bsize);
+#elif (CONFIG_FPGA & CFG_CYCLON2)
+			PRINTF ("%s: Launching the CYCLON II Loader...\n",
+					__FUNCTION__);
+			ret_val = CYC2_load (desc, buf, bsize);
 #else
 			printf ("%s: No support for ACEX1K devices.\n",
 					__FUNCTION__);
@@ -78,7 +83,7 @@ int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
 {
 	int ret_val = FPGA_FAIL;	/* assume a failure */
 
-	if (!altera_validate (desc, __FUNCTION__)) {
+	if (!altera_validate (desc, (char *)__FUNCTION__)) {
 		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
 	} else {
 		switch (desc->family) {
@@ -106,13 +111,16 @@ int altera_info( Altera_desc *desc )
 {
 	int ret_val = FPGA_FAIL;
 
-	if (altera_validate (desc, __FUNCTION__)) {
+	if (altera_validate (desc, (char *)__FUNCTION__)) {
 		printf ("Family:        \t");
 		switch (desc->family) {
 		case Altera_ACEX1K:
 			printf ("ACEX1K\n");
 			break;
 			/* Add new family types here */
+		case Altera_CYC2:
+			printf ("CYCLON II\n");
+			break;
 		default:
 			printf ("Unknown family type, %d\n", desc->family);
 		}
@@ -147,8 +155,11 @@ int altera_info( Altera_desc *desc )
 			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
 			switch (desc->family) {
 			case Altera_ACEX1K:
+			case Altera_CYC2:
 #if (CONFIG_FPGA & CFG_ACEX1K)
 				ACEX1K_info (desc);
+#elif (CONFIG_FPGA & CFG_CYCLON2)
+				CYC2_info (desc);
 #else
 				/* just in case */
 				printf ("%s: No support for ACEX1K devices.\n",
@@ -176,7 +187,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset)
 {
 	int ret_val = FPGA_FAIL;	/* assume a failure */
 
-	if (!altera_validate (desc, __FUNCTION__)) {
+	if (!altera_validate (desc, (char *)__FUNCTION__)) {
 		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
 	} else {
 		switch (desc->family) {
@@ -188,6 +199,14 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset)
 					__FUNCTION__);
 #endif
 			break;
+		case Altera_CYC2:
+#if (CONFIG_FPGA & CFG_CYCLON2)
+			ret_val = CYC2_reloc (desc, reloc_offset);
+#else
+			printf ("%s: No support for CYCLON II devices.\n",
+					__FUNCTION__);
+#endif
+			break;
 			/* Add new family types here */
 		default:
 			printf ("%s: Unsupported family type, %d\n",
diff --git a/common/cmd_ace.c b/common/cmd_ace.c
deleted file mode 100644
index b6d6105..0000000
--- a/common/cmd_ace.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * Copyright (c) 2004 Picture Elements, Inc.
- *    Stephen Williams (XXXXXXXXXXXXXXXX)
- *
- *    This source code is free software; you can redistribute it
- *    and/or modify it in source code form under the terms of the GNU
- *    General Public License as published by the Free Software
- *    Foundation; either version 2 of the License, or (at your option)
- *    any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
- */
-#ident "$Id:$"
-
-/*
- * The Xilinx SystemACE chip support is activated by defining
- * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE
- * to set the base address of the device. This code currently
- * assumes that the chip is connected via a byte-wide bus.
- *
- * The CONFIG_SYSTEMACE also adds to fat support the device class
- * "ace" that allows the user to execute "fatls ace 0" and the
- * like. This works by making the systemace_get_dev function
- * available to cmd_fat.c:get_dev and filling in a block device
- * description that has all the bits needed for FAT support to
- * read sectors.
- *
- * According to Xilinx technical support, before accessing the
- * SystemACE CF you need to set the following control bits:
- * 	FORCECFGMODE : 1
- * 	CFGMODE : 0
- * 	CFGSTART : 0
- */
-
-# include  <common.h>
-# include  <command.h>
-# include  <systemace.h>
-# include  <part.h>
-# include  <asm/io.h>
-
-#ifdef CONFIG_SYSTEMACE
-
-/*
- * The ace_readw and writew functions read/write 16bit words, but the
- * offset value is the BYTE offset as most used in the Xilinx
- * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined
- * to be the base address for the chip, usually in the local
- * peripheral bus.
- */
-static unsigned ace_readw(unsigned offset)
-{
-#if (CFG_SYSTEMACE_WIDTH == 8)
-  u16 temp;
-
-#if !defined(__BIG_ENDIAN)
-  temp =((u16)readb(CFG_SYSTEMACE_BASE+offset) << 8);
-  temp |= (u16)readb(CFG_SYSTEMACE_BASE+offset+1);
-#else
-  temp = (u16)readb(CFG_SYSTEMACE_BASE+offset);
-  temp |=((u16)readb(CFG_SYSTEMACE_BASE+offset+1) << 8);
-#endif
-  return temp;
-#else
-  return readw(CFG_SYSTEMACE_BASE+offset);
-#endif
-}
-
-static void ace_writew(unsigned val, unsigned offset)
-{
-#if (CFG_SYSTEMACE_WIDTH == 8)
-#if !defined(__BIG_ENDIAN)
-  writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset);
-  writeb((u8)val, CFG_SYSTEMACE_BASE+offset+1);
-#else
-  writeb((u8)val, CFG_SYSTEMACE_BASE+offset);
-  writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset+1);
-#endif
-#else
-  writew(val, CFG_SYSTEMACE_BASE+offset);
-#endif
-}
-
-/* */
-
-static unsigned long systemace_read(int dev,
-				    unsigned long start,
-				    unsigned long blkcnt,
-				    unsigned long *buffer);
-
-static block_dev_desc_t systemace_dev = {0};
-
-static int get_cf_lock(void)
-{
-      int retry = 10;
-
-	/* CONTROLREG = LOCKREG */
-      unsigned val=ace_readw(0x18);
-      val|=0x0002;
-      ace_writew((val&0xffff), 0x18);
-
-	/* Wait for MPULOCK in STATUSREG[15:0] */
-      while (! (ace_readw(0x04) & 0x0002)) {
-
-	    if (retry < 0)
-		  return -1;
-
-	    udelay(100000);
-	    retry -= 1;
-      }
-
-      return 0;
-}
-
-static void release_cf_lock(void)
-{
-	unsigned val=ace_readw(0x18);
-	val&=~(0x0002);
-	ace_writew((val&0xffff), 0x18);
-}
-
-block_dev_desc_t *  systemace_get_dev(int dev)
-{
-	/* The first time through this, the systemace_dev object is
-	   not yet initialized. In that case, fill it in. */
-      if (systemace_dev.blksz == 0) {
-	    systemace_dev.if_type   = IF_TYPE_UNKNOWN;
-	    systemace_dev.dev	    = 0;
-	    systemace_dev.part_type = PART_TYPE_UNKNOWN;
-	    systemace_dev.type      = DEV_TYPE_HARDDISK;
-	    systemace_dev.blksz     = 512;
-	    systemace_dev.removable = 1;
-	    systemace_dev.block_read = systemace_read;
-
-	    init_part(&systemace_dev);
-
-      }
-
-      return &systemace_dev;
-}
-
-/*
- * This function is called (by dereferencing the block_read pointer in
- * the dev_desc) to read blocks of data. The return value is the
- * number of blocks read. A zero return indicates an error.
- */
-static unsigned long systemace_read(int dev,
-				    unsigned long start,
-				    unsigned long blkcnt,
-				    unsigned long *buffer)
-{
-      int retry;
-      unsigned blk_countdown;
-      unsigned char*dp = (unsigned char*)buffer;
-      unsigned val;
-
-      if (get_cf_lock() < 0) {
-	    unsigned status = ace_readw(0x04);
-
-	      /* If CFDETECT is false, card is missing. */
-	    if (! (status&0x0010)) {
-		  printf("** CompactFlash card not present. **\n");
-		  return 0;
-	    }
-
-	    printf("**** ACE locked away from me (STATUSREG=%04x)\n", status);
-	    return 0;
-      }
-
-#ifdef DEBUG_SYSTEMACE
-      printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
-#endif
-
-      retry = 2000;
-      for (;;) {
-	    val = ace_readw(0x04);
-
-	      /* If CFDETECT is false, card is missing. */
-	    if (! (val & 0x0010)) {
-		  printf("**** ACE CompactFlash not found.\n");
-		  release_cf_lock();
-		  return 0;
-	    }
-
-	      /* If RDYFORCMD, then we are ready to go. */
-	    if (val & 0x0100)
-		  break;
-
-	    if (retry < 0) {
-		  printf("**** SystemACE not ready.\n");
-		  release_cf_lock();
-		  return 0;
-	    }
-
-	    udelay(1000);
-	    retry -= 1;
-      }
-
-	/* The SystemACE can only transfer 256 sectors at a time, so
-	   limit the current chunk of sectors. The blk_countdown
-	   variable is the number of sectors left to transfer. */
-
-      blk_countdown = blkcnt;
-      while (blk_countdown > 0) {
-	    unsigned trans = blk_countdown;
-
-	    if (trans > 256) trans = 256;
-
-#ifdef DEBUG_SYSTEMACE
-	    printf("... transfer %lu sector in a chunk\n", trans);
-#endif
-	      /* Write LBA block address */
-	    ace_writew((start>> 0) & 0xffff, 0x10);
-	    ace_writew((start>>16) & 0x00ff, 0x12);
-
-	      /* NOTE: in the Write Sector count below, a count of 0
-		 causes a transfer of 256, so &0xff gives the right
-		 value for whatever transfer count we want. */
-
-	      /* Write sector count | ReadMemCardData. */
-	    ace_writew((trans&0xff) | 0x0300, 0x14);
-
-	    /* Reset the configruation controller */
-	    val = ace_readw(0x18);
-	    val|=0x0080;
-	    ace_writew(val, 0x18);
-
-	    retry = trans * 16;
-	    while (retry > 0) {
-		  int idx;
-
-		    /* Wait for buffer to become ready. */
-		  while (! (ace_readw(0x04) & 0x0020)) {
-			udelay(100);
-		  }
-
-		    /* Read 16 words of 2bytes from the sector buffer. */
-		  for (idx = 0 ;  idx < 16 ;  idx += 1) {
-			unsigned short val = ace_readw(0x40);
-			*dp++ = val & 0xff;
-			*dp++ = (val>>8) & 0xff;
-		  }
-
-		  retry -= 1;
-	    }
-
-	    /* Clear the configruation controller reset */
-	    val = ace_readw(0x18);
-	    val&=~0x0080;
-	    ace_writew(val, 0x18);
-
-	      /* Count the blocks we transfer this time. */
-	    start += trans;
-	    blk_countdown -= trans;
-      }
-
-      release_cf_lock();
-
-      return blkcnt;
-}
-#endif	/* CONFIG_SYSTEMACE */
diff --git a/common/cmd_boot.c b/common/cmd_boot.c
index 182e2ab..e68f16f 100644
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -83,7 +83,7 @@ U_BOOT_CMD(
 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 
 U_BOOT_CMD(
-	reset, CFG_MAXARGS, 1,	do_reset,
+	reset, 1, 0,	do_reset,
 	"reset   - Perform RESET of the CPU\n",
 	NULL
 );
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 3091a58..c0ed076 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -242,26 +242,26 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	len_ptr = (ulong *)data;
 
-#if defined(__PPC__)
-	if (hdr->ih_arch != IH_CPU_PPC)
-#elif defined(__ARM__)
+#if defined(__ARM__)
 	if (hdr->ih_arch != IH_CPU_ARM)
+#elif defined(__avr32__)
+	if (hdr->ih_arch != IH_CPU_AVR32)
+#elif defined(__bfin__)
+	if (hdr->ih_arch != IH_CPU_BLACKFIN)
 #elif defined(__I386__)
 	if (hdr->ih_arch != IH_CPU_I386)
-#elif defined(__mips__)
-	if (hdr->ih_arch != IH_CPU_MIPS)
-#elif defined(__nios__)
-	if (hdr->ih_arch != IH_CPU_NIOS)
 #elif defined(__M68K__)
 	if (hdr->ih_arch != IH_CPU_M68K)
 #elif defined(__microblaze__)
 	if (hdr->ih_arch != IH_CPU_MICROBLAZE)
+#elif defined(__mips__)
+	if (hdr->ih_arch != IH_CPU_MIPS)
+#elif defined(__nios__)
+	if (hdr->ih_arch != IH_CPU_NIOS)
 #elif defined(__nios2__)
 	if (hdr->ih_arch != IH_CPU_NIOS2)
-#elif defined(__blackfin__)
-	if (hdr->ih_arch != IH_CPU_BLACKFIN)
-#elif defined(__avr32__)
-	if (hdr->ih_arch != IH_CPU_AVR32)
+#elif defined(__PPC__)
+	if (hdr->ih_arch != IH_CPU_PPC)
 #else
 # error Unknown CPU type
 #endif
@@ -833,10 +833,6 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 			printf ("ERROR: flat device tree size does not agree with image\n");
 			return;
 		}
-
-	} else if (getenv("disable_of") == NULL) {
-		printf ("ERROR: bootm needs flat device tree as third argument\n");
-		return;
 	}
 #endif
 	if (!data) {
@@ -913,23 +909,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 
 	SHOW_BOOT_PROGRESS (15);
 
-#ifndef CONFIG_OF_FLAT_TREE
-
 #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
 	unlock_ram_in_cache();
 #endif
 
-	/*
-	 * Linux Kernel Parameters:
-	 *   r3: ptr to board info data
-	 *   r4: initrd_start or 0 if no initrd
-	 *   r5: initrd_end - unused if r4 is 0
-	 *   r6: Start of command line string
-	 *   r7: End   of command line string
-	 */
-	(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
-
-#else	/* CONFIG_OF_FLAT_TREE */
+#ifdef CONFIG_OF_FLAT_TREE
 	/* move of_flat_tree if needed */
 	if (of_data) {
 		ulong of_start, of_len;
@@ -948,30 +932,36 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 			of_start, of_start + of_len - 1);
 		memmove ((void *)of_start, (void *)of_data, of_len);
 	}
+#endif
 
-	ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
-	/* ft_dump_blob(of_flat_tree); */
-
-#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
-	unlock_ram_in_cache();
+	/*
+	 * Linux Kernel Parameters (passing board info data):
+	 *   r3: ptr to board info data
+	 *   r4: initrd_start or 0 if no initrd
+	 *   r5: initrd_end - unused if r4 is 0
+	 *   r6: Start of command line string
+	 *   r7: End   of command line string
+	 */
+#ifdef CONFIG_OF_FLAT_TREE
+	if (!of_flat_tree)	/* no device tree; boot old style */
 #endif
+		(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
+		/* does not return */
+
+#ifdef CONFIG_OF_FLAT_TREE
 	/*
-	 * Linux Kernel Parameters:
+	 * Linux Kernel Parameters (passing device tree):
 	 *   r3: ptr to OF flat tree, followed by the board info data
 	 *   r4: physical pointer to the kernel itself
 	 *   r5: NULL
 	 *   r6: NULL
 	 *   r7: NULL
 	 */
-	if (getenv("disable_of") != NULL)
-		(*kernel) ((bd_t *)of_flat_tree, initrd_start, initrd_end,
-			cmd_start, cmd_end);
-	else {
-		ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
-		/* ft_dump_blob(of_flat_tree); */
-		(*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
-	}
-#endif	/* CONFIG_OF_FLAT_TREE */
+	ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
+	/* ft_dump_blob(of_flat_tree); */
+
+	(*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
+#endif
 }
 #endif /* CONFIG_PPC */
 
@@ -1364,19 +1354,20 @@ print_type (image_header_t *hdr)
 	case IH_CPU_ALPHA:	arch = "Alpha";			break;
 	case IH_CPU_ARM:	arch = "ARM";			break;
 	case IH_CPU_AVR32:	arch = "AVR32";			break;
+	case IH_CPU_BLACKFIN:	arch = "Blackfin";		break;
 	case IH_CPU_I386:	arch = "Intel x86";		break;
 	case IH_CPU_IA64:	arch = "IA64";			break;
-	case IH_CPU_MIPS:	arch = "MIPS";			break;
+	case IH_CPU_M68K:	arch = "M68K"; 			break;
+	case IH_CPU_MICROBLAZE:	arch = "Microblaze"; 		break;
 	case IH_CPU_MIPS64:	arch = "MIPS 64 Bit";		break;
+	case IH_CPU_MIPS:	arch = "MIPS";			break;
+	case IH_CPU_NIOS2:	arch = "Nios-II";		break;
+	case IH_CPU_NIOS:	arch = "Nios";			break;
 	case IH_CPU_PPC:	arch = "PowerPC";		break;
 	case IH_CPU_S390:	arch = "IBM S390";		break;
 	case IH_CPU_SH:		arch = "SuperH";		break;
-	case IH_CPU_SPARC:	arch = "SPARC";			break;
 	case IH_CPU_SPARC64:	arch = "SPARC 64 Bit";		break;
-	case IH_CPU_M68K:	arch = "M68K"; 			break;
-	case IH_CPU_MICROBLAZE:	arch = "Microblaze"; 		break;
-	case IH_CPU_NIOS:	arch = "Nios";			break;
-	case IH_CPU_NIOS2:	arch = "Nios-II";		break;
+	case IH_CPU_SPARC:	arch = "SPARC";			break;
 	default:		arch = "Unknown Architecture";	break;
 	}
 
diff --git a/common/cmd_date.c b/common/cmd_date.c
index 84932f7..33d2e56 100644
--- a/common/cmd_date.c
+++ b/common/cmd_date.c
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <command.h>
 #include <rtc.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -44,6 +45,11 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	struct rtc_time tm;
 	int rcode = 0;
+	int old_bus;
+
+	/* switch to correct I2C bus */
+	old_bus = I2C_GET_BUS();
+	I2C_SET_BUS(CFG_RTC_BUS_NUM);
 
 	switch (argc) {
 	case 2:			/* set date & time */
@@ -56,7 +62,7 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			/* insert new date & time */
 			if (mk_date (argv[1], &tm) != 0) {
 				puts ("## Bad date format\n");
-				return 1;
+				break;
 			}
 			/* and write to RTC */
 			rtc_set (&tm);
@@ -71,11 +77,15 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 				"unknown " : RELOC(weekdays[tm.tm_wday]),
 			tm.tm_hour, tm.tm_min, tm.tm_sec);
 
-		return 0;
+		break;
 	default:
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		rcode = 1;
 	}
+
+	/* switch back to original I2C bus */
+	I2C_SET_BUS(old_bus);
+
 	return rcode;
 }
 
diff --git a/common/cmd_dtt.c b/common/cmd_dtt.c
index 9db64e9..4f7b049 100644
--- a/common/cmd_dtt.c
+++ b/common/cmd_dtt.c
@@ -28,19 +28,27 @@
 #if (CONFIG_COMMANDS & CFG_CMD_DTT)
 
 #include <dtt.h>
+#include <i2c.h>
 
 int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	int i;
 	unsigned char sensors[] = CONFIG_DTT_SENSORS;
+	int old_bus;
+
+	/* switch to correct I2C bus */
+	old_bus = I2C_GET_BUS();
+	I2C_SET_BUS(CFG_DTT_BUS_NUM);
 
 	/*
 	 * Loop through sensors, read
 	 * temperature, and output it.
 	 */
-	for (i = 0; i < sizeof (sensors); i++) {
+	for (i = 0; i < sizeof (sensors); i++)
 		printf ("DTT%d: %i C\n", i + 1, dtt_get_temp (sensors[i]));
-	}
+
+	/* switch back to original I2C bus */
+	I2C_SET_BUS(old_bus);
 
 	return 0;
 }	/* do_dtt() */
diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index 1d92bb3..0e3d56f 100644
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -79,7 +79,7 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  * be either an ELF image or a raw binary.  Will attempt to setup the
  * bootline and other parameters correctly.
  * ====================================================================== */
-int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	unsigned long addr;		/* Address of image            */
 	unsigned long bootaddr;		/* Address to put the bootline */
@@ -96,12 +96,10 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 * If we don't know where the image is then we're done.
 	 */
 
-	if ((tmp = getenv ("loadaddr")) != NULL) {
-		addr = simple_strtoul (tmp, NULL, 16);
-	} else {
-		puts ("No load address provided\n");
-		return 1;
-	}
+	if (argc < 2)
+		addr = load_addr;
+	else
+		addr = simple_strtoul (argv[1], NULL, 16);
 
 #if (CONFIG_COMMANDS & CFG_CMD_NET)
 	/* Check to see if we need to tftp the image ourselves before starting */
diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c
index 5db42f2..94bd9b6 100644
--- a/common/cmd_ext2.c
+++ b/common/cmd_ext2.c
@@ -33,6 +33,7 @@
  * Ext2fs support
  */
 #include <common.h>
+#include <part.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_EXT2)
 #include <config.h>
@@ -57,41 +58,6 @@
 #define PRINTF(fmt,args...)
 #endif
 
-static block_dev_desc_t *get_dev (char* ifname, int dev)
-{
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
-	if (strncmp(ifname,"ide",3)==0) {
-		extern block_dev_desc_t * ide_get_dev(int dev);
-		return((dev >= CFG_IDE_MAXDEVICE) ? NULL : ide_get_dev(dev));
-	}
-#endif
-#if (CONFIG_COMMANDS & CFG_CMD_SCSI)
-	if (strncmp(ifname,"scsi",4)==0) {
-		extern block_dev_desc_t * scsi_get_dev(int dev);
-		return((dev >= CFG_SCSI_MAXDEVICE) ? NULL : scsi_get_dev(dev));
-	}
-#endif
-#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE))
-	if (strncmp(ifname,"usb",3)==0) {
-		extern block_dev_desc_t * usb_stor_get_dev(int dev);
-		return((dev >= USB_MAX_STOR_DEV) ? NULL : usb_stor_get_dev(dev));
-	}
-#endif
-#if defined(CONFIG_MMC)
-	if (strncmp(ifname,"mmc",3)==0) {
-		extern block_dev_desc_t *  mmc_get_dev(int dev);
-		return((dev >= 1) ? NULL : mmc_get_dev(dev));
-	}
-#endif
-#if defined(CONFIG_SYSTEMACE)
-	if (strcmp(ifname,"ace")==0) {
-		extern block_dev_desc_t *  systemace_get_dev(int dev);
-		return((dev >= 1) ? NULL : systemace_get_dev(dev));
-	}
-#endif
-	return(NULL);
-}
-
 int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	char *filename = "/";
@@ -106,7 +72,7 @@ int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return(1);
 	}
 	dev = (int)simple_strtoul (argv[2], &ep, 16);
-	dev_desc=get_dev(argv[1],dev);
+	dev_desc = get_dev(argv[1],dev);
 
 	if (dev_desc == NULL) {
 		printf ("\n** Block device %s %d not supported\n", argv[1], dev);
@@ -210,7 +176,7 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 
 	dev = (int)simple_strtoul (argv[2], &ep, 16);
-	dev_desc=get_dev(argv[1],dev);
+	dev_desc = get_dev(argv[1],dev);
 	if (dev_desc==NULL) {
 		printf ("\n** Block device %s %d not supported\n", argv[1], dev);
 		return(1);
diff --git a/common/cmd_fat.c b/common/cmd_fat.c
index 6844c10..afaf299 100644
--- a/common/cmd_fat.c
+++ b/common/cmd_fat.c
@@ -29,6 +29,7 @@
 #include <s_record.h>
 #include <net.h>
 #include <ata.h>
+#include <part.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_FAT)
 
@@ -37,42 +38,6 @@
 #include <fat.h>
 
 
-block_dev_desc_t *get_dev (char* ifname, int dev)
-{
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
-	if (strncmp(ifname,"ide",3)==0) {
-		extern block_dev_desc_t * ide_get_dev(int dev);
-		return(ide_get_dev(dev));
-	}
-#endif
-#if (CONFIG_COMMANDS & CFG_CMD_SCSI)
-	if (strncmp(ifname,"scsi",4)==0) {
-		extern block_dev_desc_t * scsi_get_dev(int dev);
-		return(scsi_get_dev(dev));
-	}
-#endif
-#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE))
-	if (strncmp(ifname,"usb",3)==0) {
-		extern block_dev_desc_t * usb_stor_get_dev(int dev);
-		return(usb_stor_get_dev(dev));
-	}
-#endif
-#if defined(CONFIG_MMC)
-	if (strncmp(ifname,"mmc",3)==0) {
-		extern block_dev_desc_t *  mmc_get_dev(int dev);
-		return(mmc_get_dev(dev));
-	}
-#endif
-#if defined(CONFIG_SYSTEMACE)
-	if (strcmp(ifname,"ace")==0) {
-		extern block_dev_desc_t *  systemace_get_dev(int dev);
-		return(systemace_get_dev(dev));
-	}
-#endif
-	return NULL;
-}
-
-
 int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	long size;
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index 9a01e7d..3444091 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -55,6 +55,7 @@ static int fpga_get_op (char *opstr);
 #define FPGA_LOAD   1
 #define FPGA_LOADB  2
 #define FPGA_DUMP   3
+#define FPGA_LOADMK 4
 
 /* Convert bitstream data and load into the fpga */
 int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
@@ -251,6 +252,23 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		rc = fpga_loadbitstream(dev, fpga_data, data_size);
 		break;
 
+	case FPGA_LOADMK:
+		{
+			image_header_t header;
+			image_header_t *hdr = &header;
+			ulong	data;
+
+			memmove (&header, (char *)fpga_data, sizeof(image_header_t));
+			if (ntohl(hdr->ih_magic) != IH_MAGIC) {
+				puts ("Bad Magic Number\n");
+				return 1;
+			}
+			data = ((ulong)fpga_data + sizeof(image_header_t));
+			data_size  = ntohl(hdr->ih_size);
+			rc = fpga_load (dev, (void *)data, data_size);
+		}
+		break;
+
 	case FPGA_DUMP:
 		rc = fpga_dump (dev, fpga_data, data_size);
 		break;
@@ -282,6 +300,8 @@ static int fpga_get_op (char *opstr)
 		op = FPGA_LOADB;
 	} else if (!strcmp ("load", opstr)) {
 		op = FPGA_LOAD;
+	} else if (!strcmp ("loadmk", opstr)) {
+		op = FPGA_LOADMK;
 	} else if (!strcmp ("dump", opstr)) {
 		op = FPGA_DUMP;
 	}
@@ -299,5 +319,6 @@ U_BOOT_CMD (fpga, 6, 1, do_fpga,
 	    "\tinfo\tlist known device information\n"
 	    "\tload\tLoad device from memory buffer\n"
 	    "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
+	    "\tloadmk\tLoad device generated with mkimage\n"
 	    "\tdump\tLoad device to memory buffer\n");
 #endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index c543bb5..34571ee 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -101,8 +101,31 @@ static uchar	i2c_mm_last_chip;
 static uint	i2c_mm_last_addr;
 static uint	i2c_mm_last_alen;
 
+/* If only one I2C bus is present, the list of devices to ignore when
+ * the probe command is issued is represented by a 1D array of addresses.
+ * When multiple buses are present, the list is an array of bus-address
+ * pairs.  The following macros take care of this */
+
 #if defined(CFG_I2C_NOPROBES)
+#if defined(CONFIG_I2C_MULTI_BUS)
+static struct
+{
+	uchar	bus;
+	uchar	addr;
+} i2c_no_probes[] = CFG_I2C_NOPROBES;
+#define GET_BUS_NUM	i2c_get_bus_num()
+#define COMPARE_BUS(b,i)	(i2c_no_probes[(i)].bus == (b))
+#define COMPARE_ADDR(a,i)	(i2c_no_probes[(i)].addr == (a))
+#define NO_PROBE_ADDR(i)	i2c_no_probes[(i)].addr
+#else		/* single bus */
 static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
+#define GET_BUS_NUM	0
+#define COMPARE_BUS(b,i)	((b) == 0)	/* Make compiler happy */
+#define COMPARE_ADDR(a,i)	(i2c_no_probes[(i)] == (a))
+#define NO_PROBE_ADDR(i)	i2c_no_probes[(i)]
+#endif	/* CONFIG_MULTI_BUS */
+
+#define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
 #endif
 
 static int
@@ -151,7 +174,7 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		 */
 		addr = simple_strtoul(argv[2], NULL, 16);
 		alen = 1;
-		for(j = 0; j < 8; j++) {
+		for (j = 0; j < 8; j++) {
 			if (argv[2][j] == '.') {
 				alen = argv[2][j+1] - '0';
 				if (alen > 4) {
@@ -159,9 +182,8 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 					return 1;
 				}
 				break;
-			} else if (argv[2][j] == '\0') {
+			} else if (argv[2][j] == '\0')
 				break;
-			}
 		}
 
 		/*
@@ -185,9 +207,9 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 		linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
 
-		if(i2c_read(chip, addr, alen, linebuf, linebytes) != 0) {
+		if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
 			puts ("Error reading the chip.\n");
-		} else {
+		else {
 			printf("%04x:", addr);
 			cp = linebuf;
 			for (j=0; j<linebytes; j++) {
@@ -256,17 +278,16 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 */
 	addr = simple_strtoul(argv[2], NULL, 16);
 	alen = 1;
-	for(j = 0; j < 8; j++) {
+	for (j = 0; j < 8; j++) {
 		if (argv[2][j] == '.') {
 			alen = argv[2][j+1] - '0';
-			if(alen > 4) {
+			if (alen > 4) {
 				printf ("Usage:\n%s\n", cmdtp->usage);
 				return 1;
 			}
 			break;
-		} else if (argv[2][j] == '\0') {
+		} else if (argv[2][j] == '\0')
 			break;
-		}
 	}
 
 	/*
@@ -277,16 +298,14 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	/*
 	 * Optional count
 	 */
-	if(argc == 5) {
+	if (argc == 5)
 		count = simple_strtoul(argv[4], NULL, 16);
-	} else {
+	else
 		count = 1;
-	}
 
 	while (count-- > 0) {
-		if(i2c_write(chip, addr++, alen, &byte, 1) != 0) {
+		if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
 			puts ("Error writing the chip.\n");
-		}
 		/*
 		 * Wait for the write to complete.  The write can take
 		 * up to 10mSec (we allow a little more time).
@@ -303,9 +322,9 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #endif
 
 #if 0
-		for(timeout = 0; timeout < 10; timeout++) {
+		for (timeout = 0; timeout < 10; timeout++) {
 			udelay(2000);
-			if(i2c_probe(chip) == 0)
+			if (i2c_probe(chip) == 0)
 				break;
 		}
 #endif
@@ -346,17 +365,16 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 */
 	addr = simple_strtoul(argv[2], NULL, 16);
 	alen = 1;
-	for(j = 0; j < 8; j++) {
+	for (j = 0; j < 8; j++) {
 		if (argv[2][j] == '.') {
 			alen = argv[2][j+1] - '0';
-			if(alen > 4) {
+			if (alen > 4) {
 				printf ("Usage:\n%s\n", cmdtp->usage);
 				return 1;
 			}
 			break;
-		} else if (argv[2][j] == '\0') {
+		} else if (argv[2][j] == '\0')
 			break;
-		}
 	}
 
 	/*
@@ -371,19 +389,16 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 */
 	crc = 0;
 	err = 0;
-	while(count-- > 0) {
-		if(i2c_read(chip, addr, alen, &byte, 1) != 0) {
+	while (count-- > 0) {
+		if (i2c_read(chip, addr, alen, &byte, 1) != 0)
 			err++;
-		}
 		crc = crc32 (crc, &byte, 1);
 		addr++;
 	}
-	if(err > 0)
-	{
+	if (err > 0)
 		puts ("Error reading the chip,\n");
-	} else {
+	else
 		printf ("%08lx\n", crc);
-	}
 
 	return 0;
 }
@@ -441,17 +456,16 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 		 */
 		addr = simple_strtoul(argv[2], NULL, 16);
 		alen = 1;
-		for(j = 0; j < 8; j++) {
+		for (j = 0; j < 8; j++) {
 			if (argv[2][j] == '.') {
 				alen = argv[2][j+1] - '0';
-				if(alen > 4) {
+				if (alen > 4) {
 					printf ("Usage:\n%s\n", cmdtp->usage);
 					return 1;
 				}
 				break;
-			} else if (argv[2][j] == '\0') {
+			} else if (argv[2][j] == '\0')
 				break;
-			}
 		}
 	}
 
@@ -461,17 +475,16 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 	 */
 	do {
 		printf("%08lx:", addr);
-		if(i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) {
+		if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
 			puts ("\nError reading the chip,\n");
-		} else {
+		else {
 			data = cpu_to_be32(data);
-			if(size == 1) {
+			if (size == 1)
 				printf(" %02lx", (data >> 24) & 0x000000FF);
-			} else if(size == 2) {
+			else if (size == 2)
 				printf(" %04lx", (data >> 16) & 0x0000FFFF);
-			} else {
+			else
 				printf(" %08lx", data);
-			}
 		}
 
 		nbytes = readline (" ? ");
@@ -488,19 +501,17 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 #endif
 		}
 #ifdef CONFIG_BOOT_RETRY_TIME
-		else if (nbytes == -2) {
+		else if (nbytes == -2)
 			break;	/* timed out, exit the command	*/
-		}
 #endif
 		else {
 			char *endp;
 
 			data = simple_strtoul(console_buffer, &endp, 16);
-			if(size == 1) {
+			if (size == 1)
 				data = data << 24;
-			} else if(size == 2) {
+			else if (size == 2)
 				data = data << 16;
-			}
 			data = be32_to_cpu(data);
 			nbytes = endp - console_buffer;
 			if (nbytes) {
@@ -510,9 +521,8 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 				 */
 				reset_cmd_timeout();
 #endif
-				if(i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) {
+				if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
 					puts ("Error writing the chip.\n");
-				}
 #ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
 				udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 #endif
@@ -538,14 +548,15 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	int j;
 #if defined(CFG_I2C_NOPROBES)
 	int k, skip;
-#endif
+	uchar bus = GET_BUS_NUM;
+#endif	/* NOPROBES */
 
 	puts ("Valid chip addresses:");
-	for(j = 0; j < 128; j++) {
+	for (j = 0; j < 128; j++) {
 #if defined(CFG_I2C_NOPROBES)
 		skip = 0;
-		for (k = 0; k < sizeof(i2c_no_probes); k++){
-			if (j == i2c_no_probes[k]){
+		for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
+			if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
 				skip = 1;
 				break;
 			}
@@ -553,16 +564,17 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		if (skip)
 			continue;
 #endif
-		if(i2c_probe(j) == 0) {
+		if (i2c_probe(j) == 0)
 			printf(" %02X", j);
-		}
 	}
 	putc ('\n');
 
 #if defined(CFG_I2C_NOPROBES)
 	puts ("Excluded chip addresses:");
-	for( k = 0; k < sizeof(i2c_no_probes); k++ )
-		printf(" %02X", i2c_no_probes[k] );
+	for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
+		if (COMPARE_BUS(bus,k))
+			printf(" %02X", NO_PROBE_ADDR(k));
+	}
 	putc ('\n');
 #endif
 
@@ -601,7 +613,7 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 */
 	addr = simple_strtoul(argv[2], NULL, 16);
 	alen = 1;
-	for(j = 0; j < 8; j++) {
+	for (j = 0; j < 8; j++) {
 		if (argv[2][j] == '.') {
 			alen = argv[2][j+1] - '0';
 			if (alen > 4) {
@@ -609,9 +621,8 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 				return 1;
 			}
 			break;
-		} else if (argv[2][j] == '\0') {
+		} else if (argv[2][j] == '\0')
 			break;
-		}
 	}
 
 	/*
@@ -619,24 +630,21 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 */
 	length = 1;
 	length = simple_strtoul(argv[3], NULL, 16);
-	if(length > sizeof(bytes)) {
+	if (length > sizeof(bytes))
 		length = sizeof(bytes);
-	}
 
 	/*
 	 * The delay time (uSec) is optional.
 	 */
 	delay = 1000;
-	if (argc > 3) {
+	if (argc > 3)
 		delay = simple_strtoul(argv[4], NULL, 10);
-	}
 	/*
 	 * Run the loop...
 	 */
-	while(1) {
-		if(i2c_read(chip, addr, alen, bytes, length) != 0) {
+	while (1) {
+		if (i2c_read(chip, addr, alen, bytes, length) != 0)
 			puts ("Error reading the chip.\n");
-		}
 		udelay(delay);
 	}
 
@@ -671,7 +679,7 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  	 */
 	chip = simple_strtoul(argv[1], NULL, 16);
 
-	if(i2c_read(chip, 0, 1, data, sizeof(data)) != 0) {
+	if (i2c_read(chip, 0, 1, data, sizeof(data)) != 0) {
 		puts ("No SDRAM Serial Presence Detect found.\n");
 		return 1;
 	}
@@ -680,7 +688,7 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	for (j = 0; j < 63; j++) {
 		cksum += data[j];
 	}
-	if(cksum != data[63]) {
+	if (cksum != data[63]) {
 		printf ("WARNING: Configuration data checksum failure:\n"
 			"  is 0x%02x, calculated 0x%02x\n",
 			data[63], cksum);
@@ -693,20 +701,19 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	switch(data[2]) {
 		case 2:  puts ("EDO\n");	break;
 		case 4:  puts ("SDRAM\n");	break;
+		case 8:  puts ("DDR2\n");	break;
 		default: puts ("unknown\n");	break;
 	}
 	puts ("Row address bits             ");
-	if((data[3] & 0x00F0) == 0) {
+	if ((data[3] & 0x00F0) == 0)
 		printf("%d\n", data[3] & 0x0F);
-	} else {
+	else
 		printf("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
-	}
 	puts ("Column address bits          ");
-	if((data[4] & 0x00F0) == 0) {
+	if ((data[4] & 0x00F0) == 0)
 		printf("%d\n", data[4] & 0x0F);
-	} else {
+	else
 		printf("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
-	}
 	printf("Module rows                  %d\n", data[5]);
 	printf("Module data width            %d bits\n", (data[7] << 8) | data[6]);
 	puts ("Interface signal levels      ");
@@ -716,6 +723,7 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		case 2:  puts ("HSTL 1.5\n");	break;
 		case 3:  puts ("SSTL 3.3\n");	break;
 		case 4:  puts ("SSTL 2.5\n");	break;
+		case 5:  puts ("SSTL 1.8\n");	break;
 		default: puts ("unknown\n");	break;
 	}
 	printf("SDRAM cycle time             %d.%d nS\n",
@@ -729,11 +737,10 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		case 2:  puts ("ECC\n");	break;
 		default: puts ("unknown\n");	break;
 	}
-	if((data[12] & 0x80) == 0) {
+	if ((data[12] & 0x80) == 0)
 		puts ("No self refresh, rate        ");
-	} else {
+	else
 		puts ("Self refresh, rate           ");
-	}
 	switch(data[12] & 0x7F) {
 		case 0:  puts ("15.625uS\n");	break;
 		case 1:  puts ("3.9uS\n");	break;
@@ -744,17 +751,16 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		default: puts ("unknown\n");	break;
 	}
 	printf("SDRAM width (primary)        %d\n", data[13] & 0x7F);
-	if((data[13] & 0x80) != 0) {
+	if ((data[13] & 0x80) != 0) {
 		printf("  (second bank)              %d\n",
 			2 * (data[13] & 0x7F));
 	}
-	if(data[14] != 0) {
+	if (data[14] != 0) {
 		printf("EDC width                    %d\n",
 			data[14] & 0x7F);
-		if((data[14] & 0x80) != 0) {
+		if ((data[14] & 0x80) != 0)
 			printf("  (second bank)              %d\n",
 				2 * (data[14] & 0x7F));
-		}
 	}
 	printf("Min clock delay, back-to-back random column addresses %d\n",
 		data[15]);
@@ -852,18 +858,18 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		(data[35] & 0x80) ? '-' : '+',
 		(data[35] >> 4) & 0x07, data[35] & 0x0F);
 	puts ("Manufacturer's JEDEC ID      ");
-	for(j = 64; j <= 71; j++)
+	for (j = 64; j <= 71; j++)
 		printf("%02X ", data[j]);
 	putc ('\n');
 	printf("Manufacturing Location       %02X\n", data[72]);
 	puts ("Manufacturer's Part Number   ");
-	for(j = 73; j <= 90; j++)
+	for (j = 73; j <= 90; j++)
 		printf("%02X ", data[j]);
 	putc ('\n');
 	printf("Revision Code                %02X %02X\n", data[91], data[92]);
 	printf("Manufacturing Date           %02X %02X\n", data[93], data[94]);
 	puts ("Assembly Serial Number       ");
-	for(j = 95; j <= 98; j++)
+	for (j = 95; j <= 98; j++)
 		printf("%02X ", data[j]);
 	putc ('\n');
 	printf("Speed rating                 PC%d\n",
@@ -873,9 +879,97 @@ int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 #endif	/* CFG_CMD_SDRAM */
 
+#if defined(CONFIG_I2C_CMD_TREE)
+#if defined(CONFIG_I2C_MULTI_BUS)
+int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int bus_idx, ret=0;
+
+	if (argc == 1)
+		/* querying current setting */
+		printf("Current bus is %d\n", i2c_get_bus_num());
+	else {
+		bus_idx = simple_strtoul(argv[1], NULL, 10);
+		printf("Setting bus to %d\n", bus_idx);
+		ret = i2c_set_bus_num(bus_idx);
+		if (ret)
+			printf("Failure changing bus number (%d)\n", ret);
+	}
+	return ret;
+}
+#endif  /* CONFIG_I2C_MULTI_BUS */
+
+int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int speed, ret=0;
+
+	if (argc == 1)
+		/* querying current speed */
+		printf("Current bus speed=%d\n", i2c_get_bus_speed());
+	else {
+		speed = simple_strtoul(argv[1], NULL, 10);
+		printf("Setting bus speed to %d Hz\n", speed);
+		ret = i2c_set_bus_speed(speed);
+		if (ret)
+			printf("Failure changing bus speed (%d)\n", ret);
+	}
+	return ret;
+}
+
+int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+#if defined(CONFIG_I2C_MULTI_BUS)
+	if (!strncmp(argv[1], "de", 2))
+		return do_i2c_bus_num(cmdtp, flag, --argc, ++argv);
+#endif  /* CONFIG_I2C_MULTI_BUS */
+	if (!strncmp(argv[1], "sp", 2))
+		return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
+	if (!strncmp(argv[1], "md", 2))
+		return do_i2c_md(cmdtp, flag, --argc, ++argv);
+	if (!strncmp(argv[1], "mm", 2))
+		return do_i2c_mm(cmdtp, flag, --argc, ++argv);
+	if (!strncmp(argv[1], "mw", 2))
+		return do_i2c_mw(cmdtp, flag, --argc, ++argv);
+	if (!strncmp(argv[1], "nm", 2))
+		return do_i2c_nm(cmdtp, flag, --argc, ++argv);
+	if (!strncmp(argv[1], "cr", 2))
+		return do_i2c_crc(cmdtp, flag, --argc, ++argv);
+	if (!strncmp(argv[1], "pr", 2))
+		return do_i2c_probe(cmdtp, flag, --argc, ++argv);
+	if (!strncmp(argv[1], "lo", 2))
+		return do_i2c_loop(cmdtp, flag, --argc, ++argv);
+#if (CONFIG_COMMANDS & CFG_CMD_SDRAM)
+	if (!strncmp(argv[1], "sd", 2))
+		return do_sdram(cmdtp, flag, --argc, ++argv);
+#endif	/* CFG_CMD_SDRAM */
+	else
+		printf ("Usage:\n%s\n", cmdtp->usage);
+	return 0;
+}
+#endif  /* CONFIG_I2C_CMD_TREE */
 
 /***************************************************/
 
+#if defined(CONFIG_I2C_CMD_TREE)
+U_BOOT_CMD(
+	i2c, 6, 1, do_i2c,
+ 	"i2c     - I2C sub-system\n",
+#if defined(CONFIG_I2C_MULTI_BUS)
+	"dev [dev] - show or set current I2C bus\n"
+#endif  /* CONFIG_I2C_MULTI_BUS */
+	"i2c speed [speed] - show or set I2C bus speed\n"
+	"i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
+	"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
+	"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
+	"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
+	"i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
+	"i2c probe - show devices on the I2C bus\n"
+	"i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
+#if (CONFIG_COMMANDS & CFG_CMD_SDRAM)
+	"i2c sdram chip - print SDRAM configuration information\n"
+#endif  /* CFG_CMD_SDRAM */
+);
+#else /* CONFIG_I2C_CMD_TREE */
 U_BOOT_CMD(
 	imd,	4,	1,	do_i2c_md,		\
 	"imd     - i2c memory display\n",				\
@@ -930,4 +1024,6 @@ U_BOOT_CMD(
 	"      (valid chip values 50..57)\n"
 );
 #endif
+#endif  /* CONFIG_I2C_CMD_TREE */
+
 #endif	/* CFG_CMD_I2C */
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index a415502..2e185cc 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -31,20 +31,26 @@
 #include <command.h>
 #include <image.h>
 #include <asm/byteorder.h>
+
 #if defined(CONFIG_IDE_8xx_DIRECT) || defined(CONFIG_IDE_PCMCIA)
 # include <pcmcia.h>
 #endif
+
 #ifdef CONFIG_8xx
 # include <mpc8xx.h>
 #endif
+
 #ifdef CONFIG_MPC5xxx
 #include <mpc5xxx.h>
 #endif
+
 #include <ide.h>
 #include <ata.h>
+
 #ifdef CONFIG_STATUS_LED
 # include <status_led.h>
 #endif
+
 #ifndef __PPC__
 #include <asm/io.h>
 #ifdef __MIPS__
@@ -182,7 +188,7 @@ static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len
 
 #ifdef CONFIG_ATAPI
 static void	atapi_inquiry(block_dev_desc_t *dev_desc);
-ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
+ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer);
 #endif
 
 
@@ -697,7 +703,7 @@ void ide_init (void)
 
 block_dev_desc_t * ide_get_dev(int dev)
 {
-	return ((block_dev_desc_t *)&ide_dev_desc[dev]);
+	return (dev < CFG_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL;
 }
 
 
@@ -1227,7 +1233,7 @@ static void ide_ident (block_dev_desc_t *dev_desc)
 
 /* ------------------------------------------------------------------------- */
 
-ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
+ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
 {
 	ulong n = 0;
 	unsigned char c;
@@ -1347,7 +1353,7 @@ IDE_READ_E:
 /* ------------------------------------------------------------------------- */
 
 
-ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
+ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
 {
 	ulong n = 0;
 	unsigned char c;
@@ -2009,7 +2015,7 @@ static void	atapi_inquiry(block_dev_desc_t * dev_desc)
 #define ATAPI_READ_BLOCK_SIZE	2048	/* assuming CD part */
 #define ATAPI_READ_MAX_BLOCK ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE	/* max blocks */
 
-ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
+ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
 {
 	ulong n = 0;
 	unsigned char ccb[12]; /* Command descriptor block */
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index d0fae6b..fcbb023 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -92,8 +92,9 @@ static	ulong	base_address = 0;
 int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	ulong	addr, length;
-	ulong	i, nbytes, linebytes;
-	u_char	*cp;
+#if defined(CONFIG_HAS_DATAFLASH)
+	ulong	nbytes, linebytes;
+#endif
 	int	size;
 	int rc = 0;
 
@@ -128,6 +129,7 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 			length = simple_strtoul(argv[2], NULL, 16);
 	}
 
+#if defined(CONFIG_HAS_DATAFLASH)
 	/* Print the lines.
 	 *
 	 * We buffer all read data, so we can make sure data is read only
@@ -136,64 +138,25 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	nbytes = length * size;
 	do {
 		char	linebuf[DISP_LINE_LEN];
-		uint	*uip = (uint   *)linebuf;
-		ushort	*usp = (ushort *)linebuf;
-		u_char	*ucp = (u_char *)linebuf;
-#ifdef CONFIG_HAS_DATAFLASH
-		int rc;
-#endif
-		printf("%08lx:", addr);
+		void* p;
 		linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
 
-#ifdef CONFIG_HAS_DATAFLASH
-		if ((rc = read_dataflash(addr, (linebytes/size)*size, linebuf)) == DATAFLASH_OK){
-			/* if outside dataflash */
-			/*if (rc != 1) {
-				dataflash_perror (rc);
-				return (1);
-			}*/
-			for (i=0; i<linebytes; i+= size) {
-				if (size == 4) {
-					printf(" %08x", *uip++);
-				} else if (size == 2) {
-					printf(" %04x", *usp++);
-				} else {
-					printf(" %02x", *ucp++);
-				}
-				addr += size;
-			}
+		rc = read_dataflash(addr, (linebytes/size)*size, linebuf);
+		p = (rc == DATAFLASH_OK) ? linebuf : (void*)addr;
+		print_buffer(addr, p, size, linebytes/size, DISP_LINE_LEN/size);
 
-		} else {	/* addr does not correspond to DataFlash */
-#endif
-		for (i=0; i<linebytes; i+= size) {
-			if (size == 4) {
-				printf(" %08x", (*uip++ = *((uint *)addr)));
-			} else if (size == 2) {
-				printf(" %04x", (*usp++ = *((ushort *)addr)));
-			} else {
-				printf(" %02x", (*ucp++ = *((u_char *)addr)));
-			}
-			addr += size;
-		}
-#ifdef CONFIG_HAS_DATAFLASH
-		}
-#endif
-		puts ("    ");
-		cp = (u_char *)linebuf;
-		for (i=0; i<linebytes; i++) {
-			if ((*cp < 0x20) || (*cp > 0x7e))
-				putc ('.');
-			else
-				printf("%c", *cp);
-			cp++;
-		}
-		putc ('\n');
 		nbytes -= linebytes;
+		addr += linebytes;
 		if (ctrlc()) {
 			rc = 1;
 			break;
 		}
 	} while (nbytes > 0);
+#else
+	/* Print the lines. */
+	print_buffer(addr, (void*)addr, size, length, DISP_LINE_LEN/size);
+	addr += size*length;
+#endif
 
 	dp_last_addr = addr;
 	dp_last_length = length;
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 7286726..b011b5e 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -684,178 +684,182 @@ extern int nand_write_oob(struct nand_chip *nand, size_t ofs,
 				size_t len, size_t *retlen, const u_char *buf);
 
 
-int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-    int rcode = 0;
-
-    switch (argc) {
-    case 0:
-    case 1:
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    case 2:
-	if (strcmp(argv[1],"info") == 0) {
-		int i;
+	int rcode = 0;
 
-		putc ('\n');
+	switch (argc) {
+	case 0:
+	case 1:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 2:
+		if (strcmp (argv[1], "info") == 0) {
+			int i;
 
-		for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) {
-			if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
-				continue; /* list only known devices */
-			printf ("Device %d: ", i);
-			nand_print(&nand_dev_desc[i]);
-		}
-		return 0;
+			putc ('\n');
 
-	} else if (strcmp(argv[1],"device") == 0) {
-		if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
-			puts ("\nno devices available\n");
-			return 1;
-		}
-		printf ("\nDevice %d: ", curr_device);
-		nand_print(&nand_dev_desc[curr_device]);
-		return 0;
+			for (i = 0; i < CFG_MAX_NAND_DEVICE; ++i) {
+				if (nand_dev_desc[i].ChipID ==
+				    NAND_ChipID_UNKNOWN)
+					continue;	/* list only known devices */
+				printf ("Device %d: ", i);
+				nand_print (&nand_dev_desc[i]);
+			}
+			return 0;
 
-	} else if (strcmp(argv[1],"bad") == 0) {
-		if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
-			puts ("\nno devices available\n");
-			return 1;
-		}
-		printf ("\nDevice %d bad blocks:\n", curr_device);
-		nand_print_bad(&nand_dev_desc[curr_device]);
-		return 0;
+		} else if (strcmp (argv[1], "device") == 0) {
+			if ((curr_device < 0)
+			    || (curr_device >= CFG_MAX_NAND_DEVICE)) {
+				puts ("\nno devices available\n");
+				return 1;
+			}
+			printf ("\nDevice %d: ", curr_device);
+			nand_print (&nand_dev_desc[curr_device]);
+			return 0;
 
-	}
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    case 3:
-	if (strcmp(argv[1],"device") == 0) {
-		int dev = (int)simple_strtoul(argv[2], NULL, 10);
+		} else if (strcmp (argv[1], "bad") == 0) {
+			if ((curr_device < 0)
+			    || (curr_device >= CFG_MAX_NAND_DEVICE)) {
+				puts ("\nno devices available\n");
+				return 1;
+			}
+			printf ("\nDevice %d bad blocks:\n", curr_device);
+			nand_print_bad (&nand_dev_desc[curr_device]);
+			return 0;
 
-		printf ("\nDevice %d: ", dev);
-		if (dev >= CFG_MAX_NAND_DEVICE) {
-			puts ("unknown device\n");
-			return 1;
 		}
-		nand_print(&nand_dev_desc[dev]);
-		/*nand_print (dev);*/
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 3:
+		if (strcmp (argv[1], "device") == 0) {
+			int dev = (int) simple_strtoul (argv[2], NULL, 10);
 
-		if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
-			return 1;
-		}
+			printf ("\nDevice %d: ", dev);
+			if (dev >= CFG_MAX_NAND_DEVICE) {
+				puts ("unknown device\n");
+				return 1;
+			}
+			nand_print (&nand_dev_desc[dev]);
+			/*nand_print (dev); */
+
+			if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
+				return 1;
+			}
 
-		curr_device = dev;
+			curr_device = dev;
 
-		puts ("... is now current device\n");
+			puts ("... is now current device\n");
 
-		return 0;
-	}
-	else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) {
-		struct nand_chip* nand = &nand_dev_desc[curr_device];
-		ulong off = 0;
-		ulong size = nand->totlen;
-		int ret;
+			return 0;
+		} else if (strcmp (argv[1], "erase") == 0
+			   && strcmp (argv[2], "clean") == 0) {
+			struct nand_chip *nand = &nand_dev_desc[curr_device];
+			ulong off = 0;
+			ulong size = nand->totlen;
+			int ret;
 
-		printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
-			curr_device, off, size);
+			printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size);
 
-		ret = nand_legacy_erase (nand, off, size, 1);
+			ret = nand_legacy_erase (nand, off, size, 1);
 
-		printf("%s\n", ret ? "ERROR" : "OK");
+			printf ("%s\n", ret ? "ERROR" : "OK");
 
-		return ret;
-	}
+			return ret;
+		}
 
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-    default:
-	/* at least 4 args */
-
-	if (strncmp(argv[1], "read", 4) == 0 ||
-	    strncmp(argv[1], "write", 5) == 0) {
-		ulong addr = simple_strtoul(argv[2], NULL, 16);
-		ulong off  = simple_strtoul(argv[3], NULL, 16);
-		ulong size = simple_strtoul(argv[4], NULL, 16);
-		int cmd    = (strncmp(argv[1], "read", 4) == 0) ?
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	default:
+		/* at least 4 args */
+
+		if (strncmp (argv[1], "read", 4) == 0 ||
+		    strncmp (argv[1], "write", 5) == 0) {
+			ulong addr = simple_strtoul (argv[2], NULL, 16);
+			ulong off = simple_strtoul (argv[3], NULL, 16);
+			ulong size = simple_strtoul (argv[4], NULL, 16);
+			int cmd = (strncmp (argv[1], "read", 4) == 0) ?
 				NANDRW_READ : NANDRW_WRITE;
-		int ret, total;
-		char* cmdtail = strchr(argv[1], '.');
-
-		if (cmdtail && !strncmp(cmdtail, ".oob", 2)) {
-			/* read out-of-band data */
-			if (cmd & NANDRW_READ) {
-				ret = nand_read_oob(nand_dev_desc + curr_device,
-						    off, size, (size_t *)&total,
-						    (u_char*)addr);
-			}
-			else {
-				ret = nand_write_oob(nand_dev_desc + curr_device,
-						     off, size, (size_t *)&total,
-						     (u_char*)addr);
+			int ret, total;
+			char *cmdtail = strchr (argv[1], '.');
+
+			if (cmdtail && !strncmp (cmdtail, ".oob", 2)) {
+				/* read out-of-band data */
+				if (cmd & NANDRW_READ) {
+					ret = nand_read_oob (nand_dev_desc + curr_device,
+							     off, size, (size_t *) & total,
+							     (u_char *) addr);
+				} else {
+					ret = nand_write_oob (nand_dev_desc + curr_device,
+							      off, size, (size_t *) & total,
+							      (u_char *) addr);
+				}
+				return ret;
+			} else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2))
+				cmd |= NANDRW_JFFS2;	/* skip bad blocks */
+			else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 2)) {
+				cmd |= NANDRW_JFFS2;	/* skip bad blocks (on read too) */
+				if (cmd & NANDRW_READ)
+					cmd |= NANDRW_JFFS2_SKIP;	/* skip bad blocks (on read too) */
 			}
-			return ret;
-		}
-		else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2))
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks */
-		else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) {
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks (on read too) */
-			if (cmd & NANDRW_READ)
-				cmd |= NANDRW_JFFS2_SKIP;	/* skip bad blocks (on read too) */
-		}
 #ifdef SXNI855T
-		/* need ".e" same as ".j" for compatibility with older units */
-		else if (cmdtail && !strcmp(cmdtail, ".e"))
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks */
+			/* need ".e" same as ".j" for compatibility with older units */
+			else if (cmdtail && !strcmp (cmdtail, ".e"))
+				cmd |= NANDRW_JFFS2;	/* skip bad blocks */
 #endif
 #ifdef CFG_NAND_SKIP_BAD_DOT_I
-		/* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
-		/* ".i" for image -> read skips bad block (no 0xff) */
-		else if (cmdtail && !strcmp(cmdtail, ".i")) {
-			cmd |= NANDRW_JFFS2;	/* skip bad blocks (on read too) */
-			if (cmd & NANDRW_READ)
-				cmd |= NANDRW_JFFS2_SKIP;	/* skip bad blocks (on read too) */
-		}
+			/* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
+			/* ".i" for image -> read skips bad block (no 0xff) */
+			else if (cmdtail && !strcmp (cmdtail, ".i")) {
+				cmd |= NANDRW_JFFS2;	/* skip bad blocks (on read too) */
+				if (cmd & NANDRW_READ)
+					cmd |= NANDRW_JFFS2_SKIP;	/* skip bad blocks (on read too) */
+			}
 #endif /* CFG_NAND_SKIP_BAD_DOT_I */
-		else if (cmdtail) {
-			printf ("Usage:\n%s\n", cmdtp->usage);
-			return 1;
-		}
+			else if (cmdtail) {
+				printf ("Usage:\n%s\n", cmdtp->usage);
+				return 1;
+			}
 
-		printf ("\nNAND %s: device %d offset %ld, size %ld ...\n",
-			(cmd & NANDRW_READ) ? "read" : "write",
-			curr_device, off, size);
+			printf ("\nNAND %s: device %d offset %ld, size %ld ...\n",
+				(cmd & NANDRW_READ) ? "read" : "write",
+				curr_device, off, size);
 
-		ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size,
-			     (size_t *)&total, (u_char*)addr);
+			ret = nand_legacy_rw (nand_dev_desc + curr_device,
+					      cmd, off, size,
+					      (size_t *) & total,
+					      (u_char *) addr);
 
-		printf (" %d bytes %s: %s\n", total,
-			(cmd & NANDRW_READ) ? "read" : "written",
-			ret ? "ERROR" : "OK");
+			printf (" %d bytes %s: %s\n", total,
+				(cmd & NANDRW_READ) ? "read" : "written",
+				ret ? "ERROR" : "OK");
 
-		return ret;
-	} else if (strcmp(argv[1],"erase") == 0 &&
-		   (argc == 4 || strcmp("clean", argv[2]) == 0)) {
-		int clean = argc == 5;
-		ulong off = simple_strtoul(argv[2 + clean], NULL, 16);
-		ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
-		int ret;
+			return ret;
+		} else if (strcmp (argv[1], "erase") == 0 &&
+			   (argc == 4 || strcmp ("clean", argv[2]) == 0)) {
+			int clean = argc == 5;
+			ulong off =
+				simple_strtoul (argv[2 + clean], NULL, 16);
+			ulong size =
+				simple_strtoul (argv[3 + clean], NULL, 16);
+			int ret;
 
-		printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
-			curr_device, off, size);
+			printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
+				curr_device, off, size);
 
-		ret = nand_legacy_erase (nand_dev_desc + curr_device,
-					off, size, clean);
+			ret = nand_legacy_erase (nand_dev_desc + curr_device,
+						 off, size, clean);
 
-		printf("%s\n", ret ? "ERROR" : "OK");
+			printf ("%s\n", ret ? "ERROR" : "OK");
 
-		return ret;
-	} else {
-		printf ("Usage:\n%s\n", cmdtp->usage);
-		rcode = 1;
-	}
+			return ret;
+		} else {
+			printf ("Usage:\n%s\n", cmdtp->usage);
+			rcode = 1;
+		}
 
-	return rcode;
-    }
+		return rcode;
+	}
 }
 
 U_BOOT_CMD(
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index d3f50f8..9834ba6 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -248,7 +248,7 @@ int _do_setenv (int flag, int argc, char *argv[])
 				baudrate);
 			udelay(50000);
 			gd->baudrate = baudrate;
-#ifdef CONFIG_PPC
+#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2)
 			gd->bd->bi_baudrate = baudrate;
 #endif
 
diff --git a/common/cmd_reiser.c b/common/cmd_reiser.c
index 508ffcb..09c86e6 100644
--- a/common/cmd_reiser.c
+++ b/common/cmd_reiser.c
@@ -35,6 +35,7 @@
 #include <linux/ctype.h>
 #include <asm/byteorder.h>
 #include <reiserfs.h>
+#include <part.h>
 
 #ifndef CONFIG_DOS_PARTITION
 #error DOS partition support must be selected
@@ -48,41 +49,6 @@
 #define PRINTF(fmt,args...)
 #endif
 
-static block_dev_desc_t *get_dev (char* ifname, int dev)
-{
-#if (CONFIG_COMMANDS & CFG_CMD_IDE)
-	if (strncmp(ifname,"ide",3)==0) {
-		extern block_dev_desc_t * ide_get_dev(int dev);
-		return((dev >= CFG_IDE_MAXDEVICE) ? NULL : ide_get_dev(dev));
-	}
-#endif
-#if (CONFIG_COMMANDS & CFG_CMD_SCSI)
-	if (strncmp(ifname,"scsi",4)==0) {
-		extern block_dev_desc_t * scsi_get_dev(int dev);
-		return((dev >= CFG_SCSI_MAXDEVICE) ? NULL : scsi_get_dev(dev));
-	}
-#endif
-#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE))
-	if (strncmp(ifname,"usb",3)==0) {
-		extern block_dev_desc_t * usb_stor_get_dev(int dev);
-		return((dev >= USB_MAX_STOR_DEV) ? NULL : usb_stor_get_dev(dev));
-	}
-#endif
-#if defined(CONFIG_MMC)
-	if (strncmp(ifname,"mmc",3)==0) {
-		extern block_dev_desc_t *  mmc_get_dev(int dev);
-		return((dev >= 1) ? NULL : mmc_get_dev(dev));
-	}
-#endif
-#if defined(CONFIG_SYSTEMACE)
-	if (strcmp(ifname,"ace")==0) {
-		extern block_dev_desc_t *  systemace_get_dev(int dev);
-		return((dev >= 1) ? NULL : systemace_get_dev(dev));
-	}
-#endif
-	return NULL;
-}
-
 int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	char *filename = "/";
@@ -97,7 +63,7 @@ int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 	dev = (int)simple_strtoul (argv[2], &ep, 16);
-	dev_desc=get_dev(argv[1],dev);
+	dev_desc = get_dev(argv[1],dev);
 
 	if (dev_desc == NULL) {
 		printf ("\n** Block device %s %d not supported\n", argv[1], dev);
@@ -196,7 +162,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 
 	dev = (int)simple_strtoul (argv[2], &ep, 16);
-	dev_desc=get_dev(argv[1],dev);
+	dev_desc = get_dev(argv[1],dev);
 	if (dev_desc==NULL) {
 		printf ("\n** Block device %s %d not supported\n", argv[1], dev);
 		return 1;
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index cc08743..da36ed9 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -74,7 +74,7 @@ void scsi_setup_inquiry(ccb * pccb);
 void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
 
 
-ulong scsi_read(int device, ulong blknr, ulong blkcnt, ulong *buffer);
+ulong scsi_read(int device, ulong blknr, ulong blkcnt, void *buffer);
 
 
 /*********************************************************************************
@@ -194,7 +194,7 @@ void scsi_init(void)
 
 block_dev_desc_t * scsi_get_dev(int dev)
 {
-	return((block_dev_desc_t *)&scsi_dev_desc[dev]);
+	return (dev < CFG_SCSI_MAX_DEVICE) ? &scsi_dev_desc[dev] : NULL;
 }
 
 
@@ -424,7 +424,7 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 #define SCSI_MAX_READ_BLK 0xFFFF /* almost the maximum amount of the scsi_ext command.. */
 
-ulong scsi_read(int device, ulong blknr, ulong blkcnt, ulong *buffer)
+ulong scsi_read(int device, ulong blknr, ulong blkcnt, void *buffer)
 {
 	ulong start,blks, buf_addr;
 	unsigned short smallblks;
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index 28c05aa..904df71 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/byteorder.h>
+#include <part.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_USB)
 
diff --git a/common/cyclon2.c b/common/cyclon2.c
new file mode 100644
index 0000000..dce13b5
--- /dev/null
+++ b/common/cyclon2.c
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, hs@denx.de
+ * Based on ACE1XK.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>		/* core U-Boot definitions */
+#include <altera.h>
+#include <ACEX1K.h>		/* ACEX device family */
+
+#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2))
+
+/* Define FPGA_DEBUG to get debug printf's */
+#ifdef	FPGA_DEBUG
+#define PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+/* Note: The assumption is that we cannot possibly run fast enough to
+ * overrun the device (the Slave Parallel mode can free run at 50MHz).
+ * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * the board config file to slow things down.
+ */
+#ifndef CONFIG_FPGA_DELAY
+#define CONFIG_FPGA_DELAY()
+#endif
+
+#ifndef CFG_FPGA_WAIT
+#define CFG_FPGA_WAIT CFG_HZ/10		/* 100 ms */
+#endif
+
+static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize );
+static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
+/* static int CYC2_ps_info( Altera_desc *desc ); */
+static int CYC2_ps_reloc( Altera_desc *desc, ulong reloc_offset );
+
+/* ------------------------------------------------------------------------- */
+/* CYCLON2 Generic Implementation */
+int CYC2_load (Altera_desc * desc, void *buf, size_t bsize)
+{
+	int ret_val = FPGA_FAIL;
+
+	switch (desc->iface) {
+	case passive_serial:
+		PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
+		ret_val = CYC2_ps_load (desc, buf, bsize);
+		break;
+
+		/* Add new interface types here */
+
+	default:
+		printf ("%s: Unsupported interface type, %d\n",
+				__FUNCTION__, desc->iface);
+	}
+
+	return ret_val;
+}
+
+int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize)
+{
+	int ret_val = FPGA_FAIL;
+
+	switch (desc->iface) {
+	case passive_serial:
+		PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
+		ret_val = CYC2_ps_dump (desc, buf, bsize);
+		break;
+
+		/* Add new interface types here */
+
+	default:
+		printf ("%s: Unsupported interface type, %d\n",
+				__FUNCTION__, desc->iface);
+	}
+
+	return ret_val;
+}
+
+int CYC2_info( Altera_desc *desc )
+{
+	return FPGA_SUCCESS;
+}
+
+int CYC2_reloc (Altera_desc * desc, ulong reloc_offset)
+{
+	int ret_val = FPGA_FAIL;	/* assume a failure */
+
+	if (desc->family != Altera_CYC2) {
+		printf ("%s: Unsupported family type, %d\n",
+				__FUNCTION__, desc->family);
+		return FPGA_FAIL;
+	} else
+		switch (desc->iface) {
+		case passive_serial:
+			ret_val = CYC2_ps_reloc (desc, reloc_offset);
+			break;
+
+		/* Add new interface types here */
+
+		default:
+			printf ("%s: Unsupported interface type, %d\n",
+					__FUNCTION__, desc->iface);
+		}
+
+	return ret_val;
+}
+
+/* ------------------------------------------------------------------------- */
+/* CYCLON2 Passive Serial Generic Implementation                                  */
+static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize)
+{
+	int ret_val = FPGA_FAIL;	/* assume the worst */
+	Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
+	int	ret = 0;
+
+	PRINTF ("%s: start with interface functions @ 0x%p\n",
+			__FUNCTION__, fn);
+
+	if (fn) {
+		int cookie = desc->cookie;	/* make a local copy */
+		unsigned long ts;		/* timestamp */
+
+		PRINTF ("%s: Function Table:\n"
+				"ptr:\t0x%p\n"
+				"struct: 0x%p\n"
+				"config:\t0x%p\n"
+				"status:\t0x%p\n"
+				"write:\t0x%p\n"
+				"done:\t0x%p\n\n",
+				__FUNCTION__, &fn, fn, fn->config, fn->status,
+				fn->write, fn->done);
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		printf ("Loading FPGA Device %d...", cookie);
+#endif
+
+		/*
+		 * Run the pre configuration function if there is one.
+		 */
+		if (*fn->pre) {
+			(*fn->pre) (cookie);
+		}
+
+		/* Establish the initial state */
+		(*fn->config) (TRUE, TRUE, cookie);	/* Assert nCONFIG */
+
+		udelay(2);		/* T_cfg > 2us	*/
+
+		/* Wait for nSTATUS to be asserted */
+		ts = get_timer (0);		/* get current time */
+		do {
+			CONFIG_FPGA_DELAY ();
+			if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
+				puts ("** Timeout waiting for STATUS to go high.\n");
+				(*fn->abort) (cookie);
+				return FPGA_FAIL;
+			}
+		} while (!(*fn->status) (cookie));
+
+		/* Get ready for the burn */
+		CONFIG_FPGA_DELAY ();
+
+		ret = (*fn->write) (buf, bsize, TRUE, cookie);
+		if (ret) {
+			puts ("** Write failed.\n");
+			(*fn->abort) (cookie);
+			return FPGA_FAIL;
+		}
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		puts(" OK? ...");
+#endif
+
+		CONFIG_FPGA_DELAY ();
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		putc (' ');			/* terminate the dotted line */
+#endif
+
+	/*
+	 * Checking FPGA's CONF_DONE signal - correctly booted ?
+	 */
+
+	if ( ! (*fn->done) (cookie) ) {
+		puts ("** Booting failed! CONF_DONE is still deasserted.\n");
+		(*fn->abort) (cookie);
+		return (FPGA_FAIL);
+	}
+#ifdef CFG_FPGA_PROG_FEEDBACK
+	puts(" OK\n");
+#endif
+
+	ret_val = FPGA_SUCCESS;
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+	if (ret_val == FPGA_SUCCESS) {
+		puts ("Done.\n");
+	}
+	else {
+		puts ("Fail.\n");
+	}
+#endif
+	(*fn->post) (cookie);
+
+	} else {
+		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+	}
+
+	return ret_val;
+}
+
+static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
+{
+	/* Readback is only available through the Slave Parallel and         */
+	/* boundary-scan interfaces.                                         */
+	printf ("%s: Passive Serial Dumping is unavailable\n",
+			__FUNCTION__);
+	return FPGA_FAIL;
+}
+
+static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset)
+{
+	int ret_val = FPGA_FAIL;	/* assume the worst */
+	Altera_CYC2_Passive_Serial_fns *fn_r, *fn =
+			(Altera_CYC2_Passive_Serial_fns *) (desc->iface_fns);
+
+	if (fn) {
+		ulong addr;
+
+		/* Get the relocated table address */
+		addr = (ulong) fn + reloc_offset;
+		fn_r = (Altera_CYC2_Passive_Serial_fns *) addr;
+
+		if (!fn_r->relocated) {
+
+			if (memcmp (fn_r, fn,
+						sizeof (Altera_CYC2_Passive_Serial_fns))
+				== 0) {
+				/* good copy of the table, fix the descriptor pointer */
+				desc->iface_fns = fn_r;
+			} else {
+				PRINTF ("%s: Invalid function table at 0x%p\n",
+						__FUNCTION__, fn_r);
+				return FPGA_FAIL;
+			}
+
+			PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
+					desc);
+
+			addr = (ulong) (fn->pre) + reloc_offset;
+			fn_r->pre = (Altera_pre_fn) addr;
+
+			addr = (ulong) (fn->config) + reloc_offset;
+			fn_r->config = (Altera_config_fn) addr;
+
+			addr = (ulong) (fn->status) + reloc_offset;
+			fn_r->status = (Altera_status_fn) addr;
+
+			addr = (ulong) (fn->done) + reloc_offset;
+			fn_r->done = (Altera_done_fn) addr;
+
+			addr = (ulong) (fn->write) + reloc_offset;
+			fn_r->write = (Altera_write_fn) addr;
+
+			addr = (ulong) (fn->abort) + reloc_offset;
+			fn_r->abort = (Altera_abort_fn) addr;
+
+			addr = (ulong) (fn->post) + reloc_offset;
+			fn_r->post = (Altera_post_fn) addr;
+
+			fn_r->relocated = TRUE;
+
+		} else {
+			/* this table has already been moved */
+			/* XXX - should check to see if the descriptor is correct */
+			desc->iface_fns = fn_r;
+		}
+
+		ret_val = FPGA_SUCCESS;
+	} else {
+		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+	}
+
+	return ret_val;
+}
+
+#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */
diff --git a/common/environment.c b/common/environment.c
index 19bdeb0..1d425a7 100644
--- a/common/environment.c
+++ b/common/environment.c
@@ -61,6 +61,7 @@
      defined(CONFIG_TRAB)   	|| \
      defined(CONFIG_PPCHAMELEONEVB) || \
      defined(CONFIG_M5271EVB)	|| \
+     defined(CONFIG_IDMR)	|| \
      defined(CONFIG_NAND_U_BOOT))	&& \
      defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
 /* XXX - This only works with GNU C */
diff --git a/common/fpga.c b/common/fpga.c
index 02d3e42..2eff239 100644
--- a/common/fpga.c
+++ b/common/fpga.c
@@ -139,7 +139,7 @@ static int fpga_dev_info( int devnum )
 			printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc );
 			ret_val = xilinx_info( desc->devdesc );
 #else
-			fpga_no_sup( __FUNCTION__, "Xilinx devices" );
+			fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
 #endif
 			break;
 		case fpga_altera:
@@ -178,7 +178,7 @@ int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off )
 #if CONFIG_FPGA & CFG_FPGA_XILINX
 		ret_val = xilinx_reloc( desc, reloc_off );
 #else
-		fpga_no_sup( __FUNCTION__, "Xilinx devices" );
+		fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
 #endif
 		break;
 	case fpga_altera:
@@ -271,7 +271,7 @@ int fpga_load( int devnum, void *buf, size_t bsize )
 #if CONFIG_FPGA & CFG_FPGA_XILINX
 			ret_val = xilinx_load( desc->devdesc, buf, bsize );
 #else
-			fpga_no_sup( __FUNCTION__, "Xilinx devices" );
+			fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
 #endif
 			break;
 		case fpga_altera:
@@ -304,7 +304,7 @@ int fpga_dump( int devnum, void *buf, size_t bsize )
 #if CONFIG_FPGA & CFG_FPGA_XILINX
 			ret_val = xilinx_dump( desc->devdesc, buf, bsize );
 #else
-			fpga_no_sup( __FUNCTION__, "Xilinx devices" );
+			fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
 #endif
 			break;
 		case fpga_altera:
diff --git a/common/ft_build.c b/common/ft_build.c
index 980e40f..5a0575e 100644
--- a/common/ft_build.c
+++ b/common/ft_build.c
@@ -29,6 +29,7 @@
 #include <stddef.h>
 
 #include <ft_build.h>
+#include <linux/ctype.h>
 
 #undef DEBUG
 
@@ -180,11 +181,6 @@ void ft_finalize_tree(struct ft_cxt *cxt) {
 	bph->dt_strings_size = cxt->p_end - cxt->p;
 }
 
-static inline int isprint(int c)
-{
-	return c >= 0x20 && c <= 0x7e;
-}
-
 static int is_printable_string(const void *data, int len)
 {
 	const char *s = data;
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 06ea99b..196ceb7 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -56,6 +56,7 @@
 
 
 #if (CONFIG_COMMANDS & CFG_CMD_USB)
+#include <part.h>
 #include <usb.h>
 
 #ifdef CONFIG_USB_STORAGE
@@ -168,13 +169,13 @@ static struct us_data usb_stor[USB_MAX_STOR_DEV];
 
 int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc);
 int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data *ss);
-unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, unsigned long *buffer);
+unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer);
 struct usb_device * usb_get_dev_index(int index);
 void uhci_show_temp_int_td(void);
 
 block_dev_desc_t *usb_stor_get_dev(int index)
 {
-	return &usb_dev_desc[index];
+	return (index < USB_MAX_STOR_DEV) ? &usb_dev_desc[index] : NULL;
 }
 
 
@@ -940,7 +941,7 @@ static void usb_bin_fixup(struct usb_device_descriptor descriptor,
 
 #define USB_MAX_READ_BLK 20
 
-unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, unsigned long *buffer)
+unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer)
 {
 	unsigned long start,blks, buf_addr;
 	unsigned short smallblks;
diff --git a/config.mk b/config.mk
index 6e280bc..582df32 100644
--- a/config.mk
+++ b/config.mk
@@ -70,7 +70,7 @@ endif
 endif
 
 ifeq ($(ARCH),blackfin)
-PLATFORM_CPPFLAGS+= -D__BLACKFIN__ -mno-underscore
+PLATFORM_CPPFLAGS+= -D__BLACKFIN__
 endif
 
 ifdef	ARCH
diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c
index ca45e17..f4e5fc5 100644
--- a/cpu/74xx_7xx/cpu.c
+++ b/cpu/74xx_7xx/cpu.c
@@ -101,6 +101,10 @@ get_cpu_type(void)
 		type = CPU_7457;
 		break;
 
+	case 0x8004:
+		type = CPU_7448;
+		break;
+
 	default:
 		break;
 	}
@@ -152,6 +156,10 @@ int checkcpu (void)
 		str = "MPC7410";
 		break;
 
+	case CPU_7448:
+		str = "MPC7448";
+		break;
+
 	case CPU_7450:
 		str = "MPC7450";
 		break;
@@ -221,7 +229,7 @@ soft_restart(unsigned long addr)
 void
 do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-    	ulong addr;
+	ulong addr;
 	/* flush and disable I/D cache */
 	__asm__ __volatile__ ("mfspr	3, 1008"	::: "r3");
 	__asm__ __volatile__ ("ori	5, 5, 0xcc00"	::: "r5");
diff --git a/cpu/74xx_7xx/cpu_init.c b/cpu/74xx_7xx/cpu_init.c
index 93f180f..e02a4cc 100644
--- a/cpu/74xx_7xx/cpu_init.c
+++ b/cpu/74xx_7xx/cpu_init.c
@@ -43,6 +43,7 @@ cpu_init_f (void)
 	case CPU_7450:
 	case CPU_7455:
 	case CPU_7457:
+	case CPU_7448:
 		/* enable the timebase bit in HID0 */
 		set_hid0(get_hid0() | 0x4000000);
 		break;
diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c
index 2dc5107..d1800ed 100644
--- a/cpu/74xx_7xx/speed.c
+++ b/cpu/74xx_7xx/speed.c
@@ -91,6 +91,7 @@ int get_clocks (void)
 
 	/* calculate the clock frequency based upon the CPU type */
 	switch (get_cpu_type()) {
+	case CPU_7448:
 	case CPU_7455:
 	case CPU_7457:
 		/*
diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S
index 1fc0fe6..1143038 100644
--- a/cpu/74xx_7xx/start.S
+++ b/cpu/74xx_7xx/start.S
@@ -44,7 +44,8 @@
 
 #if !defined(CONFIG_DB64360) && \
     !defined(CONFIG_DB64460) && \
-    !defined(CONFIG_CPCI750)
+    !defined(CONFIG_CPCI750) && \
+    !defined(CONFIG_P3Mx)
 #include <galileo/gt64260R.h>
 #endif
 
@@ -270,7 +271,7 @@ in_flash:
 	 * gt-regs BAT can be reused after board_init_f calls
 	 * board_early_init_f (EVB only).
 	 */
-#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC)
+#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
 	/* enable address translation */
 	bl	enable_addr_trans
 	sync
@@ -757,7 +758,8 @@ in_ram:
     defined(CONFIG_DB64360)	 || \
     defined(CONFIG_DB64460)      || \
     defined(CONFIG_CPCI750)	|| \
-    defined(CONFIG_PPMC7XX)
+    defined(CONFIG_PPMC7XX)     || \
+    defined(CONFIG_P3Mx)
 	mr	r4, r9		/* Use RAM copy of the global data */
 #endif
 	bl	after_reloc
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index a5b6de7..60c1aa9 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -73,7 +73,7 @@ int cleanup_before_linux (void)
 	/* go to high speed */
 	IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
 #endif
-#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B)
+#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
 	disable_interrupts ();
 	/* Nothing more needed */
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
@@ -252,6 +252,7 @@ int dcache_status (void)
 	void icache_enable (void)
 	{
 	}
+#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */
 #else
 #error No icache/dcache enable/disable functions defined for this CPU type
 #endif
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c
index da62502..8f32124 100644
--- a/cpu/arm720t/interrupts.c
+++ b/cpu/arm720t/interrupts.c
@@ -36,6 +36,12 @@
 #define TIMER_LOAD_VAL 0xffff
 /* macro to read the 16 bit timer */
 #define READ_TIMER (IO_TC1D & 0xffff)
+
+#ifdef CONFIG_LPC2292
+#undef READ_TIMER
+#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
+#endif
+
 #else
 #define IRQEN	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
 #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
@@ -195,6 +201,13 @@ void do_irq (struct pt_regs *pt_regs)
 	}
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 	/* No do_irq() for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_LPC2292)
+
+    void (*pfnct)(void);
+
+    pfnct = (void (*)(void))VICVectAddr;
+
+    (*pfnct)();
 #else
 #error do_irq() not defined for this CPU type
 #endif
@@ -293,6 +306,13 @@ int interrupt_init (void)
 
 	/* Start timer */
 	SET_REG( REG_TMOD, TM0_RUN);
+#elif defined(CONFIG_LPC2292)
+	PUT32(T0IR, 0);		/* disable all timer0 interrupts */
+	PUT32(T0TCR, 0);	/* disable timer0 */
+	PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ);
+ 	PUT32(T0MCR, 0);
+	PUT32(T0TC, 0);
+	PUT32(T0TCR, 1);	/* enable timer0 */
 
 #else
 #error No interrupt_init() defined for this CPU type
@@ -309,7 +329,7 @@ int interrupt_init (void)
  */
 
 
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292)
 
 void reset_timer (void)
 {
@@ -337,7 +357,12 @@ void udelay (unsigned long usec)
 	tmo += get_timer (0);
 
 	while (get_timer_masked () < tmo)
+#ifdef CONFIG_LPC2292
+		/* GJ - not sure whether this is really needed or a misunderstanding */
+		__asm__ __volatile__(" nop");
+#else
 		/*NOP*/;
+#endif
 }
 
 void reset_timer_masked (void)
diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c
index 054bab9..15c54af 100644
--- a/cpu/arm720t/serial.c
+++ b/cpu/arm720t/serial.c
@@ -123,4 +123,80 @@ serial_puts (const char *s)
 	}
 }
 
-#endif /* defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) */
+#elif defined(CONFIG_LPC2292)
+
+#include <asm/arch/hardware.h>
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned short divisor = 0;
+
+	switch (gd->baudrate) {
+	case   1200:	divisor = 3072;	break;
+	case   9600:	divisor =  384;	break;
+	case  19200:	divisor =  192;	break;
+	case  38400:	divisor =   96;	break;
+	case  57600:	divisor =   64;	break;
+	case 115200:	divisor =   32;	break;
+	default:	hang ();	break;
+	}
+
+	/* init serial UART0 */
+	PUT8(U0LCR, 0);
+	PUT8(U0IER, 0);
+	PUT8(U0LCR, 0x80);	/* DLAB=1 */
+	PUT8(U0DLL, (unsigned char)(divisor & 0x00FF));
+	PUT8(U0DLM, (unsigned char)(divisor >> 8));
+	PUT8(U0LCR, 0x03);	/* 8N1, DLAB=0  */
+	PUT8(U0FCR, 1);		/* Enable RX and TX FIFOs */
+}
+
+int serial_init (void)
+{
+	unsigned long pinsel0;
+
+	serial_setbrg ();
+
+	pinsel0 = GET32(PINSEL0);
+	pinsel0 &= ~(0x00000003);
+	pinsel0 |= 5;
+	PUT32(PINSEL0, pinsel0);
+
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+	{
+		while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
+		PUT8(U0THR, '\r');
+	}
+
+	while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
+	PUT8(U0THR, c);
+}
+
+int serial_getc (void)
+{
+	while((GET8(U0LSR) & 1) == 0);
+	return GET8(U0RBR);
+}
+
+void
+serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+/* Test if there is a byte to read */
+int serial_tstc (void)
+{
+	return (GET8(U0LSR) & 1);
+}
+
+#endif
diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S
index e66d109..8423e4f 100644
--- a/cpu/arm720t/start.S
+++ b/cpu/arm720t/start.S
@@ -43,7 +43,11 @@ _start: b	reset
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
+#ifdef CONFIG_LPC2292
+	.word	0xB4405F76 /* 2's complement of the checksum of the vectors */
+#else
 	ldr	pc, _not_used
+#endif
 	ldr	pc, _irq
 	ldr	pc, _fiq
 
@@ -123,6 +127,10 @@ reset:
 	bl	cpu_init_crit
 #endif
 
+#ifdef CONFIG_LPC2292
+	bl	lowlevel_init
+#endif
+
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 relocate:				/* relocate U-Boot to RAM	    */
 	adr	r0, _start		/* r0 <- current position of code   */
@@ -131,6 +139,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	beq	stack_setup
 
 #if TEXT_BASE
+#ifndef CONFIG_LPC2292 /* already done in lowlevel_init */
 	ldr	r2, =0x0		/* Relocate the exception vectors   */
 	cmp	r1, r2			/* and associated data to address   */
 	ldmneia r0!, {r3-r10}		/* 0x0. Do nothing if TEXT_BASE is  */
@@ -138,6 +147,7 @@ relocate:				/* relocate U-Boot to RAM	    */
 	ldmneia r0, {r3-r9}
 	stmneia r2, {r3-r9}
 	adrne	r0, _start		/* restore r0			    */
+#endif	/* !CONFIG_LPC2292 */
 #endif
 
 	ldr	r2, _armboot_start
@@ -206,6 +216,14 @@ SYSCON3:	.word	0x80002200
 #define CLKCTL_49      0x4  /* 49.152 MHz */
 #define CLKCTL_73      0x6  /* 73.728 MHz */
 
+#elif defined(CONFIG_LPC2292)
+PLLCFG_ADR:	.word	PLLCFG
+PLLFEED_ADR:	.word	PLLFEED
+PLLCON_ADR:	.word	PLLCON
+PLLSTAT_ADR:	.word	PLLSTAT
+VPBDIV_ADR:	.word	VPBDIV
+MEMMAP_ADR:	.word	MEMMAP
+
 #endif
 
 cpu_init_crit:
@@ -306,6 +324,50 @@ cpu_init_crit:
 
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 	/* No specific initialisation for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_LPC2292)
+	/* Set-up PLL */
+	mov	r3, #0xAA
+	mov	r4, #0x55
+	/* First disconnect and disable the PLL */
+	ldr	r0, PLLCON_ADR
+	mov	r1, #0x00
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Set new M and P values */
+	ldr	r0, PLLCFG_ADR
+	mov	r1, #0x23	/* M=4 and P=2 */
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Then enable the PLL */
+	ldr	r0, PLLCON_ADR
+	mov	r1, #0x01	/* PLL enable bit */
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Wait for the lock */
+	ldr	r0, PLLSTAT_ADR
+	mov	r1, #0x400	/* lock bit */
+lock_loop:
+	ldr	r2, [r0]
+	and	r2, r1, r2
+	cmp	r2, #0
+	beq	lock_loop
+	/* And finally connect the PLL */
+	ldr	r0, PLLCON_ADR
+	mov	r1, #0x03	/* PLL enable bit and connect bit */
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Set-up VPBDIV register */
+	ldr	r0, VPBDIV_ADR
+	mov	r1, #0x01	/* VPB clock is same as process clock */
+	str	r1, [r0]
 #else
 #error No cpu_init_crit() defined for current CPU type
 #endif
@@ -321,6 +383,7 @@ cpu_init_crit:
 	str	r1, [r0]
 #endif
 
+#ifndef CONFIG_LPC2292
 	mov	ip, lr
 	/*
 	 * before relocating, we have to setup RAM timing
@@ -329,6 +392,7 @@ cpu_init_crit:
 	 */
 	bl	lowlevel_init
 	mov	lr, ip
+#endif
 
 	mov	pc, lr
 
@@ -537,6 +601,11 @@ reset_cpu:
  * on external peripherals such as watchdog timers, etc. */
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 	/* No specific reset actions for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_LPC2292)
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	mov	pc, r0
 #else
 #error No reset_cpu() defined for current CPU type
 #endif
diff --git a/cpu/bf533/Makefile b/cpu/bf533/Makefile
index 9f4a0d8..90018f3 100644
--- a/cpu/bf533/Makefile
+++ b/cpu/bf533/Makefile
@@ -28,14 +28,16 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).a
 
-START	= start.o start1.o interrupt.o cache.o cplbhdlr.o cplbmgr.o flush.o
-COBJS	= cpu.o traps.o ints.o serial.o interrupts.o
+START	= start.o start1.o interrupt.o cache.o flush.o init_sdram.o
+COBJS	= cpu.o traps.o ints.o serial.o interrupts.o video.o
+
+EXTRA = init_sdram_bootrom_initblock.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 START	:= $(addprefix $(obj),$(START))
 
-all:	$(obj).depend $(START) $(LIB)
+all:	$(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
 
 $(LIB):	$(OBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h
index d430e6c..0a04f3e 100644
--- a/cpu/bf533/bf533_serial.h
+++ b/cpu/bf533/bf533_serial.h
@@ -63,8 +63,7 @@ int serial_getc(void);
 void serial_puts(const char *s);
 static void local_put_char(char ch);
 
-extern int get_clock(void);
-int baud_table[5] = {9600, 19200, 38400, 57600, 115200};
+int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
 
 struct {
 	unsigned char dl_high;
diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
index 8fac402..03aebe4 100644
--- a/cpu/bf533/cache.S
+++ b/cpu/bf533/cache.S
@@ -1,12 +1,11 @@
-
-
 #define ASSEMBLY
 #include <asm/linkage.h>
-#include <asm/cpu/def_LPBlackfin.h>
+#include <config.h>
+#include <asm/blackfin.h>
 
 .text
 .align 2
-ENTRY(blackfin_icache_flush_range)
+ENTRY(_blackfin_icache_flush_range)
 	R2 = -32;
 	R2 = R0 & R2;
 	P0 = R2;
@@ -20,7 +19,7 @@ ENTRY(blackfin_icache_flush_range)
 	SSYNC;
 	RTS;
 
-ENTRY(blackfin_dcache_flush_range)
+ENTRY(_blackfin_dcache_flush_range)
 	R2 = -32;
 	R2 = R0 & R2;
 	P0 = R2;
@@ -35,19 +34,21 @@ ENTRY(blackfin_dcache_flush_range)
 	RTS;
 
 ENTRY(_icache_invalidate)
-ENTRY(invalidate_entire_icache)
-	[--SP] = ( R7:5);
+ENTRY(_invalidate_entire_icache)
+	[--SP] = (R7:5);
 
 	P0.L = (IMEM_CONTROL & 0xFFFF);
 	P0.H = (IMEM_CONTROL >> 16);
-	R7 = [P0];
+	R7 =[P0];
 
-	/* Clear the IMC bit , All valid bits in the instruction
+	/*
+	 * Clear the IMC bit , All valid bits in the instruction
 	 * cache are set to the invalid state
 	 */
-	BITCLR(R7,IMC_P);
+	BITCLR(R7, IMC_P);
 	CLI R6;
-	SSYNC;		/* SSYNC required before invalidating cache. */
+	/* SSYNC required before invalidating cache. */
+	SSYNC;
 	.align 8;
 	[P0] = R7;
 	SSYNC;
@@ -58,54 +59,55 @@ ENTRY(invalidate_entire_icache)
 	R7 = R7 | R6;
 
 	CLI R6;
-	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
+	SSYNC;
 	.align 8;
 	[P0] = R7;
 	SSYNC;
 	STI R6;
 
-	( R7:5) = [SP++];
+	(R7:5) =[SP++];
 	RTS;
 
-/* Invalidate the Entire Data cache by
+/*
+ * Invalidate the Entire Data cache by
  * clearing DMC[1:0] bits
  */
-ENTRY(invalidate_entire_dcache)
+ENTRY(_invalidate_entire_dcache)
 ENTRY(_dcache_invalidate)
-	[--SP] = ( R7:6);
+	[--SP] = (R7:6);
 
 	P0.L = (DMEM_CONTROL & 0xFFFF);
 	P0.H = (DMEM_CONTROL >> 16);
-	R7 = [P0];
+	R7 =[P0];
 
-	/* Clear the DMC[1:0] bits, All valid bits in the data
+	/*
+	 * Clear the DMC[1:0] bits, All valid bits in the data
 	 * cache are set to the invalid state
 	 */
-	BITCLR(R7,DMC0_P);
-	BITCLR(R7,DMC1_P);
+	BITCLR(R7, DMC0_P);
+	BITCLR(R7, DMC1_P);
 	CLI R6;
-	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */
+	SSYNC;
 	.align 8;
 	[P0] = R7;
 	SSYNC;
 	STI R6;
-
 	/* Configures the data cache again */
 
 	R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
 	R7 = R7 | R6;
 
 	CLI R6;
-	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */
+	SSYNC;
 	.align 8;
 	[P0] = R7;
 	SSYNC;
 	STI R6;
 
-	( R7:6) = [SP++];
+	(R7:6) =[SP++];
 	RTS;
 
-ENTRY(blackfin_dcache_invalidate_range)
+ENTRY(_blackfin_dcache_invalidate_range)
 	R2 = -32;
 	R2 = R0 & R2;
 	P0 = R2;
@@ -113,13 +115,14 @@ ENTRY(blackfin_dcache_invalidate_range)
 	CSYNC;
 1:
 	FLUSHINV[P0++];
-	CC = P0 < P1 (iu);
-	IF CC JUMP 1b (bp);
+	CC = P0 < P1(iu);
+	IF CC JUMP 1b(bp);
 
-	/* If the data crosses a cache line, then we'll be pointing to
-	** the last cache line, but won't have flushed/invalidated it yet, so do
-	** one more.
-	*/
+	/*
+	 * If the data crosses a cache line, then we'll be pointing to
+	 * the last cache line, but won't have flushed/invalidated it yet, so do
+	 * one more.
+	 */
 	FLUSHINV[P0];
 	SSYNC;
 	RTS;
diff --git a/cpu/bf533/config.mk b/cpu/bf533/config.mk
index a9d529e..10817d9 100644
--- a/cpu/bf533/config.mk
+++ b/cpu/bf533/config.mk
@@ -24,4 +24,4 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -ffixed-P5
+PLATFORM_RELFLAGS += -mcpu=bf533 -ffixed-P5
diff --git a/cpu/bf533/cplbhdlr.S b/cpu/bf533/cplbhdlr.S
deleted file mode 100644
index 61be5bb..0000000
--- a/cpu/bf533/cplbhdlr.S
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.
- *
- * Blackfin BF533/2.6 support : LG Soft India
- */
-
-
-/* Include an exception handler to invoke the CPLB manager
- */
-
-#include <asm-blackfin/linkage.h>
-#include <asm/cplb.h>
-#include <asm/entry.h>
-
-
-.text
-
-.globl _cplb_hdr;
-.type _cplb_hdr, STT_FUNC;
-.extern _cplb_mgr;
-.type _cplb_mgr, STT_FUNC;
-.extern __unknown_exception_occurred;
-.type __unknown_exception_occurred, STT_FUNC;
-.extern __cplb_miss_all_locked;
-.type __cplb_miss_all_locked, STT_FUNC;
-.extern __cplb_miss_without_replacement;
-.type __cplb_miss_without_replacement, STT_FUNC;
-.extern __cplb_protection_violation;
-.type __cplb_protection_violation, STT_FUNC;
-.extern panic_pv;
-
-.align 2;
-
-ENTRY(_cplb_hdr)
-	SSYNC;
-	[--SP] = ( R7:0, P5:0 );
-	[--SP] = ASTAT;
-	[--SP] = SEQSTAT;
-	[--SP] = I0;
-	[--SP] = I1;
-	[--SP] = I2;
-	[--SP] = I3;
-	[--SP] = LT0;
-	[--SP] = LB0;
-	[--SP] = LC0;
-	[--SP] = LT1;
-	[--SP] = LB1;
-	[--SP] = LC1;
-	R2 = SEQSTAT;
-
-	/*Mask the contents of SEQSTAT and leave only EXCAUSE in R2*/
-	R2 <<= 26;
-	R2 >>= 26;
-
-	R1 = 0x23; /* Data access CPLB protection violation */
-	CC = R2 == R1;
-	IF !CC JUMP not_data_write;
-	R0 = 2;		/* is a write to data space*/
-	JUMP is_icplb_miss;
-
-not_data_write:
-	R1 = 0x2C; /* CPLB miss on an instruction fetch */
-	CC = R2 == R1;
-	R0 = 0;		/* is_data_miss == False*/
-	IF CC JUMP is_icplb_miss;
-
-	R1 = 0x26;
-	CC = R2 == R1;
-	IF !CC JUMP unknown;
-
-	R0 = 1;		/* is_data_miss == True*/
-
-is_icplb_miss:
-
-#if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE))
-#if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE))
-	R1 = CPLB_ENABLE_ICACHE;
-#endif
-#if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
-	R1 = CPLB_ENABLE_DCACHE;
-#endif
-#if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
-	R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
-#endif
-#else
-	R1 = 0;
-#endif
-
-	[--SP] = RETS;
-	CALL _cplb_mgr;
-	RETS = [SP++];
-	CC = R0 == 0;
-	IF !CC JUMP not_replaced;
-	LC1 = [SP++];
-	LB1 = [SP++];
-	LT1 = [SP++];
-	LC0 = [SP++];
-	LB0 = [SP++];
-	LT0 = [SP++];
-	I3 = [SP++];
-	I2 = [SP++];
-	I1 = [SP++];
-	I0 = [SP++];
-	SEQSTAT = [SP++];
-	ASTAT = [SP++];
-	( R7:0, P5:0 ) = [SP++];
-	RTS;
-
-unknown:
-	[--SP] = RETS;
-	CALL __unknown_exception_occurred;
-	RETS = [SP++];
-	JUMP unknown;
-not_replaced:
-	CC = R0 == CPLB_NO_UNLOCKED;
-	IF !CC JUMP next_check;
-	[--SP] = RETS;
-	CALL __cplb_miss_all_locked;
-	RETS = [SP++];
-next_check:
-	CC = R0 == CPLB_NO_ADDR_MATCH;
-	IF !CC JUMP next_check2;
-	[--SP] = RETS;
-	CALL __cplb_miss_without_replacement;
-	RETS = [SP++];
-	JUMP not_replaced;
-next_check2:
-	CC = R0 == CPLB_PROT_VIOL;
-	IF !CC JUMP strange_return_from_cplb_mgr;
-	[--SP] = RETS;
-	CALL __cplb_protection_violation;
-	RETS = [SP++];
-	JUMP not_replaced;
-strange_return_from_cplb_mgr:
-	IDLE;
-	CSYNC;
-	JUMP strange_return_from_cplb_mgr;
-
-/************************************
- * Diagnostic exception handlers
- */
-
-__cplb_miss_all_locked:
-	sp += -12;
-	R0 = CPLB_NO_UNLOCKED;
-	call panic_bfin;
-	SP += 12;
-	RTS;
-
- __cplb_miss_without_replacement:
-	sp += -12;
-	R0 = CPLB_NO_ADDR_MATCH;
-	call panic_bfin;
-	SP += 12;
-	RTS;
-
-__cplb_protection_violation:
-	sp += -12;
-	R0 = CPLB_PROT_VIOL;
-	call panic_bfin;
-	SP += 12;
-	RTS;
-
-__unknown_exception_occurred:
-
-	/* This function is invoked by the default exception
-	 * handler, if it does not recognise the kind of
-	 * exception that has occurred. In other words, the
-	 * default handler only handles some of the system's
-	 * exception types, and it does not expect any others
-	 * to occur. If your application is going to be using
-	 * other kinds of exceptions, you must replace the
-	 * default handler with your own, that handles all the
-	 * exceptions you will use.
-	 *
-	 * Since there's nothing we can do, we just loop here
-	 * at what we hope is a suitably informative label.
-	 */
-
-	IDLE;
-do_not_know_what_to_do:
-	CSYNC;
-	JUMP __unknown_exception_occurred;
-
-	RTS;
-.__unknown_exception_occurred.end:
-.global __unknown_exception_occurred;
-.type __unknown_exception_occurred, STT_FUNC;
-
-panic_bfin:
-	RTS;
diff --git a/cpu/bf533/cplbmgr.S b/cpu/bf533/cplbmgr.S
deleted file mode 100644
index 7a0b048..0000000
--- a/cpu/bf533/cplbmgr.S
+++ /dev/null
@@ -1,601 +0,0 @@
-/*This file is subject to the terms and conditions of the GNU General Public
- * License.
- *
- * Blackfin BF533/2.6 support : LG Soft India
- * Modification: Dec 07 2004
- *	1. Correction in icheck_lock.  Valid lock entries were
- *	   geting victimized, for instruction cplb replacement.
- *	2. Setup loop's are modified as now toolchain support's P Indexed
- *	   addressing
- *	   :LG Soft India
- *
- */
-
-/* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
- * is_data_miss==2 => Mark as Dirty, write to the clean data page
- * is_data_miss==1 => Replace a data CPLB.
- * is_data_miss==0 => Replace an instruction CPLB.
- *
- * Returns:
- * CPLB_RELOADED	=> Successfully updated CPLB table.
- * CPLB_NO_UNLOCKED	=> All CPLBs are locked, so cannot be evicted.This indicates
- *				that the CPLBs in the configuration tablei are badly
- *				configured, as this should never occur.
- * CPLB_NO_ADDR_MATCH	=> The address being accessed, that triggered the exception,
- *				is not covered by any of the CPLBs in the configuration
- *				table. The application isi presumably misbehaving.
- * CPLB_PROT_VIOL	=> The address being accessed, that triggered thei exception,
- *				was not a first-write to a clean Write Back Data page,
- *				and so presumably is a genuine violation of the page's
- *				protection attributes. The application is misbehaving.
- */
-#define ASSEMBLY
-
-#include <asm-blackfin/linkage.h>
-#include <asm-blackfin/blackfin.h>
-#include <asm-blackfin/cplbtab.h>
-#include <asm-blackfin/cplb.h>
-
-.text
-
-.align 2;
-ENTRY(_cplb_mgr)
-
-	[--SP]=( R7:0,P5:0 );
-
-	CC = R0 == 2;
-	IF CC JUMP dcplb_write;
-
-	CC = R0 == 0;
-	IF !CC JUMP dcplb_miss_compare;
-
-	/* ICPLB Miss Exception. We need to choose one of the
-	* currently-installed CPLBs, and replace it with one
-	* from the configuration table.
-	*/
-
-	P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
-	P4.H = (ICPLB_FAULT_ADDR >> 16);
-
-	P1 = 16;
-	P5.L = page_size_table;
-	P5.H = page_size_table;
-
-	P0.L = (ICPLB_DATA0 & 0xFFFF);
-	P0.H = (ICPLB_DATA0 >> 16);
-	R4 = [P4];		/* Get faulting address*/
-	R6 = 64;		/* Advance past the fault address, which*/
-	R6 = R6 + R4;		/* we'll use if we find a match*/
-	R3 = ((16 << 8) | 2);	/* Extract mask, bits 16 and 17.*/
-
-	R5 = 0;
-isearch:
-
-	R1 = [P0-0x100];	/* Address for this CPLB */
-
-	R0 = [P0++];		/* Info for this CPLB*/
-	CC = BITTST(R0,0);	/* Is the CPLB valid?*/
-	IF !CC JUMP nomatch;	/* Skip it, if not.*/
-	CC = R4 < R1(IU);	/* If fault address less than page start*/
-	IF CC JUMP nomatch;	/* then skip this one.*/
-	R2 = EXTRACT(R0,R3.L) (Z);	/* Get page size*/
-	P1 = R2;
-	P1 = P5 + (P1<<2);	/* index into page-size table*/
-	R2 = [P1];		/* Get the page size*/
-	R1 = R1 + R2;		/* and add to page start, to get page end*/
-	CC = R4 < R1(IU);	/* and see whether fault addr is in page.*/
-	IF !CC R4 = R6;		/* If so, advance the address and finish loop.*/
-	IF !CC JUMP isearch_done;
-nomatch:
-	/* Go around again*/
-	R5 += 1;
-	CC = BITTST(R5, 4);	/* i.e CC = R5 >= 16*/
-	IF !CC JUMP isearch;
-
-isearch_done:
-	I0 = R4;		/* Fault address we'll search for*/
-
-	/* set up pointers */
-	P0.L = (ICPLB_DATA0 & 0xFFFF);
-	P0.H = (ICPLB_DATA0 >> 16);
-
-	/* The replacement procedure for ICPLBs */
-
-	P4.L = (IMEM_CONTROL & 0xFFFF);
-	P4.H = (IMEM_CONTROL >> 16);
-
-	/* disable cplbs */
-	R5 = [P4];		/* Control Register*/
-	BITCLR(R5,ENICPLB_P);
-	CLI R1;
-	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
-	.align 8;
-	[P4] = R5;
-	SSYNC;
-	STI R1;
-
-	R1 = -1;		/* end point comparison */
-	R3 = 16;		/* counter */
-
-	/* Search through CPLBs for first non-locked entry */
-	/* Overwrite it by moving everyone else up by 1 */
-icheck_lock:
-	R0 = [P0++];
-	R3 = R3 + R1;
-	CC = R3 == R1;
-	IF CC JUMP all_locked;
-	CC = BITTST(R0, 0);		/* an invalid entry is good */
-	IF !CC JUMP ifound_victim;
-	CC = BITTST(R0,1);		/* but a locked entry isn't */
-	IF CC JUMP icheck_lock;
-
-ifound_victim:
-#ifdef CONFIG_CPLB_INFO
-	R7 = [P0 - 0x104];
-	P2.L = ipdt_table;
-	P2.H = ipdt_table;
-	P3.L = ipdt_swapcount_table;
-	P3.H = ipdt_swapcount_table;
-	P3 += -4;
-icount:
-	R2 = [P2];	/* address from config table */
-	P2 += 8;
-	P3 += 8;
-	CC = R2==-1;
-	IF CC JUMP icount_done;
-	CC = R7==R2;
-	IF !CC JUMP icount;
-	R7 = [P3];
-	R7 += 1;
-	[P3] = R7;
-	CSYNC;
-icount_done:
-#endif
-	LC0=R3;
-	LSETUP(is_move,ie_move) LC0;
-is_move:
-	R0 = [P0];
-	[P0 - 4] = R0;
-	R0 = [P0 - 0x100];
-	[P0-0x104] = R0;
-ie_move:P0+=4;
-
-	/* We've made space in the ICPLB table, so that ICPLB15
-	 * is now free to be overwritten. Next, we have to determine
-	 * which CPLB we need to install, from the configuration
-	 * table. This is a matter of getting the start-of-page
-	 * addresses and page-lengths from the config table, and
-	 * determining whether the fault address falls within that
-	 * range.
-	 */
-
-	P2.L = ipdt_table;
-	P2.H = ipdt_table;
-#ifdef	CONFIG_CPLB_INFO
-	P3.L = ipdt_swapcount_table;
-	P3.H = ipdt_swapcount_table;
-	P3 += -8;
-#endif
-	P0.L = page_size_table;
-	P0.H = page_size_table;
-
-	/* Retrieve our fault address (which may have been advanced
-	 * because the faulting instruction crossed a page boundary).
-	 */
-
-	R0 = I0;
-
-	/* An extraction pattern, to get the page-size bits from
-	 * the CPLB data entry. Bits 16-17, so two bits at posn 16.
-	 */
-
-	R1 = ((16<<8)|2);
-inext:	R4 = [P2++];	/* address from config table */
-	R2 = [P2++];	/* data from config table */
-#ifdef	CONFIG_CPLB_INFO
-	P3 += 8;
-#endif
-
-	CC = R4 == -1;	/* End of config table*/
-	IF CC JUMP no_page_in_table;
-
-	/* See if failed address > start address */
-	CC = R4 <= R0(IU);
-	IF !CC JUMP inext;
-
-	/* extract page size (17:16)*/
-	R3 = EXTRACT(R2, R1.L) (Z);
-
-	/* add page size to addr to get range */
-
-	P5 = R3;
-	P5 = P0 + (P5 << 2);	/* scaled, for int access*/
-	R3 = [P5];
-	R3 = R3 + R4;
-
-	/* See if failed address < (start address + page size) */
-	CC = R0 < R3(IU);
-	IF !CC JUMP inext;
-
-	/* We've found a CPLB in the config table that covers
-	 * the faulting address, so install this CPLB into the
-	 * last entry of the table.
-	 */
-
-	P1.L = (ICPLB_DATA15 & 0xFFFF);		/*ICPLB_DATA15*/
-	P1.H = (ICPLB_DATA15 >> 16);
-	[P1] = R2;
-	[P1-0x100] = R4;
-#ifdef	CONFIG_CPLB_INFO
-	R3 = [P3];
-	R3 += 1;
-	[P3] = R3;
-#endif
-
-	/* P4 points to IMEM_CONTROL, and R5 contains its old
-	 * value, after we disabled ICPLBS. Re-enable them.
-	 */
-
-	BITSET(R5,ENICPLB_P);
-	CLI R2;
-	SSYNC;		/* SSYNC required before writing to IMEM_CONTROL. */
-	.align 8;
-	[P4] = R5;
-	SSYNC;
-	STI R2;
-
-	( R7:0,P5:0 ) = [SP++];
-	R0 = CPLB_RELOADED;
-	RTS;
-
-/* FAILED CASES*/
-no_page_in_table:
-	( R7:0,P5:0 ) = [SP++];
-	R0 = CPLB_NO_ADDR_MATCH;
-	RTS;
-all_locked:
-	( R7:0,P5:0 ) = [SP++];
-	R0 = CPLB_NO_UNLOCKED;
-	RTS;
-prot_violation:
-	( R7:0,P5:0 ) = [SP++];
-	R0 = CPLB_PROT_VIOL;
-	RTS;
-
-dcplb_write:
-
-	/* if a DCPLB is marked as write-back (CPLB_WT==0), and
-	 * it is clean (CPLB_DIRTY==0), then a write to the
-	 * CPLB's page triggers a protection violation. We have to
-	 * mark the CPLB as dirty, to indicate that there are
-	 * pending writes associated with the CPLB.
-	 */
-
-	P4.L = (DCPLB_STATUS & 0xFFFF);
-	P4.H = (DCPLB_STATUS >> 16);
-	P3.L = (DCPLB_DATA0 & 0xFFFF);
-	P3.H = (DCPLB_DATA0 >> 16);
-	R5 = [P4];
-
-	/* A protection violation can be caused by more than just writes
-	 * to a clean WB page, so we have to ensure that:
-	 * - It's a write
-	 * - to a clean WB page
-	 * - and is allowed in the mode the access occurred.
-	 */
-
-	CC = BITTST(R5, 16);	/* ensure it was a write*/
-	IF !CC JUMP prot_violation;
-
-	/* to check the rest, we have to retrieve the DCPLB.*/
-
-	/* The low half of DCPLB_STATUS is a bit mask*/
-
-	R2 = R5.L (Z);	/* indicating which CPLB triggered the event.*/
-	R3 = 30;	/* so we can use this to determine the offset*/
-	R2.L = SIGNBITS R2;
-	R2 = R2.L (Z);	/* into the DCPLB table.*/
-	R3 = R3 - R2;
-	P4 = R3;
-	P3 = P3 + (P4<<2);
-	R3 = [P3];	/* Retrieve the CPLB*/
-
-	/* Now we can check whether it's a clean WB page*/
-
-	CC = BITTST(R3, 14);	/* 0==WB, 1==WT*/
-	IF CC JUMP prot_violation;
-	CC = BITTST(R3, 7);	/* 0 == clean, 1 == dirty*/
-	IF CC JUMP prot_violation;
-
-	/* Check whether the write is allowed in the mode that was active.*/
-
-	R2 = 1<<3;		/* checking write in user mode*/
-	CC = BITTST(R5, 17);	/* 0==was user, 1==was super*/
-	R5 = CC;
-	R2 <<= R5;		/* if was super, check write in super mode*/
-	R2 = R3 & R2;
-	CC = R2 == 0;
-	IF CC JUMP prot_violation;
-
-	/* It's a genuine write-to-clean-page.*/
-
-	BITSET(R3, 7);		/* mark as dirty*/
-	[P3] = R3;		/* and write back.*/
-	CSYNC;
-	( R7:0,P5:0 ) = [SP++];
-	R0 = CPLB_RELOADED;
-	RTS;
-
-dcplb_miss_compare:
-
-	/* Data CPLB Miss event. We need to choose a CPLB to
-	 * evict, and then locate a new CPLB to install from the
-	 * config table, that covers the faulting address.
-	 */
-
-	P1.L = (DCPLB_DATA15 & 0xFFFF);
-	P1.H = (DCPLB_DATA15 >> 16);
-
-	P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
-	P4.H = (DCPLB_FAULT_ADDR >> 16);
-	R4 = [P4];
-	I0 = R4;
-
-	/* The replacement procedure for DCPLBs*/
-
-	R6 = R1;	/* Save for later*/
-
-	/* Turn off CPLBs while we work.*/
-	P4.L = (DMEM_CONTROL & 0xFFFF);
-	P4.H = (DMEM_CONTROL >> 16);
-	R5 = [P4];
-	BITCLR(R5,ENDCPLB_P);
-	CLI R0;
-	SSYNC;		/* SSYNC required before writing to DMEM_CONTROL. */
-	.align 8;
-	[P4] = R5;
-	SSYNC;
-	STI R0;
-
-	/* Start looking for a CPLB to evict. Our order of preference
-	 * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
-	 * are no good.
-	 */
-
-	I1.L = (DCPLB_DATA0 & 0xFFFF);
-	I1.H = (DCPLB_DATA0 >> 16);
-	P1 = 3;
-	P2 = 16;
-	I2.L = dcplb_preference;
-	I2.H = dcplb_preference;
-	LSETUP(sdsearch1, edsearch1) LC0 = P1;
-sdsearch1:
-	R0 = [I2++];		/* Get the bits we're interested in*/
-	P0 = I1;		/* Go back to start of table*/
-	LSETUP (sdsearch2, edsearch2) LC1 = P2;
-sdsearch2:
-	R1 = [P0++];		/* Fetch each installed CPLB in turn*/
-	R2 = R1 & R0;		/* and test for interesting bits.*/
-	CC = R2 == 0;		/* If none are set, it'll do.*/
-	IF !CC JUMP skip_stack_check;
-
-	R2 = [P0 - 0x104];	/* R2 - PageStart */
-	P3.L = page_size_table; /* retrive end address */
-	P3.H = page_size_table; /* retrive end address */
-	R3 = 0x2;		/* 0th - position, 2 bits -length */
-	nop;			/*Anamoly 05000209*/
-	R7 = EXTRACT(R1,R3.l);
-	R7 = R7 << 2;		/* Page size index offset */
-	P5 = R7;
-	P3 = P3 + P5;
-	R7 = [P3];		/* page size in 1K bytes */
-
-	R7 = R7 << 0xA;		/* in bytes * 1024*/
-	R7 = R2 + R7;		/* R7 - PageEnd */
-	R4 = SP;		/* Test SP is in range */
-
-	CC = R7 < R4;		/* if PageEnd < SP */
-	IF CC JUMP dfound_victim;
-	R3 = 0x284;		/* stack length from start of trap till the point */
-				/* 20 stack locations for future modifications */
-	R4 = R4 + R3;
-	CC = R4 < R2;		/* if SP + stacklen < PageStart */
-	IF CC JUMP dfound_victim;
-skip_stack_check:
-
-edsearch2: NOP;
-edsearch1: NOP;
-
-	/* If we got here, we didn't find a DCPLB we considered
-	 * replacable, which means all of them were locked.
-	 */
-
-	JUMP all_locked;
-dfound_victim:
-
-#ifdef CONFIG_CPLB_INFO
-	R1 = [P0 - 0x104];
-	P2.L = dpdt_table;
-	P2.H = dpdt_table;
-	P3.L = dpdt_swapcount_table;
-	P3.H = dpdt_swapcount_table;
-	P3 += -4;
-dicount:
-	R2 = [P2];
-	P2 += 8;
-	P3 += 8;
-	CC = R2==-1;
-	IF CC JUMP dicount_done;
-	CC = R1==R2;
-	IF !CC JUMP dicount;
-	R1 = [P3];
-	R1 += 1;
-	[P3] = R1;
-	CSYNC;
-dicount_done:
-#endif
-
-	/* Clean down the hardware loops*/
-	R2 = 0;
-	LC1 = R2;
-	LC0 = R2;
-
-	/* There's a suitable victim in [P0-4] (because we've
-	 * advanced already). If it's a valid dirty write-back
-	 * CPLB, we need to flush the pending writes first.
-	 */
-
-	CC = BITTST(R1, 0);	/* Is it valid?*/
-	IF !CC JUMP Ddoverwrite;/* nope.*/
-	CC = BITTST(R1, 7);	/* Is it dirty?*/
-	IF !CC JUMP Ddoverwrite (BP);	/* Nope.*/
-	CC = BITTST(R1, 14);	/* Is it Write-Through?*/
-	IF CC JUMP Ddoverwrite; /* Yep*/
-
-	/* This is a dirty page, so we need to flush all writes
-	 * that are pending on the page.
-	 */
-
-	/* Retrieve the page start address*/
-	R0 = [P0 - 0x104];
-	[--sp] = rets;
-	CALL dcplb_flush;	/* R0==CPLB addr, R1==CPLB data*/
-	rets = [sp++];
-Ddoverwrite:
-
-	/* [P0-4] is a suitable victim CPLB, so we want to
-	 * overwrite it by moving all the following CPLBs
-	 * one space closer to the start.
-	 */
-
-	R1.L = ((DCPLB_DATA15+4) & 0xFFFF);		/*DCPLB_DATA15+4*/
-	R1.H = ((DCPLB_DATA15+4) >> 16);
-	R0 = P0;
-
-	/* If the victim happens to be in DCPLB15,
-	 * we don't need to move anything.
-	 */
-
-	CC = R1 == R0;
-	IF CC JUMP de_moved;
-	R1 = R1 - R0;
-	R1 >>= 2;
-	P1 = R1;
-	LSETUP(ds_move, de_move) LC0=P1;
-ds_move:
-	 R0 = [P0++];	/* move data */
-	[P0 - 8] = R0;
-	R0 = [P0-0x104] /* move address */
-de_move: [P0-0x108] = R0;
-
-	/* We've now made space in DCPLB15 for the new CPLB to be
-	 * installed. The next stage is to locate a CPLB in the
-	 * config table that covers the faulting address.
-	 */
-
-de_moved:NOP;
-	R0 = I0;		/* Our faulting address */
-
-	P2.L = dpdt_table;
-	P2.H = dpdt_table;
-#ifdef	CONFIG_CPLB_INFO
-	P3.L = dpdt_swapcount_table;
-	P3.H = dpdt_swapcount_table;
-	P3 += -8;
-#endif
-
-	P1.L = page_size_table;
-	P1.H = page_size_table;
-
-	/* An extraction pattern, to retrieve bits 17:16.*/
-
-	R1 = (16<<8)|2;
-dnext:	R4 = [P2++];	/* address */
-	R2 = [P2++];	/* data */
-#ifdef	CONFIG_CPLB_INFO
-	P3 += 8;
-#endif
-
-	CC = R4 == -1;
-	IF CC JUMP no_page_in_table;
-
-	/* See if failed address > start address */
-	CC = R4 <= R0(IU);
-	IF !CC JUMP dnext;
-
-	/* extract page size (17:16)*/
-	R3 = EXTRACT(R2, R1.L) (Z);
-
-	/* add page size to addr to get range */
-
-	P5 = R3;
-	P5 = P1 + (P5 << 2);
-	R3 = [P5];
-	R3 = R3 + R4;
-
-	/* See if failed address < (start address + page size) */
-	CC = R0 < R3(IU);
-	IF !CC JUMP dnext;
-
-	/* We've found the CPLB that should be installed, so
-	 * write it into CPLB15, masking off any caching bits
-	 * if necessary.
-	 */
-
-	P1.L = (DCPLB_DATA15 & 0xFFFF);
-	P1.H = (DCPLB_DATA15 >> 16);
-
-	/* If the DCPLB has cache bits set, but caching hasn't
-	 * been enabled, then we want to mask off the cache-in-L1
-	 * bit before installing. Moreover, if caching is off, we
-	 * also want to ensure that the DCPLB has WT mode set, rather
-	 * than WB, since WB pages still trigger first-write exceptions
-	 * even when not caching is off, and the page isn't marked as
-	 * cachable. Finally, we could mark the page as clean, not dirty,
-	 * but we choose to leave that decision to the user; if the user
-	 * chooses to have a CPLB pre-defined as dirty, then they always
-	 * pay the cost of flushing during eviction, but don't pay the
-	 * cost of first-write exceptions to mark the page as dirty.
-	 */
-
-#ifdef CONFIG_BLKFIN_WT
-	BITSET(R6, 14);		/* Set WT*/
-#endif
-
-	[P1] = R2;
-	[P1-0x100] = R4;
-#ifdef	CONFIG_CPLB_INFO
-	R3 = [P3];
-	R3 += 1;
-	[P3] = R3;
-#endif
-
-	/* We've installed the CPLB, so re-enable CPLBs. P4
-	 * points to DMEM_CONTROL, and R5 is the value we
-	 * last wrote to it, when we were disabling CPLBs.
-	 */
-
-	BITSET(R5,ENDCPLB_P);
-	CLI R2;
-	.align 8;
-	[P4] = R5;
-	SSYNC;
-	STI R2;
-
-	( R7:0,P5:0 ) = [SP++];
-	R0 = CPLB_RELOADED;
-	RTS;
-
-.data
-.align 4;
-page_size_table:
-.byte4	0x00000400;	/* 1K */
-.byte4	0x00001000;	/* 4K */
-.byte4	0x00100000;	/* 1M */
-.byte4	0x00400000;	/* 4M */
-
-.align 4;
-dcplb_preference:
-.byte4	0x00000001;	/* valid bit */
-.byte4	0x00000082;	/* dirty+lock bits */
-.byte4	0x00000002;	/* lock bit */
diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c
index 78e2b96..ac8ec51 100644
--- a/cpu/bf533/cpu.c
+++ b/cpu/bf533/cpu.c
@@ -29,72 +29,19 @@
 #include <asm/blackfin.h>
 #include <command.h>
 #include <asm/entry.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
 
-#define SSYNC() asm("ssync;")
 #define CACHE_ON 1
 #define CACHE_OFF 0
 
-/* Data Attibutes*/
-
-#define SDRAM_IGENERIC		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
-#define SDRAM_IKERNEL		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define L1_IMEMORY            	(PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL		(PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
-
-#define ANOMALY_05000158		0x200
-#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
-#define L1_DMEMORY              (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-
-static unsigned int icplb_table[16][2]={
-			{0xFFA00000, L1_IMEMORY},
-			{0x00000000, SDRAM_IKERNEL},	/*SDRAM_Page1*/
-			{0x00400000, SDRAM_IKERNEL},	/*SDRAM_Page1*/
-			{0x07C00000, SDRAM_IKERNEL},    /*SDRAM_Page14*/
-			{0x00800000, SDRAM_IGENERIC},	/*SDRAM_Page2*/
-			{0x00C00000, SDRAM_IGENERIC},	/*SDRAM_Page2*/
-			{0x01000000, SDRAM_IGENERIC},	/*SDRAM_Page4*/
-			{0x01400000, SDRAM_IGENERIC},	/*SDRAM_Page5*/
-			{0x01800000, SDRAM_IGENERIC},	/*SDRAM_Page6*/
-			{0x01C00000, SDRAM_IGENERIC},	/*SDRAM_Page7*/
-			{0x02000000, SDRAM_IGENERIC},	/*SDRAM_Page8*/
-			{0x02400000, SDRAM_IGENERIC},	/*SDRAM_Page9*/
-			{0x02800000, SDRAM_IGENERIC},	/*SDRAM_Page10*/
-			{0x02C00000, SDRAM_IGENERIC},	/*SDRAM_Page11*/
-			{0x03000000, SDRAM_IGENERIC},	/*SDRAM_Page12*/
-			{0x03400000, SDRAM_IGENERIC},	/*SDRAM_Page13*/
-};
-
-static unsigned int dcplb_table[16][2]={
-			{0xFFA00000,L1_DMEMORY},
-			{0x00000000,SDRAM_DKERNEL},	/*SDRAM_Page1*/
-			{0x00400000,SDRAM_DKERNEL},	/*SDRAM_Page1*/
-			{0x07C00000,SDRAM_DKERNEL},	/*SDRAM_Page15*/
-			{0x00800000,SDRAM_DGENERIC},	/*SDRAM_Page2*/
-			{0x00C00000,SDRAM_DGENERIC},	/*SDRAM_Page3*/
-			{0x01000000,SDRAM_DGENERIC},	/*SDRAM_Page4*/
-			{0x01400000,SDRAM_DGENERIC},	/*SDRAM_Page5*/
-			{0x01800000,SDRAM_DGENERIC},	/*SDRAM_Page6*/
-			{0x01C00000,SDRAM_DGENERIC},	/*SDRAM_Page7*/
-			{0x02000000,SDRAM_DGENERIC},	/*SDRAM_Page8*/
-			{0x02400000,SDRAM_DGENERIC},	/*SDRAM_Page9*/
-			{0x02800000,SDRAM_DGENERIC},	/*SDRAM_Page10*/
-			{0x02C00000,SDRAM_DGENERIC},	/*SDRAM_Page11*/
-			{0x03000000,SDRAM_DGENERIC},	/*SDRAM_Page12*/
-			{0x20000000,SDRAM_EBIU},	/*For Network */
-};
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+extern unsigned int icplb_table[page_descriptor_table_size][2];
+extern unsigned int dcplb_table[page_descriptor_table_size][2];
+
+int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	__asm__ __volatile__
-	("cli r3;"
-	"P0 = %0;"
-	"JUMP (P0);"
-	:
-	: "r" (L1_ISRAM)
-	);
+	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
+	    );
 
 	return 0;
 }
@@ -112,29 +59,62 @@ int cleanup_before_linux(void)
 
 void icache_enable(void)
 {
-	unsigned int *I0,*I1;
-	int i;
+	unsigned int *I0, *I1;
+	int i, j = 0;
 
+	/* Before enable icache, disable it first */
+	icache_disable();
 	I0 = (unsigned int *)ICPLB_ADDR0;
 	I1 = (unsigned int *)ICPLB_DATA0;
 
-	for(i=0;i<16;i++){
-		*I0++ = icplb_table[i][0];
-		*I1++ = icplb_table[i][1];
+	/* make sure the locked ones go in first */
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (CPLB_LOCK & icplb_table[i][1]) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+				 icplb_table[i][0], icplb_table[i][1]);
+			*I0++ = icplb_table[i][0];
+			*I1++ = icplb_table[i][1];
+			j++;
+		}
+	}
+
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (!(CPLB_LOCK & icplb_table[i][1])) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+				 icplb_table[i][0], icplb_table[i][1]);
+			*I0++ = icplb_table[i][0];
+			*I1++ = icplb_table[i][1];
+			j++;
+			if (j == 16) {
+				break;
+			}
+		}
+	}
+
+	/* Fill the rest with invalid entry */
+	if (j <= 15) {
+		for (; j <= 16; j++) {
+			debug("filling %i with 0", j);
+			*I1++ = 0x0;
 		}
+
+	}
+
 	cli();
-	SSYNC();
+	sync();
+	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-	SSYNC();
+	sync();
 	sti();
 }
 
 void icache_disable(void)
 {
 	cli();
-	SSYNC();
+	sync();
+	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-	SSYNC();
+	sync();
 	sti();
 }
 
@@ -143,7 +123,7 @@ int icache_status(void)
 	unsigned int value;
 	value = *(unsigned int *)IMEM_CONTROL;
 
-	if( value & (IMC|ENICPLB) )
+	if (value & (IMC | ENICPLB))
 		return CACHE_ON;
 	else
 		return CACHE_OFF;
@@ -151,38 +131,90 @@ int icache_status(void)
 
 void dcache_enable(void)
 {
-	unsigned int *I0,*I1;
+	unsigned int *I0, *I1;
 	unsigned int temp;
-	int i;
+	int i, j = 0;
+
+	/* Before enable dcache, disable it first */
+	dcache_disable();
 	I0 = (unsigned int *)DCPLB_ADDR0;
 	I1 = (unsigned int *)DCPLB_DATA0;
 
-	for(i=0;i<16;i++){
-		*I0++ = dcplb_table[i][0];
-		*I1++ = dcplb_table[i][1];
+	/* make sure the locked ones go in first */
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (CPLB_LOCK & dcplb_table[i][1]) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+				 dcplb_table[i][0], dcplb_table[i][1]);
+			*I0++ = dcplb_table[i][0];
+			*I1++ = dcplb_table[i][1];
+			j++;
+		} else {
+			debug("skip   %02i %02i 0x%08x 0x%08x\n", i, j,
+				 dcplb_table[i][0], dcplb_table[i][1]);
+		}
+	}
+
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (!(CPLB_LOCK & dcplb_table[i][1])) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+				 dcplb_table[i][0], dcplb_table[i][1]);
+			*I0++ = dcplb_table[i][0];
+			*I1++ = dcplb_table[i][1];
+			j++;
+			if (j == 16) {
+				break;
+			}
 		}
+	}
+
+	/* Fill the rest with invalid entry */
+	if (j <= 15) {
+		for (; j <= 16; j++) {
+			debug("filling %i with 0", j);
+			*I1++ = 0x0;
+		}
+	}
+
 	cli();
 	temp = *(unsigned int *)DMEM_CONTROL;
-	SSYNC();
-	*(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp;
-	SSYNC();
+	sync();
+	asm(" .align 8; ");
+	*(unsigned int *)DMEM_CONTROL =
+	    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
+	sync();
 	sti();
 }
 
 void dcache_disable(void)
 {
+	unsigned int *I0, *I1;
+	int i;
+
 	cli();
-	SSYNC();
-	*(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0);
-	SSYNC();
+	sync();
+	asm(" .align 8; ");
+	*(unsigned int *)DMEM_CONTROL &=
+	    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+	sync();
 	sti();
+
+	/* after disable dcache,
+	 * clear it so we don't confuse the next application
+	 */
+	I0 = (unsigned int *)DCPLB_ADDR0;
+	I1 = (unsigned int *)DCPLB_DATA0;
+
+	for (i = 0; i < 16; i++) {
+		*I0++ = 0x0;
+		*I1++ = 0x0;
+	}
 }
 
 int dcache_status(void)
 {
 	unsigned int value;
 	value = *(unsigned int *)DMEM_CONTROL;
-	if( value & (ENDCPLB))
+	if (value & (ENDCPLB))
 		return CACHE_ON;
 	else
 		return CACHE_OFF;
diff --git a/cpu/bf533/cpu.h b/cpu/bf533/cpu.h
index 7ec3387..821363e 100644
--- a/cpu/bf533/cpu.h
+++ b/cpu/bf533/cpu.h
@@ -32,8 +32,8 @@
 #define DEF_INTERRUPT_FLAGS 1
 #define MAX_TIM_LOAD	0xFFFFFFFF
 
-void blackfin_irq_panic(int reason, struct pt_regs * reg);
-extern void dump(struct pt_regs * regs);
+void blackfin_irq_panic(int reason, struct pt_regs *reg);
+extern void dump(struct pt_regs *regs);
 void display_excp(void);
 asmlinkage void evt_nmi(void);
 asmlinkage void evt_exception(void);
@@ -50,16 +50,17 @@ asmlinkage void evt_evt12(void);
 asmlinkage void evt_evt13(void);
 asmlinkage void evt_soft_int1(void);
 asmlinkage void evt_system_call(void);
-void blackfin_irq_panic(int reason, struct pt_regs * regs);
+void blackfin_irq_panic(int reason, struct pt_regs *regs);
 void blackfin_free_irq(unsigned int irq, void *dev_id);
-void call_isr(int irq, struct pt_regs * fp);
+void call_isr(int irq, struct pt_regs *fp);
 void blackfin_do_irq(int vec, struct pt_regs *fp);
 void blackfin_init_IRQ(void);
 void blackfin_enable_irq(unsigned int irq);
 void blackfin_disable_irq(unsigned int irq);
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
 int blackfin_request_irq(unsigned int irq,
-		     void (*handler)(int, void *, struct pt_regs *),
-		     unsigned long flags,const char *devname,void *dev_id);
+			 void (*handler) (int, void *, struct pt_regs *),
+			 unsigned long flags, const char *devname,
+			 void *dev_id);
 void timer_init(void);
 #endif
diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S
index 9fbdefc..0512f3b 100644
--- a/cpu/bf533/flush.S
+++ b/cpu/bf533/flush.S
@@ -3,13 +3,12 @@
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.
- *
- * Blackfin BF533/2.6 support : LG Soft India
  */
 #define ASSEMBLY
 
 #include <asm/linkage.h>
 #include <asm/cplb.h>
+#include <config.h>
 #include <asm/blackfin.h>
 
 .text
@@ -20,7 +19,7 @@
  * in the instruction cache.
  */
 
-ENTRY(flush_instruction_cache)
+ENTRY(_flush_instruction_cache)
 	[--SP] = ( R7:6, P5:4 );
 	LINK 12;
 	SP += -12;
@@ -33,7 +32,7 @@ ENTRY(flush_instruction_cache)
 inext:	R0 = [P5++];
 	R1 = [P4++];
 	[--SP] =  RETS;
-	CALL icplb_flush;	/* R0 = page, R1 = data*/
+	CALL _icplb_flush;	/* R0 = page, R1 = data*/
 	RETS = [SP++];
 iskip:	R6 += -1;
 	CC = R6;
@@ -52,7 +51,7 @@ iskip:	R6 += -1;
  */
 
 .align 2
-ENTRY(icplb_flush)
+ENTRY(_icplb_flush)
 	[--SP] = ( R7:0, P5:0 );
 	[--SP] = LC0;
 	[--SP] = LT0;
@@ -86,16 +85,17 @@ ENTRY(icplb_flush)
 	 */
 
 	R3 = ((12<<8)|2);		/* Extraction pattern */
-	nop;				/*Anamoly 05000209*/
-	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits*/
-	R3.H = R4.L << 0 ;		/* Save in extraction pattern for later deposit.*/
+	nop;				/* Anamoly 05000209 */
+	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits */
 
+	/* Save in extraction pattern for later deposit. */
+	R3.H = R4.L << 0;
 
 	/* So:
 	 * R0 = Page start
 	 * R1 = Page length (actually, offset into size/prefix tables)
 	 * R3 = sub-bank deposit values
-  	 *
+	 *
 	 * The cache has 2 Ways, and 64 sets, so we iterate through
 	 * the sets, accessing the tag for each Way, for our Bank and
 	 * sub-bank, looking for dirty, valid tags that match our
@@ -180,8 +180,10 @@ iflush_whole_page:
 	SSYNC;
 	IFLUSH [P0++];		/* because CSYNC can't end loops.*/
 	LSETUP (isall, ieall) LC0 = P1;
-isall:IFLUSH [P0++];
-ieall: NOP;
+isall:
+	IFLUSH [P0++];
+ieall:
+	NOP;
 	SSYNC;
 	JUMP ifinished;
 
@@ -191,7 +193,7 @@ ieall: NOP;
  * in the data cache.
  */
 
-ENTRY(flush_data_cache)
+ENTRY(_flush_data_cache)
 	[--SP] = ( R7:6, P5:4 );
 	LINK 12;
 	SP += -12;
@@ -209,7 +211,7 @@ next:	R0 = [P5++];
 	CC = R2;
 	IF !CC JUMP skip;	/* If not, ignore it.*/
 	[--SP] = RETS;
-	CALL dcplb_flush;	/* R0 = page, R1 = data*/
+	CALL _dcplb_flush;	/* R0 = page, R1 = data*/
 	RETS = [SP++];
 skip:	R6 += -1;
 	CC = R6;
@@ -228,7 +230,7 @@ skip:	R6 += -1;
  */
 
 .align 2
-ENTRY(dcplb_flush)
+ENTRY(_dcplb_flush)
 	[--SP] = ( R7:0, P5:0 );
 	[--SP] = LC0;
 	[--SP] = LT0;
@@ -290,14 +292,15 @@ bank_chosen:
 	R3 = ((12<<8)|2);		/* Extraction pattern */
 	nop;				/*Anamoly 05000209*/
 	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits*/
-	R3.H = R4.L << 0 ;		/* Save in extraction pattern for later deposit.*/
+	/* Save in extraction pattern for later deposit.*/
+	R3.H = R4.L << 0;
 
 	/* So:
 	 * R0 = Page start
 	 * R1 = Page length (actually, offset into size/prefix tables)
 	 * R2 = Bank select mask
 	 * R3 = sub-bank deposit values
-  	 *
+	 *
 	 * The cache has 2 Ways, and 64 sets, so we iterate through
 	 * the sets, accessing the tag for each Way, for our Bank and
 	 * sub-bank, looking for dirty, valid tags that match our
@@ -386,7 +389,7 @@ dflush_whole_page:
 	CC = BITTST(R1, 16);	/* Whether 1K or 4K*/
 	IF CC P1 = P2;
 	P1 += -1;		/* Unroll one iteration*/
-    SSYNC;
+	SSYNC;
 	FLUSHINV [P0++];	/* because CSYNC can't end loops.*/
 	LSETUP (eall, eall) LC0 = P1;
 eall:	FLUSHINV [P0++];
diff --git a/cpu/bf533/init_sdram.S b/cpu/bf533/init_sdram.S
new file mode 100644
index 0000000..e1a8e2f
--- /dev/null
+++ b/cpu/bf533/init_sdram.S
@@ -0,0 +1,179 @@
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mem_init.h>
+.global init_sdram;
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+init_sdram:
+	[--SP] = ASTAT;
+	[--SP] = RETS;
+	[--SP] = (R7:0);
+	[--SP] = (P5:0);
+
+#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+	p0.h = hi(SPI_BAUD);
+	p0.l = lo(SPI_BAUD);
+	r0.l = CONFIG_SPI_BAUD;
+	w[p0] = r0.l;
+	SSYNC;
+#endif
+
+	/*
+	 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+	 */
+	p0.h = hi(PLL_LOCKCNT);
+	p0.l = lo(PLL_LOCKCNT);
+	r0 = 0x300(Z);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * Put SDRAM in self-refresh, incase anything is running
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITSET (R0, 24);
+	[P2] = R0;
+	SSYNC;
+
+	/*
+	 *  Set PLL_CTL with the value that we calculate in R0
+	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+	 *   - [7]     = output delay (add 200ps of delay to mem signals)
+	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
+	 *   - [5]     = PDWN      : 1=All Clocks off
+	 *   - [3]     = STOPCK    : 1=Core Clock off
+	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+	 *   all other bits set to zero
+	 */
+
+	r0 = CONFIG_VCO_MULT & 63;	/* Load the VCO multiplier         */
+	r0 = r0 << 9;			/* Shift it over,                  */
+	r1 = CONFIG_CLKIN_HALF;		/* Do we need to divide CLKIN by 2?*/
+	r0 = r1 | r0;
+	r1 = CONFIG_PLL_BYPASS;		/* Bypass the PLL?                 */
+	r1 = r1 << 8;			/* Shift it over                   */
+	r0 = r1 | r0;			/* add them all together           */
+
+	p0.h = hi(PLL_CTL);
+	p0.l = lo(PLL_CTL);		/* Load the address                */
+	cli r2;				/* Disable interrupts              */
+	ssync;
+	w[p0] = r0.l;			/* Set the value                   */
+	idle;				/* Wait for the PLL to stablize    */
+	sti r2;				/* Enable interrupts               */
+
+check_again:
+	p0.h = hi(PLL_STAT);
+	p0.l = lo(PLL_STAT);
+	R0 = W[P0](Z);
+	CC = BITTST(R0,5);
+	if ! CC jump check_again;
+
+	/* Configure SCLK & CCLK Dividers */
+	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+	p0.h = hi(PLL_DIV);
+	p0.l = lo(PLL_DIV);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * We now are running at speed, time to set the Async mem bank wait states
+	 * This will speed up execution, since we are normally running from FLASH.
+	 */
+
+	p2.h = (EBIU_AMBCTL1 >> 16);
+	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+	r0.h = (AMBCTL1VAL >> 16);
+	r0.l = (AMBCTL1VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMBCTL0 >> 16);
+	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+	r0.h = (AMBCTL0VAL >> 16);
+	r0.l = (AMBCTL0VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMGCTL >> 16);
+	p2.l = (EBIU_AMGCTL & 0xffff);
+	r0 = AMGCTLVAL;
+	w[p2] = r0;
+	ssync;
+
+	/*
+	 * Now, Initialize the SDRAM,
+	 * start with the SDRAM Refresh Rate Control Register
+	 */
+	p0.l = lo(EBIU_SDRRC);
+	p0.h = hi(EBIU_SDRRC);
+	r0 = mem_SDRRC;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Memory Bank Control Register - bank specific parameters
+	 */
+	p0.l = (EBIU_SDBCTL & 0xFFFF);
+	p0.h = (EBIU_SDBCTL >> 16);
+	r0 = mem_SDBCTL;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Global Control Register - global programmable parameters
+	 * Disable self-refresh
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITCLR (R0, 24);
+
+	/*
+	 * Check if SDRAM is already powered up, if it is, enable self-refresh
+	 */
+	p0.h = hi(EBIU_SDSTAT);
+	p0.l = lo(EBIU_SDSTAT);
+	r2.l = w[p0];
+	cc = bittst(r2,3);
+	if !cc jump skip;
+	NOP;
+	BITSET (R0, 23);
+skip:
+	[P2] = R0;
+	SSYNC;
+
+	/* Write in the new value in the register */
+	R0.L = lo(mem_SDGCTL);
+	R0.H = hi(mem_SDGCTL);
+	[P2] = R0;
+	SSYNC;
+	nop;
+
+	(P5:0) = [SP++];
+	(R7:0) = [SP++];
+	RETS   = [SP++];
+	ASTAT  = [SP++];
+	RTS;
diff --git a/cpu/bf533/init_sdram_bootrom_initblock.S b/cpu/bf533/init_sdram_bootrom_initblock.S
new file mode 100644
index 0000000..99ed920
--- /dev/null
+++ b/cpu/bf533/init_sdram_bootrom_initblock.S
@@ -0,0 +1,179 @@
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mem_init.h>
+.global init_sdram;
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+init_sdram:
+	[--SP] = ASTAT;
+	[--SP] = RETS;
+	[--SP] = (R7:0);
+	[--SP] = (P5:0);
+
+#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+	p0.h = hi(SPI_BAUD);
+	p0.l = lo(SPI_BAUD);
+	r0.l = CONFIG_SPI_BAUD_INITBLOCK;
+	w[p0] = r0.l;
+	SSYNC;
+#endif
+
+	/*
+	 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+	 */
+	p0.h = hi(PLL_LOCKCNT);
+	p0.l = lo(PLL_LOCKCNT);
+	r0 = 0x300(Z);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * Put SDRAM in self-refresh, incase anything is running
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITSET (R0, 24);
+	[P2] = R0;
+	SSYNC;
+
+	/*
+	 *  Set PLL_CTL with the value that we calculate in R0
+	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+	 *   - [7]     = output delay (add 200ps of delay to mem signals)
+	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
+	 *   - [5]     = PDWN      : 1=All Clocks off
+	 *   - [3]     = STOPCK    : 1=Core Clock off
+	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+	 *   all other bits set to zero
+	 */
+
+	r0 = CONFIG_VCO_MULT & 63;	/* Load the VCO multiplier         */
+	r0 = r0 << 9;			/* Shift it over,                  */
+	r1 = CONFIG_CLKIN_HALF;		/* Do we need to divide CLKIN by 2?*/
+	r0 = r1 | r0;
+	r1 = CONFIG_PLL_BYPASS;		/* Bypass the PLL?                 */
+	r1 = r1 << 8;			/* Shift it over                   */
+	r0 = r1 | r0;			/* add them all together           */
+
+	p0.h = hi(PLL_CTL);
+	p0.l = lo(PLL_CTL);		/* Load the address                */
+	cli r2;				/* Disable interrupts              */
+	ssync;
+	w[p0] = r0.l;			/* Set the value                   */
+	idle;				/* Wait for the PLL to stablize    */
+	sti r2;				/* Enable interrupts               */
+
+check_again:
+	p0.h = hi(PLL_STAT);
+	p0.l = lo(PLL_STAT);
+	R0 = W[P0](Z);
+	CC = BITTST(R0,5);
+	if ! CC jump check_again;
+
+	/* Configure SCLK & CCLK Dividers */
+	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+	p0.h = hi(PLL_DIV);
+	p0.l = lo(PLL_DIV);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * We now are running at speed, time to set the Async mem bank wait states
+	 * This will speed up execution, since we are normally running from FLASH.
+	 */
+
+	p2.h = (EBIU_AMBCTL1 >> 16);
+	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+	r0.h = (AMBCTL1VAL >> 16);
+	r0.l = (AMBCTL1VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMBCTL0 >> 16);
+	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+	r0.h = (AMBCTL0VAL >> 16);
+	r0.l = (AMBCTL0VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMGCTL >> 16);
+	p2.l = (EBIU_AMGCTL & 0xffff);
+	r0 = AMGCTLVAL;
+	w[p2] = r0;
+	ssync;
+
+	/*
+	 * Now, Initialize the SDRAM,
+	 * start with the SDRAM Refresh Rate Control Register
+	 */
+	p0.l = lo(EBIU_SDRRC);
+	p0.h = hi(EBIU_SDRRC);
+	r0 = mem_SDRRC;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Memory Bank Control Register - bank specific parameters
+	 */
+	p0.l = (EBIU_SDBCTL & 0xFFFF);
+	p0.h = (EBIU_SDBCTL >> 16);
+	r0 = mem_SDBCTL;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Global Control Register - global programmable parameters
+	 * Disable self-refresh
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITCLR (R0, 24);
+
+	/*
+	 * Check if SDRAM is already powered up, if it is, enable self-refresh
+	 */
+	p0.h = hi(EBIU_SDSTAT);
+	p0.l = lo(EBIU_SDSTAT);
+	r2.l = w[p0];
+	cc = bittst(r2,3);
+	if !cc jump skip;
+	NOP;
+	BITSET (R0, 23);
+skip:
+	[P2] = R0;
+	SSYNC;
+
+	/* Write in the new value in the register */
+	R0.L = lo(mem_SDGCTL);
+	R0.H = hi(mem_SDGCTL);
+	[P2] = R0;
+	SSYNC;
+	nop;
+
+	(P5:0) = [SP++];
+	(R7:0) = [SP++];
+	RETS   = [SP++];
+	ASTAT  = [SP++];
+	RTS;
diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S
index e780dc6..524da8f 100644
--- a/cpu/bf533/interrupt.S
+++ b/cpu/bf533/interrupt.S
@@ -40,203 +40,58 @@
  */
 
 #define ASSEMBLY
-
+#include <config.h>
+#include <asm/blackfin.h>
 #include <asm/hw_irq.h>
 #include <asm/entry.h>
 #include <asm/blackfin_defs.h>
-#include <asm/cpu/bf533_irq.h>
 
-.global blackfin_irq_panic;
+.global _blackfin_irq_panic;
 
 .text
 .align 2
 
 #ifndef CONFIG_KGDB
-.global evt_emulation
-evt_emulation:
+.global _evt_emulation
+_evt_emulation:
 	SAVE_CONTEXT
 	r0 = IRQ_EMU;
 	r1 = seqstat;
 	sp += -12;
-	call blackfin_irq_panic;
+	call _blackfin_irq_panic;
 	sp += 12;
 	rte;
 #endif
 
-.global evt_nmi
-evt_nmi:
+.global _evt_nmi
+_evt_nmi:
 	SAVE_CONTEXT
 	r0 = IRQ_NMI;
 	r1 = RETN;
 	sp += -12;
-	call blackfin_irq_panic;
+	call _blackfin_irq_panic;
 	sp += 12;
 
 _evt_nmi_exit:
 	rtn;
 
-.global trap
-trap:
-	[--sp] = r0;
-	[--sp] = r1;
-	[--sp] = p0;
-	[--sp] = p1;
-	[--sp] = astat;
-	r0 = seqstat;
-	R0 <<= 26;
-	R0 >>= 26;
-	p0 = r0;
-	p1.l = EVTABLE;
-	p1.h = EVTABLE;
-	p0 = p1 + (p0 << 1);
-	r1 = W[p0] (Z);
-	p1 = r1;
-	jump (pc + p1);
-
-.global _EVENT1
-_EVENT1:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT2
-_EVENT2:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT3
-_EVENT3:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT4
-_EVENT4:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT5
-_EVENT5:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT6
-_EVENT6:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT7
-_EVENT7:
-	RAISE 15;
-	JUMP.S _EXIT;
-
-.global _EVENT8
-_EVENT8:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT9
-_EVENT9:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT10
-_EVENT10:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT11
-_EVENT11:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT12
-_EVENT12:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT13
-_EVENT13:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT14
-_EVENT14:
-/*	RAISE 14;	*/
-	CALL	_cplb_hdr;
-	JUMP.S _EXIT;
-
-.global _EVENT19
-_EVENT19:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT20
-_EVENT20:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EVENT21
-_EVENT21:
-	RAISE 14;
-	JUMP.S _EXIT;
-
-.global _EXIT
-_EXIT:
-	ASTAT = [sp++];
-	p1 = [sp++];
-	p0 = [sp++];
-	r1 = [sp++];
-	r0 = [sp++];
-	RTX;
-
-EVTABLE:
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x0000;
-	.byte2 0x003E;
-	.byte2 0x0042;
-	.byte4 0x0000;
-	.byte4 0x0000;
-	.byte4 0x0000;
-	.byte4 0x0000;
-	.byte4 0x0000;
-	.byte4 0x0000;
-	.byte4 0x0000;
-	.byte2 0x0000;
-	.byte2 0x001E;
-	.byte2 0x0022;
-	.byte2 0x0032;
-	.byte2 0x002e;
-	.byte2 0x0002;
-	.byte2 0x0036;
-	.byte2 0x002A;
-	.byte2 0x001A;
-	.byte2 0x0016;
-	.byte2 0x000A;
-	.byte2 0x000E;
-	.byte2 0x0012;
-	.byte2 0x0006;
-	.byte2 0x0026;
+.global _trap
+_trap:
+	SAVE_ALL_SYS
+	r0 = sp;        /* stack frame pt_regs pointer argument ==> r0 */
+	sp += -12;
+	call _trap_c
+	sp += 12;
+	RESTORE_ALL_SYS
+	rtx;
 
-.global evt_rst
-evt_rst:
+.global _evt_rst
+_evt_rst:
 	SAVE_CONTEXT
 	r0 = IRQ_RST;
 	r1 = RETN;
 	sp += -12;
-	call do_reset;
+	call _do_reset;
 	sp += 12;
 
 _evt_rst_exit:
@@ -246,19 +101,19 @@ irq_panic:
 	r0 = IRQ_EVX;
 	r1 =  sp;
 	sp += -12;
-	call blackfin_irq_panic;
+	call _blackfin_irq_panic;
 	sp += 12;
 
-.global evt_ivhw
-evt_ivhw:
+.global _evt_ivhw
+_evt_ivhw:
 	SAVE_CONTEXT
 	RAISE 14;
 
 _evt_ivhw_exit:
 	 rti;
 
-.global evt_timer
-evt_timer:
+.global _evt_timer
+_evt_timer:
 	SAVE_CONTEXT
 	r0 = IRQ_CORETMR;
 	sp += -12;
@@ -269,91 +124,91 @@ evt_timer:
 	rti;
 	nop;
 
-.global evt_evt7
-evt_evt7:
+.global _evt_evt7
+_evt_evt7:
 	SAVE_CONTEXT
 	r0 = 7;
 	sp += -12;
-	call process_int;
+	call _process_int;
 	sp += 12;
 
 evt_evt7_exit:
 	RESTORE_CONTEXT
 	rti;
 
-.global evt_evt8
-evt_evt8:
+.global _evt_evt8
+_evt_evt8:
 	SAVE_CONTEXT
 	r0 = 8;
 	sp += -12;
-	call process_int;
+	call _process_int;
 	sp += 12;
 
 evt_evt8_exit:
 	RESTORE_CONTEXT
 	rti;
 
-.global evt_evt9
-evt_evt9:
+.global _evt_evt9
+_evt_evt9:
 	SAVE_CONTEXT
 	r0 = 9;
 	sp += -12;
-	call process_int;
+	call _process_int;
 	sp += 12;
 
 evt_evt9_exit:
 	RESTORE_CONTEXT
 	rti;
 
-.global evt_evt10
-evt_evt10:
+.global _evt_evt10
+_evt_evt10:
 	SAVE_CONTEXT
 	r0 = 10;
 	sp += -12;
-	call process_int;
+	call _process_int;
 	sp += 12;
 
 evt_evt10_exit:
 	RESTORE_CONTEXT
 	rti;
 
-.global evt_evt11
-evt_evt11:
+.global _evt_evt11
+_evt_evt11:
 	SAVE_CONTEXT
 	r0 = 11;
 	sp += -12;
-	call process_int;
+	call _process_int;
 	sp += 12;
 
 evt_evt11_exit:
 	RESTORE_CONTEXT
 	rti;
 
-.global evt_evt12
-evt_evt12:
+.global _evt_evt12
+_evt_evt12:
 	SAVE_CONTEXT
 	r0 = 12;
 	sp += -12;
-	call process_int;
+	call _process_int;
 	sp += 12;
 evt_evt12_exit:
 	 RESTORE_CONTEXT
 	 rti;
 
-.global evt_evt13
-evt_evt13:
+.global _evt_evt13
+_evt_evt13:
 	SAVE_CONTEXT
 	r0 = 13;
 	sp += -12;
-	call process_int;
+	call _process_int;
 	sp += 12;
 
 evt_evt13_exit:
 	 RESTORE_CONTEXT
 	 rti;
 
-.global evt_system_call
-evt_system_call:
+.global _evt_system_call
+_evt_system_call:
 	[--sp] = r0;
 	[--SP] = RETI;
 	r0 = [sp++];
@@ -363,7 +218,7 @@ evt_system_call:
 	r0 = [SP++];
 	SAVE_CONTEXT
 	sp += -12;
-	call display_excp;
+	call _exception_handle;
 	sp += 12;
 	RESTORE_CONTEXT
 	RTI;
@@ -371,8 +226,8 @@ evt_system_call:
 evt_system_call_exit:
 	rti;
 
-.global evt_soft_int1
-evt_soft_int1:
+.global _evt_soft_int1
+_evt_soft_int1:
 	[--sp] = r0;
 	[--SP] = RETI;
 	r0 = [sp++];
@@ -382,7 +237,7 @@ evt_soft_int1:
 	r0 = [SP++];
 	SAVE_CONTEXT
 	sp += -12;
-	call display_excp;
+	call _exception_handle;
 	sp += 12;
 	RESTORE_CONTEXT
 	RTI;
diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c
index df1a25e..9317f26 100644
--- a/cpu/bf533/interrupts.c
+++ b/cpu/bf533/interrupts.c
@@ -10,7 +10,7 @@
  * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
  * Copyright 2003 Metrowerks/Motorola
  * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
- * 			BuyWays B.V. (www.buyways.nl)
+ *			BuyWays B.V. (www.buyways.nl)
  *
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -37,14 +37,15 @@
 #include <common.h>
 #include <asm/machdep.h>
 #include <asm/irq.h>
-#include <asm/cpu/defBF533.h>
+#include <config.h>
+#include <asm/blackfin.h>
 #include "cpu.h"
 
 static ulong timestamp;
 static ulong last_time;
 static int int_flag;
 
-int irq_flags; /* needed by asm-blackfin/system.h */
+int irq_flags;			/* needed by asm-blackfin/system.h */
 
 /* Functions just to satisfy the linker */
 
@@ -61,7 +62,7 @@ unsigned long long get_ticks(void)
  * This function is derived from PowerPC code (timebase clock frequency).
  * On BF533 it returns the number of timer ticks per second.
  */
-ulong get_tbclk (void)
+ulong get_tbclk(void)
 {
 	ulong tbclk;
 
@@ -91,22 +92,22 @@ void udelay(unsigned long usec)
 	unsigned long cclk;
 	cclk = (CONFIG_CCLK_HZ);
 
-	while ( usec > 1 ) {
-	       /*
-		* how many clock ticks to delay?
-		*  - request(in useconds) * clock_ticks(Hz) / useconds/second
-		*/
+	while (usec > 1) {
+		/*
+		 * how many clock ticks to delay?
+		 *  - request(in useconds) * clock_ticks(Hz) / useconds/second
+		 */
 		if (usec < 1000) {
-			delay = (usec * (cclk/244)) >> 12 ;
+			delay = (usec * (cclk / 244)) >> 12;
 			usec = 0;
 		} else {
-			delay = (1000 * (cclk/244)) >> 12 ;
+			delay = (1000 * (cclk / 244)) >> 12;
 			usec -= 1000;
 		}
 
-		asm volatile (" %0 = CYCLES;": "=g"(start));
+		asm volatile (" %0 = CYCLES;":"=r" (start));
 		do {
-			asm volatile (" %0 = CYCLES; ": "=g"(stop));
+			asm volatile (" %0 = CYCLES; ":"=r" (stop));
 		} while (stop - start < delay);
 	}
 
@@ -117,7 +118,7 @@ void timer_init(void)
 {
 	*pTCNTL = 0x1;
 	*pTSCALE = 0x0;
-	*pTCOUNT  = MAX_TIM_LOAD;
+	*pTCOUNT = MAX_TIM_LOAD;
 	*pTPERIOD = MAX_TIM_LOAD;
 	*pTCNTL = 0x7;
 	asm("CSYNC;");
@@ -146,20 +147,23 @@ ulong get_timer(ulong base)
 	/* Number of clocks elapsed */
 	ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
 
-	/* Find if the TCOUNT is reset
-	timestamp gives the number of times
-	TCOUNT got reset */
-	if(clocks < last_time)
+	/**
+	 * Find if the TCOUNT is reset
+	 * timestamp gives the number of times
+	 * TCOUNT got reset
+	 */
+	if (clocks < last_time)
 		timestamp++;
 	last_time = clocks;
 
 	/* Get the number of milliseconds */
-	milisec = clocks/(CONFIG_CCLK_HZ / 1000);
+	milisec = clocks / (CONFIG_CCLK_HZ / 1000);
 
-	/* Find the number of millisonds
-	that got elapsed before this TCOUNT
-	cycle */
-	milisec += timestamp * (MAX_TIM_LOAD/(CONFIG_CCLK_HZ / 1000));
+	/**
+	 * Find the number of millisonds
+	 * that got elapsed before this TCOUNT cycle
+	 */
+	milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
 
 	return (milisec - base);
 }
diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c
index 859f4b2..f476f14 100644
--- a/cpu/bf533/ints.c
+++ b/cpu/bf533/ints.c
@@ -51,9 +51,9 @@
 void blackfin_irq_panic(int reason, struct pt_regs *regs)
 {
 	printf("\n\nException: IRQ 0x%x entered\n", reason);
-	printf("code=[0x%x], ", (unsigned int) (regs->seqstat & 0x3f));
-	printf("stack frame=0x%x, ", (unsigned int) regs);
-	printf("bad PC=0x%04x\n", (unsigned int) regs->pc);
+	printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
+	printf("stack frame=0x%x, ", (unsigned int)regs);
+	printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
 	dump(regs);
 	printf("Unhandled IRQ or exceptions!\n");
 	printf("Please reset the board \n");
@@ -61,46 +61,56 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs)
 
 void blackfin_init_IRQ(void)
 {
-	*(unsigned volatile long *) (SIC_IMASK) = SIC_UNMASK_ALL;
+	*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
 	cli();
 #ifndef CONFIG_KGDB
-	*(unsigned volatile long *) (EVT_EMULATION_ADDR) = 0x0;
+	*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
 #endif
-	*(unsigned volatile long *) (EVT_NMI_ADDR) =
-		(unsigned volatile long) evt_nmi;
-	*(unsigned volatile long *) (EVT_EXCEPTION_ADDR) =
-		(unsigned volatile long) trap;
-	*(unsigned volatile long *) (EVT_HARDWARE_ERROR_ADDR) =
-		(unsigned volatile long) evt_ivhw;
-	*(unsigned volatile long *) (EVT_RESET_ADDR) =
-		(unsigned volatile long) evt_rst;
-	*(unsigned volatile long *) (EVT_TIMER_ADDR) =
-		(unsigned volatile long) evt_timer;
-	*(unsigned volatile long *) (EVT_IVG7_ADDR) =
-		(unsigned volatile long) evt_evt7;
-	*(unsigned volatile long *) (EVT_IVG8_ADDR) =
-		(unsigned volatile long) evt_evt8;
-	*(unsigned volatile long *) (EVT_IVG9_ADDR) =
-		(unsigned volatile long) evt_evt9;
-	*(unsigned volatile long *) (EVT_IVG10_ADDR) =
-		(unsigned volatile long) evt_evt10;
-	*(unsigned volatile long *) (EVT_IVG11_ADDR) =
-		(unsigned volatile long) evt_evt11;
-	*(unsigned volatile long *) (EVT_IVG12_ADDR) =
-		(unsigned volatile long) evt_evt12;
-	*(unsigned volatile long *) (EVT_IVG13_ADDR) =
-		(unsigned volatile long) evt_evt13;
-	*(unsigned volatile long *) (EVT_IVG14_ADDR) =
-		(unsigned volatile long) evt_system_call;
-	*(unsigned volatile long *) (EVT_IVG15_ADDR) =
-		(unsigned volatile long) evt_soft_int1;
-	*(volatile unsigned long *) ILAT = 0;
+	*(unsigned volatile long *)(EVT_NMI_ADDR) =
+	    (unsigned volatile long)evt_nmi;
+	*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
+	    (unsigned volatile long)trap;
+	*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
+	    (unsigned volatile long)evt_ivhw;
+	*(unsigned volatile long *)(EVT_RESET_ADDR) =
+	    (unsigned volatile long)evt_rst;
+	*(unsigned volatile long *)(EVT_TIMER_ADDR) =
+	    (unsigned volatile long)evt_timer;
+	*(unsigned volatile long *)(EVT_IVG7_ADDR) =
+	    (unsigned volatile long)evt_evt7;
+	*(unsigned volatile long *)(EVT_IVG8_ADDR) =
+	    (unsigned volatile long)evt_evt8;
+	*(unsigned volatile long *)(EVT_IVG9_ADDR) =
+	    (unsigned volatile long)evt_evt9;
+	*(unsigned volatile long *)(EVT_IVG10_ADDR) =
+	    (unsigned volatile long)evt_evt10;
+	*(unsigned volatile long *)(EVT_IVG11_ADDR) =
+	    (unsigned volatile long)evt_evt11;
+	*(unsigned volatile long *)(EVT_IVG12_ADDR) =
+	    (unsigned volatile long)evt_evt12;
+	*(unsigned volatile long *)(EVT_IVG13_ADDR) =
+	    (unsigned volatile long)evt_evt13;
+	*(unsigned volatile long *)(EVT_IVG14_ADDR) =
+	    (unsigned volatile long)evt_system_call;
+	*(unsigned volatile long *)(EVT_IVG15_ADDR) =
+	    (unsigned volatile long)evt_soft_int1;
+	*(volatile unsigned long *)ILAT = 0;
 	asm("csync;");
 	sti();
-	*(volatile unsigned long *) IMASK = 0xffbf;
+	*(volatile unsigned long *)IMASK = 0xffbf;
 	asm("csync;");
 }
 
+void exception_handle(void)
+{
+#if defined (CONFIG_PANIC_HANG)
+	display_excp();
+#else
+	udelay(100000);		/* allow messages to go out */
+	do_reset(NULL, 0, 0, NULL);
+#endif
+}
+
 void display_excp(void)
 {
 	printf("Exception!\n");
diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c
index 7b43ffd..11a46be 100644
--- a/cpu/bf533/serial.c
+++ b/cpu/bf533/serial.c
@@ -49,6 +49,7 @@
 #include <asm/bitops.h>
 #include <asm/delay.h>
 #include <asm/uaccess.h>
+#include <asm/io.h>
 #include "bf533_serial.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -58,15 +59,16 @@ unsigned long pll_div_fact;
 void calc_baud(void)
 {
 	unsigned char i;
-	int	temp;
+	int temp;
+	u_long sclk = get_sclk();
 
-	for(i = 0; i < sizeof(baud_table)/sizeof(int); i++) {
-		temp =  CONFIG_SCLK_HZ/(baud_table[i]*8);
-		if ( temp && 0x1 == 1 ) {
+	for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
+		temp = sclk / (baud_table[i] * 8);
+		if ((temp & 0x1) == 1) {
 			temp++;
 		}
-		temp = temp/2;
-		hw_baud_table[i].dl_high = (temp >> 8)& 0xFF;
+		temp = temp / 2;
+		hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
 		hw_baud_table[i].dl_low = (temp) & 0xFF;
 	}
 }
@@ -74,6 +76,7 @@ void calc_baud(void)
 void serial_setbrg(void)
 {
 	int i;
+	DECLARE_GLOBAL_DATA_PTR;
 
 	calc_baud();
 
@@ -84,29 +87,29 @@ void serial_setbrg(void)
 
 	/* Enable UART */
 	*pUART_GCTL |= UART_GCTL_UCEN;
-	asm("ssync;");
+	sync();
 
 	/* Set DLAB in LCR to Access DLL and DLH */
 	ACCESS_LATCH;
-	asm("ssync;");
+	sync();
 
 	*pUART_DLL = hw_baud_table[i].dl_low;
-	asm("ssync;");
+	sync();
 	*pUART_DLH = hw_baud_table[i].dl_high;
-	asm("ssync;");
+	sync();
 
 	/* Clear DLAB in LCR to Access THR RBR IER */
 	ACCESS_PORT_IER;
-	asm("ssync;");
+	sync();
 
 	/* Enable  ERBFI and ELSI interrupts
-	* to poll SIC_ISR register*/
+	 * to poll SIC_ISR register*/
 	*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
-	asm("ssync;");
+	sync();
 
 	/* Set LCR to Word Lengh 8-bit word select */
 	*pUART_LCR = UART_LCR_WLS8;
-	asm("ssync;");
+	sync();
 
 	return;
 }
@@ -119,8 +122,7 @@ int serial_init(void)
 
 void serial_putc(const char c)
 {
-	if ((*pUART_LSR) & UART_LSR_TEMT)
-	{
+	if ((*pUART_LSR) & UART_LSR_TEMT) {
 		if (c == '\n')
 			serial_putc('\r');
 
@@ -148,17 +150,16 @@ int serial_getc(void)
 	int ret;
 
 	/* Poll for RX Interrupt */
-	while (!((isr_val = *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT));
+	while (!((isr_val =
+		  *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
 	asm("csync;");
 
 	uart_lsr_val = *pUART_LSR;	/* Clear status bit */
 	uart_rbr_val = *pUART_RBR;	/* getc() */
 
 	if (isr_val & IRQ_UART_ERROR_BIT) {
-		ret =  -1;
-	}
-	else
-	{
+		ret = -1;
+	} else {
 		ret = uart_rbr_val & 0xff;
 	}
 
@@ -180,10 +181,10 @@ static void local_put_char(char ch)
 	save_and_cli(flags);
 
 	/* Poll for TX Interruput */
-	while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT));
+	while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
 	asm("csync;");
 
-	*pUART_THR = ch;			/* putc() */
+	*pUART_THR = ch;	/* putc() */
 
 	if (isr_val & IRQ_UART_ERROR_BIT) {
 		printf("?");
@@ -191,5 +192,5 @@ static void local_put_char(char ch)
 
 	restore_flags(flags);
 
-	return ;
+	return;
 }
diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S
index 6d58575..94556d6 100644
--- a/cpu/bf533/start.S
+++ b/cpu/bf533/start.S
@@ -1,5 +1,5 @@
 /*
- * U-boot - start.S Startup file of u-boot for BF533
+ * U-boot - start.S Startup file of u-boot for BF533/BF561
  *
  * Copyright (c) 2005 blackfin.uclinux.org
  *
@@ -38,9 +38,23 @@
 #define ASSEMBLY
 
 #include <linux/config.h>
-#include <asm/blackfin.h>
 #include <config.h>
-#include <asm/mem_init.h>
+#include <asm/blackfin.h>
+
+.global _stext;
+.global __bss_start;
+.global start;
+.global _start;
+.global _rambase;
+.global _ramstart;
+.global _ramend;
+.global _bf533_data_dest;
+.global _bf533_data_size;
+.global edata;
+.global _initialize;
+.global _exit;
+.global flashdataend;
+.global init_sdram;
 
 #if (CONFIG_CCLK_DIV == 1)
 #define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
@@ -58,26 +72,12 @@
 #define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
 #endif
 
-.global _stext;
-.global __bss_start;
-.global start;
-.global _start;
-.global _rambase;
-.global _ramstart;
-.global _ramend;
-.global _bf533_data_dest;
-.global _bf533_data_size;
-.global edata;
-.global _initialize;
-.global _exit;
-.global flashdataend;
-
 .text
 _start:
 start:
 _stext:
 
-	R0 = 0x30;
+	R0 = 0x32;
 	SYSCFG = R0;
 	SSYNC;
 
@@ -120,8 +120,9 @@ _stext:
 	/* Set loop counters to zero, to make sure that
 	 * hw loops are disabled.
 	 */
-	lc0 = 0;
-	lc1 = 0;
+	r0  = 0;
+	lc0 = r0;
+	lc1 = r0;
 
 	SSYNC;
 
@@ -150,105 +151,40 @@ no_soft_reset:
 	LSETUP(4,4) lc0 = p1;
 	[ p0 ++ ] = r1;
 
-	/*
-	 *  Set PLL_CTL
-	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
-	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
-	 *   - [7]     = output delay (add 200ps of delay to mem signals)
-	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
-	 *   - [5]     = PDWN      : 1=All Clocks off
-	 *   - [3]     = STOPCK    : 1=Core Clock off
-	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
-	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
-	 *   all other bits set to zero
-	 */
-
-	r0 = CONFIG_VCO_MULT;	/* Load the VCO multiplier */
-	r0 = r0 << 9;		/* Shift it over */
-	r1 =  CONFIG_CLKIN_HALF;	/* Do we need to divide CLKIN by 2? */
-	r0 = r1 | r0;
-	r1 = CONFIG_PLL_BYPASS;	/* Bypass the PLL?                 */
-	r1 = r1 << 8;	/* Shift it over */
-	r0 = r1 | r0;	/* add them all together */
-
-	p0.h = (PLL_CTL >> 16);
-	p0.l = (PLL_CTL & 0xFFFF);	/* Load the address */
-	cli r2;				/* Disable interrupts */
-	w[p0] = r0;			/* Set the value */
-	idle;				/* Wait for the PLL to stablize */
-	sti r2;				/* Enable interrupts */
-	ssync;
-
-	/*
-	 * Turn on the CYCLES COUNTER
-	 */
-	r2 = SYSCFG;
-	BITSET (r2,1);
-	SYSCFG = r2;
-
-	/* Configure SCLK & CCLK Dividers */
-	r0 = CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV;
-	p0.h = (PLL_DIV >> 16);
-	p0.l = (PLL_DIV & 0xFFFF);
-	w[p0] = r0;
-	ssync;
-
-wait_for_pll_stab:
-	p0.h = (PLL_STAT >> 16);
-	p0.l = (PLL_STAT & 0xFFFF);
-	r0.l = w[p0];
-	cc = bittst(r0,5);
-	if !cc jump wait_for_pll_stab;
-
-	/* Configure SDRAM if SDRAM is already not enabled */
-	p0.l = (EBIU_SDSTAT & 0xFFFF);
-	p0.h = (EBIU_SDSTAT >> 16);
-	r0.l = w[p0];
-	cc = bittst(r0, 3);
-	if !cc jump skip_sdram_enable;
-
-	/* SDRAM initialization */
-	p0.l = (EBIU_SDGCTL & 0xFFFF);
-	p0.h = (EBIU_SDGCTL >> 16);	/* SDRAM Memory Global Control Register */
-	r0.h = (mem_SDGCTL >> 16);
-	r0.l = (mem_SDGCTL & 0xFFFF);
-	[p0] = r0;
-	ssync;
-
-	p0.l = (EBIU_SDBCTL & 0xFFFF);
-	p0.h = (EBIU_SDBCTL >> 16);	/* SDRAM Memory Bank Control Register */
-	r0 = mem_SDBCTL;
+	p0.h = hi(SIC_IWR);
+	p0.l = lo(SIC_IWR);
+	r0.l = 0x1;
 	w[p0] = r0.l;
-	ssync;
+	SSYNC;
 
-	p0.l = (EBIU_SDRRC & 0xFFFF);
-	p0.h = (EBIU_SDRRC >> 16);	/* SDRAM Refresh Rate Control Register */
-	r0 = mem_SDRRC;
-	w[p0] = r0.l;
-	ssync;
+	sp.l = (0xffb01000 & 0xFFFF);
+	sp.h = (0xffb01000 >> 16);
 
-skip_sdram_enable:
-	nop;
+	call init_sdram;
 
-#ifndef	CFG_NO_FLASH
 	/* relocate into to RAM */
-	p1.l = (CFG_FLASH_BASE & 0xffff);
-	p1.h = (CFG_FLASH_BASE >> 16);
+	call get_pc;
+offset:
+	r2.l = offset;
+	r2.h = offset;
+	r3.l = start;
+	r3.h = start;
+	r1 = r2 - r3;
+
+	r0 = r0 - r1;
+	p1 = r0;
+
 	p2.l = (CFG_MONITOR_BASE & 0xffff);
 	p2.h = (CFG_MONITOR_BASE >> 16);
-	r0.l = (CFG_MONITOR_LEN & 0xffff);
-	r0.h = (CFG_MONITOR_LEN >> 16);
+
+	p3 = 0x04;
+	p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
+	p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
 loop1:
-	r1 = [p1];
-	[p2] = r1;
-	p3=0x4;
-	p1=p1+p3;
-	p2=p2+p3;
-	r2=0x4;
-	r0=r0-r2;
-	cc=r0==0x0;
+	r1 = [p1 ++ p3];
+	[p2 ++ p3] = r1;
+	cc=p2==p4;
 	if !cc jump loop1;
-#endif
 	/*
 	 * configure STACK
 	 */
@@ -273,7 +209,8 @@ loop1:
 
 	p0.l = (IMASK & 0xFFFF);
 	p0.h = (IMASK >> 16);
-	r0 = IVG15_POS;
+	r0.l = LO(IVG15_POS);
+	r0.h = HI(IVG15_POS);
 	[p0] = r0;
 	raise 15;
 	p0.l = WAIT_HERE;
@@ -288,37 +225,10 @@ WAIT_HERE:
 _real_start:
 	[ -- sp ] = reti;
 
-#ifdef CONFIG_EZKIT533
-	p0.l = (WDOG_CTL & 0xFFFF);
-	p0.h = (WDOG_CTL >> 16);
-	r0 = WATCHDOG_DISABLE(z);
-	w[p0] = r0;
-#endif
-
-	/* Code for initializing Async mem banks */
-	p2.h = (EBIU_AMBCTL1 >> 16);
-	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
-	r0.h = (AMBCTL1VAL >> 16);
-	r0.l = (AMBCTL1VAL & 0xFFFF);
-	[p2] = r0;
-	ssync;
-
-	p2.h = (EBIU_AMBCTL0 >> 16);
-	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
-	r0.h = (AMBCTL0VAL >> 16);
-	r0.l = (AMBCTL0VAL & 0xFFFF);
-	[p2] = r0;
-	ssync;
-
-	p2.h = (EBIU_AMGCTL >> 16);
-	p2.l = (EBIU_AMGCTL & 0xffff);
-	r0 = AMGCTLVAL;
-	w[p2] = r0;
-	ssync;
-
 	/* DMA reset code to Hi of L1 SRAM */
 copy:
-	P1.H = hi(SYSMMR_BASE);	/* P1 Points to the beginning of SYSTEM MMR Space */
+	/* P1 Points to the beginning of SYSTEM MMR Space */
+	P1.H = hi(SYSMMR_BASE);
 	P1.L = lo(SYSMMR_BASE);
 
 	R0.H = reset_start;	/* Source Address (high) */
@@ -329,7 +239,8 @@ copy:
 	R1.H = hi(L1_ISRAM);	/* Destination Address (high) */
 	R1.L = lo(L1_ISRAM);	/* Destination Address (low) */
 	R3.L = DMAEN;		/* Source DMAConfig Value (8-bit words) */
-	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
+	/* Destination DMAConfig Value (8-bit words) */
+	R4.L = (DI_EN | WNR | DMAEN);
 
 DMA:
 	R6 = 0x1 (Z);
@@ -342,57 +253,24 @@ DMA:
 	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
 	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
 
-	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
-	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
-	/* Set Destination DMAConfig = DMA Enable,
-	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
-	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
-
-	IDLE;	/* Wait for DMA to Complete */
-
-	R0 = 0x1;
-	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
-
-	/* DMA reset code to DATA BANK A which uses this port
-	 * to avoid following problem
-	 * " Data from a Data Cache fill can be corrupoted after or during
-	 *   instruction DMA if certain core stalls exist"
-	 */
-
-copy_as_data:
-	R0.H = reset_start;	/* Source Address (high) */
-	R0.L = reset_start;	/* Source Address (low) */
-	R1.H = reset_end;
-	R1.L = reset_end;
-	R2 = R1 - R0;	/* Count */
-	R1.H = hi(DATA_BANKA_SRAM);	/* Destination Address (high) */
-	R1.L = lo(DATA_BANKA_SRAM);	/* Destination Address (low) */
-	R3.L = DMAEN;	/* Source DMAConfig Value (8-bit words) */
-	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
-
-DMA_DATA:
-	R6 = 0x1 (Z);
-	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
-	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
-
- 	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
-	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
-	/* Set Source      DMAConfig = DMA Enable,
-	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
-	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
-
-	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
+	/* Set Destination Base Address */
+	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;
 	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
 	/* Set Destination DMAConfig = DMA Enable,
 	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
 	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
 
-	IDLE;	/* Wait for DMA to Complete */
+WAIT_DMA_DONE:
+	p0.h = hi(MDMA_D0_IRQ_STATUS);
+	p0.l = lo(MDMA_D0_IRQ_STATUS);
+	R0 = W[P0](Z);
+	CC = BITTST(R0, 0);
+	if ! CC jump WAIT_DMA_DONE
 
 	R0 = 0x1;
-	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
 
-copy_end: nop;
+	/* Write 1 to clear DMA interrupt */
+	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;
 
 	/* Initialize BSS Section with 0 s */
 	p1.l = __bss_start;
@@ -433,3 +311,6 @@ reset_end: nop;
 
 _exit:
 	jump.s	_exit;
+get_pc:
+	r0 = rets;
+	rts;
diff --git a/cpu/bf533/start1.S b/cpu/bf533/start1.S
index 6f48124..72cfafb 100644
--- a/cpu/bf533/start1.S
+++ b/cpu/bf533/start1.S
@@ -24,8 +24,8 @@
 
 #define ASSEMBLY
 #include <linux/config.h>
-#include <asm/blackfin.h>
 #include <config.h>
+#include <asm/blackfin.h>
 
 .global	start1;
 .global	_start1;
@@ -34,5 +34,5 @@
 _start1:
 start1:
 	sp += -12;
-	call	board_init_f;
+	call	_board_init_f;
 	sp += 12;
diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c
index 37470d5..248e34f 100644
--- a/cpu/bf533/traps.c
+++ b/cpu/bf533/traps.c
@@ -42,6 +42,9 @@
 #include <asm/page.h>
 #include <asm/machdep.h>
 #include "cpu.h"
+#include <asm/arch/anomaly.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
 
 void init_IRQ(void)
 {
@@ -51,23 +54,187 @@ void init_IRQ(void)
 
 void process_int(unsigned long vec, struct pt_regs *fp)
 {
+	printf("interrupt\n");
 	return;
 }
 
+extern unsigned int icplb_table[page_descriptor_table_size][2];
+extern unsigned int dcplb_table[page_descriptor_table_size][2];
+
+unsigned long last_cplb_fault_retx;
+
+static unsigned int cplb_sizes[4] =
+    { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
+
+void trap_c(struct pt_regs *regs)
+{
+	unsigned int addr;
+	unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
+	unsigned int i, j, size, *I0, *I1;
+	unsigned short data = 0;
+
+	switch (trapnr) {
+	/* 0x26 - Data CPLB Miss */
+	case VEC_CPLB_M:
+
+#ifdef ANOMALY_05000261
+		/*
+		 * Work around an anomaly: if we see a new DCPLB fault,
+		 * return without doing anything. Then,
+		 * if we get the same fault again, handle it.
+		 */
+		addr = last_cplb_fault_retx;
+		last_cplb_fault_retx = regs->retx;
+		printf("this time, curr = 0x%08x last = 0x%08x\n",
+		       addr, last_cplb_fault_retx);
+		if (addr != last_cplb_fault_retx)
+			goto trap_c_return;
+#endif
+		data = 1;
+
+	case VEC_CPLB_I_M:
+
+		if (data) {
+			addr = *(unsigned int *)pDCPLB_FAULT_ADDR;
+		} else {
+			addr = *(unsigned int *)pICPLB_FAULT_ADDR;
+		}
+		for (i = 0; i < page_descriptor_table_size; i++) {
+			if (data) {
+				size = cplb_sizes[dcplb_table[i][1] >> 16];
+				j = dcplb_table[i][0];
+			} else {
+				size = cplb_sizes[icplb_table[i][1] >> 16];
+				j = icplb_table[i][0];
+			}
+			if ((j <= addr) && ((j + size) > addr)) {
+				debug("found %i 0x%08x\n", i, j);
+				break;
+			}
+		}
+		if (i == page_descriptor_table_size) {
+			printf("something is really wrong\n");
+			do_reset(NULL, 0, 0, NULL);
+		}
+
+		/* Turn the cache off */
+		if (data) {
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)DMEM_CONTROL &=
+			    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+			sync();
+		} else {
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+			sync();
+		}
+
+		if (data) {
+			I0 = (unsigned int *)DCPLB_ADDR0;
+			I1 = (unsigned int *)DCPLB_DATA0;
+		} else {
+			I0 = (unsigned int *)ICPLB_ADDR0;
+			I1 = (unsigned int *)ICPLB_DATA0;
+		}
+
+		j = 0;
+		while (*I1 & CPLB_LOCK) {
+			debug("skipping %i %08p - %08x\n", j, I1, *I1);
+			*I0++;
+			*I1++;
+			j++;
+		}
+
+		debug("remove %i 0x%08x  0x%08x\n", j, *I0, *I1);
+
+		for (; j < 15; j++) {
+			debug("replace %i 0x%08x  0x%08x\n", j, I0, I0 + 1);
+			*I0++ = *(I0 + 1);
+			*I1++ = *(I1 + 1);
+		}
+
+		if (data) {
+			*I0 = dcplb_table[i][0];
+			*I1 = dcplb_table[i][1];
+			I0 = (unsigned int *)DCPLB_ADDR0;
+			I1 = (unsigned int *)DCPLB_DATA0;
+		} else {
+			*I0 = icplb_table[i][0];
+			*I1 = icplb_table[i][1];
+			I0 = (unsigned int *)ICPLB_ADDR0;
+			I1 = (unsigned int *)ICPLB_DATA0;
+		}
+
+		for (j = 0; j < 16; j++) {
+			debug("%i 0x%08x  0x%08x\n", j, *I0++, *I1++);
+		}
+
+		/* Turn the cache back on */
+		if (data) {
+			j = *(unsigned int *)DMEM_CONTROL;
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)DMEM_CONTROL =
+			    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
+			sync();
+		} else {
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+			sync();
+		}
+
+		break;
+	default:
+		/* All traps come here */
+		printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
+		printf("stack frame=0x%x, ", (unsigned int)regs);
+		printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
+		dump(regs);
+		printf("\n\n");
+
+		printf("Unhandled IRQ or exceptions!\n");
+		printf("Please reset the board \n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	return;
+
+}
+
 void dump(struct pt_regs *fp)
 {
-	printf("PC: %08lx\n", fp->pc);
-	printf("SEQSTAT: %08lx    SP: %08lx\n", (long) fp->seqstat,
-		(long) fp);
-	printf("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
-		fp->r0, fp->r1, fp->r2, fp->r3);
-	printf("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
-		fp->r4, fp->r5, fp->r6, fp->r7);
-	printf("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
-		fp->p0, fp->p1, fp->p2, fp->p3);
-	printf("P4: %08lx    P5: %08lx    FP: %08lx\n", fp->p4, fp->p5,
-		fp->fp);
-	printf("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
-		fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-	printf("\n");
+	debug("RETE:  %08lx  RETN: %08lx  RETX: %08lx  RETS: %08lx\n",
+		 fp->rete, fp->retn, fp->retx, fp->rets);
+	debug("IPEND: %04lx  SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
+	debug("SEQSTAT: %08lx    SP: %08lx\n", (long)fp->seqstat, (long)fp);
+	debug("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
+		 fp->r0, fp->r1, fp->r2, fp->r3);
+	debug("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
+		 fp->r4, fp->r5, fp->r6, fp->r7);
+	debug("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
+		 fp->p0, fp->p1, fp->p2, fp->p3);
+	debug("P4: %08lx    P5: %08lx    FP: %08lx\n",
+		 fp->p4, fp->p5, fp->fp);
+	debug("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
+		 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+
+	debug("LB0: %08lx  LT0: %08lx  LC0: %08lx\n",
+		 fp->lb0, fp->lt0, fp->lc0);
+	debug("LB1: %08lx  LT1: %08lx  LC1: %08lx\n",
+		 fp->lb1, fp->lt1, fp->lc1);
+	debug("B0: %08lx  L0: %08lx  M0: %08lx  I0: %08lx\n",
+		 fp->b0, fp->l0, fp->m0, fp->i0);
+	debug("B1: %08lx  L1: %08lx  M1: %08lx  I1: %08lx\n",
+		 fp->b1, fp->l1, fp->m1, fp->i1);
+	debug("B2: %08lx  L2: %08lx  M2: %08lx  I2: %08lx\n",
+		 fp->b2, fp->l2, fp->m2, fp->i2);
+	debug("B3: %08lx  L3: %08lx  M3: %08lx  I3: %08lx\n",
+		 fp->b3, fp->l3, fp->m3, fp->i3);
+
+	debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
+	debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
+
 }
diff --git a/cpu/bf533/video.c b/cpu/bf533/video.c
new file mode 100644
index 0000000..3ff0151
--- /dev/null
+++ b/cpu/bf533/video.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ * (C) Copyright 2002
+ * Wolfgang Denk, wd@denx.de
+ * (C) Copyright 2006
+ * Aubrey Li, aubrey.li@analog.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <devices.h>
+
+#ifdef CONFIG_VIDEO
+#define NTSC_FRAME_ADDR 0x06000000
+#include "video.h"
+
+/* NTSC OUTPUT SIZE  720 * 240 */
+#define VERTICAL	2
+#define HORIZONTAL	4
+
+int is_vblank_line(const int line)
+{
+	/*
+	 *  This array contains a single bit for each line in
+	 *  an NTSC frame.
+	 */
+	if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
+		return true;
+
+	return false;
+}
+
+int NTSC_framebuffer_init(char *base_address)
+{
+	const int NTSC_frames = 1;
+	const int NTSC_lines = 525;
+	char *dest = base_address;
+	int frame_num, line_num;
+
+	for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
+		for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
+			unsigned int code;
+			int offset = 0;
+			int i;
+
+			if (is_vblank_line(line_num))
+				offset++;
+
+			if (line_num > 266 || line_num < 3)
+				offset += 2;
+
+			/* Output EAV code */
+			code = SystemCodeMap[offset].EAV;
+			write_dest_byte((char)(code >> 24) & 0xff);
+			write_dest_byte((char)(code >> 16) & 0xff);
+			write_dest_byte((char)(code >> 8) & 0xff);
+			write_dest_byte((char)(code) & 0xff);
+
+			/* Output horizontal blanking */
+			for (i = 0; i < 67 * 2; ++i) {
+				write_dest_byte(0x80);
+				write_dest_byte(0x10);
+			}
+
+			/* Output SAV */
+			code = SystemCodeMap[offset].SAV;
+			write_dest_byte((char)(code >> 24) & 0xff);
+			write_dest_byte((char)(code >> 16) & 0xff);
+			write_dest_byte((char)(code >> 8) & 0xff);
+			write_dest_byte((char)(code) & 0xff);
+
+			/* Output empty horizontal data */
+			for (i = 0; i < 360 * 2; ++i) {
+				write_dest_byte(0x80);
+				write_dest_byte(0x10);
+			}
+		}
+	}
+
+	return dest - base_address;
+}
+
+void fill_frame(char *Frame, int Value)
+{
+	int *OddPtr32;
+	int OddLine;
+	int *EvenPtr32;
+	int EvenLine;
+	int i;
+	int *data;
+	int m, n;
+
+	/* fill odd and even frames */
+	for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
+		OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
+		EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
+		for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
+			*OddPtr32 = Value;
+			*EvenPtr32 = Value;
+		}
+	}
+
+	for (m = 0; m < VERTICAL; m++) {
+		data = (int *)u_boot_logo.data;
+		for (OddLine = (22 + m), EvenLine = (285 + m);
+		     OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
+		     OddLine += VERTICAL, EvenLine += VERTICAL) {
+			OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
+			EvenPtr32 =
+			    (int *)((Frame + ((EvenLine) * 1716)) + 276);
+			for (i = 0; i < u_boot_logo.width / 2; i++) {
+				/* enlarge one pixel to m x n */
+				for (n = 0; n < HORIZONTAL; n++) {
+					*OddPtr32++ = *data;
+					*EvenPtr32++ = *data;
+				}
+				data++;
+			}
+		}
+	}
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+static int video_init(void)
+{
+	char *NTSCFrame;
+	NTSCFrame = (char *)NTSC_FRAME_ADDR;
+	NTSC_framebuffer_init(NTSCFrame);
+	fill_frame(NTSCFrame, BLUE);
+
+	*pPPI_CONTROL = 0x0082;
+	*pPPI_FRAME = 0x020D;
+
+	*pDMA0_START_ADDR = NTSCFrame;
+	*pDMA0_X_COUNT = 0x035A;
+	*pDMA0_X_MODIFY = 0x0002;
+	*pDMA0_Y_COUNT = 0x020D;
+	*pDMA0_Y_MODIFY = 0x0002;
+	*pDMA0_CONFIG = 0x1015;
+	*pPPI_CONTROL = 0x0083;
+	return 0;
+}
+
+int drv_video_init(void)
+{
+	int error, devices = 1;
+
+	device_t videodev;
+
+	video_init();		/* Video initialization */
+
+	memset(&videodev, 0, sizeof(videodev));
+
+	strcpy(videodev.name, "video");
+	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
+	videodev.flags = DEV_FLAGS_OUTPUT;	/* Output only */
+	videodev.putc = video_putc;	/* 'putc' function */
+	videodev.puts = video_puts;	/* 'puts' function */
+
+	error = device_register(&videodev);
+
+	return (error == 0) ? devices : error;
+}
+#endif
diff --git a/cpu/bf533/video.h b/cpu/bf533/video.h
new file mode 100644
index 0000000..d237f6a
--- /dev/null
+++ b/cpu/bf533/video.h
@@ -0,0 +1,25 @@
+#include <video_logo.h>
+#define write_dest_byte(val) {*dest++=val;}
+#define BLACK   (0x01800180)	/* black pixel pattern  */
+#define BLUE    (0x296E29F0)	/* blue pixel pattern   */
+#define RED     (0x51F0515A)	/* red pixel pattern    */
+#define MAGENTA (0x6ADE6ACA)	/* magenta pixel pattern */
+#define GREEN   (0x91229136)	/* green pixel pattern  */
+#define CYAN    (0xAA10AAA6)	/* cyan pixel pattern   */
+#define YELLOW  (0xD292D210)	/* yellow pixel pattern */
+#define WHITE   (0xFE80FE80)	/* white pixel pattern  */
+
+#define true 	1
+#define false	0
+
+typedef struct {
+	unsigned int SAV;
+	unsigned int EAV;
+} SystemCodeType;
+
+const SystemCodeType SystemCodeMap[4] = {
+	{0xFF000080, 0xFF00009D},
+	{0xFF0000AB, 0xFF0000B6},
+	{0xFF0000C7, 0xFF0000DA},
+	{0xFF0000EC, 0xFF0000F1}
+};
diff --git a/cpu/bf537/Makefile b/cpu/bf537/Makefile
new file mode 100644
index 0000000..61c7338
--- /dev/null
+++ b/cpu/bf537/Makefile
@@ -0,0 +1,52 @@
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).a
+
+START	= start.o start1.o interrupt.o cache.o flush.o init_sdram.o
+COBJS	= cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o
+
+EXTRA = init_sdram_bootrom_initblock.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/bf537/cache.S b/cpu/bf537/cache.S
new file mode 100644
index 0000000..5bda5bf
--- /dev/null
+++ b/cpu/bf537/cache.S
@@ -0,0 +1,128 @@
+#define ASSEMBLY
+#include <asm/linkage.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.text
+.align 2
+ENTRY(_blackfin_icache_flush_range)
+	R2 = -32;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
+	1:
+	IFLUSH[P0++];
+	CC = P0 < P1(iu);
+	IF CC JUMP 1b(bp);
+	IFLUSH[P0];
+	SSYNC;
+	RTS;
+
+ENTRY(_blackfin_dcache_flush_range)
+	R2 = -32;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
+1:
+	FLUSH[P0++];
+	CC = P0 < P1(iu);
+	IF CC JUMP 1b(bp);
+	FLUSH[P0];
+	SSYNC;
+	RTS;
+
+ENTRY(_icache_invalidate)
+ENTRY(_invalidate_entire_icache)
+	[--SP] = (R7:5);
+
+	P0.L = (IMEM_CONTROL & 0xFFFF);
+	P0.H = (IMEM_CONTROL >> 16);
+	R7 =[P0];
+
+	/*
+	 * Clear the IMC bit , All valid bits in the instruction
+	 * cache are set to the invalid state
+	 */
+	BITCLR(R7, IMC_P);
+	CLI R6;
+	/* SSYNC required before invalidating cache. */
+	SSYNC;
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	/* Configures the instruction cache agian */
+	R6 = (IMC | ENICPLB);
+	R7 = R7 | R6;
+
+	CLI R6;
+	SSYNC;
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	(R7:5) =[SP++];
+	RTS;
+
+/*
+ * Invalidate the Entire Data cache by
+ * clearing DMC[1:0] bits
+ */
+ENTRY(_invalidate_entire_dcache)
+ENTRY(_dcache_invalidate)
+	[--SP] = (R7:6);
+
+	P0.L = (DMEM_CONTROL & 0xFFFF);
+	P0.H = (DMEM_CONTROL >> 16);
+	R7 =[P0];
+
+	/*
+	 * Clear the DMC[1:0] bits, All valid bits in the data
+	 * cache are set to the invalid state
+	 */
+	BITCLR(R7, DMC0_P);
+	BITCLR(R7, DMC1_P);
+	CLI R6;
+	SSYNC;
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+	/* Configures the data cache again */
+
+	R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+	R7 = R7 | R6;
+
+	CLI R6;
+	SSYNC;
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	(R7:6) =[SP++];
+	RTS;
+
+ENTRY(_blackfin_dcache_invalidate_range)
+	R2 = -32;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
+1:
+	FLUSHINV[P0++];
+	CC = P0 < P1(iu);
+	IF CC JUMP 1b(bp);
+
+	/*
+	 * If the data crosses a cache line, then we'll be pointing to
+	 * the last cache line, but won't have flushed/invalidated it yet, so do
+	 * one more.
+	 */
+	FLUSHINV[P0];
+	SSYNC;
+	RTS;
diff --git a/cpu/bf537/config.mk b/cpu/bf537/config.mk
new file mode 100644
index 0000000..4d57d9c
--- /dev/null
+++ b/cpu/bf537/config.mk
@@ -0,0 +1,27 @@
+# U-boot - config.mk
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -mcpu=bf537 -ffixed-P5
diff --git a/cpu/bf537/cpu.c b/cpu/bf537/cpu.c
new file mode 100644
index 0000000..cb8dc3c
--- /dev/null
+++ b/cpu/bf537/cpu.c
@@ -0,0 +1,227 @@
+/*
+ * U-boot - cpu.c CPU specific functions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <command.h>
+#include <asm/entry.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
+
+#define CACHE_ON 1
+#define CACHE_OFF 0
+
+extern unsigned int icplb_table[page_descriptor_table_size][2];
+extern unsigned int dcplb_table[page_descriptor_table_size][2];
+
+int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
+	    );
+
+	return 0;
+}
+
+/* These functions are just used to satisfy the linker */
+int cpu_init(void)
+{
+	return 0;
+}
+
+int cleanup_before_linux(void)
+{
+	return 0;
+}
+
+void icache_enable(void)
+{
+	unsigned int *I0, *I1;
+	int i, j = 0;
+
+	if ((*pCHIPID >> 28) < 2)
+		return;
+
+	/* Before enable icache, disable it first */
+	icache_disable();
+	I0 = (unsigned int *)ICPLB_ADDR0;
+	I1 = (unsigned int *)ICPLB_DATA0;
+
+	/* make sure the locked ones go in first */
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (CPLB_LOCK & icplb_table[i][1]) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+				 icplb_table[i][0], icplb_table[i][1]);
+			*I0++ = icplb_table[i][0];
+			*I1++ = icplb_table[i][1];
+			j++;
+		}
+	}
+
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (!(CPLB_LOCK & icplb_table[i][1])) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+				 icplb_table[i][0], icplb_table[i][1]);
+			*I0++ = icplb_table[i][0];
+			*I1++ = icplb_table[i][1];
+			j++;
+			if (j == 16) {
+				break;
+			}
+		}
+	}
+
+	/* Fill the rest with invalid entry */
+	if (j <= 15) {
+		for (; j < 16; j++) {
+			debug("filling %i with 0", j);
+			*I1++ = 0x0;
+		}
+
+	}
+
+	cli();
+	sync();
+	asm(" .align 8; ");
+	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+	sync();
+	sti();
+}
+
+void icache_disable(void)
+{
+	if ((*pCHIPID >> 28) < 2)
+		return;
+	cli();
+	sync();
+	asm(" .align 8; ");
+	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+	sync();
+	sti();
+}
+
+int icache_status(void)
+{
+	unsigned int value;
+	value = *(unsigned int *)IMEM_CONTROL;
+
+	if (value & (IMC | ENICPLB))
+		return CACHE_ON;
+	else
+		return CACHE_OFF;
+}
+
+void dcache_enable(void)
+{
+	unsigned int *I0, *I1;
+	unsigned int temp;
+	int i, j = 0;
+
+	/* Before enable dcache, disable it first */
+	dcache_disable();
+	I0 = (unsigned int *)DCPLB_ADDR0;
+	I1 = (unsigned int *)DCPLB_DATA0;
+
+	/* make sure the locked ones go in first */
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (CPLB_LOCK & dcplb_table[i][1]) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+				 dcplb_table[i][0], dcplb_table[i][1]);
+			*I0++ = dcplb_table[i][0];
+			*I1++ = dcplb_table[i][1];
+			j++;
+		} else {
+			debug("skip   %02i %02i 0x%08x 0x%08x\n", i, j,
+				 dcplb_table[i][0], dcplb_table[i][1]);
+		}
+	}
+
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (!(CPLB_LOCK & dcplb_table[i][1])) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+				 dcplb_table[i][0], dcplb_table[i][1]);
+			*I0++ = dcplb_table[i][0];
+			*I1++ = dcplb_table[i][1];
+			j++;
+			if (j == 16) {
+				break;
+			}
+		}
+	}
+
+	/* Fill the rest with invalid entry */
+	if (j <= 15) {
+		for (; j < 16; j++) {
+			debug("filling %i with 0", j);
+			*I1++ = 0x0;
+		}
+	}
+
+	cli();
+	temp = *(unsigned int *)DMEM_CONTROL;
+	sync();
+	asm(" .align 8; ");
+	*(unsigned int *)DMEM_CONTROL =
+	    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
+	sync();
+	sti();
+}
+
+void dcache_disable(void)
+{
+	unsigned int *I0, *I1;
+	int i;
+
+	cli();
+	sync();
+	asm(" .align 8; ");
+	*(unsigned int *)DMEM_CONTROL &=
+	    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+	sync();
+	sti();
+
+	/* after disable dcache,
+	 * clear it so we don't confuse the next application
+	 */
+	I0 = (unsigned int *)DCPLB_ADDR0;
+	I1 = (unsigned int *)DCPLB_DATA0;
+
+	for (i = 0; i < 16; i++) {
+		*I0++ = 0x0;
+		*I1++ = 0x0;
+	}
+}
+
+int dcache_status(void)
+{
+	unsigned int value;
+	value = *(unsigned int *)DMEM_CONTROL;
+
+	if (value & (ENDCPLB))
+		return CACHE_ON;
+	else
+		return CACHE_OFF;
+}
diff --git a/cpu/bf537/cpu.h b/cpu/bf537/cpu.h
new file mode 100644
index 0000000..821363e
--- /dev/null
+++ b/cpu/bf537/cpu.h
@@ -0,0 +1,66 @@
+/*
+ *  U-boot - cpu.h
+ *
+ *  Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <command.h>
+
+#define INTERNAL_IRQS (32)
+#define NUM_IRQ_NODES 16
+#define DEF_INTERRUPT_FLAGS 1
+#define MAX_TIM_LOAD	0xFFFFFFFF
+
+void blackfin_irq_panic(int reason, struct pt_regs *reg);
+extern void dump(struct pt_regs *regs);
+void display_excp(void);
+asmlinkage void evt_nmi(void);
+asmlinkage void evt_exception(void);
+asmlinkage void trap(void);
+asmlinkage void evt_ivhw(void);
+asmlinkage void evt_rst(void);
+asmlinkage void evt_timer(void);
+asmlinkage void evt_evt7(void);
+asmlinkage void evt_evt8(void);
+asmlinkage void evt_evt9(void);
+asmlinkage void evt_evt10(void);
+asmlinkage void evt_evt11(void);
+asmlinkage void evt_evt12(void);
+asmlinkage void evt_evt13(void);
+asmlinkage void evt_soft_int1(void);
+asmlinkage void evt_system_call(void);
+void blackfin_irq_panic(int reason, struct pt_regs *regs);
+void blackfin_free_irq(unsigned int irq, void *dev_id);
+void call_isr(int irq, struct pt_regs *fp);
+void blackfin_do_irq(int vec, struct pt_regs *fp);
+void blackfin_init_IRQ(void);
+void blackfin_enable_irq(unsigned int irq);
+void blackfin_disable_irq(unsigned int irq);
+extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
+int blackfin_request_irq(unsigned int irq,
+			 void (*handler) (int, void *, struct pt_regs *),
+			 unsigned long flags, const char *devname,
+			 void *dev_id);
+void timer_init(void);
+#endif
diff --git a/cpu/bf537/flush.S b/cpu/bf537/flush.S
new file mode 100644
index 0000000..c260a8f
--- /dev/null
+++ b/cpu/bf537/flush.S
@@ -0,0 +1,403 @@
+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2004 LG SOft India. All Rights Reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ */
+#define ASSEMBLY
+
+#include <asm/linkage.h>
+#include <asm/cplb.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.text
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the instruction cache.
+ */
+
+ENTRY(_flush_instruction_cache)
+	[--SP] = ( R7:6, P5:4 );
+	LINK 12;
+	SP += -12;
+	P5.H = (ICPLB_ADDR0 >> 16);
+	P5.L = (ICPLB_ADDR0 & 0xFFFF);
+	P4.H = (ICPLB_DATA0 >> 16);
+	P4.L = (ICPLB_DATA0 & 0xFFFF);
+	R7 = CPLB_VALID | CPLB_L1_CHBL;
+	R6 = 16;
+inext:	R0 = [P5++];
+	R1 = [P4++];
+	[--SP] =  RETS;
+	CALL _icplb_flush;	/* R0 = page, R1 = data*/
+	RETS = [SP++];
+iskip:	R6 += -1;
+	CC = R6;
+	IF CC JUMP inext;
+	SSYNC;
+	SP += 12;
+	UNLINK;
+	( R7:6, P5:4 ) = [SP++];
+	RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular ICPLB.
+ *
+ * R0 -  page's start address
+ * R1 -  CPLB's data field.
+ */
+
+.align 2
+ENTRY(_icplb_flush)
+	[--SP] = ( R7:0, P5:0 );
+	[--SP] = LC0;
+	[--SP] = LT0;
+	[--SP] = LB0;
+	[--SP] = LC1;
+	[--SP] = LT1;
+	[--SP] = LB1;
+
+	/* If it's a 1K or 4K page, then it's quickest to
+	 * just systematically flush all the addresses in
+	 * the page, regardless of whether they're in the
+	 * cache, or dirty. If it's a 1M or 4M page, there
+	 * are too many addresses, and we have to search the
+	 * cache for lines corresponding to the page.
+	 */
+
+	CC = BITTST(R1, 17);	/* 1MB or 4MB */
+	IF !CC JUMP iflush_whole_page;
+
+	/* We're only interested in the page's size, so extract
+	 * this from the CPLB (bits 17:16), and scale to give an
+	 * offset into the page_size and page_prefix tables.
+	 */
+
+	R1 <<= 14;
+	R1 >>= 30;
+	R1 <<= 2;
+
+	/* We can also determine the sub-bank used, because this is
+	 * taken from bits 13:12 of the address.
+	 */
+
+	R3 = ((12<<8)|2);		/* Extraction pattern */
+	nop;				/* Anamoly 05000209 */
+	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits */
+
+	/* Save in extraction pattern for later deposit. */
+	R3.H = R4.L << 0;
+
+	/* So:
+	 * R0 = Page start
+	 * R1 = Page length (actually, offset into size/prefix tables)
+	 * R3 = sub-bank deposit values
+	 *
+	 * The cache has 2 Ways, and 64 sets, so we iterate through
+	 * the sets, accessing the tag for each Way, for our Bank and
+	 * sub-bank, looking for dirty, valid tags that match our
+	 * address prefix.
+	 */
+
+	P5.L = (ITEST_COMMAND & 0xFFFF);
+	P5.H = (ITEST_COMMAND >> 16);
+	P4.L = (ITEST_DATA0 & 0xFFFF);
+	P4.H = (ITEST_DATA0 >> 16);
+
+	P0.L = page_prefix_table;
+	P0.H = page_prefix_table;
+	P1 = R1;
+	R5 = 0;			/* Set counter*/
+	P0 = P1 + P0;
+	R4 = [P0];		/* This is the address prefix*/
+
+	/* We're reading (bit 1==0) the tag (bit 2==0), and we
+	 * don't care about which double-word, since we're only
+	 * fetching tags, so we only have to set Set, Bank,
+	 * Sub-bank and Way.
+	 */
+
+	P2 = 4;
+	LSETUP (ifs1, ife1) LC1 = P2;
+ifs1:	P0 = 32;		/* iterate over all sets*/
+	LSETUP (ifs0, ife0) LC0 = P0;
+ifs0:	R6 = R5 << 5;		/* Combine set*/
+	R6.H = R3.H << 0 ;	/* and sub-bank*/
+	[P5] = R6;		/* Issue Command*/
+	SSYNC;			/* CSYNC will not work here :(*/
+	R7 = [P4];		/* and read Tag.*/
+	CC = BITTST(R7, 0);	/* Check if valid*/
+	IF !CC JUMP ifskip;	/* and skip if not.*/
+
+	/* Compare against the page address. First, plant bits 13:12
+	 * into the tag, since those aren't part of the returned data.
+	 */
+
+	R7 = DEPOSIT(R7, R3);	/* set 13:12*/
+	R1 = R7 & R4;		/* Mask off lower bits*/
+	CC = R1 == R0;		/* Compare against page start.*/
+	IF !CC JUMP ifskip;	/* Skip it if it doesn't match.*/
+
+	/* Tag address matches against page, so this is an entry
+	 * we must flush.
+	 */
+
+	R7 >>= 10;		/* Mask off the non-address bits*/
+	R7 <<= 10;
+	P3 = R7;
+	IFLUSH [P3];		/* And flush the entry*/
+ifskip:
+ife0:	R5 += 1;		/* Advance to next Set*/
+ife1:	NOP;
+
+ifinished:
+	SSYNC;			/* Ensure the data gets out to mem.*/
+
+	/*Finished. Restore context.*/
+	LB1 = [SP++];
+	LT1 = [SP++];
+	LC1 = [SP++];
+	LB0 = [SP++];
+	LT0 = [SP++];
+	LC0 = [SP++];
+	( R7:0, P5:0 ) = [SP++];
+	RTS;
+
+iflush_whole_page:
+	/* It's a 1K or 4K page, so quicker to just flush the
+	 * entire page.
+	 */
+
+	P1 = 32;		/* For 1K pages*/
+	P2 = P1 << 2;		/* For 4K pages*/
+	P0 = R0;		/* Start of page*/
+	CC = BITTST(R1, 16);	/* Whether 1K or 4K*/
+	IF CC P1 = P2;
+	P1 += -1;		/* Unroll one iteration*/
+	SSYNC;
+	IFLUSH [P0++];		/* because CSYNC can't end loops.*/
+	LSETUP (isall, ieall) LC0 = P1;
+isall:IFLUSH [P0++];
+ieall: NOP;
+	SSYNC;
+	JUMP ifinished;
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the data cache.
+ */
+
+ENTRY(_flush_data_cache)
+	[--SP] = ( R7:6, P5:4 );
+	LINK 12;
+	SP += -12;
+	P5.H = (DCPLB_ADDR0 >> 16);
+	P5.L = (DCPLB_ADDR0 & 0xFFFF);
+	P4.H = (DCPLB_DATA0 >> 16);
+	P4.L = (DCPLB_DATA0 & 0xFFFF);
+	R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
+	R6 = 16;
+next:	R0 = [P5++];
+	R1 = [P4++];
+	CC = BITTST(R1, 14);	/* Is it write-through?*/
+	IF CC JUMP skip;	/* If so, ignore it.*/
+	R2 = R1 & R7;		/* Is it a dirty, cached page?*/
+	CC = R2;
+	IF !CC JUMP skip;	/* If not, ignore it.*/
+	[--SP] = RETS;
+	CALL _dcplb_flush;	/* R0 = page, R1 = data*/
+	RETS = [SP++];
+skip:	R6 += -1;
+	CC = R6;
+	IF CC JUMP next;
+	SSYNC;
+	SP += 12;
+	UNLINK;
+	( R7:6, P5:4 ) = [SP++];
+	RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular DCPLB.
+ *
+ * R0 -  page's start address
+ * R1 -  CPLB's data field.
+ */
+
+.align 2
+ENTRY(_dcplb_flush)
+	[--SP] = ( R7:0, P5:0 );
+	[--SP] = LC0;
+	[--SP] = LT0;
+	[--SP] = LB0;
+	[--SP] = LC1;
+	[--SP] = LT1;
+	[--SP] = LB1;
+
+	/* If it's a 1K or 4K page, then it's quickest to
+	 * just systematically flush all the addresses in
+	 * the page, regardless of whether they're in the
+	 * cache, or dirty. If it's a 1M or 4M page, there
+	 * are too many addresses, and we have to search the
+	 * cache for lines corresponding to the page.
+	 */
+
+	CC = BITTST(R1, 17);	/* 1MB or 4MB */
+	IF !CC JUMP dflush_whole_page;
+
+	/* We're only interested in the page's size, so extract
+	 * this from the CPLB (bits 17:16), and scale to give an
+	 * offset into the page_size and page_prefix tables.
+	 */
+
+	R1 <<= 14;
+	R1 >>= 30;
+	R1 <<= 2;
+
+	/* The page could be mapped into Bank A or Bank B, depending
+	 * on (a) whether both banks are configured as cache, and
+	 * (b) on whether address bit A[x] is set. x is determined
+	 * by DCBS in DMEM_CONTROL
+	 */
+
+	R2 = 0;			/* Default to Bank A (Bank B would be 1)*/
+
+	P0.L = (DMEM_CONTROL & 0xFFFF);
+	P0.H = (DMEM_CONTROL >> 16);
+
+	R3 = [P0];		/* If Bank B is not enabled as cache*/
+	CC = BITTST(R3, 2);	/* then Bank A is our only option.*/
+	IF CC JUMP bank_chosen;
+
+	R4 = 1<<14;		/* If DCBS==0, use A[14].*/
+	R5 = R4 << 7;		/* If DCBS==1, use A[23];*/
+	CC = BITTST(R3, 4);
+	IF CC R4 = R5;		/* R4 now has either bit 14 or bit 23 set.*/
+	R5 = R0 & R4;		/* Use it to test the Page address*/
+	CC = R5;		/* and if that bit is set, we use Bank B,*/
+	R2 = CC;		/* else we use Bank A.*/
+	R2 <<= 23;		/* The Bank selection's at posn 23.*/
+
+bank_chosen:
+
+	/* We can also determine the sub-bank used, because this is
+	 * taken from bits 13:12 of the address.
+	 */
+
+	R3 = ((12<<8)|2);		/* Extraction pattern */
+	nop;				/*Anamoly 05000209*/
+	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits*/
+	/* Save in extraction pattern for later deposit.*/
+	R3.H = R4.L << 0;
+
+	/* So:
+	 * R0 = Page start
+	 * R1 = Page length (actually, offset into size/prefix tables)
+	 * R2 = Bank select mask
+	 * R3 = sub-bank deposit values
+	 *
+	 * The cache has 2 Ways, and 64 sets, so we iterate through
+	 * the sets, accessing the tag for each Way, for our Bank and
+	 * sub-bank, looking for dirty, valid tags that match our
+	 * address prefix.
+	 */
+
+	P5.L = (DTEST_COMMAND & 0xFFFF);
+	P5.H = (DTEST_COMMAND >> 16);
+	P4.L = (DTEST_DATA0 & 0xFFFF);
+	P4.H = (DTEST_DATA0 >> 16);
+
+	P0.L = page_prefix_table;
+	P0.H = page_prefix_table;
+	P1 = R1;
+	R5 = 0;			/* Set counter*/
+	P0 = P1 + P0;
+	R4 = [P0];		/* This is the address prefix*/
+
+
+	/* We're reading (bit 1==0) the tag (bit 2==0), and we
+	 * don't care about which double-word, since we're only
+	 * fetching tags, so we only have to set Set, Bank,
+	 * Sub-bank and Way.
+	 */
+
+	P2 = 2;
+	LSETUP (fs1, fe1) LC1 = P2;
+fs1:	P0 = 64;		/* iterate over all sets*/
+	LSETUP (fs0, fe0) LC0 = P0;
+fs0:	R6 = R5 << 5;		/* Combine set*/
+	R6.H = R3.H << 0 ;	/* and sub-bank*/
+	R6 = R6 | R2;		/* and Bank. Leave Way==0 at first.*/
+	BITSET(R6,14);
+	[P5] = R6;		/* Issue Command*/
+	SSYNC;
+	R7 = [P4];		/* and read Tag.*/
+	CC = BITTST(R7, 0);	/* Check if valid*/
+	IF !CC JUMP fskip;	/* and skip if not.*/
+	CC = BITTST(R7, 1);	/* Check if dirty*/
+	IF !CC JUMP fskip;	/* and skip if not.*/
+
+	/* Compare against the page address. First, plant bits 13:12
+	 * into the tag, since those aren't part of the returned data.
+	 */
+
+	R7 = DEPOSIT(R7, R3);	/* set 13:12*/
+	R1 = R7 & R4;		/* Mask off lower bits*/
+	CC = R1 == R0;		/* Compare against page start.*/
+	IF !CC JUMP fskip;	/* Skip it if it doesn't match.*/
+
+	/* Tag address matches against page, so this is an entry
+	 * we must flush.
+	 */
+
+	R7 >>= 10;		/* Mask off the non-address bits*/
+	R7 <<= 10;
+	P3 = R7;
+	SSYNC;
+	FLUSHINV [P3];		/* And flush the entry*/
+fskip:
+fe0:	R5 += 1;		/* Advance to next Set*/
+fe1:	BITSET(R2, 26);		/* Go to next Way.*/
+
+dfinished:
+	SSYNC;			/* Ensure the data gets out to mem.*/
+
+	/*Finished. Restore context.*/
+	LB1 = [SP++];
+	LT1 = [SP++];
+	LC1 = [SP++];
+	LB0 = [SP++];
+	LT0 = [SP++];
+	LC0 = [SP++];
+	( R7:0, P5:0 ) = [SP++];
+	RTS;
+
+dflush_whole_page:
+
+	/* It's a 1K or 4K page, so quicker to just flush the
+	 * entire page.
+	 */
+
+	P1 = 32;		/* For 1K pages*/
+	P2 = P1 << 2;		/* For 4K pages*/
+	P0 = R0;		/* Start of page*/
+	CC = BITTST(R1, 16);	/* Whether 1K or 4K*/
+	IF CC P1 = P2;
+	P1 += -1;		/* Unroll one iteration*/
+	SSYNC;
+	FLUSHINV [P0++];	/* because CSYNC can't end loops.*/
+	LSETUP (eall, eall) LC0 = P1;
+eall:	FLUSHINV [P0++];
+	SSYNC;
+	JUMP dfinished;
+
+.align 4;
+page_prefix_table:
+.byte4 	0xFFFFFC00;	/* 1K */
+.byte4	0xFFFFF000;	/* 4K */
+.byte4	0xFFF00000;	/* 1M */
+.byte4	0xFFC00000;	/* 4M */
+.page_prefix_table.end:
diff --git a/cpu/bf537/i2c.c b/cpu/bf537/i2c.c
new file mode 100644
index 0000000..3b0d026
--- /dev/null
+++ b/cpu/bf537/i2c.c
@@ -0,0 +1,460 @@
+/****************************************************************
+ * $ID: i2c.c	24 Oct 2006 12:00:00 +0800 $ 			*
+ *								*
+ * Description:							*
+ *								*
+ * Maintainer:  sonicz  <sonic.zhang@analog.com>		*
+ *								*
+ * CopyRight (c)  2006  Analog Device				*
+ * All rights reserved.						*
+ *								*
+ * This file is free software;					*
+ *	you are free to modify and/or redistribute it		*
+ *	under the terms of the GNU General Public Licence (GPL).*
+ *								*
+ ****************************************************************/
+
+#include <common.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#include <asm/blackfin.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#define bfin_read16(addr) ({ unsigned __v; \
+			__asm__ __volatile__ (\
+			"%0 = w[%1] (z);\n\t"\
+			: "=d"(__v) : "a"(addr)); (unsigned short)__v; })
+
+#define bfin_write16(addr,val) ({\
+			__asm__ __volatile__ (\
+			"w[%0] = %1;\n\t"\
+			: : "a"(addr) , "d"(val) : "memory");})
+
+/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF) */
+#define bfin_read_TWI_CLKDIV()		bfin_read16(TWI_CLKDIV)
+#define bfin_write_TWI_CLKDIV(val)	bfin_write16(TWI_CLKDIV,val)
+#define bfin_read_TWI_CONTROL()		bfin_read16(TWI_CONTROL)
+#define bfin_write_TWI_CONTROL(val)	bfin_write16(TWI_CONTROL,val)
+#define bfin_read_TWI_SLAVE_CTL()	bfin_read16(TWI_SLAVE_CTL)
+#define bfin_write_TWI_SLAVE_CTL(val)	bfin_write16(TWI_SLAVE_CTL,val)
+#define bfin_read_TWI_SLAVE_STAT()	bfin_read16(TWI_SLAVE_STAT)
+#define bfin_write_TWI_SLAVE_STAT(val)	bfin_write16(TWI_SLAVE_STAT,val)
+#define bfin_read_TWI_SLAVE_ADDR()	bfin_read16(TWI_SLAVE_ADDR)
+#define bfin_write_TWI_SLAVE_ADDR(val)	bfin_write16(TWI_SLAVE_ADDR,val)
+#define bfin_read_TWI_MASTER_CTL()	bfin_read16(TWI_MASTER_CTL)
+#define bfin_write_TWI_MASTER_CTL(val)	bfin_write16(TWI_MASTER_CTL,val)
+#define bfin_read_TWI_MASTER_STAT()	bfin_read16(TWI_MASTER_STAT)
+#define bfin_write_TWI_MASTER_STAT(val)	bfin_write16(TWI_MASTER_STAT,val)
+#define bfin_read_TWI_MASTER_ADDR()	bfin_read16(TWI_MASTER_ADDR)
+#define bfin_write_TWI_MASTER_ADDR(val)	bfin_write16(TWI_MASTER_ADDR,val)
+#define bfin_read_TWI_INT_STAT()	bfin_read16(TWI_INT_STAT)
+#define bfin_write_TWI_INT_STAT(val)	bfin_write16(TWI_INT_STAT,val)
+#define bfin_read_TWI_INT_MASK()	bfin_read16(TWI_INT_MASK)
+#define bfin_write_TWI_INT_MASK(val)	bfin_write16(TWI_INT_MASK,val)
+#define bfin_read_TWI_FIFO_CTL()	bfin_read16(TWI_FIFO_CTL)
+#define bfin_write_TWI_FIFO_CTL(val)	bfin_write16(TWI_FIFO_CTL,val)
+#define bfin_read_TWI_FIFO_STAT()	bfin_read16(TWI_FIFO_STAT)
+#define bfin_write_TWI_FIFO_STAT(val)	bfin_write16(TWI_FIFO_STAT,val)
+#define bfin_read_TWI_XMT_DATA8()	bfin_read16(TWI_XMT_DATA8)
+#define bfin_write_TWI_XMT_DATA8(val)	bfin_write16(TWI_XMT_DATA8,val)
+#define bfin_read_TWI_XMT_DATA16()	bfin_read16(TWI_XMT_DATA16)
+#define bfin_write_TWI_XMT_DATA16(val)	bfin_write16(TWI_XMT_DATA16,val)
+#define bfin_read_TWI_RCV_DATA8()	bfin_read16(TWI_RCV_DATA8)
+#define bfin_write_TWI_RCV_DATA8(val)	bfin_write16(TWI_RCV_DATA8,val)
+#define bfin_read_TWI_RCV_DATA16()	bfin_read16(TWI_RCV_DATA16)
+#define bfin_write_TWI_RCV_DATA16(val)	bfin_write16(TWI_RCV_DATA16,val)
+
+#ifdef DEBUG_I2C
+#define PRINTD(fmt,args...)	do {	\
+	DECLARE_GLOBAL_DATA_PTR;	\
+	if (gd->have_console)		\
+		printf(fmt ,##args);	\
+	} while (0)
+#else
+#define PRINTD(fmt,args...)
+#endif
+
+#ifndef CONFIG_TWICLK_KHZ
+#define CONFIG_TWICLK_KHZ	50
+#endif
+
+/* All transfers are described by this data structure */
+struct i2c_msg {
+	u16 addr;		/* slave address */
+	u16 flags;
+#define I2C_M_STOP		0x2
+#define I2C_M_RD		0x1
+	u16 len;		/* msg length */
+	u8 *buf;		/* pointer to msg data */
+};
+
+/**
+ * i2c_reset: - reset the host controller
+ *
+ */
+
+static void i2c_reset(void)
+{
+	/* Disable TWI */
+	bfin_write_TWI_CONTROL(0);
+	sync();
+
+	/* Set TWI internal clock as 10MHz */
+	bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
+
+	/* Set Twi interface clock as specified */
+	if (CONFIG_TWICLK_KHZ > 400)
+		bfin_write_TWI_CLKDIV(((5 * 1024 / 400) << 8) | ((5 * 1024 /
+						400) & 0xFF));
+	else
+		bfin_write_TWI_CLKDIV(((5 * 1024 /
+					CONFIG_TWICLK_KHZ) << 8) | ((5 * 1024 /
+						CONFIG_TWICLK_KHZ)
+						& 0xFF));
+
+	/* Enable TWI */
+	bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
+	sync();
+}
+
+int wait_for_completion(struct i2c_msg *msg, int timeout_count)
+{
+	unsigned short twi_int_stat;
+	unsigned short mast_stat;
+	int i;
+
+	for (i = 0; i < timeout_count; i++) {
+		twi_int_stat = bfin_read_TWI_INT_STAT();
+		mast_stat = bfin_read_TWI_MASTER_STAT();
+
+		if (XMTSERV & twi_int_stat) {
+			/* Transmit next data */
+			if (msg->len > 0) {
+				bfin_write_TWI_XMT_DATA8(*(msg->buf++));
+				msg->len--;
+			} else if (msg->flags & I2C_M_STOP)
+				bfin_write_TWI_MASTER_CTL
+				    (bfin_read_TWI_MASTER_CTL() | STOP);
+			sync();
+			/* Clear status */
+			bfin_write_TWI_INT_STAT(XMTSERV);
+			sync();
+			i = 0;
+		}
+		if (RCVSERV & twi_int_stat) {
+			if (msg->len > 0) {
+				/* Receive next data */
+				*(msg->buf++) = bfin_read_TWI_RCV_DATA8();
+				msg->len--;
+			} else if (msg->flags & I2C_M_STOP) {
+				bfin_write_TWI_MASTER_CTL
+				    (bfin_read_TWI_MASTER_CTL() | STOP);
+				sync();
+			}
+			/* Clear interrupt source */
+			bfin_write_TWI_INT_STAT(RCVSERV);
+			sync();
+			i = 0;
+		}
+		if (MERR & twi_int_stat) {
+			bfin_write_TWI_INT_STAT(MERR);
+			bfin_write_TWI_INT_MASK(0);
+			bfin_write_TWI_MASTER_STAT(0x3e);
+			bfin_write_TWI_MASTER_CTL(0);
+			sync();
+			/*
+			 * if both err and complete int stats are set,
+			 * return proper results.
+			 */
+			if (MCOMP & twi_int_stat) {
+				bfin_write_TWI_INT_STAT(MCOMP);
+				bfin_write_TWI_INT_MASK(0);
+				bfin_write_TWI_MASTER_CTL(0);
+				sync();
+				/*
+				 * If it is a quick transfer,
+				 * only address bug no data, not an err.
+				 */
+				if (msg->len == 0 && mast_stat & BUFRDERR)
+					return 0;
+				/*
+				 * If address not acknowledged return -3,
+				 * else return 0.
+				 */
+				else if (!(mast_stat & ANAK))
+					return 0;
+				else
+					return -3;
+			}
+			return -1;
+		}
+		if (MCOMP & twi_int_stat) {
+			bfin_write_TWI_INT_STAT(MCOMP);
+			sync();
+			bfin_write_TWI_INT_MASK(0);
+			bfin_write_TWI_MASTER_CTL(0);
+			sync();
+			return 0;
+		}
+	}
+	if (msg->flags & I2C_M_RD)
+		return -4;
+	else
+		return -2;
+}
+
+/**
+ * i2c_transfer: - Transfer one byte over the i2c bus
+ *
+ * This function can tranfer a byte over the i2c bus in both directions.
+ * It is used by the public API functions.
+ *
+ * @return:	 0: transfer successful
+ *		-1: transfer fail
+ *		-2: transmit timeout
+ *		-3: ACK missing
+ *		-4: receive timeout
+ *		-5: controller not ready
+ */
+int i2c_transfer(struct i2c_msg *msg)
+{
+	int ret = 0;
+	int timeout_count = 10000;
+	int len = msg->len;
+
+	if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) {
+		ret = -5;
+		goto transfer_error;
+	}
+
+	while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) ;
+
+	/* Set Transmit device address */
+	bfin_write_TWI_MASTER_ADDR(msg->addr);
+
+	/*
+	 * FIFO Initiation.
+	 * Data in FIFO should be discarded before start a new operation.
+	 */
+	bfin_write_TWI_FIFO_CTL(0x3);
+	sync();
+	bfin_write_TWI_FIFO_CTL(0);
+	sync();
+
+	if (!(msg->flags & I2C_M_RD)) {
+		/* Transmit first data */
+		if (msg->len > 0) {
+			PRINTD("1 in i2c_transfer: buf=%d, len=%d\n", *msg->buf,
+			       len);
+			bfin_write_TWI_XMT_DATA8(*(msg->buf++));
+			msg->len--;
+			sync();
+		}
+	}
+
+	/* clear int stat */
+	bfin_write_TWI_INT_STAT(MERR | MCOMP | XMTSERV | RCVSERV);
+
+	/* Interrupt mask . Enable XMT, RCV interrupt */
+	bfin_write_TWI_INT_MASK(MCOMP | MERR |
+			((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV));
+	sync();
+
+	if (len > 0 && len <= 255)
+		bfin_write_TWI_MASTER_CTL((len << 6));
+	else if (msg->len > 255) {
+		bfin_write_TWI_MASTER_CTL((0xff << 6));
+		msg->flags &= I2C_M_STOP;
+	} else
+		bfin_write_TWI_MASTER_CTL(0);
+
+	/* Master enable */
+	bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
+			((msg->flags & I2C_M_RD)
+			 ? MDIR : 0) | ((CONFIG_TWICLK_KHZ >
+					 100) ? FAST : 0));
+	sync();
+
+	ret = wait_for_completion(msg, timeout_count);
+	PRINTD("3 in i2c_transfer: ret=%d\n", ret);
+
+transfer_error:
+	switch (ret) {
+	case 1:
+		PRINTD(("i2c_transfer: error: transfer fail\n"));
+		break;
+	case 2:
+		PRINTD(("i2c_transfer: error: transmit timeout\n"));
+		break;
+	case 3:
+		PRINTD(("i2c_transfer: error: ACK missing\n"));
+		break;
+	case 4:
+		PRINTD(("i2c_transfer: error: receive timeout\n"));
+		break;
+	case 5:
+		PRINTD(("i2c_transfer: error: controller not ready\n"));
+		i2c_reset();
+		break;
+	default:
+		break;
+	}
+	return ret;
+
+}
+
+/* ---------------------------------------------------------------------*/
+/* API Functions							*/
+/* ---------------------------------------------------------------------*/
+
+void i2c_init(int speed, int slaveaddr)
+{
+	i2c_reset();
+}
+
+/**
+ * i2c_probe: - Test if a chip answers for a given i2c address
+ *
+ * @chip:	address of the chip which is searched for
+ * @return: 	0 if a chip was found, -1 otherwhise
+ */
+
+int i2c_probe(uchar chip)
+{
+	struct i2c_msg msg;
+	u8 probebuf;
+
+	i2c_reset();
+
+	probebuf = 0;
+	msg.addr = chip;
+	msg.flags = 0;
+	msg.len = 1;
+	msg.buf = &probebuf;
+	if (i2c_transfer(&msg))
+		return -1;
+
+	msg.addr = chip;
+	msg.flags = I2C_M_RD;
+	msg.len = 1;
+	msg.buf = &probebuf;
+	if (i2c_transfer(&msg))
+		return -1;
+
+	return 0;
+}
+
+/**
+ *   i2c_read: - Read multiple bytes from an i2c device
+ *
+ *   chip:    I2C chip address, range 0..127
+ *   addr:    Memory (register) address within the chip
+ *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
+ *		memories, 0 for register type devices with only one
+ *		register)
+ *   buffer:  Where to read/write the data
+ *   len:     How many bytes to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+
+int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+	struct i2c_msg msg;
+	u8 addr_bytes[3];	/* lowest...highest byte of data address */
+
+	PRINTD("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x\n", chip,
+			addr, alen, len);
+
+	if (alen > 0) {
+		addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
+		addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
+		addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
+		msg.addr = chip;
+		msg.flags = 0;
+		msg.len = alen;
+		msg.buf = addr_bytes;
+		if (i2c_transfer(&msg))
+			return -1;
+	}
+
+	/* start read sequence */
+	PRINTD(("i2c_read: start read sequence\n"));
+	msg.addr = chip;
+	msg.flags = I2C_M_RD;
+	msg.len = len;
+	msg.buf = buffer;
+	if (i2c_transfer(&msg))
+		return -1;
+
+	return 0;
+}
+
+/**
+ *   i2c_write: -  Write multiple bytes to an i2c device
+ *
+ *   chip:    I2C chip address, range 0..127
+ *   addr:    Memory (register) address within the chip
+ *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
+ *		memories, 0 for register type devices with only one
+ *		register)
+ *   buffer:  Where to read/write the data
+ *   len:     How many bytes to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+
+int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+	struct i2c_msg msg;
+	u8 addr_bytes[3];	/* lowest...highest byte of data address */
+
+	PRINTD
+		("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n",
+		 chip, addr, alen, len, buffer[0]);
+
+	/* chip address write */
+	if (alen > 0) {
+		addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
+		addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
+		addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
+		msg.addr = chip;
+		msg.flags = 0;
+		msg.len = alen;
+		msg.buf = addr_bytes;
+		if (i2c_transfer(&msg))
+			return -1;
+	}
+
+	/* start read sequence */
+	PRINTD(("i2c_write: start write sequence\n"));
+	msg.addr = chip;
+	msg.flags = 0;
+	msg.len = len;
+	msg.buf = buffer;
+	if (i2c_transfer(&msg))
+		return -1;
+
+	return 0;
+
+}
+
+uchar i2c_reg_read(uchar chip, uchar reg)
+{
+	uchar buf;
+
+	PRINTD("i2c_reg_read: chip=0x%02x, reg=0x%02x\n", chip, reg);
+	i2c_read(chip, reg, 0, &buf, 1);
+	return (buf);
+}
+
+void i2c_reg_write(uchar chip, uchar reg, uchar val)
+{
+	PRINTD("i2c_reg_write: chip=0x%02x, reg=0x%02x, val=0x%02x\n", chip,
+			reg, val);
+	i2c_write(chip, reg, 0, &val, 1);
+}
+
+#endif				/* CONFIG_HARD_I2C */
diff --git a/cpu/bf537/init_sdram.S b/cpu/bf537/init_sdram.S
new file mode 100644
index 0000000..897a589
--- /dev/null
+++ b/cpu/bf537/init_sdram.S
@@ -0,0 +1,174 @@
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mem_init.h>
+.global init_sdram;
+
+#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+#endif
+
+init_sdram:
+	[--SP] = ASTAT;
+	[--SP] = RETS;
+	[--SP] = (R7:0);
+	[--SP] = (P5:0);
+
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+	p0.h = hi(SIC_IWR);
+	p0.l = lo(SIC_IWR);
+	r0.l = 0x1;
+	w[p0] = r0.l;
+	SSYNC;
+
+	p0.h = hi(SPI_BAUD);
+	p0.l = lo(SPI_BAUD);
+	r0.l = CONFIG_SPI_BAUD;
+	w[p0] = r0.l;
+	SSYNC;
+#endif
+
+#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
+
+#ifdef CONFIG_BF537
+	/* Enable PHY CLK buffer output */
+	p0.h = hi(VR_CTL);
+	p0.l = lo(VR_CTL);
+	r0.l = w[p0];
+	bitset(r0, 14);
+	w[p0] = r0.l;
+	ssync;
+#endif
+	/*
+	 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+	 */
+	p0.h = hi(PLL_LOCKCNT);
+	p0.l = lo(PLL_LOCKCNT);
+	r0 = 0x300(Z);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * Put SDRAM in self-refresh, incase anything is running
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITSET (R0, 24);
+	[P2] = R0;
+	SSYNC;
+
+	/*
+	 *  Set PLL_CTL with the value that we calculate in R0
+	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+	 *   - [7]     = output delay (add 200ps of delay to mem signals)
+	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
+	 *   - [5]     = PDWN      : 1=All Clocks off
+	 *   - [3]     = STOPCK    : 1=Core Clock off
+	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+	 *   - [0]     = DF	: 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+	 *   all other bits set to zero
+	 */
+
+	r0 = CONFIG_VCO_MULT & 63;	/* Load the VCO multiplier */
+	r0 = r0 << 9;			/* Shift it over */
+	r1 = CONFIG_CLKIN_HALF;		/* Do we need to divide CLKIN by 2?*/
+	r0 = r1 | r0;
+	r1 = CONFIG_PLL_BYPASS;		/* Bypass the PLL? */
+	r1 = r1 << 8;			/* Shift it over */
+	r0 = r1 | r0;			/* add them all together */
+
+	p0.h = hi(PLL_CTL);
+	p0.l = lo(PLL_CTL);		/* Load the address */
+	cli r2;				/* Disable interrupts */
+	ssync;
+	w[p0] = r0.l;			/* Set the value */
+	idle;				/* Wait for the PLL to stablize */
+	sti r2;				/* Enable interrupts */
+
+check_again:
+	p0.h = hi(PLL_STAT);
+	p0.l = lo(PLL_STAT);
+	R0 = W[P0](Z);
+	CC = BITTST(R0,5);
+	if ! CC jump check_again;
+
+	/* Configure SCLK & CCLK Dividers */
+	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+	p0.h = hi(PLL_DIV);
+	p0.l = lo(PLL_DIV);
+	w[p0] = r0.l;
+	ssync;
+#endif
+
+	/*
+	 * Now, Initialize the SDRAM,
+	 * start with the SDRAM Refresh Rate Control Register
+	 */
+	p0.l = lo(EBIU_SDRRC);
+	p0.h = hi(EBIU_SDRRC);
+	r0 = mem_SDRRC;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Memory Bank Control Register - bank specific parameters
+	 */
+	p0.l = (EBIU_SDBCTL & 0xFFFF);
+	p0.h = (EBIU_SDBCTL >> 16);
+	r0 = mem_SDBCTL;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Global Control Register - global programmable parameters
+	 * Disable self-refresh
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITCLR (R0, 24);
+
+	/*
+	 * Check if SDRAM is already powered up, if it is, enable self-refresh
+	 */
+	p0.h = hi(EBIU_SDSTAT);
+	p0.l = lo(EBIU_SDSTAT);
+	r2.l = w[p0];
+	cc = bittst(r2,3);
+	if !cc jump skip;
+	NOP;
+	BITSET (R0, 23);
+skip:
+	[P2] = R0;
+	SSYNC;
+
+	/* Write in the new value in the register */
+	R0.L = lo(mem_SDGCTL);
+	R0.H = hi(mem_SDGCTL);
+	[P2] = R0;
+	SSYNC;
+	nop;
+
+	(P5:0) = [SP++];
+	(R7:0) = [SP++];
+	RETS   = [SP++];
+	ASTAT  = [SP++];
+	RTS;
diff --git a/cpu/bf537/init_sdram_bootrom_initblock.S b/cpu/bf537/init_sdram_bootrom_initblock.S
new file mode 100644
index 0000000..f9adbb9
--- /dev/null
+++ b/cpu/bf537/init_sdram_bootrom_initblock.S
@@ -0,0 +1,199 @@
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mem_init.h>
+.global init_sdram;
+
+#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+#endif
+
+init_sdram:
+	[--SP] = ASTAT;
+	[--SP] = RETS;
+	[--SP] = (R7:0);
+	[--SP] = (P5:0);
+
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+	p0.h = hi(SIC_IWR);
+	p0.l = lo(SIC_IWR);
+	r0.l = 0x1;
+	w[p0] = r0.l;
+	SSYNC;
+
+	p0.h = hi(SPI_BAUD);
+	p0.l = lo(SPI_BAUD);
+	r0.l = CONFIG_SPI_BAUD_INITBLOCK;
+	w[p0] = r0.l;
+	SSYNC;
+#endif
+
+#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
+
+#ifdef CONFIG_BF537
+	/* Enable PHY CLK buffer output */
+	p0.h = hi(VR_CTL);
+	p0.l = lo(VR_CTL);
+	r0.l = w[p0];
+	bitset(r0, 14);
+	w[p0] = r0.l;
+	ssync;
+#endif
+	/*
+	 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+	 */
+	p0.h = hi(PLL_LOCKCNT);
+	p0.l = lo(PLL_LOCKCNT);
+	r0 = 0x300(Z);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * Put SDRAM in self-refresh, incase anything is running
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITSET (R0, 24);
+	[P2] = R0;
+	SSYNC;
+
+	/*
+	 *  Set PLL_CTL with the value that we calculate in R0
+	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+	 *   - [7]     = output delay (add 200ps of delay to mem signals)
+	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
+	 *   - [5]     = PDWN      : 1=All Clocks off
+	 *   - [3]     = STOPCK    : 1=Core Clock off
+	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+	 *   - [0]     = DF	: 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+	 *   all other bits set to zero
+	 */
+
+	r0 = CONFIG_VCO_MULT & 63;	/* Load the VCO multiplier */
+	r0 = r0 << 9;			/* Shift it over */
+	r1 = CONFIG_CLKIN_HALF;		/* Do we need to divide CLKIN by 2?*/
+	r0 = r1 | r0;
+	r1 = CONFIG_PLL_BYPASS;		/* Bypass the PLL? */
+	r1 = r1 << 8;			/* Shift it over */
+	r0 = r1 | r0;			/* add them all together */
+
+	p0.h = hi(PLL_CTL);
+	p0.l = lo(PLL_CTL);		/* Load the address */
+	cli r2;				/* Disable interrupts */
+	ssync;
+	w[p0] = r0.l;			/* Set the value */
+	idle;				/* Wait for the PLL to stablize */
+	sti r2;				/* Enable interrupts */
+
+check_again:
+	p0.h = hi(PLL_STAT);
+	p0.l = lo(PLL_STAT);
+	R0 = W[P0](Z);
+	CC = BITTST(R0,5);
+	if ! CC jump check_again;
+
+	/* Configure SCLK & CCLK Dividers */
+	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+	p0.h = hi(PLL_DIV);
+	p0.l = lo(PLL_DIV);
+	w[p0] = r0.l;
+	ssync;
+#endif
+
+	/*
+	 * We now are running at speed, time to set the Async mem bank wait states
+	 * This will speed up execution, since we are normally running from FLASH.
+	 */
+
+	p2.h = (EBIU_AMBCTL1 >> 16);
+	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+	r0.h = (AMBCTL1VAL >> 16);
+	r0.l = (AMBCTL1VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMBCTL0 >> 16);
+	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+	r0.h = (AMBCTL0VAL >> 16);
+	r0.l = (AMBCTL0VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMGCTL >> 16);
+	p2.l = (EBIU_AMGCTL & 0xffff);
+	r0 = AMGCTLVAL;
+	w[p2] = r0;
+	ssync;
+
+	/*
+	 * Now, Initialize the SDRAM,
+	 * start with the SDRAM Refresh Rate Control Register
+	 */
+	p0.l = lo(EBIU_SDRRC);
+	p0.h = hi(EBIU_SDRRC);
+	r0 = mem_SDRRC;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Memory Bank Control Register - bank specific parameters
+	 */
+	p0.l = (EBIU_SDBCTL & 0xFFFF);
+	p0.h = (EBIU_SDBCTL >> 16);
+	r0 = mem_SDBCTL;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Global Control Register - global programmable parameters
+	 * Disable self-refresh
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITCLR (R0, 24);
+
+	/*
+	 * Check if SDRAM is already powered up, if it is, enable self-refresh
+	 */
+	p0.h = hi(EBIU_SDSTAT);
+	p0.l = lo(EBIU_SDSTAT);
+	r2.l = w[p0];
+	cc = bittst(r2,3);
+	if !cc jump skip;
+	NOP;
+	BITSET (R0, 23);
+skip:
+	[P2] = R0;
+	SSYNC;
+
+	/* Write in the new value in the register */
+	R0.L = lo(mem_SDGCTL);
+	R0.H = hi(mem_SDGCTL);
+	[P2] = R0;
+	SSYNC;
+	nop;
+
+	(P5:0) = [SP++];
+	(R7:0) = [SP++];
+	RETS   = [SP++];
+	ASTAT  = [SP++];
+	RTS;
diff --git a/cpu/bf537/interrupt.S b/cpu/bf537/interrupt.S
new file mode 100644
index 0000000..a8be34f
--- /dev/null
+++ b/cpu/bf537/interrupt.S
@@ -0,0 +1,246 @@
+/*
+ * U-boot - interrupt.S Processing of interrupts and exception handling
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file is based on interrupt.S
+ *
+ * Copyright (C) 2003  Metrowerks, Inc. <mwaddel@metrowerks.com>
+ * Copyright (C) 2002  Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
+ * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ *                     Kenneth Albanowski <kjahds@kjahds.com>,
+ *                     The Silver Hammer Group, Ltd.
+ *
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * This file is also based on exception.asm
+ * (C) Copyright 2001-2005 - Analog Devices, Inc.  All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/hw_irq.h>
+#include <asm/entry.h>
+#include <asm/blackfin_defs.h>
+
+.global _blackfin_irq_panic;
+
+.text
+.align 2
+
+#ifndef CONFIG_KGDB
+.global _evt_emulation
+_evt_emulation:
+	SAVE_CONTEXT
+	r0 = IRQ_EMU;
+	r1 = seqstat;
+	sp += -12;
+	call _blackfin_irq_panic;
+	sp += 12;
+	rte;
+#endif
+
+.global _evt_nmi
+_evt_nmi:
+	SAVE_CONTEXT
+	r0 = IRQ_NMI;
+	r1 = RETN;
+	sp += -12;
+	call _blackfin_irq_panic;
+	sp += 12;
+
+_evt_nmi_exit:
+	rtn;
+
+.global _trap
+_trap:
+	SAVE_ALL_SYS
+	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
+	sp += -12;
+	call _trap_c
+	sp += 12;
+	RESTORE_ALL_SYS
+	rtx;
+
+.global _evt_rst
+_evt_rst:
+	SAVE_CONTEXT
+	r0 = IRQ_RST;
+	r1 = RETN;
+	sp += -12;
+	call _do_reset;
+	sp += 12;
+
+_evt_rst_exit:
+	rtn;
+
+irq_panic:
+	r0 = IRQ_EVX;
+	r1 =  sp;
+	sp += -12;
+	call _blackfin_irq_panic;
+	sp += 12;
+
+.global _evt_ivhw
+_evt_ivhw:
+	SAVE_CONTEXT
+	RAISE 14;
+
+_evt_ivhw_exit:
+	 rti;
+
+.global _evt_timer
+_evt_timer:
+	SAVE_CONTEXT
+	r0 = IRQ_CORETMR;
+	sp += -12;
+	/* Polling method used now. */
+	/* call timer_int; */
+	sp += 12;
+	RESTORE_CONTEXT
+	rti;
+	nop;
+
+.global _evt_evt7
+_evt_evt7:
+	SAVE_CONTEXT
+	r0 = 7;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt7_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global _evt_evt8
+_evt_evt8:
+	SAVE_CONTEXT
+	r0 = 8;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt8_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global _evt_evt9
+_evt_evt9:
+	SAVE_CONTEXT
+	r0 = 9;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt9_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global _evt_evt10
+_evt_evt10:
+	SAVE_CONTEXT
+	r0 = 10;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt10_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global _evt_evt11
+_evt_evt11:
+	SAVE_CONTEXT
+	r0 = 11;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt11_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global _evt_evt12
+_evt_evt12:
+	SAVE_CONTEXT
+	r0 = 12;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+evt_evt12_exit:
+	 RESTORE_CONTEXT
+	 rti;
+
+.global _evt_evt13
+_evt_evt13:
+	SAVE_CONTEXT
+	r0 = 13;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt13_exit:
+	 RESTORE_CONTEXT
+	 rti;
+
+.global _evt_system_call
+_evt_system_call:
+	[--sp] = r0;
+	[--SP] = RETI;
+	r0 = [sp++];
+	r0 += 2;
+	[--sp] = r0;
+	RETI = [SP++];
+	r0 = [SP++];
+	SAVE_CONTEXT
+	sp += -12;
+	call _exception_handle;
+	sp += 12;
+	RESTORE_CONTEXT
+	RTI;
+
+evt_system_call_exit:
+	rti;
+
+.global _evt_soft_int1
+_evt_soft_int1:
+	[--sp] = r0;
+	[--SP] = RETI;
+	r0 = [sp++];
+	r0 += 2;
+	[--sp] = r0;
+	RETI = [SP++];
+	r0 = [SP++];
+	SAVE_CONTEXT
+	sp += -12;
+	call _exception_handle;
+	sp += 12;
+	RESTORE_CONTEXT
+	RTI;
+
+evt_soft_int1_exit:
+	rti;
diff --git a/cpu/bf537/interrupts.c b/cpu/bf537/interrupts.c
new file mode 100644
index 0000000..2ca76ec
--- /dev/null
+++ b/cpu/bf537/interrupts.c
@@ -0,0 +1,174 @@
+/*
+ * U-boot - interrupts.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on interrupts.c
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
+ *			BuyWays B.V. (www.buyways.nl)
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+static ulong timestamp;
+static ulong last_time;
+static int int_flag;
+
+int irq_flags;			/* needed by asm-blackfin/system.h */
+
+/* Functions just to satisfy the linker */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On BF533 it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On BF533 it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return tbclk;
+}
+
+void enable_interrupts(void)
+{
+	restore_flags(int_flag);
+}
+
+int disable_interrupts(void)
+{
+	save_and_cli(int_flag);
+	return 1;
+}
+
+int interrupt_init(void)
+{
+	return (0);
+}
+
+void udelay(unsigned long usec)
+{
+	unsigned long delay, start, stop;
+	unsigned long cclk;
+	cclk = (CONFIG_CCLK_HZ);
+
+	while (usec > 1) {
+		/*
+		 * how many clock ticks to delay?
+		 *  - request(in useconds) * clock_ticks(Hz) / useconds/second
+		 */
+		if (usec < 1000) {
+			delay = (usec * (cclk / 244)) >> 12;
+			usec = 0;
+		} else {
+			delay = (1000 * (cclk / 244)) >> 12;
+			usec -= 1000;
+		}
+
+		asm volatile (" %0 = CYCLES;":"=r" (start));
+		do {
+			asm volatile (" %0 = CYCLES; ":"=r" (stop));
+		} while (stop - start < delay);
+	}
+
+	return;
+}
+
+void timer_init(void)
+{
+	*pTCNTL = 0x1;
+	*pTSCALE = 0x0;
+	*pTCOUNT = MAX_TIM_LOAD;
+	*pTPERIOD = MAX_TIM_LOAD;
+	*pTCNTL = 0x7;
+	asm("CSYNC;");
+
+	timestamp = 0;
+	last_time = 0;
+}
+
+/* Any network command or flash
+ * command is started get_timer shall
+ * be called before TCOUNT gets reset,
+ * to implement the accurate timeouts.
+ *
+ * How ever milliconds doesn't return
+ * the number that has been elapsed from
+ * the last reset.
+ *
+ *  As get_timer is used in the u-boot
+ *  only for timeouts this should be
+ *  sufficient
+ */
+ulong get_timer(ulong base)
+{
+	ulong milisec;
+
+	/* Number of clocks elapsed */
+	ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
+
+	/**
+	 * Find if the TCOUNT is reset
+	 * timestamp gives the number of times
+	 * TCOUNT got reset
+	 */
+	if (clocks < last_time)
+		timestamp++;
+	last_time = clocks;
+
+	/* Get the number of milliseconds */
+	milisec = clocks / (CONFIG_CCLK_HZ / 1000);
+
+	/**
+	 * Find the number of millisonds
+	 * that got elapsed before this TCOUNT cycle
+	 */
+	milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
+
+	return (milisec - base);
+}
+
+void reset_timer (void)
+{
+	timestamp = 0;
+}
diff --git a/cpu/bf537/ints.c b/cpu/bf537/ints.c
new file mode 100644
index 0000000..f476f14
--- /dev/null
+++ b/cpu/bf537/ints.c
@@ -0,0 +1,117 @@
+/*
+ * U-boot - ints.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on ints.c
+ *
+ * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
+ *             drivers
+ *
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/stddef.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/traps.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/machdep.h>
+#include <asm/setup.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+void blackfin_irq_panic(int reason, struct pt_regs *regs)
+{
+	printf("\n\nException: IRQ 0x%x entered\n", reason);
+	printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
+	printf("stack frame=0x%x, ", (unsigned int)regs);
+	printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
+	dump(regs);
+	printf("Unhandled IRQ or exceptions!\n");
+	printf("Please reset the board \n");
+}
+
+void blackfin_init_IRQ(void)
+{
+	*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
+	cli();
+#ifndef CONFIG_KGDB
+	*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
+#endif
+	*(unsigned volatile long *)(EVT_NMI_ADDR) =
+	    (unsigned volatile long)evt_nmi;
+	*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
+	    (unsigned volatile long)trap;
+	*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
+	    (unsigned volatile long)evt_ivhw;
+	*(unsigned volatile long *)(EVT_RESET_ADDR) =
+	    (unsigned volatile long)evt_rst;
+	*(unsigned volatile long *)(EVT_TIMER_ADDR) =
+	    (unsigned volatile long)evt_timer;
+	*(unsigned volatile long *)(EVT_IVG7_ADDR) =
+	    (unsigned volatile long)evt_evt7;
+	*(unsigned volatile long *)(EVT_IVG8_ADDR) =
+	    (unsigned volatile long)evt_evt8;
+	*(unsigned volatile long *)(EVT_IVG9_ADDR) =
+	    (unsigned volatile long)evt_evt9;
+	*(unsigned volatile long *)(EVT_IVG10_ADDR) =
+	    (unsigned volatile long)evt_evt10;
+	*(unsigned volatile long *)(EVT_IVG11_ADDR) =
+	    (unsigned volatile long)evt_evt11;
+	*(unsigned volatile long *)(EVT_IVG12_ADDR) =
+	    (unsigned volatile long)evt_evt12;
+	*(unsigned volatile long *)(EVT_IVG13_ADDR) =
+	    (unsigned volatile long)evt_evt13;
+	*(unsigned volatile long *)(EVT_IVG14_ADDR) =
+	    (unsigned volatile long)evt_system_call;
+	*(unsigned volatile long *)(EVT_IVG15_ADDR) =
+	    (unsigned volatile long)evt_soft_int1;
+	*(volatile unsigned long *)ILAT = 0;
+	asm("csync;");
+	sti();
+	*(volatile unsigned long *)IMASK = 0xffbf;
+	asm("csync;");
+}
+
+void exception_handle(void)
+{
+#if defined (CONFIG_PANIC_HANG)
+	display_excp();
+#else
+	udelay(100000);		/* allow messages to go out */
+	do_reset(NULL, 0, 0, NULL);
+#endif
+}
+
+void display_excp(void)
+{
+	printf("Exception!\n");
+}
diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c
new file mode 100644
index 0000000..dd4f916
--- /dev/null
+++ b/cpu/bf537/serial.c
@@ -0,0 +1,194 @@
+/*
+ * U-boot - serial.c Serial driver for BF537
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf537_serial.c: Serial driver for BlackFin BF537 internal UART.
+ * Copyright (c) 2003	Bas Vermeulen <bas@buyways.nl>,
+ * 			BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on blkfinserial.c
+ * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
+ * Copyright(c) 2003	Metrowerks	<mwaddel@metrowerks.com>
+ * Copyright(c)	2001	Tony Z. Kou	<tonyko@arcturusnetworks.com>
+ * Copyright(c)	2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328 version serial driver imlpementation which was:
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/segment.h>
+#include <asm/bitops.h>
+#include <asm/delay.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include "serial.h"
+
+unsigned long pll_div_fact;
+
+void calc_baud(void)
+{
+	unsigned char i;
+	int temp;
+	u_long sclk = get_sclk();
+
+	for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
+		temp = sclk / (baud_table[i] * 8);
+		if ((temp & 0x1) == 1) {
+			temp++;
+		}
+		temp = temp / 2;
+		hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
+		hw_baud_table[i].dl_low = (temp) & 0xFF;
+	}
+}
+
+void serial_setbrg(void)
+{
+	int i;
+	DECLARE_GLOBAL_DATA_PTR;
+
+	calc_baud();
+
+	for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
+		if (gd->baudrate == baud_table[i])
+			break;
+	}
+
+	/* Enable UART */
+	*pUART_GCTL |= UART_GCTL_UCEN;
+	sync();
+
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH;
+	sync();
+
+	*pUART_DLL = hw_baud_table[i].dl_low;
+	sync();
+	*pUART_DLH = hw_baud_table[i].dl_high;
+	sync();
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER;
+	sync();
+
+	/* Enable  ERBFI and ELSI interrupts
+	 * to poll SIC_ISR register*/
+	*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
+	sync();
+
+	/* Set LCR to Word Lengh 8-bit word select */
+	*pUART_LCR = UART_LCR_WLS8;
+	sync();
+
+	return;
+}
+
+int serial_init(void)
+{
+	serial_setbrg();
+	return (0);
+}
+
+void serial_putc(const char c)
+{
+	if ((*pUART_LSR) & UART_LSR_TEMT) {
+		if (c == '\n')
+			serial_putc('\r');
+
+		local_put_char(c);
+	}
+
+	while (!((*pUART_LSR) & UART_LSR_TEMT))
+		SYNC_ALL;
+
+	return;
+}
+
+int serial_tstc(void)
+{
+	if (*pUART_LSR & UART_LSR_DR)
+		return 1;
+	else
+		return 0;
+}
+
+int serial_getc(void)
+{
+	unsigned short uart_lsr_val, uart_rbr_val;
+	unsigned long isr_val;
+	int ret;
+
+	/* Poll for RX Interrupt */
+	while (!((isr_val =
+		  *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
+	asm("csync;");
+
+	uart_lsr_val = *pUART_LSR;	/* Clear status bit */
+	uart_rbr_val = *pUART_RBR;	/* getc() */
+
+	if (isr_val & IRQ_UART_ERROR_BIT) {
+		ret = -1;
+	} else {
+		ret = uart_rbr_val & 0xff;
+	}
+
+	return ret;
+}
+
+void serial_puts(const char *s)
+{
+	while (*s) {
+		serial_putc(*s++);
+	}
+}
+
+static void local_put_char(char ch)
+{
+	int flags = 0;
+	unsigned long isr_val;
+
+	save_and_cli(flags);
+
+	/* Poll for TX Interruput */
+	while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
+	asm("csync;");
+
+	*pUART_THR = ch;	/* putc() */
+
+	if (isr_val & IRQ_UART_ERROR_BIT) {
+		printf("?");
+	}
+
+	restore_flags(flags);
+
+	return;
+}
diff --git a/cpu/bf537/serial.h b/cpu/bf537/serial.h
new file mode 100644
index 0000000..c9ee3dc
--- /dev/null
+++ b/cpu/bf537/serial.h
@@ -0,0 +1,77 @@
+/*
+ * U-boot - bf537_serial.h Serial Driver defines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
+ * Copyright (C) 2003	Bas Vermeulen <bas@buyways.nl>
+ * 			BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
+ *
+ * Copyright (C) 2001	Tony Z. Kou	tonyko@arcturusnetworks.com
+ * Copyright (C) 2001   Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328serial.c which was:
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _Bf537_SERIAL_H
+#define _Bf537_SERIAL_H
+
+#include <linux/config.h>
+#include <asm/blackfin.h>
+
+#define SYNC_ALL	__asm__ __volatile__ ("ssync;\n")
+#define ACCESS_LATCH	*pUART_LCR |= UART_LCR_DLAB;
+#define ACCESS_PORT_IER	*pUART_LCR &= (~UART_LCR_DLAB);
+
+void serial_setbrg(void);
+static void local_put_char(char ch);
+void calc_baud(void);
+void serial_setbrg(void);
+int serial_init(void);
+void serial_putc(const char c);
+int serial_tstc(void);
+int serial_getc(void);
+void serial_puts(const char *s);
+static void local_put_char(char ch);
+
+int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
+
+struct {
+	unsigned char dl_high;
+	unsigned char dl_low;
+} hw_baud_table[5];
+
+#ifdef CONFIG_STAMP
+extern unsigned long pll_div_fact;
+#endif
+
+#endif
diff --git a/cpu/bf537/start.S b/cpu/bf537/start.S
new file mode 100644
index 0000000..264e9b6
--- /dev/null
+++ b/cpu/bf537/start.S
@@ -0,0 +1,579 @@
+/*
+ * U-boot - start.S Startup file of u-boot for BF537
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on head.S
+ * Copyright (c) 2003  Metrowerks/Motorola
+ * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ *                     Kenneth Albanowski <kjahds@kjahds.com>,
+ *                     The Silver Hammer Group, Ltd.
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Note: A change in this file subsequently requires a change in
+ *       board/$(board_name)/config.mk for a valid u-boot.bin
+ */
+
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.global _stext;
+.global __bss_start;
+.global start;
+.global _start;
+.global _rambase;
+.global _ramstart;
+.global _ramend;
+.global _bf533_data_dest;
+.global _bf533_data_size;
+.global edata;
+.global _initialize;
+.global _exit;
+.global flashdataend;
+.global init_sdram;
+.global _icache_enable;
+.global _dcache_enable;
+#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
+.global _memory_post_test;
+.global _post_flag;
+#endif
+
+#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+#endif
+
+.text
+_start:
+start:
+_stext:
+
+	R0 = 0x32;
+	SYSCFG = R0;
+	SSYNC;
+
+	/* As per HW reference manual DAG registers,
+	 * DATA and Address resgister shall be zero'd
+	 * in initialization, after a reset state
+	 */
+	r1 = 0;	/* Data registers zero'd */
+	r2 = 0;
+	r3 = 0;
+	r4 = 0;
+	r5 = 0;
+	r6 = 0;
+	r7 = 0;
+
+	p0 = 0; /* Address registers zero'd */
+	p1 = 0;
+	p2 = 0;
+	p3 = 0;
+	p4 = 0;
+	p5 = 0;
+
+	i0 = 0; /* DAG Registers zero'd */
+	i1 = 0;
+	i2 = 0;
+	i3 = 0;
+	m0 = 0;
+	m1 = 0;
+	m3 = 0;
+	m3 = 0;
+	l0 = 0;
+	l1 = 0;
+	l2 = 0;
+	l3 = 0;
+	b0 = 0;
+	b1 = 0;
+	b2 = 0;
+	b3 = 0;
+
+	/* Set loop counters to zero, to make sure that
+	 * hw loops are disabled.
+	 */
+	r0  = 0;
+	lc0 = r0;
+	lc1 = r0;
+
+	SSYNC;
+
+	/* Check soft reset status */
+	p0.h = SWRST >> 16;
+	p0.l = SWRST & 0xFFFF;
+	r0.l = w[p0];
+
+	cc = bittst(r0, 15);
+	if !cc jump no_soft_reset;
+
+	/* Clear Soft reset */
+	r0 = 0x0000;
+	w[p0] = r0;
+	ssync;
+
+no_soft_reset:
+	nop;
+
+	/* Clear EVT registers */
+	p0.h = (EVT_EMULATION_ADDR >> 16);
+	p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
+	p0 += 8;
+	p1 = 14;
+	r1 = 0;
+	LSETUP(4,4) lc0 = p1;
+	[ p0 ++ ] = r1;
+
+#if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT)
+	p0.h = hi(SIC_IWR);
+	p0.l = lo(SIC_IWR);
+	r0.l = 0x1;
+	w[p0] = r0.l;
+	SSYNC;
+#endif
+
+#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
+
+	p0.h = hi(SIC_IWR);
+	p0.l = lo(SIC_IWR);
+	r0.l = 0x1;
+	w[p0] = r0.l;
+	SSYNC;
+
+	/*
+	* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+	*/
+	p0.h = hi(PLL_LOCKCNT);
+	p0.l = lo(PLL_LOCKCNT);
+	r0 = 0x300(Z);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	* Put SDRAM in self-refresh, incase anything is running
+	*/
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITSET (R0, 24);
+	[P2] = R0;
+	SSYNC;
+
+	/*
+	*  Set PLL_CTL with the value that we calculate in R0
+	*   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+	*   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+	*   - [7]     = output delay (add 200ps of delay to mem signals)
+	*   - [6]     = input delay (add 200ps of input delay to mem signals)
+	*   - [5]     = PDWN      : 1=All Clocks off
+	*   - [3]     = STOPCK    : 1=Core Clock off
+	*   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+	*   - [0]     = DF	  : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+	*   all other bits set to zero
+	*/
+
+	r0 = CONFIG_VCO_MULT & 63;      /* Load the VCO multiplier         */
+	r0 = r0 << 9;                   /* Shift it over,                  */
+	r1 = CONFIG_CLKIN_HALF;        /* Do we need to divide CLKIN by 2?*/
+	r0 = r1 | r0;
+	r1 = CONFIG_PLL_BYPASS;         /* Bypass the PLL?                 */
+	r1 = r1 << 8;                   /* Shift it over                   */
+	r0 = r1 | r0;                   /* add them all together           */
+
+	p0.h = hi(PLL_CTL);
+	p0.l = lo(PLL_CTL);             /* Load the address                */
+	cli r2;                         /* Disable interrupts              */
+		ssync;
+	w[p0] = r0.l;                   /* Set the value                   */
+	idle;                           /* Wait for the PLL to stablize    */
+	sti r2;                         /* Enable interrupts               */
+
+check_again:
+	p0.h = hi(PLL_STAT);
+	p0.l = lo(PLL_STAT);
+	R0 = W[P0](Z);
+	CC = BITTST(R0,5);
+	if ! CC jump check_again;
+
+	/* Configure SCLK & CCLK Dividers */
+	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+	p0.h = hi(PLL_DIV);
+	p0.l = lo(PLL_DIV);
+	w[p0] = r0.l;
+	ssync;
+#endif
+
+	/*
+	 * We now are running at speed, time to set the Async mem bank wait states
+	 * This will speed up execution, since we are normally running from FLASH.
+	 * we need to read MAC address from FLASH
+	 */
+	p2.h = (EBIU_AMBCTL1 >> 16);
+	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+	r0.h = (AMBCTL1VAL >> 16);
+	r0.l = (AMBCTL1VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMBCTL0 >> 16);
+	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+	r0.h = (AMBCTL0VAL >> 16);
+	r0.l = (AMBCTL0VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMGCTL >> 16);
+	p2.l = (EBIU_AMGCTL & 0xffff);
+	r0 = AMGCTLVAL;
+	w[p2] = r0;
+	ssync;
+
+#if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT))
+	sp.l = (0xffb01000 & 0xFFFF);
+	sp.h = (0xffb01000 >> 16);
+
+	call init_sdram;
+#endif
+
+
+#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
+	/* DMA POST code to Hi of L1 SRAM */
+postcopy:
+	/* P1 Points to the beginning of SYSTEM MMR Space */
+	P1.H = hi(SYSMMR_BASE);
+	P1.L = lo(SYSMMR_BASE);
+
+	R0.H = _text_l1;
+	R0.L = _text_l1;
+	R1.H = _etext_l1;
+	R1.L = _etext_l1;
+	R2 = R1 - R0;           /* Count */
+	R0.H = _etext;
+	R0.L = _etext;
+	R1.H = (CFG_MONITOR_BASE >> 16);
+	R1.L = (CFG_MONITOR_BASE & 0xFFFF);
+	R0 = R0 - R1;
+	R1.H = (CFG_FLASH_BASE >> 16);
+	R1.L = (CFG_FLASH_BASE & 0xFFFF);
+	R0 = R0 + R1;		/* Source Address */
+	R1.H = hi(L1_ISRAM);    /* Destination Address (high) */
+	R1.L = lo(L1_ISRAM);    /* Destination Address (low) */
+	R3.L = DMAEN;           /* Source DMAConfig Value (8-bit words) */
+	/* Destination DMAConfig Value (8-bit words) */
+	R4.L = (DI_EN | WNR | DMAEN);
+
+	R6 = 0x1 (Z);
+	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;   /* Source Modify = 1 */
+	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;   /* Destination Modify = 1 */
+
+	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;  /* Set Source Base Address */
+	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;    /* Set Source Count */
+	/* Set Source  DMAConfig = DMA Enable,
+	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
+	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;  /* Set Destination Base Address */
+	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;    /* Set Destination Count */
+	/* Set Destination DMAConfig = DMA Enable,
+	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+POST_DMA_DONE:
+	p0.h = hi(MDMA_D0_IRQ_STATUS);
+	p0.l = lo(MDMA_D0_IRQ_STATUS);
+	R0 = W[P0](Z);
+	CC = BITTST(R0, 0);
+	if ! CC jump POST_DMA_DONE
+
+	R0 = 0x1;
+	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
+
+	/* DMA POST data to Hi of L1 SRAM */
+	R0.H = _rodata_l1;
+	R0.L = _rodata_l1;
+	R1.H = _erodata_l1;
+	R1.L = _erodata_l1;
+	R2 = R1 - R0;           /* Count */
+	R0.H = _erodata;
+	R0.L = _erodata;
+	R1.H = (CFG_MONITOR_BASE >> 16);
+	R1.L = (CFG_MONITOR_BASE & 0xFFFF);
+	R0 = R0 - R1;
+	R1.H = (CFG_FLASH_BASE >> 16);
+	R1.L = (CFG_FLASH_BASE & 0xFFFF);
+	R0 = R0 + R1;           /* Source Address */
+	R1.H = hi(DATA_BANKB_SRAM);    /* Destination Address (high) */
+	R1.L = lo(DATA_BANKB_SRAM);    /* Destination Address (low) */
+	R3.L = DMAEN;           /* Source DMAConfig Value (8-bit words) */
+	R4.L = (DI_EN | WNR | DMAEN);   /* Destination DMAConfig Value (8-bit words) */
+
+	R6 = 0x1 (Z);
+	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;   /* Source Modify = 1 */
+	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;   /* Destination Modify = 1 */
+
+	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;  /* Set Source Base Address */
+	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;    /* Set Source Count */
+	/* Set Source  DMAConfig = DMA Enable,
+	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
+	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;  /* Set Destination Base Address */
+	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;    /* Set Destination Count */
+	/* Set Destination DMAConfig = DMA Enable,
+	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+POST_DATA_DMA_DONE:
+	p0.h = hi(MDMA_D0_IRQ_STATUS);
+	p0.l = lo(MDMA_D0_IRQ_STATUS);
+	R0 = W[P0](Z);
+	CC = BITTST(R0, 0);
+	if ! CC jump POST_DATA_DMA_DONE
+
+	R0 = 0x1;
+	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
+
+	p0.l = _memory_post_test;
+	p0.h = _memory_post_test;
+	r0 = 0x0;
+	call (p0);
+	r7 = r0;				/* save return value */
+
+	call init_sdram;
+#endif
+
+	/* relocate into to RAM */
+	call get_pc;
+offset:
+	r2.l = offset;
+	r2.h = offset;
+	r3.l = start;
+	r3.h = start;
+	r1 = r2 - r3;
+
+	r0 = r0 - r1;
+	p1 = r0;
+
+	p2.l = (CFG_MONITOR_BASE & 0xffff);
+	p2.h = (CFG_MONITOR_BASE >> 16);
+
+	p3 = 0x04;
+	p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
+	p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
+loop1:
+	r1 = [p1 ++ p3];
+	[p2 ++ p3] = r1;
+	cc=p2==p4;
+	if !cc jump loop1;
+	/*
+	 * configure STACK
+	 */
+	r0.h = (CONFIG_STACKBASE >> 16);
+	r0.l = (CONFIG_STACKBASE & 0xFFFF);
+	sp = r0;
+	fp = sp;
+
+	/*
+	 * This next section keeps the processor in supervisor mode
+	 * during kernel boot.  Switches to user mode at end of boot.
+	 * See page 3-9 of Hardware Reference manual for documentation.
+	 */
+
+	/* To keep ourselves in the supervisor mode */
+	p0.l = (EVT_IVG15_ADDR & 0xFFFF);
+	p0.h = (EVT_IVG15_ADDR >> 16);
+
+	p1.l = _real_start;
+	p1.h = _real_start;
+	[p0] = p1;
+
+	p0.l = (IMASK & 0xFFFF);
+	p0.h = (IMASK >> 16);
+	r0.l = LO(IVG15_POS);
+	r0.h = HI(IVG15_POS);
+	[p0] = r0;
+	raise 15;
+	p0.l = WAIT_HERE;
+	p0.h = WAIT_HERE;
+	reti = p0;
+	rti;
+
+WAIT_HERE:
+	jump WAIT_HERE;
+
+.global _real_start;
+_real_start:
+	[ -- sp ] = reti;
+
+#ifdef CONFIG_BF537
+/* Initialise General-Purpose I/O Modules on BF537
+ * Rev 0.0 Anomaly 05000212 - PORTx_FER,
+ * PORT_MUX Registers Do Not accept "writes" correctly
+ */
+	p0.h = hi(PORTF_FER);
+	p0.l = lo(PORTF_FER);
+	R0.L = W[P0]; /* Read */
+	nop;
+	nop;
+	nop;
+	ssync;
+	R0 = 0x000F(Z);
+	W[P0] = R0.L; /* Write */
+	nop;
+	nop;
+	nop;
+	ssync;
+	W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
+	nop;
+	nop;
+	nop;
+	ssync;
+
+	p0.h = hi(PORTH_FER);
+	p0.l = lo(PORTH_FER);
+	R0.L = W[P0]; /* Read */
+	nop;
+	nop;
+	nop;
+	ssync;
+	R0 = 0xFFFF(Z);
+	W[P0] = R0.L; /* Write */
+	nop;
+	nop;
+	nop;
+	ssync;
+	W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
+	nop;
+	nop;
+	nop;
+	ssync;
+
+#endif
+
+	/* DMA reset code to Hi of L1 SRAM */
+copy:
+	P1.H = hi(SYSMMR_BASE);	/* P1 Points to the beginning of SYSTEM MMR Space */
+	P1.L = lo(SYSMMR_BASE);
+
+	R0.H = reset_start;	/* Source Address (high) */
+	R0.L = reset_start;	/* Source Address (low) */
+	R1.H = reset_end;
+	R1.L = reset_end;
+	R2 = R1 - R0;		/* Count */
+	R1.H = hi(L1_ISRAM);	/* Destination Address (high) */
+	R1.L = lo(L1_ISRAM);	/* Destination Address (low) */
+	R3.L = DMAEN;		/* Source DMAConfig Value (8-bit words) */
+	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
+
+DMA:
+	R6 = 0x1 (Z);
+	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
+	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
+
+	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
+	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
+	/* Set Source  DMAConfig = DMA Enable,
+	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
+	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
+	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
+	/* Set Destination DMAConfig = DMA Enable,
+	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+WAIT_DMA_DONE:
+	p0.h = hi(MDMA_D0_IRQ_STATUS);
+	p0.l = lo(MDMA_D0_IRQ_STATUS);
+	R0 = W[P0](Z);
+	CC = BITTST(R0, 0);
+	if ! CC jump WAIT_DMA_DONE
+
+	R0 = 0x1;
+	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
+
+	/* Initialize BSS Section with 0 s */
+	p1.l = __bss_start;
+	p1.h = __bss_start;
+	p2.l = _end;
+	p2.h = _end;
+	r1 = p1;
+	r2 = p2;
+	r3 = r2 - r1;
+	r3 = r3 >> 2;
+	p3 = r3;
+	lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
+	CC = p2<=p1;
+	if CC jump _clear_bss_skip;
+	r0 = 0;
+_clear_bss:
+_clear_bss_end:
+	[p1++] = r0;
+_clear_bss_skip:
+
+#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
+	p0.l = _post_flag;
+	p0.h = _post_flag;
+	r0   = r7;
+	[p0] = r0;
+#endif
+
+	p0.l = _start1;
+	p0.h = _start1;
+	jump (p0);
+
+reset_start:
+	p0.h = WDOG_CNT >> 16;
+	p0.l = WDOG_CNT & 0xffff;
+	r0 = 0x0010;
+	w[p0] = r0;
+	p0.h = WDOG_CTL >> 16;
+	p0.l = WDOG_CTL & 0xffff;
+	r0 = 0x0000;
+	w[p0] = r0;
+reset_wait:
+	jump reset_wait;
+
+reset_end:
+	nop;
+
+_exit:
+	jump.s	_exit;
+get_pc:
+	r0 = rets;
+	rts;
diff --git a/cpu/bf537/start1.S b/cpu/bf537/start1.S
new file mode 100644
index 0000000..72cfafb
--- /dev/null
+++ b/cpu/bf537/start1.S
@@ -0,0 +1,38 @@
+/*
+ * U-boot - start1.S Code running out of RAM after relocation
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.global	start1;
+.global	_start1;
+
+.text
+_start1:
+start1:
+	sp += -12;
+	call	_board_init_f;
+	sp += 12;
diff --git a/cpu/bf537/traps.c b/cpu/bf537/traps.c
new file mode 100644
index 0000000..994ece8
--- /dev/null
+++ b/cpu/bf537/traps.c
@@ -0,0 +1,241 @@
+/*
+ * U-boot - traps.c Routines related to interrupts and exceptions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * No original Copyright holder listed,
+ * Probabily original (C) Roman Zippel (assigned DJD, 1999)
+ *
+ * Copyright 2003 Metrowerks - for Blackfin
+ * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
+ * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/errno.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+#include <asm/page.h>
+#include <asm/machdep.h>
+#include "cpu.h"
+#include <asm/arch/anomaly.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
+
+void init_IRQ(void)
+{
+	blackfin_init_IRQ();
+	return;
+}
+
+void process_int(unsigned long vec, struct pt_regs *fp)
+{
+	printf("interrupt\n");
+	return;
+}
+
+extern unsigned int icplb_table[page_descriptor_table_size][2];
+extern unsigned int dcplb_table[page_descriptor_table_size][2];
+
+unsigned long last_cplb_fault_retx;
+
+static unsigned int cplb_sizes[4] =
+    { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
+
+void trap_c(struct pt_regs *regs)
+{
+	unsigned int addr;
+	unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
+	unsigned int i, j, size, *I0, *I1;
+	unsigned short data = 0;
+
+	switch (trapnr) {
+		/* 0x26 - Data CPLB Miss */
+	case VEC_CPLB_M:
+
+#ifdef ANOMALY_05000261
+		/*
+		 * Work around an anomaly: if we see a new DCPLB fault,
+		 * return without doing anything. Then,
+		 * if we get the same fault again, handle it.
+		 */
+		addr = last_cplb_fault_retx;
+		last_cplb_fault_retx = regs->retx;
+		printf("this time, curr = 0x%08x last = 0x%08x\n",
+		       addr, last_cplb_fault_retx);
+		if (addr != last_cplb_fault_retx)
+			goto trap_c_return;
+#endif
+		data = 1;
+
+	case VEC_CPLB_I_M:
+
+		if (data) {
+			addr = *pDCPLB_FAULT_ADDR;
+		} else {
+			addr = *pICPLB_FAULT_ADDR;
+		}
+		for (i = 0; i < page_descriptor_table_size; i++) {
+			if (data) {
+				size = cplb_sizes[dcplb_table[i][1] >> 16];
+				j = dcplb_table[i][0];
+			} else {
+				size = cplb_sizes[icplb_table[i][1] >> 16];
+				j = icplb_table[i][0];
+			}
+			if ((j <= addr) && ((j + size) > addr)) {
+				debug("found %i 0x%08x\n", i, j);
+				break;
+			}
+		}
+		if (i == page_descriptor_table_size) {
+			printf("something is really wrong\n");
+			do_reset(NULL, 0, 0, NULL);
+		}
+
+		/* Turn the cache off */
+		if (data) {
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)DMEM_CONTROL &=
+			    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+			sync();
+		} else {
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+			sync();
+		}
+
+		if (data) {
+			I0 = (unsigned int *)DCPLB_ADDR0;
+			I1 = (unsigned int *)DCPLB_DATA0;
+		} else {
+			I0 = (unsigned int *)ICPLB_ADDR0;
+			I1 = (unsigned int *)ICPLB_DATA0;
+		}
+
+		j = 0;
+		while (*I1 & CPLB_LOCK) {
+			debug("skipping %i %08p - %08x\n", j, I1, *I1);
+			*I0++;
+			*I1++;
+			j++;
+		}
+
+		debug("remove %i 0x%08x  0x%08x\n", j, *I0, *I1);
+
+		for (; j < 15; j++) {
+			debug("replace %i 0x%08x  0x%08x\n", j, I0, I0 + 1);
+			*I0++ = *(I0 + 1);
+			*I1++ = *(I1 + 1);
+		}
+
+		if (data) {
+			*I0 = dcplb_table[i][0];
+			*I1 = dcplb_table[i][1];
+			I0 = (unsigned int *)DCPLB_ADDR0;
+			I1 = (unsigned int *)DCPLB_DATA0;
+		} else {
+			*I0 = icplb_table[i][0];
+			*I1 = icplb_table[i][1];
+			I0 = (unsigned int *)ICPLB_ADDR0;
+			I1 = (unsigned int *)ICPLB_DATA0;
+		}
+
+		for (j = 0; j < 16; j++) {
+			debug("%i 0x%08x  0x%08x\n", j, *I0++, *I1++);
+		}
+
+		/* Turn the cache back on */
+		if (data) {
+			j = *(unsigned int *)DMEM_CONTROL;
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)DMEM_CONTROL =
+			    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
+			sync();
+		} else {
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+			sync();
+		}
+
+		break;
+	default:
+		/* All traps come here */
+		printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
+		printf("stack frame=0x%x, ", (unsigned int)regs);
+		printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
+		dump(regs);
+		printf("\n\n");
+
+		printf("Unhandled IRQ or exceptions!\n");
+		printf("Please reset the board \n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+trap_c_return:
+	return;
+
+}
+
+void dump(struct pt_regs *fp)
+{
+	debug("RETE:  %08lx  RETN: %08lx  RETX: %08lx  RETS: %08lx\n",
+		 fp->rete, fp->retn, fp->retx, fp->rets);
+	debug("IPEND: %04lx  SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
+	debug("SEQSTAT: %08lx    SP: %08lx\n", (long)fp->seqstat, (long)fp);
+	debug("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
+		 fp->r0, fp->r1, fp->r2, fp->r3);
+	debug("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
+		 fp->r4, fp->r5, fp->r6, fp->r7);
+	debug("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
+		 fp->p0, fp->p1, fp->p2, fp->p3);
+	debug("P4: %08lx    P5: %08lx    FP: %08lx\n",
+		 fp->p4, fp->p5, fp->fp);
+	debug("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
+		 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+
+	debug("LB0: %08lx  LT0: %08lx  LC0: %08lx\n",
+		 fp->lb0, fp->lt0, fp->lc0);
+	debug("LB1: %08lx  LT1: %08lx  LC1: %08lx\n",
+		 fp->lb1, fp->lt1, fp->lc1);
+	debug("B0: %08lx  L0: %08lx  M0: %08lx  I0: %08lx\n",
+		 fp->b0, fp->l0, fp->m0, fp->i0);
+	debug("B1: %08lx  L1: %08lx  M1: %08lx  I1: %08lx\n",
+		 fp->b1, fp->l1, fp->m1, fp->i1);
+	debug("B2: %08lx  L2: %08lx  M2: %08lx  I2: %08lx\n",
+		 fp->b2, fp->l2, fp->m2, fp->i2);
+	debug("B3: %08lx  L3: %08lx  M3: %08lx  I3: %08lx\n",
+		 fp->b3, fp->l3, fp->m3, fp->i3);
+
+	debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
+	debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
+
+}
diff --git a/cpu/bf537/video.c b/cpu/bf537/video.c
new file mode 100644
index 0000000..3ff0151
--- /dev/null
+++ b/cpu/bf537/video.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ * (C) Copyright 2002
+ * Wolfgang Denk, wd@denx.de
+ * (C) Copyright 2006
+ * Aubrey Li, aubrey.li@analog.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <devices.h>
+
+#ifdef CONFIG_VIDEO
+#define NTSC_FRAME_ADDR 0x06000000
+#include "video.h"
+
+/* NTSC OUTPUT SIZE  720 * 240 */
+#define VERTICAL	2
+#define HORIZONTAL	4
+
+int is_vblank_line(const int line)
+{
+	/*
+	 *  This array contains a single bit for each line in
+	 *  an NTSC frame.
+	 */
+	if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
+		return true;
+
+	return false;
+}
+
+int NTSC_framebuffer_init(char *base_address)
+{
+	const int NTSC_frames = 1;
+	const int NTSC_lines = 525;
+	char *dest = base_address;
+	int frame_num, line_num;
+
+	for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
+		for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
+			unsigned int code;
+			int offset = 0;
+			int i;
+
+			if (is_vblank_line(line_num))
+				offset++;
+
+			if (line_num > 266 || line_num < 3)
+				offset += 2;
+
+			/* Output EAV code */
+			code = SystemCodeMap[offset].EAV;
+			write_dest_byte((char)(code >> 24) & 0xff);
+			write_dest_byte((char)(code >> 16) & 0xff);
+			write_dest_byte((char)(code >> 8) & 0xff);
+			write_dest_byte((char)(code) & 0xff);
+
+			/* Output horizontal blanking */
+			for (i = 0; i < 67 * 2; ++i) {
+				write_dest_byte(0x80);
+				write_dest_byte(0x10);
+			}
+
+			/* Output SAV */
+			code = SystemCodeMap[offset].SAV;
+			write_dest_byte((char)(code >> 24) & 0xff);
+			write_dest_byte((char)(code >> 16) & 0xff);
+			write_dest_byte((char)(code >> 8) & 0xff);
+			write_dest_byte((char)(code) & 0xff);
+
+			/* Output empty horizontal data */
+			for (i = 0; i < 360 * 2; ++i) {
+				write_dest_byte(0x80);
+				write_dest_byte(0x10);
+			}
+		}
+	}
+
+	return dest - base_address;
+}
+
+void fill_frame(char *Frame, int Value)
+{
+	int *OddPtr32;
+	int OddLine;
+	int *EvenPtr32;
+	int EvenLine;
+	int i;
+	int *data;
+	int m, n;
+
+	/* fill odd and even frames */
+	for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
+		OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
+		EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
+		for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
+			*OddPtr32 = Value;
+			*EvenPtr32 = Value;
+		}
+	}
+
+	for (m = 0; m < VERTICAL; m++) {
+		data = (int *)u_boot_logo.data;
+		for (OddLine = (22 + m), EvenLine = (285 + m);
+		     OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
+		     OddLine += VERTICAL, EvenLine += VERTICAL) {
+			OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
+			EvenPtr32 =
+			    (int *)((Frame + ((EvenLine) * 1716)) + 276);
+			for (i = 0; i < u_boot_logo.width / 2; i++) {
+				/* enlarge one pixel to m x n */
+				for (n = 0; n < HORIZONTAL; n++) {
+					*OddPtr32++ = *data;
+					*EvenPtr32++ = *data;
+				}
+				data++;
+			}
+		}
+	}
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+static int video_init(void)
+{
+	char *NTSCFrame;
+	NTSCFrame = (char *)NTSC_FRAME_ADDR;
+	NTSC_framebuffer_init(NTSCFrame);
+	fill_frame(NTSCFrame, BLUE);
+
+	*pPPI_CONTROL = 0x0082;
+	*pPPI_FRAME = 0x020D;
+
+	*pDMA0_START_ADDR = NTSCFrame;
+	*pDMA0_X_COUNT = 0x035A;
+	*pDMA0_X_MODIFY = 0x0002;
+	*pDMA0_Y_COUNT = 0x020D;
+	*pDMA0_Y_MODIFY = 0x0002;
+	*pDMA0_CONFIG = 0x1015;
+	*pPPI_CONTROL = 0x0083;
+	return 0;
+}
+
+int drv_video_init(void)
+{
+	int error, devices = 1;
+
+	device_t videodev;
+
+	video_init();		/* Video initialization */
+
+	memset(&videodev, 0, sizeof(videodev));
+
+	strcpy(videodev.name, "video");
+	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
+	videodev.flags = DEV_FLAGS_OUTPUT;	/* Output only */
+	videodev.putc = video_putc;	/* 'putc' function */
+	videodev.puts = video_puts;	/* 'puts' function */
+
+	error = device_register(&videodev);
+
+	return (error == 0) ? devices : error;
+}
+#endif
diff --git a/cpu/bf537/video.h b/cpu/bf537/video.h
new file mode 100644
index 0000000..a43553f
--- /dev/null
+++ b/cpu/bf537/video.h
@@ -0,0 +1,25 @@
+#include <video_logo.h>
+#define write_dest_byte(val) {*dest++=val;}
+#define BLACK   (0x01800180)	/* black pixel pattern	*/
+#define BLUE    (0x296E29F0)	/* blue pixel pattern	*/
+#define RED     (0x51F0515A)	/* red pixel pattern	*/
+#define MAGENTA (0x6ADE6ACA)	/* magenta pixel pattern*/
+#define GREEN   (0x91229136)	/* green pixel pattern	*/
+#define CYAN    (0xAA10AAA6)	/* cyan pixel pattern	*/
+#define YELLOW  (0xD292D210)	/* yellow pixel pattern	*/
+#define WHITE   (0xFE80FE80)	/* white pixel pattern	*/
+
+#define true 	1
+#define false	0
+
+typedef struct {
+	unsigned int SAV;
+	unsigned int EAV;
+} SystemCodeType;
+
+const SystemCodeType SystemCodeMap[4] = {
+	{0xFF000080, 0xFF00009D},
+	{0xFF0000AB, 0xFF0000B6},
+	{0xFF0000C7, 0xFF0000DA},
+	{0xFF0000EC, 0xFF0000F1}
+};
diff --git a/cpu/bf561/Makefile b/cpu/bf561/Makefile
new file mode 100644
index 0000000..ee7842a
--- /dev/null
+++ b/cpu/bf561/Makefile
@@ -0,0 +1,52 @@
+# U-boot - Makefile
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).a
+
+START	= start.o start1.o interrupt.o cache.o flush.o init_sdram.o
+COBJS	= cpu.o traps.o ints.o serial.o interrupts.o video.o
+
+EXTRA = init_sdram_bootrom_initblock.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/bf561/cache.S b/cpu/bf561/cache.S
new file mode 100644
index 0000000..5bda5bf
--- /dev/null
+++ b/cpu/bf561/cache.S
@@ -0,0 +1,128 @@
+#define ASSEMBLY
+#include <asm/linkage.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.text
+.align 2
+ENTRY(_blackfin_icache_flush_range)
+	R2 = -32;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
+	1:
+	IFLUSH[P0++];
+	CC = P0 < P1(iu);
+	IF CC JUMP 1b(bp);
+	IFLUSH[P0];
+	SSYNC;
+	RTS;
+
+ENTRY(_blackfin_dcache_flush_range)
+	R2 = -32;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
+1:
+	FLUSH[P0++];
+	CC = P0 < P1(iu);
+	IF CC JUMP 1b(bp);
+	FLUSH[P0];
+	SSYNC;
+	RTS;
+
+ENTRY(_icache_invalidate)
+ENTRY(_invalidate_entire_icache)
+	[--SP] = (R7:5);
+
+	P0.L = (IMEM_CONTROL & 0xFFFF);
+	P0.H = (IMEM_CONTROL >> 16);
+	R7 =[P0];
+
+	/*
+	 * Clear the IMC bit , All valid bits in the instruction
+	 * cache are set to the invalid state
+	 */
+	BITCLR(R7, IMC_P);
+	CLI R6;
+	/* SSYNC required before invalidating cache. */
+	SSYNC;
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	/* Configures the instruction cache agian */
+	R6 = (IMC | ENICPLB);
+	R7 = R7 | R6;
+
+	CLI R6;
+	SSYNC;
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	(R7:5) =[SP++];
+	RTS;
+
+/*
+ * Invalidate the Entire Data cache by
+ * clearing DMC[1:0] bits
+ */
+ENTRY(_invalidate_entire_dcache)
+ENTRY(_dcache_invalidate)
+	[--SP] = (R7:6);
+
+	P0.L = (DMEM_CONTROL & 0xFFFF);
+	P0.H = (DMEM_CONTROL >> 16);
+	R7 =[P0];
+
+	/*
+	 * Clear the DMC[1:0] bits, All valid bits in the data
+	 * cache are set to the invalid state
+	 */
+	BITCLR(R7, DMC0_P);
+	BITCLR(R7, DMC1_P);
+	CLI R6;
+	SSYNC;
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+	/* Configures the data cache again */
+
+	R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+	R7 = R7 | R6;
+
+	CLI R6;
+	SSYNC;
+	.align 8;
+	[P0] = R7;
+	SSYNC;
+	STI R6;
+
+	(R7:6) =[SP++];
+	RTS;
+
+ENTRY(_blackfin_dcache_invalidate_range)
+	R2 = -32;
+	R2 = R0 & R2;
+	P0 = R2;
+	P1 = R1;
+	CSYNC;
+1:
+	FLUSHINV[P0++];
+	CC = P0 < P1(iu);
+	IF CC JUMP 1b(bp);
+
+	/*
+	 * If the data crosses a cache line, then we'll be pointing to
+	 * the last cache line, but won't have flushed/invalidated it yet, so do
+	 * one more.
+	 */
+	FLUSHINV[P0];
+	SSYNC;
+	RTS;
diff --git a/cpu/bf561/config.mk b/cpu/bf561/config.mk
new file mode 100644
index 0000000..c49a0ba
--- /dev/null
+++ b/cpu/bf561/config.mk
@@ -0,0 +1,27 @@
+# U-boot - config.mk
+#
+# Copyright (c) 2005 blackfin.uclinux.org
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -mcpu=bf561 -ffixed-P5
diff --git a/cpu/bf561/cpu.c b/cpu/bf561/cpu.c
new file mode 100644
index 0000000..a7b53d8
--- /dev/null
+++ b/cpu/bf561/cpu.c
@@ -0,0 +1,220 @@
+/*
+ * U-boot - cpu.c CPU specific functions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <command.h>
+#include <asm/entry.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
+
+#define CACHE_ON 1
+#define CACHE_OFF 0
+
+extern unsigned int icplb_table[page_descriptor_table_size][2];
+extern unsigned int dcplb_table[page_descriptor_table_size][2];
+
+int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
+	    );
+
+	return 0;
+}
+
+/* These functions are just used to satisfy the linker */
+int cpu_init(void)
+{
+	return 0;
+}
+
+int cleanup_before_linux(void)
+{
+	return 0;
+}
+
+void icache_enable(void)
+{
+	unsigned int *I0, *I1;
+	int i, j = 0;
+
+	/* Before enable icache, disable it first */
+	icache_disable();
+	I0 = (unsigned int *)ICPLB_ADDR0;
+	I1 = (unsigned int *)ICPLB_DATA0;
+
+	/* make sure the locked ones go in first */
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (CPLB_LOCK & icplb_table[i][1]) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+			      icplb_table[i][0], icplb_table[i][1]);
+			*I0++ = icplb_table[i][0];
+			*I1++ = icplb_table[i][1];
+			j++;
+		}
+	}
+
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (!(CPLB_LOCK & icplb_table[i][1])) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+			      icplb_table[i][0], icplb_table[i][1]);
+			*I0++ = icplb_table[i][0];
+			*I1++ = icplb_table[i][1];
+			j++;
+			if (j == 16) {
+				break;
+			}
+		}
+	}
+
+	/* Fill the rest with invalid entry */
+	if (j <= 15) {
+		for (; j < 16; j++) {
+			debug("filling %i with 0", j);
+			*I1++ = 0x0;
+		}
+
+	}
+
+	cli();
+	sync();
+	asm(" .align 8; ");
+	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+	sync();
+	sti();
+}
+
+void icache_disable(void)
+{
+	cli();
+	sync();
+	asm(" .align 8; ");
+	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+	sync();
+	sti();
+}
+
+int icache_status(void)
+{
+	unsigned int value;
+	value = *(unsigned int *)IMEM_CONTROL;
+
+	if (value & (IMC | ENICPLB))
+		return CACHE_ON;
+	else
+		return CACHE_OFF;
+}
+
+void dcache_enable(void)
+{
+	unsigned int *I0, *I1;
+	unsigned int temp;
+	int i, j = 0;
+
+	/* Before enable dcache, disable it first */
+	dcache_disable();
+	I0 = (unsigned int *)DCPLB_ADDR0;
+	I1 = (unsigned int *)DCPLB_DATA0;
+
+	/* make sure the locked ones go in first */
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (CPLB_LOCK & dcplb_table[i][1]) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+			      dcplb_table[i][0], dcplb_table[i][1]);
+			*I0++ = dcplb_table[i][0];
+			*I1++ = dcplb_table[i][1];
+			j++;
+		} else {
+			debug("skip   %02i %02i 0x%08x 0x%08x\n", i, j,
+			      dcplb_table[i][0], dcplb_table[i][1]);
+		}
+	}
+
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		if (!(CPLB_LOCK & dcplb_table[i][1])) {
+			debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
+			      dcplb_table[i][0], dcplb_table[i][1]);
+			*I0++ = dcplb_table[i][0];
+			*I1++ = dcplb_table[i][1];
+			j++;
+			if (j == 16) {
+				break;
+			}
+		}
+	}
+
+	/* Fill the rest with invalid entry */
+	if (j <= 15) {
+		for (; j < 16; j++) {
+			debug("filling %i with 0", j);
+			*I1++ = 0x0;
+		}
+	}
+
+	cli();
+	temp = *(unsigned int *)DMEM_CONTROL;
+	sync();
+	asm(" .align 8; ");
+	*(unsigned int *)DMEM_CONTROL =
+	    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
+	sync();
+	sti();
+}
+
+void dcache_disable(void)
+{
+
+	unsigned int *I0, *I1;
+	int i;
+
+	cli();
+	sync();
+	asm(" .align 8; ");
+	*(unsigned int *)DMEM_CONTROL &=
+	    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+	sync();
+	sti();
+
+	/* after disable dcache, clear it so we don't confuse the next application */
+	I0 = (unsigned int *)DCPLB_ADDR0;
+	I1 = (unsigned int *)DCPLB_DATA0;
+
+	for (i = 0; i < 16; i++) {
+		*I0++ = 0x0;
+		*I1++ = 0x0;
+	}
+}
+
+int dcache_status(void)
+{
+	unsigned int value;
+	value = *(unsigned int *)DMEM_CONTROL;
+	if (value & (ENDCPLB))
+		return CACHE_ON;
+	else
+		return CACHE_OFF;
+}
diff --git a/cpu/bf561/cpu.h b/cpu/bf561/cpu.h
new file mode 100644
index 0000000..821363e
--- /dev/null
+++ b/cpu/bf561/cpu.h
@@ -0,0 +1,66 @@
+/*
+ *  U-boot - cpu.h
+ *
+ *  Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <command.h>
+
+#define INTERNAL_IRQS (32)
+#define NUM_IRQ_NODES 16
+#define DEF_INTERRUPT_FLAGS 1
+#define MAX_TIM_LOAD	0xFFFFFFFF
+
+void blackfin_irq_panic(int reason, struct pt_regs *reg);
+extern void dump(struct pt_regs *regs);
+void display_excp(void);
+asmlinkage void evt_nmi(void);
+asmlinkage void evt_exception(void);
+asmlinkage void trap(void);
+asmlinkage void evt_ivhw(void);
+asmlinkage void evt_rst(void);
+asmlinkage void evt_timer(void);
+asmlinkage void evt_evt7(void);
+asmlinkage void evt_evt8(void);
+asmlinkage void evt_evt9(void);
+asmlinkage void evt_evt10(void);
+asmlinkage void evt_evt11(void);
+asmlinkage void evt_evt12(void);
+asmlinkage void evt_evt13(void);
+asmlinkage void evt_soft_int1(void);
+asmlinkage void evt_system_call(void);
+void blackfin_irq_panic(int reason, struct pt_regs *regs);
+void blackfin_free_irq(unsigned int irq, void *dev_id);
+void call_isr(int irq, struct pt_regs *fp);
+void blackfin_do_irq(int vec, struct pt_regs *fp);
+void blackfin_init_IRQ(void);
+void blackfin_enable_irq(unsigned int irq);
+void blackfin_disable_irq(unsigned int irq);
+extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
+int blackfin_request_irq(unsigned int irq,
+			 void (*handler) (int, void *, struct pt_regs *),
+			 unsigned long flags, const char *devname,
+			 void *dev_id);
+void timer_init(void);
+#endif
diff --git a/cpu/bf561/flush.S b/cpu/bf561/flush.S
new file mode 100644
index 0000000..7e12c83
--- /dev/null
+++ b/cpu/bf561/flush.S
@@ -0,0 +1,402 @@
+/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2004 LG SOft India. All Rights Reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ */
+#define ASSEMBLY
+
+#include <asm/linkage.h>
+#include <asm/cplb.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.text
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the instruction cache.
+ */
+
+ENTRY(_flush_instruction_cache)
+	[--SP] = ( R7:6, P5:4 );
+	LINK 12;
+	SP += -12;
+	P5.H = (ICPLB_ADDR0 >> 16);
+	P5.L = (ICPLB_ADDR0 & 0xFFFF);
+	P4.H = (ICPLB_DATA0 >> 16);
+	P4.L = (ICPLB_DATA0 & 0xFFFF);
+	R7 = CPLB_VALID | CPLB_L1_CHBL;
+	R6 = 16;
+inext:	R0 = [P5++];
+	R1 = [P4++];
+	[--SP] =  RETS;
+	CALL _icplb_flush;	/* R0 = page, R1 = data*/
+	RETS = [SP++];
+iskip:	R6 += -1;
+	CC = R6;
+	IF CC JUMP inext;
+	SSYNC;
+	SP += 12;
+	UNLINK;
+	( R7:6, P5:4 ) = [SP++];
+	RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular ICPLB.
+ *
+ * R0 -  page's start address
+ * R1 -  CPLB's data field.
+ */
+
+.align 2
+ENTRY(_icplb_flush)
+	[--SP] = ( R7:0, P5:0 );
+	[--SP] = LC0;
+	[--SP] = LT0;
+	[--SP] = LB0;
+	[--SP] = LC1;
+	[--SP] = LT1;
+	[--SP] = LB1;
+
+	/* If it's a 1K or 4K page, then it's quickest to
+	 * just systematically flush all the addresses in
+	 * the page, regardless of whether they're in the
+	 * cache, or dirty. If it's a 1M or 4M page, there
+	 * are too many addresses, and we have to search the
+	 * cache for lines corresponding to the page.
+	 */
+
+	CC = BITTST(R1, 17);	/* 1MB or 4MB */
+	IF !CC JUMP iflush_whole_page;
+
+	/* We're only interested in the page's size, so extract
+	 * this from the CPLB (bits 17:16), and scale to give an
+	 * offset into the page_size and page_prefix tables.
+	 */
+
+	R1 <<= 14;
+	R1 >>= 30;
+	R1 <<= 2;
+
+	/* We can also determine the sub-bank used, because this is
+	 * taken from bits 13:12 of the address.
+	 */
+
+	R3 = ((12<<8)|2);		/* Extraction pattern */
+	nop;				/*Anamoly 05000209*/
+	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits*/
+	R3.H = R4.L << 0 ;		/* Save in extraction pattern for later deposit.*/
+
+
+	/* So:
+	 * R0 = Page start
+	 * R1 = Page length (actually, offset into size/prefix tables)
+	 * R3 = sub-bank deposit values
+	 *
+	 * The cache has 2 Ways, and 64 sets, so we iterate through
+	 * the sets, accessing the tag for each Way, for our Bank and
+	 * sub-bank, looking for dirty, valid tags that match our
+	 * address prefix.
+	 */
+
+	P5.L = (ITEST_COMMAND & 0xFFFF);
+	P5.H = (ITEST_COMMAND >> 16);
+	P4.L = (ITEST_DATA0 & 0xFFFF);
+	P4.H = (ITEST_DATA0 >> 16);
+
+	P0.L = page_prefix_table;
+	P0.H = page_prefix_table;
+	P1 = R1;
+	R5 = 0;			/* Set counter*/
+	P0 = P1 + P0;
+	R4 = [P0];		/* This is the address prefix*/
+
+	/* We're reading (bit 1==0) the tag (bit 2==0), and we
+	 * don't care about which double-word, since we're only
+	 * fetching tags, so we only have to set Set, Bank,
+	 * Sub-bank and Way.
+	 */
+
+	P2 = 4;
+	LSETUP (ifs1, ife1) LC1 = P2;
+ifs1:	P0 = 32;		/* iterate over all sets*/
+	LSETUP (ifs0, ife0) LC0 = P0;
+ifs0:	R6 = R5 << 5;		/* Combine set*/
+	R6.H = R3.H << 0 ;	/* and sub-bank*/
+	[P5] = R6;		/* Issue Command*/
+	SSYNC;			/* CSYNC will not work here :(*/
+	R7 = [P4];		/* and read Tag.*/
+	CC = BITTST(R7, 0);	/* Check if valid*/
+	IF !CC JUMP ifskip;	/* and skip if not.*/
+
+	/* Compare against the page address. First, plant bits 13:12
+	 * into the tag, since those aren't part of the returned data.
+	 */
+
+	R7 = DEPOSIT(R7, R3);	/* set 13:12*/
+	R1 = R7 & R4;		/* Mask off lower bits*/
+	CC = R1 == R0;		/* Compare against page start.*/
+	IF !CC JUMP ifskip;	/* Skip it if it doesn't match.*/
+
+	/* Tag address matches against page, so this is an entry
+	 * we must flush.
+	 */
+
+	R7 >>= 10;		/* Mask off the non-address bits*/
+	R7 <<= 10;
+	P3 = R7;
+	IFLUSH [P3];		/* And flush the entry*/
+ifskip:
+ife0:	R5 += 1;		/* Advance to next Set*/
+ife1:	NOP;
+
+ifinished:
+	SSYNC;			/* Ensure the data gets out to mem.*/
+
+	/*Finished. Restore context.*/
+	LB1 = [SP++];
+	LT1 = [SP++];
+	LC1 = [SP++];
+	LB0 = [SP++];
+	LT0 = [SP++];
+	LC0 = [SP++];
+	( R7:0, P5:0 ) = [SP++];
+	RTS;
+
+iflush_whole_page:
+	/* It's a 1K or 4K page, so quicker to just flush the
+	 * entire page.
+	 */
+
+	P1 = 32;		/* For 1K pages*/
+	P2 = P1 << 2;		/* For 4K pages*/
+	P0 = R0;		/* Start of page*/
+	CC = BITTST(R1, 16);	/* Whether 1K or 4K*/
+	IF CC P1 = P2;
+	P1 += -1;		/* Unroll one iteration*/
+	SSYNC;
+	IFLUSH [P0++];		/* because CSYNC can't end loops.*/
+	LSETUP (isall, ieall) LC0 = P1;
+isall:IFLUSH [P0++];
+ieall: NOP;
+	SSYNC;
+	JUMP ifinished;
+
+/* This is an external function being called by the user
+ * application through __flush_cache_all. Currently this function
+ * serves the purpose of flushing all the pending writes in
+ * in the data cache.
+ */
+
+ENTRY(_flush_data_cache)
+	[--SP] = ( R7:6, P5:4 );
+	LINK 12;
+	SP += -12;
+	P5.H = (DCPLB_ADDR0 >> 16);
+	P5.L = (DCPLB_ADDR0 & 0xFFFF);
+	P4.H = (DCPLB_DATA0 >> 16);
+	P4.L = (DCPLB_DATA0 & 0xFFFF);
+	R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
+	R6 = 16;
+next:	R0 = [P5++];
+	R1 = [P4++];
+	CC = BITTST(R1, 14);	/* Is it write-through?*/
+	IF CC JUMP skip;	/* If so, ignore it.*/
+	R2 = R1 & R7;		/* Is it a dirty, cached page?*/
+	CC = R2;
+	IF !CC JUMP skip;	/* If not, ignore it.*/
+	[--SP] = RETS;
+	CALL _dcplb_flush;	/* R0 = page, R1 = data*/
+	RETS = [SP++];
+skip:	R6 += -1;
+	CC = R6;
+	IF CC JUMP next;
+	SSYNC;
+	SP += 12;
+	UNLINK;
+	( R7:6, P5:4 ) = [SP++];
+	RTS;
+
+/* This is an internal function to flush all pending
+ * writes in the cache associated with a particular DCPLB.
+ *
+ * R0 -  page's start address
+ * R1 -  CPLB's data field.
+ */
+
+.align 2
+ENTRY(_dcplb_flush)
+	[--SP] = ( R7:0, P5:0 );
+	[--SP] = LC0;
+	[--SP] = LT0;
+	[--SP] = LB0;
+	[--SP] = LC1;
+	[--SP] = LT1;
+	[--SP] = LB1;
+
+	/* If it's a 1K or 4K page, then it's quickest to
+	 * just systematically flush all the addresses in
+	 * the page, regardless of whether they're in the
+	 * cache, or dirty. If it's a 1M or 4M page, there
+	 * are too many addresses, and we have to search the
+	 * cache for lines corresponding to the page.
+	 */
+
+	CC = BITTST(R1, 17);	/* 1MB or 4MB */
+	IF !CC JUMP dflush_whole_page;
+
+	/* We're only interested in the page's size, so extract
+	 * this from the CPLB (bits 17:16), and scale to give an
+	 * offset into the page_size and page_prefix tables.
+	 */
+
+	R1 <<= 14;
+	R1 >>= 30;
+	R1 <<= 2;
+
+	/* The page could be mapped into Bank A or Bank B, depending
+	 * on (a) whether both banks are configured as cache, and
+	 * (b) on whether address bit A[x] is set. x is determined
+	 * by DCBS in DMEM_CONTROL
+	 */
+
+	R2 = 0;			/* Default to Bank A (Bank B would be 1)*/
+
+	P0.L = (DMEM_CONTROL & 0xFFFF);
+	P0.H = (DMEM_CONTROL >> 16);
+
+	R3 = [P0];		/* If Bank B is not enabled as cache*/
+	CC = BITTST(R3, 2);	/* then Bank A is our only option.*/
+	IF CC JUMP bank_chosen;
+
+	R4 = 1<<14;		/* If DCBS==0, use A[14].*/
+	R5 = R4 << 7;		/* If DCBS==1, use A[23];*/
+	CC = BITTST(R3, 4);
+	IF CC R4 = R5;		/* R4 now has either bit 14 or bit 23 set.*/
+	R5 = R0 & R4;		/* Use it to test the Page address*/
+	CC = R5;		/* and if that bit is set, we use Bank B,*/
+	R2 = CC;		/* else we use Bank A.*/
+	R2 <<= 23;		/* The Bank selection's at posn 23.*/
+
+bank_chosen:
+
+	/* We can also determine the sub-bank used, because this is
+	 * taken from bits 13:12 of the address.
+	 */
+
+	R3 = ((12<<8)|2);		/* Extraction pattern */
+	nop;				/*Anamoly 05000209*/
+	R4 = EXTRACT(R0, R3.L) (Z);	/* Extract bits*/
+	/* Save in extraction pattern for later deposit.*/
+	R3.H = R4.L << 0;
+
+	/* So:
+	 * R0 = Page start
+	 * R1 = Page length (actually, offset into size/prefix tables)
+	 * R2 = Bank select mask
+	 * R3 = sub-bank deposit values
+	 *
+	 * The cache has 2 Ways, and 64 sets, so we iterate through
+	 * the sets, accessing the tag for each Way, for our Bank and
+	 * sub-bank, looking for dirty, valid tags that match our
+	 * address prefix.
+	 */
+
+	P5.L = (DTEST_COMMAND & 0xFFFF);
+	P5.H = (DTEST_COMMAND >> 16);
+	P4.L = (DTEST_DATA0 & 0xFFFF);
+	P4.H = (DTEST_DATA0 >> 16);
+
+	P0.L = page_prefix_table;
+	P0.H = page_prefix_table;
+	P1 = R1;
+	R5 = 0;			/* Set counter*/
+	P0 = P1 + P0;
+	R4 = [P0];		/* This is the address prefix*/
+
+
+	/* We're reading (bit 1==0) the tag (bit 2==0), and we
+	 * don't care about which double-word, since we're only
+	 * fetching tags, so we only have to set Set, Bank,
+	 * Sub-bank and Way.
+	 */
+
+	P2 = 2;
+	LSETUP (fs1, fe1) LC1 = P2;
+fs1:	P0 = 64;		/* iterate over all sets*/
+	LSETUP (fs0, fe0) LC0 = P0;
+fs0:	R6 = R5 << 5;		/* Combine set*/
+	R6.H = R3.H << 0 ;	/* and sub-bank*/
+	R6 = R6 | R2;		/* and Bank. Leave Way==0 at first.*/
+	BITSET(R6,14);
+	[P5] = R6;		/* Issue Command*/
+	SSYNC;
+	R7 = [P4];		/* and read Tag.*/
+	CC = BITTST(R7, 0);	/* Check if valid*/
+	IF !CC JUMP fskip;	/* and skip if not.*/
+	CC = BITTST(R7, 1);	/* Check if dirty*/
+	IF !CC JUMP fskip;	/* and skip if not.*/
+
+	/* Compare against the page address. First, plant bits 13:12
+	 * into the tag, since those aren't part of the returned data.
+	 */
+
+	R7 = DEPOSIT(R7, R3);	/* set 13:12*/
+	R1 = R7 & R4;		/* Mask off lower bits*/
+	CC = R1 == R0;		/* Compare against page start.*/
+	IF !CC JUMP fskip;	/* Skip it if it doesn't match.*/
+
+	/* Tag address matches against page, so this is an entry
+	 * we must flush.
+	 */
+
+	R7 >>= 10;		/* Mask off the non-address bits*/
+	R7 <<= 10;
+	P3 = R7;
+	SSYNC;
+	FLUSHINV [P3];		/* And flush the entry*/
+fskip:
+fe0:	R5 += 1;		/* Advance to next Set*/
+fe1:	BITSET(R2, 26);		/* Go to next Way.*/
+
+dfinished:
+	SSYNC;			/* Ensure the data gets out to mem.*/
+
+	/*Finished. Restore context.*/
+	LB1 = [SP++];
+	LT1 = [SP++];
+	LC1 = [SP++];
+	LB0 = [SP++];
+	LT0 = [SP++];
+	LC0 = [SP++];
+	( R7:0, P5:0 ) = [SP++];
+	RTS;
+
+dflush_whole_page:
+
+	/* It's a 1K or 4K page, so quicker to just flush the
+	 * entire page.
+	 */
+
+	P1 = 32;		/* For 1K pages*/
+	P2 = P1 << 2;		/* For 4K pages*/
+	P0 = R0;		/* Start of page*/
+	CC = BITTST(R1, 16);	/* Whether 1K or 4K*/
+	IF CC P1 = P2;
+	P1 += -1;		/* Unroll one iteration*/
+	SSYNC;
+	FLUSHINV [P0++];	/* because CSYNC can't end loops.*/
+	LSETUP (eall, eall) LC0 = P1;
+eall:	FLUSHINV [P0++];
+	SSYNC;
+	JUMP dfinished;
+
+.align 4;
+page_prefix_table:
+.byte4 	0xFFFFFC00;	/* 1K */
+.byte4	0xFFFFF000;	/* 4K */
+.byte4	0xFFF00000;	/* 1M */
+.byte4	0xFFC00000;	/* 4M */
+.page_prefix_table.end:
diff --git a/cpu/bf561/init_sdram.S b/cpu/bf561/init_sdram.S
new file mode 100644
index 0000000..d763f27
--- /dev/null
+++ b/cpu/bf561/init_sdram.S
@@ -0,0 +1,171 @@
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mem_init.h>
+.global init_sdram;
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+init_sdram:
+	[--SP] = ASTAT;
+	[--SP] = RETS;
+	[--SP] = (R7:0);
+	[--SP] = (P5:0);
+
+	/*
+	 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+	 */
+	p0.h = hi(PLL_LOCKCNT);
+	p0.l = lo(PLL_LOCKCNT);
+	r0 = 0x300(Z);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * Put SDRAM in self-refresh, incase anything is running
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITSET (R0, 24);
+	[P2] = R0;
+	SSYNC;
+
+	/*
+	 *  Set PLL_CTL with the value that we calculate in R0
+	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+	 *   - [8]     = BYPASS	   : BYPASS the PLL, run CLKIN into CCLK/SCLK
+	 *   - [7]     = output delay (add 200ps of delay to mem signals)
+	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
+	 *   - [5]     = PDWN	   : 1=All Clocks off
+	 *   - [3]     = STOPCK	   : 1=Core Clock off
+	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+	 *   - [0]     = DF	   : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+	 *   all other bits set to zero
+	 */
+
+	r0 = CONFIG_VCO_MULT & 63;	/* Load the VCO multiplier */
+	r0 = r0 << 9;			/* Shift it over, */
+	r1 = CONFIG_CLKIN_HALF;		/* Do we need to divide CLKIN by 2? */
+	r0 = r1 | r0;
+	r1 = CONFIG_PLL_BYPASS;		/* Bypass the PLL? */
+	r1 = r1 << 8;			/* Shift it over */
+	r0 = r1 | r0;			/* add them all together */
+
+	p0.h = hi(PLL_CTL);
+	p0.l = lo(PLL_CTL);		/* Load the address */
+	cli r2;				/* Disable interrupts */
+	ssync;
+	w[p0] = r0.l;			/* Set the value */
+	idle;				/* Wait for the PLL to stablize */
+	sti r2;				/* Enable interrupts */
+
+check_again:
+	p0.h = hi(PLL_STAT);
+	p0.l = lo(PLL_STAT);
+	R0 = W[P0](Z);
+	CC = BITTST(R0,5);
+	if ! CC jump check_again;
+
+	/* Configure SCLK & CCLK Dividers */
+	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+	p0.h = hi(PLL_DIV);
+	p0.l = lo(PLL_DIV);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * We now are running at speed, time to set the Async mem bank wait states
+	 * This will speed up execution, since we are normally running from FLASH.
+	 */
+
+	p2.h = (EBIU_AMBCTL1 >> 16);
+	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+	r0.h = (AMBCTL1VAL >> 16);
+	r0.l = (AMBCTL1VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMBCTL0 >> 16);
+	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+	r0.h = (AMBCTL0VAL >> 16);
+	r0.l = (AMBCTL0VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMGCTL >> 16);
+	p2.l = (EBIU_AMGCTL & 0xffff);
+	r0 = AMGCTLVAL;
+	w[p2] = r0;
+	ssync;
+
+	/*
+	 * Now, Initialize the SDRAM,
+	 * start with the SDRAM Refresh Rate Control Register
+	 */
+	p0.l = lo(EBIU_SDRRC);
+	p0.h = hi(EBIU_SDRRC);
+	r0 = mem_SDRRC;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Memory Bank Control Register - bank specific parameters
+	 */
+	p0.l = (EBIU_SDBCTL & 0xFFFF);
+	p0.h = (EBIU_SDBCTL >> 16);
+	r0 = mem_SDBCTL;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Global Control Register - global programmable parameters
+	 * Disable self-refresh
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITCLR (R0, 24);
+
+	/*
+	 * Check if SDRAM is already powered up, if it is, enable self-refresh
+	 */
+	p0.h = hi(EBIU_SDSTAT);
+	p0.l = lo(EBIU_SDSTAT);
+	r2.l = w[p0];
+	cc = bittst(r2,3);
+	if !cc jump skip;
+	NOP;
+	BITSET (R0, 23);
+skip:
+	[P2] = R0;
+	SSYNC;
+
+	/* Write in the new value in the register */
+	R0.L = lo(mem_SDGCTL);
+	R0.H = hi(mem_SDGCTL);
+	[P2] = R0;
+	SSYNC;
+	nop;
+
+	(P5:0) = [SP++];
+	(R7:0) = [SP++];
+	RETS   = [SP++];
+	ASTAT  = [SP++];
+	RTS;
diff --git a/cpu/bf561/init_sdram_bootrom_initblock.S b/cpu/bf561/init_sdram_bootrom_initblock.S
new file mode 100644
index 0000000..5e3c88a
--- /dev/null
+++ b/cpu/bf561/init_sdram_bootrom_initblock.S
@@ -0,0 +1,185 @@
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mem_init.h>
+.global init_sdram;
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV	CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV	CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV	CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV	CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV	CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+init_sdram:
+	[--SP] = ASTAT;
+	[--SP] = RETS;
+	[--SP] = (R7:0);
+	[--SP] = (P5:0);
+
+
+	p0.h = hi(SICA_IWR0);
+	p0.l = lo(SICA_IWR0);
+	r0.l = 0x1;
+	w[p0] = r0.l;
+	SSYNC;
+
+	p0.h = hi(SPI_BAUD);
+	p0.l = lo(SPI_BAUD);
+	r0.l = CONFIG_SPI_BAUD_INITBLOCK;
+	w[p0] = r0.l;
+	SSYNC;
+
+	/*
+	 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+	 */
+	p0.h = hi(PLL_LOCKCNT);
+	p0.l = lo(PLL_LOCKCNT);
+	r0 = 0x300(Z);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * Put SDRAM in self-refresh, incase anything is running
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITSET (R0, 24);
+	[P2] = R0;
+	SSYNC;
+
+	/*
+	 *  Set PLL_CTL with the value that we calculate in R0
+	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+	 *   - [7]     = output delay (add 200ps of delay to mem signals)
+	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
+	 *   - [5]     = PDWN	   : 1=All Clocks off
+	 *   - [3]     = STOPCK	   : 1=Core Clock off
+	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+	 *   - [0]     = DF	   : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+	 *   all other bits set to zero
+	 */
+
+	r0 = CONFIG_VCO_MULT & 63;	/* Load the VCO multiplier */
+	r0 = r0 << 9;			/* Shift it over, */
+	r1 = CONFIG_CLKIN_HALF;		/* Do we need to divide CLKIN by 2? */
+	r0 = r1 | r0;
+	r1 = CONFIG_PLL_BYPASS;		/* Bypass the PLL? */
+	r1 = r1 << 8;			/* Shift it over */
+	r0 = r1 | r0;			/* add them all together */
+
+	p0.h = hi(PLL_CTL);
+	p0.l = lo(PLL_CTL);		/* Load the address */
+	cli r2;				/* Disable interrupts */
+	ssync;
+	w[p0] = r0.l;			/* Set the value */
+	idle;				/* Wait for the PLL to stablize */
+	sti r2;				/* Enable interrupts */
+
+check_again:
+	p0.h = hi(PLL_STAT);
+	p0.l = lo(PLL_STAT);
+	R0 = W[P0](Z);
+	CC = BITTST(R0,5);
+	if ! CC jump check_again;
+
+	/* Configure SCLK & CCLK Dividers */
+	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+	p0.h = hi(PLL_DIV);
+	p0.l = lo(PLL_DIV);
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * We now are running at speed, time to set the Async mem bank wait states
+	 * This will speed up execution, since we are normally running from FLASH.
+	 */
+
+	p2.h = (EBIU_AMBCTL1 >> 16);
+	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+	r0.h = (AMBCTL1VAL >> 16);
+	r0.l = (AMBCTL1VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMBCTL0 >> 16);
+	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+	r0.h = (AMBCTL0VAL >> 16);
+	r0.l = (AMBCTL0VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+
+	p2.h = (EBIU_AMGCTL >> 16);
+	p2.l = (EBIU_AMGCTL & 0xffff);
+	r0 = AMGCTLVAL;
+	w[p2] = r0;
+	ssync;
+
+	/*
+	 * Now, Initialize the SDRAM,
+	 * start with the SDRAM Refresh Rate Control Register
+	 */
+	p0.l = lo(EBIU_SDRRC);
+	p0.h = hi(EBIU_SDRRC);
+	r0 = mem_SDRRC;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Memory Bank Control Register - bank specific parameters
+	 */
+	p0.l = (EBIU_SDBCTL & 0xFFFF);
+	p0.h = (EBIU_SDBCTL >> 16);
+	r0 = mem_SDBCTL;
+	w[p0] = r0.l;
+	ssync;
+
+	/*
+	 * SDRAM Global Control Register - global programmable parameters
+	 * Disable self-refresh
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITCLR (R0, 24);
+
+	/*
+	 * Check if SDRAM is already powered up, if it is, enable self-refresh
+	 */
+	p0.h = hi(EBIU_SDSTAT);
+	p0.l = lo(EBIU_SDSTAT);
+	r2.l = w[p0];
+	cc = bittst(r2,3);
+	if !cc jump skip;
+	NOP;
+	BITSET (R0, 23);
+skip:
+	[P2] = R0;
+	SSYNC;
+
+	/* Write in the new value in the register */
+	R0.L = lo(mem_SDGCTL);
+	R0.H = hi(mem_SDGCTL);
+	[P2] = R0;
+	SSYNC;
+	nop;
+
+
+	(P5:0) = [SP++];
+	(R7:0) = [SP++];
+	RETS   = [SP++];
+	ASTAT  = [SP++];
+	RTS;
diff --git a/cpu/bf561/interrupt.S b/cpu/bf561/interrupt.S
new file mode 100644
index 0000000..f82fd9b
--- /dev/null
+++ b/cpu/bf561/interrupt.S
@@ -0,0 +1,246 @@
+/*
+ * U-boot - interrupt.S Processing of interrupts and exception handling
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file is based on interrupt.S
+ *
+ * Copyright (C) 2003	Metrowerks, Inc. <mwaddel@metrowerks.com>
+ * Copyright (C) 2002	Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
+ * Copyright (C) 1998	D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ *			Kenneth Albanowski <kjahds@kjahds.com>,
+ *			The Silver Hammer Group, Ltd.
+ *
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * This file is also based on exception.asm
+ * (C) Copyright 2001-2005 - Analog Devices, Inc.  All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/hw_irq.h>
+#include <asm/entry.h>
+#include <asm/blackfin_defs.h>
+
+.global _blackfin_irq_panic;
+
+.text
+.align 2
+
+#ifndef CONFIG_KGDB
+.global _evt_emulation
+_evt_emulation:
+	SAVE_CONTEXT
+	r0 = IRQ_EMU;
+	r1 = seqstat;
+	sp += -12;
+	call _blackfin_irq_panic;
+	sp += 12;
+	rte;
+#endif
+
+.global _evt_nmi
+_evt_nmi:
+	SAVE_CONTEXT
+	r0 = IRQ_NMI;
+	r1 = RETN;
+	sp += -12;
+	call _blackfin_irq_panic;
+	sp += 12;
+
+_evt_nmi_exit:
+	rtn;
+
+.global _trap
+_trap:
+	SAVE_ALL_SYS
+	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
+	sp += -12;
+	call _trap_c
+	sp += 12;
+	RESTORE_ALL_SYS
+	rtx;
+
+.global _evt_rst
+_evt_rst:
+	SAVE_CONTEXT
+	r0 = IRQ_RST;
+	r1 = RETN;
+	sp += -12;
+	call _do_reset;
+	sp += 12;
+
+_evt_rst_exit:
+	rtn;
+
+irq_panic:
+	r0 = IRQ_EVX;
+	r1 =  sp;
+	sp += -12;
+	call _blackfin_irq_panic;
+	sp += 12;
+
+.global _evt_ivhw
+_evt_ivhw:
+	SAVE_CONTEXT
+	RAISE 14;
+
+_evt_ivhw_exit:
+	 rti;
+
+.global _evt_timer
+_evt_timer:
+	SAVE_CONTEXT
+	r0 = IRQ_CORETMR;
+	sp += -12;
+	/* Polling method used now. */
+	/* call timer_int; */
+	sp += 12;
+	RESTORE_CONTEXT
+	rti;
+	nop;
+
+.global _evt_evt7
+_evt_evt7:
+	SAVE_CONTEXT
+	r0 = 7;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt7_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global _evt_evt8
+_evt_evt8:
+	SAVE_CONTEXT
+	r0 = 8;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt8_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global _evt_evt9
+_evt_evt9:
+	SAVE_CONTEXT
+	r0 = 9;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt9_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global _evt_evt10
+_evt_evt10:
+	SAVE_CONTEXT
+	r0 = 10;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt10_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global _evt_evt11
+_evt_evt11:
+	SAVE_CONTEXT
+	r0 = 11;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt11_exit:
+	RESTORE_CONTEXT
+	rti;
+
+.global _evt_evt12
+_evt_evt12:
+	SAVE_CONTEXT
+	r0 = 12;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+evt_evt12_exit:
+	 RESTORE_CONTEXT
+	 rti;
+
+.global _evt_evt13
+_evt_evt13:
+	SAVE_CONTEXT
+	r0 = 13;
+	sp += -12;
+	call _process_int;
+	sp += 12;
+
+evt_evt13_exit:
+	 RESTORE_CONTEXT
+	 rti;
+
+.global _evt_system_call
+_evt_system_call:
+	[--sp] = r0;
+	[--SP] = RETI;
+	r0 = [sp++];
+	r0 += 2;
+	[--sp] = r0;
+	RETI = [SP++];
+	r0 = [SP++];
+	SAVE_CONTEXT
+	sp += -12;
+	call _exception_handle;
+	sp += 12;
+	RESTORE_CONTEXT
+	RTI;
+
+evt_system_call_exit:
+	rti;
+
+.global _evt_soft_int1
+_evt_soft_int1:
+	[--sp] = r0;
+	[--SP] = RETI;
+	r0 = [sp++];
+	r0 += 2;
+	[--sp] = r0;
+	RETI = [SP++];
+	r0 = [SP++];
+	SAVE_CONTEXT
+	sp += -12;
+	call _exception_handle;
+	sp += 12;
+	RESTORE_CONTEXT
+	RTI;
+
+evt_soft_int1_exit:
+	rti;
diff --git a/cpu/bf561/interrupts.c b/cpu/bf561/interrupts.c
new file mode 100644
index 0000000..e314f60
--- /dev/null
+++ b/cpu/bf561/interrupts.c
@@ -0,0 +1,171 @@
+/*
+ * U-boot - interrupts.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on interrupts.c
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
+ *			BuyWays B.V. (www.buyways.nl)
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/machdep.h>
+#include <asm/irq.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+static ulong timestamp;
+static ulong last_time;
+static int int_flag;
+
+int irq_flags;			/* needed by asm-blackfin/system.h */
+
+/* Functions just to satisfy the linker */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On BF561 it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On BF561 it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+	tbclk = CFG_HZ;
+	return tbclk;
+}
+
+void enable_interrupts(void)
+{
+	restore_flags(int_flag);
+}
+
+int disable_interrupts(void)
+{
+	save_and_cli(int_flag);
+	return 1;
+}
+
+int interrupt_init(void)
+{
+	return (0);
+}
+
+void udelay(unsigned long usec)
+{
+	unsigned long delay, start, stop;
+	unsigned long cclk;
+	cclk = (CONFIG_CCLK_HZ);
+
+	while (usec > 1) {
+		/*
+		 * how many clock ticks to delay?
+		 *  - request(in useconds) * clock_ticks(Hz) / useconds/second
+		 */
+		if (usec < 1000) {
+			delay = (usec * (cclk / 244)) >> 12;
+			usec = 0;
+		} else {
+			delay = (1000 * (cclk / 244)) >> 12;
+			usec -= 1000;
+		}
+
+		asm volatile (" %0 = CYCLES;":"=r" (start));
+		do {
+			asm volatile (" %0 = CYCLES; ":"=r" (stop));
+		} while (stop - start < delay);
+	}
+
+	return;
+}
+
+void timer_init(void)
+{
+	*pTCNTL = 0x1;
+	*pTSCALE = 0x0;
+	*pTCOUNT = MAX_TIM_LOAD;
+	*pTPERIOD = MAX_TIM_LOAD;
+	*pTCNTL = 0x7;
+	asm("CSYNC;");
+
+	timestamp = 0;
+	last_time = 0;
+}
+
+/*
+ * Any network command or flash
+ * command is started get_timer shall
+ * be called before TCOUNT gets reset,
+ * to implement the accurate timeouts.
+ *
+ * How ever milliconds doesn't return
+ * the number that has been elapsed from
+ * the last reset.
+ *
+ * As get_timer is used in the u-boot
+ * only for timeouts this should be
+ * sufficient
+ */
+ulong get_timer(ulong base)
+{
+	ulong milisec;
+
+	/* Number of clocks elapsed */
+	ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
+
+	/*
+	 * Find if the TCOUNT is reset
+	 * timestamp gives the number of times
+	 * TCOUNT got reset
+	 */
+	if (clocks < last_time)
+		timestamp++;
+	last_time = clocks;
+
+	/* Get the number of milliseconds */
+	milisec = clocks / (CONFIG_CCLK_HZ / 1000);
+
+	/*
+	 * Find the number of millisonds
+	 * that got elapsed before this TCOUNT
+	 * cycle
+	 */
+	milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
+
+	return (milisec - base);
+}
diff --git a/cpu/bf561/ints.c b/cpu/bf561/ints.c
new file mode 100644
index 0000000..328e5d8
--- /dev/null
+++ b/cpu/bf561/ints.c
@@ -0,0 +1,117 @@
+/*
+ * U-boot - ints.c Interrupt related routines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on ints.c
+ *
+ * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
+ *	drivers
+ *
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/stddef.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/traps.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/machdep.h>
+#include <asm/setup.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+void blackfin_irq_panic(int reason, struct pt_regs *regs)
+{
+	printf("\n\nException: IRQ 0x%x entered\n", reason);
+	printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
+	printf("stack frame=0x%x, ", (unsigned int)regs);
+	printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
+	dump(regs);
+	printf("Unhandled IRQ or exceptions!\n");
+	printf("Please reset the board \n");
+}
+
+void blackfin_init_IRQ(void)
+{
+	*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
+	cli();
+#ifndef CONFIG_KGDB
+	*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
+#endif
+	*(unsigned volatile long *)(EVT_NMI_ADDR) =
+	    (unsigned volatile long)evt_nmi;
+	*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
+	    (unsigned volatile long)trap;
+	*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
+	    (unsigned volatile long)evt_ivhw;
+	*(unsigned volatile long *)(EVT_RESET_ADDR) =
+	    (unsigned volatile long)evt_rst;
+	*(unsigned volatile long *)(EVT_TIMER_ADDR) =
+	    (unsigned volatile long)evt_timer;
+	*(unsigned volatile long *)(EVT_IVG7_ADDR) =
+	    (unsigned volatile long)evt_evt7;
+	*(unsigned volatile long *)(EVT_IVG8_ADDR) =
+	    (unsigned volatile long)evt_evt8;
+	*(unsigned volatile long *)(EVT_IVG9_ADDR) =
+	    (unsigned volatile long)evt_evt9;
+	*(unsigned volatile long *)(EVT_IVG10_ADDR) =
+	    (unsigned volatile long)evt_evt10;
+	*(unsigned volatile long *)(EVT_IVG11_ADDR) =
+	    (unsigned volatile long)evt_evt11;
+	*(unsigned volatile long *)(EVT_IVG12_ADDR) =
+	    (unsigned volatile long)evt_evt12;
+	*(unsigned volatile long *)(EVT_IVG13_ADDR) =
+	    (unsigned volatile long)evt_evt13;
+	*(unsigned volatile long *)(EVT_IVG14_ADDR) =
+	    (unsigned volatile long)evt_system_call;
+	*(unsigned volatile long *)(EVT_IVG15_ADDR) =
+	    (unsigned volatile long)evt_soft_int1;
+	*(volatile unsigned long *)ILAT = 0;
+	asm("csync;");
+	sti();
+	*(volatile unsigned long *)IMASK = 0xffbf;
+	asm("csync;");
+}
+
+void exception_handle(void)
+{
+#if defined (CONFIG_PANIC_HANG)
+	display_excp();
+#else
+	udelay(100000);		/* allow messages to go out */
+	do_reset(NULL, 0, 0, NULL);
+#endif
+}
+
+void display_excp(void)
+{
+	printf("Exception!\n");
+}
diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c
new file mode 100644
index 0000000..baec1d3
--- /dev/null
+++ b/cpu/bf561/serial.c
@@ -0,0 +1,196 @@
+/*
+ * U-boot - serial.c Serial driver for BF561
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
+ * Copyright (c) 2003	Bas Vermeulen <bas@buyways.nl>,
+ * 			BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on blkfinserial.c
+ * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
+ * Copyright(c) 2003	Metrowerks	<mwaddel@metrowerks.com>
+ * Copyright(c)	2001	Tony Z. Kou	<tonyko@arcturusnetworks.com>
+ * Copyright(c)	2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328 version serial driver imlpementation which was:
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/segment.h>
+#include <asm/bitops.h>
+#include <asm/delay.h>
+#include <asm/uaccess.h>
+#include "serial.h"
+#include <asm/io.h>
+
+unsigned long pll_div_fact;
+
+void calc_baud(void)
+{
+	unsigned char i;
+	int temp;
+	u_long sclk = get_sclk();
+
+	for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
+		temp = sclk / (baud_table[i] * 8);
+		if ((temp & 0x1) == 1) {
+			temp++;
+		}
+		temp = temp / 2;
+		hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
+		hw_baud_table[i].dl_low = (temp) & 0xFF;
+	}
+}
+
+void serial_setbrg(void)
+{
+	int i;
+	DECLARE_GLOBAL_DATA_PTR;
+
+	calc_baud();
+
+	for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
+		if (gd->baudrate == baud_table[i])
+			break;
+	}
+
+	/* Enable UART */
+	*pUART_GCTL |= UART_GCTL_UCEN;
+	sync();
+
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH;
+	sync();
+
+	*pUART_DLL = hw_baud_table[i].dl_low;
+	sync();
+	*pUART_DLH = hw_baud_table[i].dl_high;
+	sync();
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER;
+	sync();
+
+	/*
+	 * Enable  ERBFI and ELSI interrupts
+	 * to poll SIC_ISR register
+	 */
+	*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
+	sync();
+
+	/* Set LCR to Word Lengh 8-bit word select */
+	*pUART_LCR = UART_LCR_WLS8;
+	sync();
+
+	return;
+}
+
+int serial_init(void)
+{
+	serial_setbrg();
+	return (0);
+}
+
+void serial_putc(const char c)
+{
+	if ((*pUART_LSR) & UART_LSR_TEMT) {
+		if (c == '\n')
+			serial_putc('\r');
+
+		local_put_char(c);
+	}
+
+	while (!((*pUART_LSR) & UART_LSR_TEMT))
+		SYNC_ALL;
+
+	return;
+}
+
+int serial_tstc(void)
+{
+	if (*pUART_LSR & UART_LSR_DR)
+		return 1;
+	else
+		return 0;
+}
+
+int serial_getc(void)
+{
+	unsigned short uart_lsr_val, uart_rbr_val;
+	unsigned long isr_val;
+	int ret;
+
+	/* Poll for RX Interrupt */
+	while (!((isr_val =
+		  *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
+	asm("csync;");
+
+	uart_lsr_val = *pUART_LSR;	/* Clear status bit */
+	uart_rbr_val = *pUART_RBR;	/* getc() */
+
+	if (isr_val & IRQ_UART_ERROR_BIT) {
+		ret = -1;
+	} else {
+		ret = uart_rbr_val & 0xff;
+	}
+
+	return ret;
+}
+
+void serial_puts(const char *s)
+{
+	while (*s) {
+		serial_putc(*s++);
+	}
+}
+
+static void local_put_char(char ch)
+{
+	int flags = 0;
+	unsigned long isr_val;
+
+	save_and_cli(flags);
+
+	/* Poll for TX Interruput */
+	while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
+	asm("csync;");
+
+	*pUART_THR = ch;	/* putc() */
+
+	if (isr_val & IRQ_UART_ERROR_BIT) {
+		printf("?");
+	}
+
+	restore_flags(flags);
+
+	return;
+}
diff --git a/cpu/bf561/serial.h b/cpu/bf561/serial.h
new file mode 100644
index 0000000..98c1242
--- /dev/null
+++ b/cpu/bf561/serial.h
@@ -0,0 +1,77 @@
+/*
+ * U-boot - bf561_serial.h Serial Driver defines
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
+ * Copyright (C) 2003	Bas Vermeulen <bas@buyways.nl>
+ * 			BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.h: Definitions for the BlackFin DSP serial driver.
+ *
+ * Copyright (C) 2001	Tony Z. Kou	tonyko@arcturusnetworks.com
+ * Copyright (C) 2001   Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328serial.c which was:
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _Bf561_SERIAL_H
+#define _Bf561_SERIAL_H
+
+#include <linux/config.h>
+#include <asm/blackfin.h>
+
+#define SYNC_ALL	__asm__ __volatile__ ("ssync;\n")
+#define ACCESS_LATCH	*pUART_LCR |= UART_LCR_DLAB;
+#define ACCESS_PORT_IER	*pUART_LCR &= (~UART_LCR_DLAB);
+
+void serial_setbrg(void);
+static void local_put_char(char ch);
+void calc_baud(void);
+void serial_setbrg(void);
+int serial_init(void);
+void serial_putc(const char c);
+int serial_tstc(void);
+int serial_getc(void);
+void serial_puts(const char *s);
+static void local_put_char(char ch);
+
+int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
+
+struct {
+	unsigned char dl_high;
+	unsigned char dl_low;
+} hw_baud_table[5];
+
+#ifdef CONFIG_STAMP
+extern unsigned long pll_div_fact;
+#endif
+
+#endif
diff --git a/cpu/bf561/start.S b/cpu/bf561/start.S
new file mode 100644
index 0000000..9333648
--- /dev/null
+++ b/cpu/bf561/start.S
@@ -0,0 +1,311 @@
+/*
+ * U-boot - start.S Startup file of u-boot for BF533/BF561
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on head.S
+ * Copyright (c) 2003  Metrowerks/Motorola
+ * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ *		       Kenneth Albanowski <kjahds@kjahds.com>,
+ *		       The Silver Hammer Group, Ltd.
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Note: A change in this file subsequently requires a change in
+ *       board/$(board_name)/config.mk for a valid u-boot.bin
+ */
+
+#define ASSEMBLY
+
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.global _stext;
+.global __bss_start;
+.global start;
+.global _start;
+.global _rambase;
+.global _ramstart;
+.global _ramend;
+.global edata;
+.global _initialize;
+.global _exit;
+.global flashdataend;
+.global init_sdram;
+
+.text
+_start:
+start:
+_stext:
+
+	R0 = 0x32;
+	SYSCFG = R0;
+	SSYNC;
+
+	/*
+	 * As per HW reference manual DAG registers,
+	 * DATA and Address resgister shall be zero'd
+	 * in initialization, after a reset state
+	 */
+	r1 = 0;	/* Data registers zero'd */
+	r2 = 0;
+	r3 = 0;
+	r4 = 0;
+	r5 = 0;
+	r6 = 0;
+	r7 = 0;
+
+	p0 = 0; /* Address registers zero'd */
+	p1 = 0;
+	p2 = 0;
+	p3 = 0;
+	p4 = 0;
+	p5 = 0;
+
+	i0 = 0; /* DAG Registers zero'd */
+	i1 = 0;
+	i2 = 0;
+	i3 = 0;
+	m0 = 0;
+	m1 = 0;
+	m3 = 0;
+	m3 = 0;
+	l0 = 0;
+	l1 = 0;
+	l2 = 0;
+	l3 = 0;
+	b0 = 0;
+	b1 = 0;
+	b2 = 0;
+	b3 = 0;
+
+	/*
+	 * Set loop counters to zero, to make sure that
+	 * hw loops are disabled.
+	 */
+	r0  = 0;
+	lc0 = r0;
+	lc1 = r0;
+
+	SSYNC;
+
+	/* Check soft reset status */
+	p0.h = SWRST >> 16;
+	p0.l = SWRST & 0xFFFF;
+	r0.l = w[p0];
+
+	cc = bittst(r0, 15);
+	if !cc jump no_soft_reset;
+
+	/* Clear Soft reset */
+	r0 = 0x0000;
+	w[p0] = r0;
+	ssync;
+
+no_soft_reset:
+	nop;
+
+	/* Clear EVT registers */
+	p0.h = (EVT_EMULATION_ADDR >> 16);
+	p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
+	p0 += 8;
+	p1 = 14;
+	r1 = 0;
+	LSETUP(4,4) lc0 = p1;
+	[ p0 ++ ] = r1;
+
+	p0.h = hi(SIC_IWR);
+	p0.l = lo(SIC_IWR);
+	r0.l = 0x1;
+	w[p0] = r0.l;
+	SSYNC;
+
+	sp.l = (0xffb01000 & 0xFFFF);
+	sp.h = (0xffb01000 >> 16);
+
+	/*
+	 * Check if the code is in SDRAM
+	 * If the code is in SDRAM, skip SDRAM initializaiton
+	 */
+	call get_pc;
+	r3.l = 0x0;
+	r3.h = 0x2000;
+	cc = r0 < r3 (iu);
+	if cc jump sdram_initialized;
+	call init_sdram;
+	/* relocate into to RAM */
+sdram_initialized:
+	call get_pc;
+offset:
+	r2.l = offset;
+	r2.h = offset;
+	r3.l = start;
+	r3.h = start;
+	r1 = r2 - r3;
+
+	r0 = r0 - r1;
+	p1 = r0;
+
+	p2.l = (CFG_MONITOR_BASE & 0xffff);
+	p2.h = (CFG_MONITOR_BASE >> 16);
+
+	p3 = 0x04;
+	p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
+	p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
+loop1:
+	r1 = [p1 ++ p3];
+	[p2 ++ p3] = r1;
+	cc=p2==p4;
+	if !cc jump loop1;
+	/*
+	 * configure STACK
+	 */
+	r0.h = (CONFIG_STACKBASE >> 16);
+	r0.l = (CONFIG_STACKBASE & 0xFFFF);
+	sp = r0;
+	fp = sp;
+
+	/*
+	 * This next section keeps the processor in supervisor mode
+	 * during kernel boot.  Switches to user mode at end of boot.
+	 * See page 3-9 of Hardware Reference manual for documentation.
+	 */
+
+	/* To keep ourselves in the supervisor mode */
+	p0.l = (EVT_IVG15_ADDR & 0xFFFF);
+	p0.h = (EVT_IVG15_ADDR >> 16);
+
+	p1.l = _real_start;
+	p1.h = _real_start;
+	[p0] = p1;
+
+	p0.l = (IMASK & 0xFFFF);
+	p0.h = (IMASK >> 16);
+	r0.l = LO(IVG15_POS);
+	r0.h = HI(IVG15_POS);
+	[p0] = r0;
+	raise 15;
+	p0.l = WAIT_HERE;
+	p0.h = WAIT_HERE;
+	reti = p0;
+	rti;
+
+WAIT_HERE:
+	jump WAIT_HERE;
+
+.global _real_start;
+_real_start:
+	[ -- sp ] = reti;
+
+#ifdef CONFIG_EZKIT561
+	p0.l = (WDOG_CTL & 0xFFFF);
+	p0.h = (WDOG_CTL >> 16);
+	r0 = WATCHDOG_DISABLE(z);
+	w[p0] = r0;
+#endif
+
+	/* DMA reset code to Hi of L1 SRAM */
+copy:
+	P1.H = hi(SYSMMR_BASE);	/* P1 Points to the beginning of SYSTEM MMR Space */
+	P1.L = lo(SYSMMR_BASE);
+
+	R0.H = reset_start;	/* Source Address (high) */
+	R0.L = reset_start;	/* Source Address (low) */
+	R1.H = reset_end;
+	R1.L = reset_end;
+	R2 = R1 - R0;		/* Count */
+	R1.H = hi(L1_ISRAM);	/* Destination Address (high) */
+	R1.L = lo(L1_ISRAM);	/* Destination Address (low) */
+	R3.L = DMAEN;		/* Source DMAConfig Value (8-bit words) */
+	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
+
+DMA:
+	R6 = 0x1 (Z);
+	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
+	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
+
+	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
+	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
+	/* Set Source  DMAConfig = DMA Enable,
+	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
+	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+
+	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
+	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
+	/* Set Destination DMAConfig = DMA Enable,
+	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
+	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+
+WAIT_DMA_DONE:
+	p0.h = hi(MDMA_D0_IRQ_STATUS);
+	p0.l = lo(MDMA_D0_IRQ_STATUS);
+	R0 = W[P0](Z);
+	CC = BITTST(R0, 0);
+	if ! CC jump WAIT_DMA_DONE
+
+	R0 = 0x1;
+	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
+
+	/* Initialize BSS Section with 0 s */
+	p1.l = __bss_start;
+	p1.h = __bss_start;
+	p2.l = _end;
+	p2.h = _end;
+	r1 = p1;
+	r2 = p2;
+	r3 = r2 - r1;
+	r3 = r3 >> 2;
+	p3 = r3;
+	lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
+	CC = p2<=p1;
+	if CC jump _clear_bss_skip;
+	r0 = 0;
+_clear_bss:
+_clear_bss_end:
+	[p1++] = r0;
+_clear_bss_skip:
+
+	p0.l = _start1;
+	p0.h = _start1;
+	jump (p0);
+
+reset_start:
+	p0.h = WDOG_CNT >> 16;
+	p0.l = WDOG_CNT & 0xffff;
+	r0 = 0x0010;
+	w[p0] = r0;
+	p0.h = WDOG_CTL >> 16;
+	p0.l = WDOG_CTL & 0xffff;
+	r0 = 0x0000;
+	w[p0] = r0;
+reset_wait:
+	jump reset_wait;
+
+reset_end: nop;
+
+_exit:
+	jump.s	_exit;
+get_pc:
+	r0 = rets;
+	rts;
diff --git a/cpu/bf561/start1.S b/cpu/bf561/start1.S
new file mode 100644
index 0000000..72cfafb
--- /dev/null
+++ b/cpu/bf561/start1.S
@@ -0,0 +1,38 @@
+/*
+ * U-boot - start1.S Code running out of RAM after relocation
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ASSEMBLY
+#include <linux/config.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.global	start1;
+.global	_start1;
+
+.text
+_start1:
+start1:
+	sp += -12;
+	call	_board_init_f;
+	sp += 12;
diff --git a/cpu/bf561/traps.c b/cpu/bf561/traps.c
new file mode 100644
index 0000000..f5ff3a8
--- /dev/null
+++ b/cpu/bf561/traps.c
@@ -0,0 +1,239 @@
+/*
+ * U-boot - traps.c Routines related to interrupts and exceptions
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * No original Copyright holder listed,
+ * Probabily original (C) Roman Zippel (assigned DJD, 1999)
+ *
+ * Copyright 2003 Metrowerks - for Blackfin
+ * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
+ * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/errno.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+#include <asm/machdep.h>
+#include "cpu.h"
+#include <asm/arch/anomaly.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
+
+void init_IRQ(void)
+{
+	blackfin_init_IRQ();
+	return;
+}
+
+void process_int(unsigned long vec, struct pt_regs *fp)
+{
+	printf("interrupt\n");
+	return;
+}
+
+extern unsigned int icplb_table[page_descriptor_table_size][2];
+extern unsigned int dcplb_table[page_descriptor_table_size][2];
+
+unsigned long last_cplb_fault_retx;
+
+static unsigned int cplb_sizes[4] =
+    { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
+
+void trap_c(struct pt_regs *regs)
+{
+	unsigned int addr;
+	unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
+	unsigned int i, j, size, *I0, *I1;
+	unsigned short data = 0;
+
+	switch (trapnr) {
+		/* 0x26 - Data CPLB Miss */
+	case VEC_CPLB_M:
+
+#ifdef ANOMALY_05000261
+		/*
+		 * Work around an anomaly: if we see a new DCPLB fault, return
+		 * without doing anything.  Then, if we get the same fault again,
+		 * handle it.
+		 */
+		addr = last_cplb_fault_retx;
+		last_cplb_fault_retx = regs->retx;
+		printf("this time, curr = 0x%08x last = 0x%08x\n", addr,
+		       last_cplb_fault_retx);
+		if (addr != last_cplb_fault_retx)
+			goto trap_c_return;
+#endif
+		data = 1;
+
+	case VEC_CPLB_I_M:
+
+		if (data)
+			addr = *pDCPLB_FAULT_ADDR;
+		else
+			addr = *pICPLB_FAULT_ADDR;
+
+		for (i = 0; i < page_descriptor_table_size; i++) {
+			if (data) {
+				size = cplb_sizes[dcplb_table[i][1] >> 16];
+				j = dcplb_table[i][0];
+			} else {
+				size = cplb_sizes[icplb_table[i][1] >> 16];
+				j = icplb_table[i][0];
+			}
+			if ((j <= addr) && ((j + size) > addr)) {
+				debug("found %i 0x%08x\n", i, j);
+				break;
+			}
+		}
+		if (i == page_descriptor_table_size) {
+			printf("something is really wrong\n");
+			do_reset(NULL, 0, 0, NULL);
+		}
+
+		/* Turn the cache off */
+		if (data) {
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)DMEM_CONTROL &=
+			    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+			sync();
+		} else {
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
+			sync();
+		}
+
+		if (data) {
+			I0 = (unsigned int *)DCPLB_ADDR0;
+			I1 = (unsigned int *)DCPLB_DATA0;
+		} else {
+			I0 = (unsigned int *)ICPLB_ADDR0;
+			I1 = (unsigned int *)ICPLB_DATA0;
+		}
+
+		j = 0;
+		while (*I1 & CPLB_LOCK) {
+			debug("skipping %i %08p - %08x\n", j, I1, *I1);
+			*I0++;
+			*I1++;
+			j++;
+		}
+
+		debug("remove %i 0x%08x  0x%08x\n", j, *I0, *I1);
+
+		for (; j < 15; j++) {
+			debug("replace %i 0x%08x  0x%08x\n", j, I0, I0 + 1);
+			*I0++ = *(I0 + 1);
+			*I1++ = *(I1 + 1);
+		}
+
+		if (data) {
+			*I0 = dcplb_table[i][0];
+			*I1 = dcplb_table[i][1];
+			I0 = (unsigned int *)DCPLB_ADDR0;
+			I1 = (unsigned int *)DCPLB_DATA0;
+		} else {
+			*I0 = icplb_table[i][0];
+			*I1 = icplb_table[i][1];
+			I0 = (unsigned int *)ICPLB_ADDR0;
+			I1 = (unsigned int *)ICPLB_DATA0;
+		}
+
+		for (j = 0; j < 16; j++) {
+			debug("%i 0x%08x  0x%08x\n", j, *I0++, *I1++);
+		}
+
+		/* Turn the cache back on */
+		if (data) {
+			j = *(unsigned int *)DMEM_CONTROL;
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)DMEM_CONTROL =
+			    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
+			sync();
+		} else {
+			sync();
+			asm(" .align 8; ");
+			*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
+			sync();
+		}
+
+		break;
+	default:
+		/* All traps come here */
+		printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
+		printf("stack frame=0x%x, ", (unsigned int)regs);
+		printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
+		dump(regs);
+		printf("\n\n");
+
+		printf("Unhandled IRQ or exceptions!\n");
+		printf("Please reset the board \n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+trap_c_return:
+	return;
+
+}
+
+void dump(struct pt_regs *fp)
+{
+	debug("RETE:  %08lx  RETN: %08lx  RETX: %08lx  RETS: %08lx\n", fp->rete,
+	      fp->retn, fp->retx, fp->rets);
+	debug("IPEND: %04lx  SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
+	debug("SEQSTAT: %08lx    SP: %08lx\n", (long)fp->seqstat, (long)fp);
+	debug("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n", fp->r0,
+	      fp->r1, fp->r2, fp->r3);
+	debug("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n", fp->r4,
+	      fp->r5, fp->r6, fp->r7);
+	debug("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n", fp->p0,
+	      fp->p1, fp->p2, fp->p3);
+	debug("P4: %08lx    P5: %08lx    FP: %08lx\n", fp->p4, fp->p5, fp->fp);
+	debug("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
+	      fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+
+	debug("LB0: %08lx  LT0: %08lx  LC0: %08lx\n", fp->lb0, fp->lt0,
+	      fp->lc0);
+	debug("LB1: %08lx  LT1: %08lx  LC1: %08lx\n", fp->lb1, fp->lt1,
+	      fp->lc1);
+	debug("B0: %08lx  L0: %08lx  M0: %08lx  I0: %08lx\n", fp->b0, fp->l0,
+	      fp->m0, fp->i0);
+	debug("B1: %08lx  L1: %08lx  M1: %08lx  I1: %08lx\n", fp->b1, fp->l1,
+	      fp->m1, fp->i1);
+	debug("B2: %08lx  L2: %08lx  M2: %08lx  I2: %08lx\n", fp->b2, fp->l2,
+	      fp->m2, fp->i2);
+	debug("B3: %08lx  L3: %08lx  M3: %08lx  I3: %08lx\n", fp->b3, fp->l3,
+	      fp->m3, fp->i3);
+
+	debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
+	debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
+
+}
diff --git a/cpu/bf561/video.c b/cpu/bf561/video.c
new file mode 100644
index 0000000..3ff0151
--- /dev/null
+++ b/cpu/bf561/video.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ * (C) Copyright 2002
+ * Wolfgang Denk, wd@denx.de
+ * (C) Copyright 2006
+ * Aubrey Li, aubrey.li@analog.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <devices.h>
+
+#ifdef CONFIG_VIDEO
+#define NTSC_FRAME_ADDR 0x06000000
+#include "video.h"
+
+/* NTSC OUTPUT SIZE  720 * 240 */
+#define VERTICAL	2
+#define HORIZONTAL	4
+
+int is_vblank_line(const int line)
+{
+	/*
+	 *  This array contains a single bit for each line in
+	 *  an NTSC frame.
+	 */
+	if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
+		return true;
+
+	return false;
+}
+
+int NTSC_framebuffer_init(char *base_address)
+{
+	const int NTSC_frames = 1;
+	const int NTSC_lines = 525;
+	char *dest = base_address;
+	int frame_num, line_num;
+
+	for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
+		for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
+			unsigned int code;
+			int offset = 0;
+			int i;
+
+			if (is_vblank_line(line_num))
+				offset++;
+
+			if (line_num > 266 || line_num < 3)
+				offset += 2;
+
+			/* Output EAV code */
+			code = SystemCodeMap[offset].EAV;
+			write_dest_byte((char)(code >> 24) & 0xff);
+			write_dest_byte((char)(code >> 16) & 0xff);
+			write_dest_byte((char)(code >> 8) & 0xff);
+			write_dest_byte((char)(code) & 0xff);
+
+			/* Output horizontal blanking */
+			for (i = 0; i < 67 * 2; ++i) {
+				write_dest_byte(0x80);
+				write_dest_byte(0x10);
+			}
+
+			/* Output SAV */
+			code = SystemCodeMap[offset].SAV;
+			write_dest_byte((char)(code >> 24) & 0xff);
+			write_dest_byte((char)(code >> 16) & 0xff);
+			write_dest_byte((char)(code >> 8) & 0xff);
+			write_dest_byte((char)(code) & 0xff);
+
+			/* Output empty horizontal data */
+			for (i = 0; i < 360 * 2; ++i) {
+				write_dest_byte(0x80);
+				write_dest_byte(0x10);
+			}
+		}
+	}
+
+	return dest - base_address;
+}
+
+void fill_frame(char *Frame, int Value)
+{
+	int *OddPtr32;
+	int OddLine;
+	int *EvenPtr32;
+	int EvenLine;
+	int i;
+	int *data;
+	int m, n;
+
+	/* fill odd and even frames */
+	for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
+		OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
+		EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
+		for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
+			*OddPtr32 = Value;
+			*EvenPtr32 = Value;
+		}
+	}
+
+	for (m = 0; m < VERTICAL; m++) {
+		data = (int *)u_boot_logo.data;
+		for (OddLine = (22 + m), EvenLine = (285 + m);
+		     OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
+		     OddLine += VERTICAL, EvenLine += VERTICAL) {
+			OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
+			EvenPtr32 =
+			    (int *)((Frame + ((EvenLine) * 1716)) + 276);
+			for (i = 0; i < u_boot_logo.width / 2; i++) {
+				/* enlarge one pixel to m x n */
+				for (n = 0; n < HORIZONTAL; n++) {
+					*OddPtr32++ = *data;
+					*EvenPtr32++ = *data;
+				}
+				data++;
+			}
+		}
+	}
+}
+
+void video_putc(const char c)
+{
+}
+
+void video_puts(const char *s)
+{
+}
+
+static int video_init(void)
+{
+	char *NTSCFrame;
+	NTSCFrame = (char *)NTSC_FRAME_ADDR;
+	NTSC_framebuffer_init(NTSCFrame);
+	fill_frame(NTSCFrame, BLUE);
+
+	*pPPI_CONTROL = 0x0082;
+	*pPPI_FRAME = 0x020D;
+
+	*pDMA0_START_ADDR = NTSCFrame;
+	*pDMA0_X_COUNT = 0x035A;
+	*pDMA0_X_MODIFY = 0x0002;
+	*pDMA0_Y_COUNT = 0x020D;
+	*pDMA0_Y_MODIFY = 0x0002;
+	*pDMA0_CONFIG = 0x1015;
+	*pPPI_CONTROL = 0x0083;
+	return 0;
+}
+
+int drv_video_init(void)
+{
+	int error, devices = 1;
+
+	device_t videodev;
+
+	video_init();		/* Video initialization */
+
+	memset(&videodev, 0, sizeof(videodev));
+
+	strcpy(videodev.name, "video");
+	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
+	videodev.flags = DEV_FLAGS_OUTPUT;	/* Output only */
+	videodev.putc = video_putc;	/* 'putc' function */
+	videodev.puts = video_puts;	/* 'puts' function */
+
+	error = device_register(&videodev);
+
+	return (error == 0) ? devices : error;
+}
+#endif
diff --git a/cpu/bf561/video.h b/cpu/bf561/video.h
new file mode 100644
index 0000000..d237f6a
--- /dev/null
+++ b/cpu/bf561/video.h
@@ -0,0 +1,25 @@
+#include <video_logo.h>
+#define write_dest_byte(val) {*dest++=val;}
+#define BLACK   (0x01800180)	/* black pixel pattern  */
+#define BLUE    (0x296E29F0)	/* blue pixel pattern   */
+#define RED     (0x51F0515A)	/* red pixel pattern    */
+#define MAGENTA (0x6ADE6ACA)	/* magenta pixel pattern */
+#define GREEN   (0x91229136)	/* green pixel pattern  */
+#define CYAN    (0xAA10AAA6)	/* cyan pixel pattern   */
+#define YELLOW  (0xD292D210)	/* yellow pixel pattern */
+#define WHITE   (0xFE80FE80)	/* white pixel pattern  */
+
+#define true 	1
+#define false	0
+
+typedef struct {
+	unsigned int SAV;
+	unsigned int EAV;
+} SystemCodeType;
+
+const SystemCodeType SystemCodeMap[4] = {
+	{0xFF000080, 0xFF00009D},
+	{0xFF0000AB, 0xFF0000B6},
+	{0xFF0000C7, 0xFF0000DA},
+	{0xFF0000EC, 0xFF0000F1}
+};
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index aa6b2bd..ce59d39 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -49,11 +49,43 @@
 #endif
 
 #ifdef	CONFIG_M5271
+/*
+ * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
+ * determine which one we are running on, based on the Chip Identification
+ * Register (CIR).
+ */
 int checkcpu (void)
 {
 	char buf[32];
+	unsigned short cir;	/* Chip Identification Register */
+	unsigned short pin;	/* Part identification number */
+	unsigned char prn;	/* Part revision number */
+	char *cpu_model;
+
+	cir = mbar_readShort(MCF_CCM_CIR);
+	pin = cir >> MCF_CCM_CIR_PIN_LEN;
+	prn = cir & MCF_CCM_CIR_PRN_MASK;
+
+	switch (pin) {
+	case MCF_CCM_CIR_PIN_MCF5270:
+		cpu_model = "5270";
+		break;
+	case MCF_CCM_CIR_PIN_MCF5271:
+		cpu_model = "5271";
+		break;
+	default:
+		cpu_model = NULL;
+		break;
+	}
+
+	if (cpu_model)
+		printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
+			cpu_model, prn, strmhz(buf, CFG_CLK));
+	else
+		printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
+			" (PIN: 0x%x) rev. %hu, at %s MHz\n",
+			pin, prn, strmhz(buf, CFG_CLK));
 
-	printf ("CPU:   Freescale Coldfire MCF5271 at %s MHz\n", strmhz(buf, CFG_CLK));
 	return 0;
 }
 
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index f1f4077..7c9a7d2 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -140,11 +140,11 @@ _start:
 	move.l	#(CFG_MBAR + 1), %d0		/* set IPSBAR address + valid flag */
 	move.l	%d0, 0x40000000
 
-#if defined(CONFIG_M5282)
 	/* Initialize RAMBAR1: locate SRAM and validate it */
 	move.l	#(CFG_INIT_RAM_ADDR + 0x21), %d0
 	movec	%d0, %RAMBAR1
 
+#if defined(CONFIG_M5282)
 #if (TEXT_BASE == CFG_INT_FLASH_BASE)
 	/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
 
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index 6b6f828..813aa79 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -31,6 +31,10 @@
 #include <mpc5xxx.h>
 #include <asm/processor.h>
 
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int checkcpu (void)
@@ -102,3 +106,26 @@ unsigned long get_tbclk (void)
 }
 
 /* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_OF_FLAT_TREE
+void
+ft_cpu_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+	/* Core XLB bus frequency */
+	p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
+	if (p != NULL)
+		*p = cpu_to_be32(bd->bi_busfreq);
+
+	/* SOC peripherals use the IPB bus frequency */
+	p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
+	if (p != NULL)
+		*p = cpu_to_be32(bd->bi_ipbfreq);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+}
+#endif
diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index b7e00b3..7e65821 100644
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -123,7 +123,7 @@ void cpu_init_f (void)
 #endif
 
 #if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
-	*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
+	*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
 	*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
 	addecr |= (1 << 27);
 #endif
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index 37fe3e7..13a3870 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -376,7 +376,7 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 
 #if (DEBUG & 0x2)
 	if (fec->xcv_type != SEVENWIRE)
-		mpc5xxx_fec_phydump ();
+		mpc5xxx_fec_phydump (dev->name);
 #endif
 
 	/*
@@ -575,7 +575,7 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
 
 #if (DEBUG & 0x2)
 	if (fec->xcv_type != SEVENWIRE)
-		mpc5xxx_fec_phydump ();
+		mpc5xxx_fec_phydump (dev->name);
 #endif
 
 	/*
@@ -878,11 +878,13 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 	fec->eth = (ethernet_regs *)MPC5XXX_FEC;
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
 	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#if defined(CONFIG_CANMB)   || defined(CONFIG_HMI1001)	|| \
-    defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0)	|| \
-    defined(CONFIG_MCC200)  || defined(CONFIG_O2DNT)	|| \
-    defined(CONFIG_PM520)   || defined(CONFIG_TOP5200)	|| \
-    defined(CONFIG_TQM5200) || defined(CONFIG_V38B)
+#if defined(CONFIG_CANMB)    || defined(CONFIG_HMI1001)	|| \
+    defined(CONFIG_ICECUBE)  || defined(CONFIG_INKA4X0)	|| \
+    defined(CONFIG_JUPITER)  || defined(CONFIG_MCC200)	|| \
+    defined(CONFIG_MOTIONPRO)|| defined(CONFIG_O2DNT)	|| \
+    defined(CONFIG_PM520)    || defined(CONFIG_TOP5200)	|| \
+    defined(CONFIG_TQM5200)  || defined(CONFIG_UC101)	|| \
+    defined(CONFIG_V38B)
 # ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
 # else
diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c
index 4f23012..94651dc 100644
--- a/cpu/mpc8260/cpu.c
+++ b/cpu/mpc8260/cpu.c
@@ -49,6 +49,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_GET_CPU_STR_F)
+extern int get_cpu_str_f (char *buf);
+#endif
+
 int checkcpu (void)
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
@@ -81,7 +85,12 @@ int checkcpu (void)
 	if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
 		return -1;	/* whoops! someone moved the IMMR */
 
+#if defined(CONFIG_GET_CPU_STR_F)
+	get_cpu_str_f (buf);
+	printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
+#else
 	printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
+#endif
 
 	/*
 	 * the bottom 16 bits of the immr are the Part Number and Mask Number
diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c
index 640026b..380d7af 100644
--- a/cpu/mpc8260/cpu_init.c
+++ b/cpu/mpc8260/cpu_init.c
@@ -28,6 +28,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+extern unsigned long board_get_cpu_clk_f (void);
+#endif
+
 static void config_8260_ioports (volatile immap_t * immr)
 {
 	int portnum;
@@ -90,6 +94,7 @@ static void config_8260_ioports (volatile immap_t * immr)
 	}
 }
 
+#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
 /*
  * Breath some life into the CPU...
  *
@@ -102,6 +107,9 @@ void cpu_init_f (volatile immap_t * immr)
 #if !defined(CONFIG_COGENT)		/* done in start.S for the cogent */
 	uint sccr;
 #endif
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+	unsigned long cpu_clk;
+#endif
 	volatile memctl8260_t *memctl = &immr->im_memctl;
 	extern void m8260_cpm_reset (void);
 
@@ -119,10 +127,27 @@ void cpu_init_f (volatile immap_t * immr)
 	immr->im_clkrst.car_rmr = CFG_RMR;
 
 	/* BCR - Bus Configuration Register (4-25) */
+#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE)
+	if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
+		immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_60x, 0x80000010);
+	} else {
+		immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_SINGLE, 0x80000010);
+	}
+#else
 	immr->im_siu_conf.sc_bcr = CFG_BCR;
+#endif
 
 	/* SIUMCR - contains debug pin configuration (4-31) */
+#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH)
+	cpu_clk = board_get_cpu_clk_f ();
+	if (cpu_clk >= 100000000) {
+		immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_HIGH, 0x9f3cc000);
+	} else {
+		immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_LOW, 0x9f3cc000);
+	}
+#else
 	immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
+#endif
 
 	config_8260_ioports (immr);
 
@@ -157,7 +182,8 @@ void cpu_init_f (volatile immap_t * immr)
 #endif
 
 	/* now restrict to preliminary range */
-	memctl->memc_br0 = CFG_BR0_PRELIM;
+	/* the PS came from the HRCW, don´t change it */
+	memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK);
 	memctl->memc_or0 = CFG_OR0_PRELIM;
 
 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index b14fc15..75c6ab2 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -274,7 +274,8 @@ void pci_mpc8250_init (struct pci_controller *hose)
 				  | SIUMCR_CS10PC00
 				  | SIUMCR_BCTLC00
 				  | SIUMCR_MMR11;
-
+#elif defined(CONFIG_TQM8272)
+/* nothing to do for this Board here */
 #else
 	/*
 	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c
index 360404f..38cd0d9 100644
--- a/cpu/mpc8260/speed.c
+++ b/cpu/mpc8260/speed.c
@@ -25,6 +25,10 @@
 #include <mpc8260.h>
 #include <asm/processor.h>
 
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+extern unsigned long board_get_cpu_clk_f (void);
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /* ------------------------------------------------------------------------- */
@@ -112,8 +116,12 @@ int get_clocks (void)
 #if !defined(CONFIG_8260_CLKIN)
 #error clock measuring not implemented yet - define CONFIG_8260_CLKIN
 #else
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+	clkin = board_get_cpu_clk_f ();
+#else
 	clkin = CONFIG_8260_CLKIN;
 #endif
+#endif
 
 	sccr = immap->im_clkrst.car_sccr;
 	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
index b2a6b3e..4b9dcc8 100644
--- a/cpu/mpc83xx/Makefile
+++ b/cpu/mpc83xx/Makefile
@@ -27,9 +27,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).a
 
-START	= start.o resetvec.o
+START	= start.o
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o \
-	  i2c.o spd_sdram.o
+	  spd_sdram.o qe_io.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 20bba6c..e4bc405 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -18,11 +18,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
- * Change log:
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- *	     Initial file creating (porting from 85XX & 8260)
  */
 
 /*
@@ -43,35 +38,169 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int checkcpu(void)
 {
+	volatile immap_t *immr;
 	ulong clock = gd->cpu_clk;
 	u32 pvr = get_pvr();
+	u32 spridr;
 	char buf[32];
 
+	immr = (immap_t *)CFG_IMMR;
+
 	if ((pvr & 0xFFFF0000) != PVR_83xx) {
 		puts("Not MPC83xx Family!!!\n");
 		return -1;
 	}
 
-	puts("CPU:   MPC83xx, ");
-	switch(pvr) {
-	case PVR_8349_REV10:
+	spridr = immr->sysconf.spridr;
+	puts("CPU: ");
+	switch(spridr) {
+	case SPR_8349E_REV10:
+	case SPR_8349E_REV11:
+	case SPR_8349E_REV31:
+		puts("MPC8349E, ");
+		break;
+	case SPR_8349_REV10:
+	case SPR_8349_REV11:
+	case SPR_8349_REV31:
+		puts("MPC8349, ");
+		break;
+	case SPR_8347E_REV10_TBGA:
+	case SPR_8347E_REV11_TBGA:
+	case SPR_8347E_REV31_TBGA:
+	case SPR_8347E_REV10_PBGA:
+	case SPR_8347E_REV11_PBGA:
+	case SPR_8347E_REV31_PBGA:
+		puts("MPC8347E, ");
+		break;
+	case SPR_8347_REV10_TBGA:
+	case SPR_8347_REV11_TBGA:
+	case SPR_8347_REV31_TBGA:
+	case SPR_8347_REV10_PBGA:
+	case SPR_8347_REV11_PBGA:
+	case SPR_8347_REV31_PBGA:
+		puts("MPC8347, ");
+		break;
+	case SPR_8343E_REV10:
+	case SPR_8343E_REV11:
+	case SPR_8343E_REV31:
+		puts("MPC8343E, ");
+		break;
+	case SPR_8343_REV10:
+	case SPR_8343_REV11:
+	case SPR_8343_REV31:
+		puts("MPC8343, ");
+		break;
+	case SPR_8360E_REV10:
+	case SPR_8360E_REV11:
+	case SPR_8360E_REV12:
+	case SPR_8360E_REV20:
+		puts("MPC8360E, ");
 		break;
-	case PVR_8349_REV11:
+	case SPR_8360_REV10:
+	case SPR_8360_REV11:
+	case SPR_8360_REV12:
+	case SPR_8360_REV20:
+		puts("MPC8360, ");
+		break;
+	case SPR_8323E_REV10:
+	case SPR_8323E_REV11:
+		puts("MPC8323E, ");
+		break;
+	case SPR_8323_REV10:
+	case SPR_8323_REV11:
+		puts("MPC8323, ");
+		break;
+	case SPR_8321E_REV10:
+	case SPR_8321E_REV11:
+		puts("MPC8321E, ");
+		break;
+	case SPR_8321_REV10:
+	case SPR_8321_REV11:
+		puts("MPC8321, ");
 		break;
 	default:
-		puts("Rev: Unknown\n");
-		return -1;	/* Not sure what this is */
+		puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
+		return 0;
 	}
-	printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4,
-		(pvr & 0x0f), strmhz(buf, clock));
 
+#if defined(CONFIG_MPC834X)
+	/* Multiple revisons of 834x processors may have the same SPRIDR value.
+	 * So use PVR to identify the revision number.
+	 */
+	printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
+#else
+	printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
+#endif
 	return 0;
 }
 
 
+/*
+ * Program a UPM with the code supplied in the table.
+ *
+ * The 'dummy' variable is used to increment the MAD. 'dummy' is
+ * supposed to be a pointer to the memory of the device being
+ * programmed by the UPM.  The data in the MDR is written into
+ * memory and the MAD is incremented every time there's a read
+ * from 'dummy'. Unfortunately, the current prototype for this
+ * function doesn't allow for passing the address of this
+ * device, and changing the prototype will break a number lots
+ * of other code, so we need to use a round-about way of finding
+ * the value for 'dummy'.
+ *
+ * The value can be extracted from the base address bits of the
+ * Base Register (BR) associated with the specific UPM.  To find
+ * that BR, we need to scan all 8 BRs until we find the one that
+ * has its MSEL bits matching the UPM we want.  Once we know the
+ * right BR, we can extract the base address bits from it.
+ *
+ * The MxMR and the BR and OR of the chosen bank should all be
+ * configured before calling this function.
+ *
+ * Parameters:
+ * upm: 0=UPMA, 1=UPMB, 2=UPMC
+ * table: Pointer to an array of values to program
+ * size: Number of elements in the array.  Must be 64 or less.
+ */
 void upmconfig (uint upm, uint *table, uint size)
 {
-	hang();		/* FIXME: upconfig() needed? */
+#if defined(CONFIG_MPC834X)
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile lbus83xx_t *lbus = &immap->lbus;
+	volatile uchar *dummy = NULL;
+	const u32 msel = (upm + 4) << BR_MSEL_SHIFT;	/* What the MSEL field in BRn should be */
+	volatile u32 *mxmr = &lbus->mamr + upm;	/* Pointer to mamr, mbmr, or mcmr */
+	uint i;
+
+	/* Scan all the banks to determine the base address of the device */
+	for (i = 0; i < 8; i++) {
+		if ((lbus->bank[i].br & BR_MSEL) == msel) {
+			dummy = (uchar *) (lbus->bank[i].br & BR_BA);
+			break;
+		}
+	}
+
+	if (!dummy) {
+		printf("Error: %s() could not find matching BR\n", __FUNCTION__);
+		hang();
+	}
+
+	/* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
+	*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
+
+	for (i = 0; i < size; i++) {
+		lbus->mdr = table[i];
+		__asm__ __volatile__ ("sync");
+		*dummy;	/* Write the value to memory and increment MAD */
+		__asm__ __volatile__ ("sync");
+	}
+
+	/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
+	*mxmr &= 0xCFFFFFC0;
+#else
+	printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
+	hang();
+#endif
 }
 
 
@@ -83,7 +212,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	ulong addr;
 #endif
 
-	volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 
 #ifdef MPC83xx_RESET
 	/* Interrupts and MMU off */
@@ -150,9 +279,17 @@ unsigned long get_tbclk(void)
 #if defined(CONFIG_WATCHDOG)
 void watchdog_reset (void)
 {
-	hang();		/* FIXME: implement watchdog_reset()? */
+	int re_enable = disable_interrupts();
+
+	/* Reset the 83xx watchdog */
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	immr->wdt.swsrr = 0x556c;
+	immr->wdt.swsrr = 0xaa39;
+
+	if (re_enable)
+		enable_interrupts ();
 }
-#endif /* CONFIG_WATCHDOG */
+#endif
 
 #if defined(CONFIG_OF_FLAT_TREE)
 void
@@ -180,13 +317,63 @@ ft_cpu_setup(void *blob, bd_t *bd)
 		*p = cpu_to_be32(clock);
 
 #ifdef CONFIG_MPC83XX_TSEC1
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
+	if (p != NULL)
 		memcpy(p, bd->bi_enetaddr, 6);
 #endif
 
 #ifdef CONFIG_MPC83XX_TSEC2
-	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
+	if (p != NULL)
 		memcpy(p, bd->bi_enet1addr, 6);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+#endif
+
+#ifdef CONFIG_UEC_ETH1
+#if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+#elif CFG_UEC1_UCC_NUM == 2  /* UCC3 */
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enetaddr, 6);
+#endif
+#endif
+
+#ifdef CONFIG_UEC_ETH2
+#if CFG_UEC2_UCC_NUM == 1  /* UCC2 */
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+#elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+
+	p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
+	if (p != NULL)
+		memcpy(p, bd->bi_enet1addr, 6);
+#endif
 #endif
 }
 #endif
@@ -194,8 +381,8 @@ ft_cpu_setup(void *blob, bd_t *bd)
 #if defined(CONFIG_DDR_ECC)
 void dma_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile dma8349_t *dma = &immap->dma;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile dma83xx_t *dma = &immap->dma;
 	volatile u32 status = swab32(dma->dmasr0);
 	volatile u32 dmamr0 = swab32(dma->dmamr0);
 
@@ -225,8 +412,8 @@ void dma_init(void)
 
 uint dma_check(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile dma8349_t *dma = &immap->dma;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile dma83xx_t *dma = &immap->dma;
 	volatile u32 status = swab32(dma->dmasr0);
 	volatile u32 byte_count = swab32(dma->dmabcr0);
 
@@ -244,8 +431,8 @@ uint dma_check(void)
 
 int dma_xfer(void *dest, u32 count, void *src)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile dma8349_t *dma = &immap->dma;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile dma83xx_t *dma = &immap->dma;
 	volatile u32 dmamr0;
 
 	/* initialize DMASARn, DMADAR and DMAABCRn */
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 6ed0992..3ac9161 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -18,11 +18,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
- * Change log:
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- *           Initial file creating (porting from 85XX & 8260)
  */
 
 #include <common.h>
@@ -31,6 +26,30 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_QE
+extern qe_iop_conf_t qe_iop_conf_tab[];
+extern void qe_config_iopin(u8 port, u8 pin, int dir,
+			 int open_drain, int assign);
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+
+static void config_qe_ioports(void)
+{
+	u8	port, pin;
+	int	dir, open_drain, assign;
+	int	i;
+
+	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
+		port		= qe_iop_conf_tab[i].port;
+		pin		= qe_iop_conf_tab[i].pin;
+		dir		= qe_iop_conf_tab[i].dir;
+		open_drain	= qe_iop_conf_tab[i].open_drain;
+		assign		= qe_iop_conf_tab[i].assign;
+		qe_config_iopin(port, pin, dir, open_drain, assign);
+	}
+}
+#endif
+
 /*
  * Breathe some life into the CPU...
  *
@@ -46,6 +65,59 @@ void cpu_init_f (volatile immap_t * im)
 	/* Clear initial global data */
 	memset ((void *) gd, 0, sizeof (gd_t));
 
+	/* system performance tweaking */
+
+#ifdef CFG_ACR_PIPE_DEP
+	/* Arbiter pipeline depth */
+	im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
+			  (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+#endif
+
+#ifdef CFG_SPCR_TSEC1EP
+	/* TSEC1 Emergency priority */
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
+#endif
+
+#ifdef CFG_SPCR_TSEC2EP
+	/* TSEC2 Emergency priority */
+	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
+#endif
+
+#ifdef CONFIG_MPC834X
+#ifdef CFG_SCCR_TSEC1CM
+	/* TSEC1 clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
+#endif
+#ifdef CFG_SCCR_TSEC2CM
+	/* TSEC2 & I2C1 clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
+#endif
+#ifdef CFG_SCCR_USBMPHCM
+	/* USB MPH clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
+#endif
+#endif /* CONFIG_MPC834X */
+
+#ifdef CFG_SCCR_PCICM
+	/* PCI & DMA clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
+#endif
+
+#ifdef CFG_SCCR_USBDRCM
+	/* USB DR clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
+#endif
+
+#ifdef CFG_SCCR_ENCCM
+	/* Encryption clock mode */
+	im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
+#endif
+
+#ifdef CFG_ACR_RPTCNT
+	/* Arbiter repeat count */
+	im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
+#endif
+
 	/* RSR - Reset Status Register - clear all status (4.6.1.3) */
 	gd->reset_status = im->reset.rsr;
 	im->reset.rsr = ~(RSR_RES);
@@ -69,6 +141,15 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CFG_SICRL
 	im->sysconf.sicrl = CFG_SICRL;
 #endif
+	/* DDR control driver register */
+#ifdef CFG_DDRCDR
+	im->sysconf.ddrcdr = CFG_DDRCDR;
+#endif
+
+#ifdef CONFIG_QE
+	/* Config QE ioports */
+	config_qe_ioports();
+#endif
 
 	/*
 	 * Memory Controller:
@@ -148,21 +229,21 @@ void cpu_init_f (volatile immap_t * im)
 	im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
 #endif
 #ifdef CFG_GPIO1_PRELIM
-	im->pgio[0].dir = CFG_GPIO1_DIR;
-	im->pgio[0].dat = CFG_GPIO1_DAT;
+	im->gpio[0].dir = CFG_GPIO1_DIR;
+	im->gpio[0].dat = CFG_GPIO1_DAT;
 #endif
 #ifdef CFG_GPIO2_PRELIM
-	im->pgio[1].dir = CFG_GPIO2_DIR;
-	im->pgio[1].dat = CFG_GPIO2_DAT;
+	im->gpio[1].dir = CFG_GPIO2_DIR;
+	im->gpio[1].dat = CFG_GPIO2_DAT;
 #endif
 }
 
-
-/*
- * Initialize higher level parts of CPU like time base and timers.
- */
-
 int cpu_init_r (void)
 {
+#ifdef CONFIG_QE
+	uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */
+	qe_init(qe_base);
+	qe_reset();
+#endif
 	return 0;
 }
diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c
deleted file mode 100644
index 70450f9..0000000
--- a/cpu/mpc83xx/i2c.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao <x.xiao@motorola.com>
- * Adapted for Motorola 85xx chip.
- *
- * (C) Copyright 2003
- * Gleb Natapov <gnatapov@mrv.com>
- * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
- *
- * Hardware I2C driver for MPC107 PCI bridge.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Change log:
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- *           Initial file creating (porting from 85XX & 8260)
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_HARD_I2C
-#include <i2c.h>
-#include <asm/i2c.h>
-
-#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X)
-i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
-#endif
-
-void
-i2c_init(int speed, int slaveadd)
-{
-	/* stop I2C controller */
-	writeb(0x00 , &I2C->cr);
-
-	/* set clock */
-	writeb(0x3f, &I2C->fdr);
-
-	/* set default filter */
-	writeb(0x10,&I2C->dfsrr);
-
-	/* write slave address */
-	writeb(slaveadd, &I2C->adr);
-
-	/* clear status register */
-	writeb(0x00, &I2C->sr);
-
-	/* start I2C controller */
-	writeb(I2C_CR_MEN, &I2C->cr);
-}
-
-static __inline__ int
-i2c_wait4bus (void)
-{
-	ulong timeval = get_timer (0);
-	while (readb(&I2C->sr) & I2C_SR_MBB) {
-		if (get_timer (timeval) > I2C_TIMEOUT) {
-			return -1;
-		}
-	}
-	return 0;
-}
-
-static __inline__ int
-i2c_wait (int write)
-{
-	u32 csr;
-	ulong timeval = get_timer(0);
-	do {
-		csr = readb(&I2C->sr);
-
-		if (!(csr & I2C_SR_MIF))
-			continue;
-
-		writeb(0x0, &I2C->sr);
-
-		if (csr & I2C_SR_MAL) {
-			debug("i2c_wait: MAL\n");
-			return -1;
-		}
-
-		if (!(csr & I2C_SR_MCF))	{
-			debug("i2c_wait: unfinished\n");
-			return -1;
-		}
-
-		if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
-			debug("i2c_wait: No RXACK\n");
-			return -1;
-		}
-
-		return 0;
-	} while (get_timer (timeval) < I2C_TIMEOUT);
-
-	debug("i2c_wait: timed out\n");
-	return -1;
-}
-
-static __inline__ int
-i2c_write_addr (u8 dev, u8 dir, int rsta)
-{
-	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX |
-	       (rsta?I2C_CR_RSTA:0),
-	       &I2C->cr);
-
-	writeb((dev << 1) | dir, &I2C->dr);
-
-	if (i2c_wait (I2C_WRITE) < 0)
-		return 0;
-	return 1;
-}
-
-static __inline__ int
-__i2c_write (u8 *data, int length)
-{
-	int i;
-
-	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
-	       &I2C->cr);
-
-	for (i=0; i < length; i++) {
-		writeb(data[i], &I2C->dr);
-
-		if (i2c_wait (I2C_WRITE) < 0)
-			break;
-	}
-	return i;
-}
-
-static __inline__ int
-__i2c_read (u8 *data, int length)
-{
-	int i;
-
-	writeb(I2C_CR_MEN | I2C_CR_MSTA |
-	       ((length == 1) ? I2C_CR_TXAK : 0),
-	       &I2C->cr);
-
-	/* dummy read */
-	readb(&I2C->dr);
-
-	for (i=0; i < length; i++) {
-		if (i2c_wait (I2C_READ) < 0)
-			break;
-
-		/* Generate ack on last next to last byte */
-		if (i == length - 2)
-			writeb(I2C_CR_MEN | I2C_CR_MSTA |
-			       I2C_CR_TXAK,
-			       &I2C->cr);
-
-		/* Generate stop on last byte */
-		if (i == length - 1)
-			writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr);
-
-		data[i] = readb(&I2C->dr);
-	}
-	return i;
-}
-
-int
-i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
-{
-	int i = 0;
-	u8 *a = (u8*)&addr;
-
-	if (i2c_wait4bus () < 0)
-		goto exit;
-
-	if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
-		goto exit;
-
-	if (__i2c_write (&a[4 - alen], alen) != alen)
-		goto exit;
-
-	if (i2c_write_addr (dev, I2C_READ, 1) == 0)
-		goto exit;
-
-	i = __i2c_read (data, length);
-
- exit:
-	writeb(I2C_CR_MEN, &I2C->cr);
-	return !(i == length);
-}
-
-int
-i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
-{
-	int i = 0;
-	u8 *a = (u8*)&addr;
-
-	if (i2c_wait4bus () < 0)
-		goto exit;
-
-	if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
-		goto exit;
-
-	if (__i2c_write (&a[4 - alen], alen) != alen)
-		goto exit;
-
-	i = __i2c_write (data, length);
-
- exit:
-	writeb(I2C_CR_MEN, &I2C->cr);
-	return !(i == length);
-}
-
-int i2c_probe (uchar chip)
-{
-	int tmp;
-
-	/*
-	 * Try to read the first location of the chip.  The underlying
-	 * driver doesn't appear to support sending just the chip address
-	 * and looking for an <ACK> back.
-	 */
-	udelay(10000);
-	return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
-}
-
-uchar i2c_reg_read (uchar i2c_addr, uchar reg)
-{
-	uchar buf[1];
-
-	i2c_read (i2c_addr, reg, 1, buf, 1);
-
-	return (buf[0]);
-}
-
-void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
-{
-	i2c_write (i2c_addr, reg, 1, &val, 1);
-}
-
-#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c
index 5a0babf..bb1fe1a 100644
--- a/cpu/mpc83xx/interrupts.c
+++ b/cpu/mpc83xx/interrupts.c
@@ -21,13 +21,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
- * Change log:
- *
- * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- *           Initial file creating (porting from 85XX & 8260)
  */
 
 #include <common.h>
@@ -45,7 +38,7 @@ struct irq_action {
 
 int interrupt_init_cpu (unsigned *decrementer_count)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMRBAR;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 
 	*decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
 
diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c
new file mode 100644
index 0000000..8b3937a
--- /dev/null
+++ b/cpu/mpc83xx/qe_io.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "common.h"
+#include "asm/errno.h"
+#include "asm/io.h"
+#include "asm/immap_83xx.h"
+
+#if defined(CONFIG_QE)
+#define	NUM_OF_PINS	32
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+{
+	u32			pin_2bit_mask;
+	u32			pin_2bit_dir;
+	u32			pin_2bit_assign;
+	u32			pin_1bit_mask;
+	u32			tmp_val;
+	volatile immap_t	*im = (volatile immap_t *)CFG_IMMR;
+	volatile qepio83xx_t	*par_io = (volatile qepio83xx_t *)&im->qepio;
+
+	/* Caculate pin location and 2bit mask and dir */
+	pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+	pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+
+	/* Setup the direction */
+	tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
+		in_be32(&par_io->ioport[port].dir2) :
+		in_be32(&par_io->ioport[port].dir1);
+
+	if (pin > (NUM_OF_PINS/2) -1) {
+		out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val);
+	} else {
+		out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val);
+	}
+
+	/* Calculate pin location for 1bit mask */
+	pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
+
+	/* Setup the open drain */
+	tmp_val = in_be32(&par_io->ioport[port].podr);
+	if (open_drain) {
+		out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val);
+	} else {
+		out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val);
+	}
+
+	/* Setup the assignment */
+	tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
+		in_be32(&par_io->ioport[port].ppar2):
+		in_be32(&par_io->ioport[port].ppar1);
+	pin_2bit_assign = (u32)(assign
+				<< (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
+
+	/* Clear and set 2 bits mask */
+	if (pin > (NUM_OF_PINS/2) - 1) {
+		out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val);
+	} else {
+		out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val);
+		out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val);
+	}
+}
+
+#endif /* CONFIG_QE */
diff --git a/cpu/mpc83xx/resetvec.S b/cpu/mpc83xx/resetvec.S
deleted file mode 100644
index 3dfcd0d..0000000
--- a/cpu/mpc83xx/resetvec.S
+++ /dev/null
@@ -1,6 +0,0 @@
-	.section .resetvec,"ax"
-#ifndef FIXME
-#if 0
-	b _start_e500
-#endif
-#endif
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 48624fe..d9b8753 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -1,8 +1,10 @@
 /*
+ * (C) Copyright 2006 Freescale Semiconductor, Inc.
+ *
  * (C) Copyright 2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
@@ -23,11 +25,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
- * Change log:
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- *           Initial file creating (porting from 85XX & 8260)
  */
 
 #include <common.h>
@@ -39,7 +36,9 @@
 
 #ifdef CONFIG_SPD_EEPROM
 
-#if defined(CONFIG_DDR_ECC)
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 extern void dma_init(void);
 extern uint dma_check(void);
 extern int dma_xfer(void *dest, uint count, void *src);
@@ -52,16 +51,16 @@ extern int dma_xfer(void *dest, uint count, void *src);
 /*
  * Convert picoseconds into clock cycles (rounding up if needed).
  */
-
 int
 picos_to_clk(int picos)
 {
+	unsigned int ddr_bus_clk;
 	int clks;
 
-	clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
-	if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
-	clks++;
-	}
+	ddr_bus_clk = gd->ddr_clk >> 1;
+	clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
+	if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
+		clks++;
 
 	return clks;
 }
@@ -103,60 +102,141 @@ static void spd_debug(spd_eeprom_t *spd)
 
 long int spd_sdram()
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile ddr8349_t *ddr = &immap->ddr;
-	volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
+	volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
 	spd_eeprom_t spd;
-	unsigned tmp, tmp1;
+	unsigned int n_ranks;
+	unsigned int odt_rd_cfg, odt_wr_cfg;
+	unsigned char twr_clk, twtr_clk;
+	unsigned char sdram_type;
 	unsigned int memsize;
 	unsigned int law_size;
-	unsigned char caslat;
-	unsigned int trfc, trfc_clk, trfc_low;
-
+	unsigned char caslat, caslat_ctrl;
+	unsigned int trfc, trfc_clk, trfc_low, trfc_high;
+	unsigned int trcd_clk, trtp_clk;
+	unsigned char cke_min_clk;
+	unsigned char add_lat, wr_lat;
+	unsigned char wr_data_delay;
+	unsigned char four_act;
+	unsigned char cpo;
+	unsigned char burstlen;
+	unsigned char odt_cfg, mode_odt_enable;
+	unsigned int max_bus_clk;
+	unsigned int max_data_rate, effective_data_rate;
+	unsigned int ddrc_clk;
+	unsigned int refresh_clk;
+	unsigned int sdram_cfg;
+	unsigned int ddrc_ecc_enable;
+	unsigned int pvr = get_pvr();
+
+	/* Read SPD parameters with I2C */
 	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
 #ifdef SPD_DEBUG
 	spd_debug(&spd);
 #endif
-	if (spd.nrows > 2) {
-		puts("DDR:Only two chip selects are supported on ADS.\n");
+	/* Check the memory type */
+	if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
+		printf("DDR: Module mem type is %02X\n", spd.mem_type);
+		return 0;
+	}
+
+	/* Check the number of physical bank */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		n_ranks = spd.nrows;
+	} else {
+		n_ranks = (spd.nrows & 0x7) + 1;
+	}
+
+	if (n_ranks > 2) {
+		printf("DDR: The number of physical bank is %02X\n", n_ranks);
+		return 0;
+	}
+
+	/* Check if the number of row of the module is in the range of DDRC */
+	if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
+		printf("DDR: Row number is out of range of DDRC, row=%02X\n",
+							 spd.nrow_addr);
 		return 0;
 	}
 
-	if (spd.nrow_addr < 12
-	    || spd.nrow_addr > 14
-	    || spd.ncol_addr < 8
-	    || spd.ncol_addr > 11) {
-		puts("DDR:Row or Col number unsupported.\n");
+	/* Check if the number of col of the module is in the range of DDRC */
+	if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
+		printf("DDR: Col number is out of range of DDRC, col=%02X\n",
+							 spd.ncol_addr);
 		return 0;
 	}
 
+#ifdef CFG_DDRCDR_VALUE
+	/*
+	 * Adjust DDR II IO voltage biasing.  It just makes it work.
+	 */
+	if(spd.mem_type == SPD_MEMTYPE_DDR2) {
+		immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+	}
+#endif
+
+	/*
+	 * ODT configuration recommendation from DDR Controller Chapter.
+	 */
+	odt_rd_cfg = 0;			/* Never assert ODT */
+	odt_wr_cfg = 0;			/* Never assert ODT */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		odt_wr_cfg = 1;		/* Assert ODT on writes to CSn */
+	}
+
+	/* Setup DDR chip select register */
+#ifdef CFG_83XX_DDR_USES_CS0
+	ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
+	ddr->cs_config[0] = ( 1 << 31
+			    | (odt_rd_cfg << 20)
+			    | (odt_wr_cfg << 16)
+			    | (spd.nrow_addr - 12) << 8
+			    | (spd.ncol_addr - 8) );
+	debug("\n");
+	debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
+	debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
+
+	if (n_ranks == 2) {
+		ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
+				  | ((banksize(spd.row_dens) >> 23) - 1) );
+		ddr->cs_config[1] = ( 1<<31
+				    | (odt_rd_cfg << 20)
+				    | (odt_wr_cfg << 16)
+				    | (spd.nrow_addr-12) << 8
+				    | (spd.ncol_addr-8) );
+		debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
+		debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
+	}
+
+#else
 	ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
 	ddr->cs_config[2] = ( 1 << 31
+			    | (odt_rd_cfg << 20)
+			    | (odt_wr_cfg << 16)
 			    | (spd.nrow_addr - 12) << 8
 			    | (spd.ncol_addr - 8) );
 	debug("\n");
 	debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
 	debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
 
-	if (spd.nrows == 2) {
+	if (n_ranks == 2) {
 		ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
 				  | ((banksize(spd.row_dens) >> 23) - 1) );
 		ddr->cs_config[3] = ( 1<<31
+				    | (odt_rd_cfg << 20)
+				    | (odt_wr_cfg << 16)
 				    | (spd.nrow_addr-12) << 8
 				    | (spd.ncol_addr-8) );
 		debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
 		debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
 	}
-
-	if (spd.mem_type != 0x07) {
-		puts("No DDR module found!\n");
-		return 0;
-	}
+#endif
 
 	/*
 	 * Figure out memory size in Megabytes.
 	 */
-	memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
+	memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
 
 	/*
 	 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
@@ -172,218 +252,520 @@ long int spd_sdram()
 	debug("DDR:ar=0x%08x\n", ecm->ar);
 
 	/*
-	 * find the largest CAS
+	 * Find the largest CAS by locating the highest 1 bit
+	 * in the spd.cas_lat field.  Translate it to a DDR
+	 * controller field value:
+	 *
+	 *	CAS Lat	DDR I	DDR II	Ctrl
+	 *	Clocks	SPD Bit	SPD Bit	Value
+	 *	-------	-------	-------	-----
+	 *	1.0	0		0001
+	 *	1.5	1		0010
+	 *	2.0	2	2	0011
+	 *	2.5	3		0100
+	 *	3.0	4	3	0101
+	 *	3.5	5		0110
+	 *	4.0	6	4	0111
+	 *	4.5			1000
+	 *	5.0		5	1001
 	 */
-	if(spd.cas_lat & 0x40) {
-		caslat = 7;
-	} else if (spd.cas_lat & 0x20) {
-		caslat = 6;
-	} else if (spd.cas_lat & 0x10) {
-		caslat = 5;
-	} else if (spd.cas_lat & 0x08) {
-		caslat = 4;
-	} else if (spd.cas_lat & 0x04) {
-		caslat = 3;
-	} else if (spd.cas_lat & 0x02) {
-		caslat = 2;
-	} else if (spd.cas_lat & 0x01) {
-		caslat = 1;
-	} else {
-		puts("DDR:no valid CAS Latency information.\n");
+	caslat = __ilog2(spd.cas_lat);
+	if ((spd.mem_type == SPD_MEMTYPE_DDR)
+	    && (caslat > 6)) {
+		printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
+		return 0;
+	} else if (spd.mem_type == SPD_MEMTYPE_DDR2
+		   && (caslat < 2 || caslat > 5)) {
+		printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
+		       spd.cas_lat);
 		return 0;
 	}
+	debug("DDR: caslat SPD bit is %d\n", caslat);
+
+	max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
+			+ (spd.clk_cycle & 0x0f));
+	max_data_rate = max_bus_clk * 2;
+
+	debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
+
+	ddrc_clk = gd->ddr_clk / 1000000;
+	effective_data_rate = 0;
+
+	if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
+		if (ddrc_clk <= 460 && ddrc_clk > 350) {
+			/* DDR controller clk at 350~460 */
+			effective_data_rate = 400; /* 5ns */
+			caslat = caslat;
+		} else if (ddrc_clk <= 350 && ddrc_clk > 280) {
+			/* DDR controller clk at 280~350 */
+			effective_data_rate = 333; /* 6ns */
+			if (spd.clk_cycle2 == 0x60)
+				caslat = caslat - 1;
+			else
+				caslat = caslat;
+		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+			/* DDR controller clk at 230~280 */
+			effective_data_rate = 266; /* 7.5ns */
+			if (spd.clk_cycle3 == 0x75)
+				caslat = caslat - 2;
+			else if (spd.clk_cycle2 == 0x75)
+				caslat = caslat - 1;
+			else
+				caslat = caslat;
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
+			if (spd.clk_cycle3 == 0xa0)
+				caslat = caslat - 2;
+			else if (spd.clk_cycle2 == 0xa0)
+				caslat = caslat - 1;
+			else
+				caslat = caslat;
+		}
+	} else if (max_data_rate >= 323) { /* it is DDR 333 */
+		if (ddrc_clk <= 350 && ddrc_clk > 280) {
+			/* DDR controller clk at 280~350 */
+			effective_data_rate = 333; /* 6ns */
+			caslat = caslat;
+		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+			/* DDR controller clk at 230~280 */
+			effective_data_rate = 266; /* 7.5ns */
+			if (spd.clk_cycle2 == 0x75)
+				caslat = caslat - 1;
+			else
+				caslat = caslat;
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
+			if (spd.clk_cycle3 == 0xa0)
+				caslat = caslat - 2;
+			else if (spd.clk_cycle2 == 0xa0)
+				caslat = caslat - 1;
+			else
+				caslat = caslat;
+		}
+	} else if (max_data_rate >= 256) { /* it is DDR 266 */
+		if (ddrc_clk <= 350 && ddrc_clk > 280) {
+			/* DDR controller clk at 280~350 */
+			printf("DDR: DDR controller freq is more than "
+				"max data rate of the module\n");
+			return 0;
+		} else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+			/* DDR controller clk at 230~280 */
+			effective_data_rate = 266; /* 7.5ns */
+			caslat = caslat;
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
+			if (spd.clk_cycle2 == 0xa0)
+				caslat = caslat - 1;
+		}
+	} else if (max_data_rate >= 190) { /* it is DDR 200 */
+		if (ddrc_clk <= 350 && ddrc_clk > 230) {
+			/* DDR controller clk at 230~350 */
+			printf("DDR: DDR controller freq is more than "
+				"max data rate of the module\n");
+			return 0;
+		} else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+			/* DDR controller clk at 90~230 */
+			effective_data_rate = 200; /* 10ns */
+			caslat = caslat;
+		}
+	}
 
-	tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
-		       + (spd.clk_cycle & 0x0f));
-	debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
-
-	tmp1 = get_bus_freq(0) / 1000000;
-	if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
-		/* 90~230 range, treated as DDR 200 */
-		if (spd.clk_cycle3 == 0xa0)
-			caslat -= 2;
-		else if(spd.clk_cycle2 == 0xa0)
-			caslat--;
-	} else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
-		/* 230-280 range, treated as DDR 266 */
-		if (spd.clk_cycle3 == 0x75)
-			caslat -= 2;
-		else if (spd.clk_cycle2 == 0x75)
-			caslat--;
-	} else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
-		/* 280~350 range, treated as DDR 333 */
-		if (spd.clk_cycle3 == 0x60)
-			caslat -= 2;
-		else if (spd.clk_cycle2 == 0x60)
-			caslat--;
-	} else if (tmp1 < 90 || tmp1 >= 350) {
-		/* DDR rate out-of-range */
-		puts("DDR:platform frequency is not fit for DDR rate\n");
-		return 0;
+	debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
+	debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
+
+	/*
+	 * Errata DDR6 work around: input enable 2 cycles earlier.
+	 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
+	 */
+	if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
+		if (caslat == 2)
+			ddr->debug_reg = 0x201c0000; /* CL=2 */
+		else if (caslat == 3)
+			ddr->debug_reg = 0x202c0000; /* CL=2.5 */
+		else if (caslat == 4)
+			ddr->debug_reg = 0x202c0000; /* CL=3.0 */
+
+		__asm__ __volatile__ ("sync");
+
+		debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
 	}
 
 	/*
-	 * note: caslat must also be programmed into ddr->sdram_mode
-	 * register.
-	 *
-	 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
-	 * use conservative value here.
+	 * Convert caslat clocks to DDR controller value.
+	 * Force caslat_ctrl to be DDR Controller field-sized.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		caslat_ctrl = (caslat + 1) & 0x07;
+	} else {
+		caslat_ctrl =  (2 * caslat - 1) & 0x0f;
+	}
+
+	debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
+	debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
+	      caslat, caslat_ctrl);
+
+	/*
+	 * Timing Config 0.
+	 * Avoid writing for DDR I.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		unsigned char taxpd_clk = 8;		/* By the book. */
+		unsigned char tmrd_clk = 2;		/* By the book. */
+		unsigned char act_pd_exit = 2;		/* Empirical? */
+		unsigned char pre_pd_exit = 6;		/* Empirical? */
+
+		ddr->timing_cfg_0 = (0
+			| ((act_pd_exit & 0x7) << 20)	/* ACT_PD_EXIT */
+			| ((pre_pd_exit & 0x7) << 16)	/* PRE_PD_EXIT */
+			| ((taxpd_clk & 0xf) << 8)	/* ODT_PD_EXIT */
+			| ((tmrd_clk & 0xf) << 0)	/* MRS_CYC */
+			);
+		debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
+	}
+
+	/*
+	 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
+	 * use conservative value.
+	 * For DDR II, they are bytes 36 and 37, in quarter nanos.
 	 */
-	trfc = spd.trfc * 1000;         /* up to ps */
+
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		twr_clk = 3;	/* Clocks */
+		twtr_clk = 1;	/* Clocks */
+	} else {
+		twr_clk = picos_to_clk(spd.twr * 250);
+		twtr_clk = picos_to_clk(spd.twtr * 250);
+	}
+
+	/*
+	 * Calculate Trfc, in picos.
+	 * DDR I:  Byte 42 straight up in ns.
+	 * DDR II: Byte 40 and 42 swizzled some, in ns.
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		trfc = spd.trfc * 1000;		/* up to ps */
+	} else {
+		unsigned int byte40_table_ps[8] = {
+			0,
+			250,
+			330,
+			500,
+			660,
+			750,
+			0,
+			0
+		};
+
+		trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
+			+ byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
+	}
 	trfc_clk = picos_to_clk(trfc);
+
+	/*
+	 * Trcd, Byte 29, from quarter nanos to ps and clocks.
+	 */
+	trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
+
+	/*
+	 * Convert trfc_clk to DDR controller fields.  DDR I should
+	 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
+	 * 83xx controller has an extended REFREC field of three bits.
+	 * The controller automatically adds 8 clocks to this value,
+	 * so preadjust it down 8 first before splitting it up.
+	 */
 	trfc_low = (trfc_clk - 8) & 0xf;
+	trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
 
 	ddr->timing_cfg_1 =
-	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
-	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
-	     ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
-	     ((caslat & 0x07) << 16 ) |
-	     (trfc_low << 12 ) |
-	     ( 0x300 ) |
-	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
+	    (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |	/* PRETOACT */
+	     ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
+	     (trcd_clk << 20 ) |  				/* ACTTORW */
+	     (caslat_ctrl << 16 ) |				/* CASLAT */
+	     (trfc_low << 12 ) |				/* REFEC */
+	     ((twr_clk & 0x07) << 8) |				/* WRRREC */
+	     ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) |	/* ACTTOACT */
+	     ((twtr_clk & 0x07) << 0)				/* WRTORD */
+	    );
+
+	/*
+	 * Additive Latency
+	 * For DDR I, 0.
+	 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
+	 * which comes from Trcd, and also note that:
+	 *	add_lat + caslat must be >= 4
+	 */
+	add_lat = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2
+	    && (odt_wr_cfg || odt_rd_cfg)
+	    && (caslat < 4)) {
+		add_lat = trcd_clk - 1;
+		if ((add_lat + caslat) < 4) {
+			add_lat = 0;
+		}
+	}
+
+	/*
+	 * Write Data Delay
+	 * Historically 0x2 == 4/8 clock delay.
+	 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
+	 */
+	wr_data_delay = 2;
+
+	/*
+	 * Write Latency
+	 * Read to Precharge
+	 * Minimum CKE Pulse Width.
+	 * Four Activate Window
+	 */
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		/*
+		 * This is a lie.  It should really be 1, but if it is
+		 * set to 1, bits overlap into the old controller's
+		 * otherwise unused ACSM field.  If we leave it 0, then
+		 * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
+		 */
+		wr_lat = 0;
+
+		trtp_clk = 2;		/* By the book. */
+		cke_min_clk = 1;	/* By the book. */
+		four_act = 1;		/* By the book. */
+
+	} else {
+		wr_lat = caslat - 1;
+
+		/* Convert SPD value from quarter nanos to picos. */
+		trtp_clk = picos_to_clk(spd.trtp * 250);
+
+		cke_min_clk = 3;	/* By the book. */
+		four_act = picos_to_clk(37500);	/* By the book. 1k pages? */
+	}
+
+	/*
+	 * Empirically set ~MCAS-to-preamble override for DDR 2.
+	 * Your milage will vary.
+	 */
+	cpo = 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		if (effective_data_rate == 266 || effective_data_rate == 333) {
+			cpo = 0x7;		/* READ_LAT + 5/4 */
+		} else if (effective_data_rate == 400) {
+			cpo = 0x9;		/* READ_LAT + 7/4 */
+		} else {
+			/* Automatic calibration */
+			cpo = 0x1f;
+		}
+	}
 
-	ddr->timing_cfg_2 = 0x00000800;
+	ddr->timing_cfg_2 = (0
+		| ((add_lat & 0x7) << 28)		/* ADD_LAT */
+		| ((cpo & 0x1f) << 23)			/* CPO */
+		| ((wr_lat & 0x7) << 19)		/* WR_LAT */
+		| ((trtp_clk & 0x7) << 13)		/* RD_TO_PRE */
+		| ((wr_data_delay & 0x7) << 10)		/* WR_DATA_DELAY */
+		| ((cke_min_clk & 0x7) << 6)		/* CKE_PLS */
+		| ((four_act & 0x1f) << 0)		/* FOUR_ACT */
+		);
 
 	debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
 	debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
 
-	/*
-	 * Only DDR I is supported
-	 * DDR I and II have different mode-register-set definition
+	/* Check DIMM data bus width */
+	if (spd.dataw_lsb == 0x20) {
+		burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
+		printf("\n   DDR DIMM: data bus width is 32 bit");
+	} else {
+		burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
+		printf("\n   DDR DIMM: data bus width is 64 bit");
+	}
+
+	/* Is this an ECC DDR chip? */
+	if (spd.config == 0x02)
+		printf(" with ECC\n");
+	else
+		printf(" without ECC\n");
+
+	/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
+	   Burst type is sequential
 	 */
-	switch(caslat) {
-	case 2:
-		tmp = 0x50; /* 1.5 */
-		break;
-	case 3:
-		tmp = 0x20; /* 2.0 */
-		break;
-	case 4:
-		tmp = 0x60; /* 2.5 */
-		break;
-	case 5:
-		tmp = 0x30; /* 3.0 */
-		break;
-	default:
-		puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
-		return 0;
+	if (spd.mem_type == SPD_MEMTYPE_DDR) {
+		switch (caslat) {
+		case 1:
+			ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
+			break;
+		case 2:
+			ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
+			break;
+		case 3:
+			ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
+			break;
+		case 4:
+			ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
+			break;
+		default:
+			printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
+			return 0;
+		}
+	} else {
+		mode_odt_enable = 0x0;                  /* Default disabled */
+		if (odt_wr_cfg || odt_rd_cfg) {
+			/*
+			 * Bits 6 and 2 in Extended MRS(1)
+			 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
+			 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
+			 */
+			mode_odt_enable = 0x40;         /* 150 Ohm */
+		}
+
+		ddr->sdram_mode =
+			(0
+			 | (1 << (16 + 10))             /* DQS Differential disable */
+			 | (add_lat << (16 + 3))        /* Additive Latency in EMRS1 */
+			 | (mode_odt_enable << 16)      /* ODT Enable in EMRS1 */
+			 | ((twr_clk >> 1) << 9)        /* Write Recovery Autopre */
+			 | (caslat << 4)                /* caslat */
+			 | (burstlen << 0)              /* Burst length */
+			);
 	}
-#if defined (CONFIG_DDR_32BIT)
-	/* set burst length to 8 for 32-bit data path */
-	tmp |= 0x03;
-#else
-	/* set burst length to 4 - default for 64-bit data path */
-	tmp |= 0x02;
-#endif
-	ddr->sdram_mode = tmp;
 	debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
 
-	switch(spd.refresh) {
-	case 0x00:
-	case 0x80:
-		tmp = picos_to_clk(15625000);
-		break;
-	case 0x01:
-	case 0x81:
-		tmp = picos_to_clk(3900000);
-		break;
-	case 0x02:
-	case 0x82:
-		tmp = picos_to_clk(7800000);
-		break;
-	case 0x03:
-	case 0x83:
-		tmp = picos_to_clk(31300000);
-		break;
-	case 0x04:
-	case 0x84:
-		tmp = picos_to_clk(62500000);
-		break;
-	case 0x05:
-	case 0x85:
-		tmp = picos_to_clk(125000000);
-		break;
-	default:
-		tmp = 0x512;
-		break;
+	/*
+	 * Clear EMRS2 and EMRS3.
+	 */
+	ddr->sdram_mode2 = 0;
+	debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
+
+	switch (spd.refresh) {
+		case 0x00:
+		case 0x80:
+			refresh_clk = picos_to_clk(15625000);
+			break;
+		case 0x01:
+		case 0x81:
+			refresh_clk = picos_to_clk(3900000);
+			break;
+		case 0x02:
+		case 0x82:
+			refresh_clk = picos_to_clk(7800000);
+			break;
+		case 0x03:
+		case 0x83:
+			refresh_clk = picos_to_clk(31300000);
+			break;
+		case 0x04:
+		case 0x84:
+			refresh_clk = picos_to_clk(62500000);
+			break;
+		case 0x05:
+		case 0x85:
+			refresh_clk = picos_to_clk(125000000);
+			break;
+		default:
+			refresh_clk = 0x512;
+			break;
 	}
 
 	/*
 	 * Set BSTOPRE to 0x100 for page mode
 	 * If auto-charge is used, set BSTOPRE = 0
 	 */
-	ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
+	ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
 	debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
 
 	/*
-	 * Is this an ECC DDR chip?
+	 * SDRAM Cfg 2
 	 */
-#if defined(CONFIG_DDR_ECC)
-	if (spd.config == 0x02) {
-		/* disable error detection */
-		ddr->err_disable = ~ECC_ERROR_ENABLE;
-
-		/* set single bit error threshold to maximum value,
-		 * reset counter to zero */
-		ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
-			(0 << ECC_ERROR_MAN_SBEC_SHIFT);
+	odt_cfg = 0;
+	if (odt_rd_cfg | odt_wr_cfg) {
+		odt_cfg = 0x2;		/* ODT to IOs during reads */
 	}
-	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
-	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
+	if (spd.mem_type == SPD_MEMTYPE_DDR2) {
+		ddr->sdram_cfg2 = (0
+			    | (0 << 26)	/* True DQS */
+			    | (odt_cfg << 21)	/* ODT only read */
+			    | (1 << 12)	/* 1 refresh at a time */
+			    );
+
+		debug("DDR: sdram_cfg2  = 0x%08x\n", ddr->sdram_cfg2);
+	}
+
+#ifdef CFG_DDR_SDRAM_CLK_CNTL	/* Optional platform specific value */
+	ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+#else
+	/* SS_EN = 0, source synchronous disable
+	 * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
+	 */
+	ddr->sdram_clk_cntl = 0x00000000;
 #endif
-	asm("sync;isync");
+	debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
 
-	udelay(500);
+	asm("sync;isync");
 
-	/*
-	 * SS_EN=1,
-	 * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
-	 * clock cycle after address/command
-	 */
-	/*ddr->sdram_clk_cntl = 0x82000000;*/
-	ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
+	udelay(600);
 
 	/*
-	 * Figure out the settings for the sdram_cfg register.  Build up
-	 * the entire register in 'tmp' before writing since the write into
+	 * Figure out the settings for the sdram_cfg register. Build up
+	 * the value in 'sdram_cfg' before writing since the write into
 	 * the register will actually enable the memory controller, and all
 	 * settings must be done before enabling.
 	 *
 	 * sdram_cfg[0]   = 1 (ddr sdram logic enable)
 	 * sdram_cfg[1]   = 1 (self-refresh-enable)
-	 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
+	 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
+	 *			010 DDR 1 SDRAM
+	 *			011 DDR 2 SDRAM
+	 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
+	 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
 	 */
-	tmp = 0xc2000000;
+	if (spd.mem_type == SPD_MEMTYPE_DDR)
+		sdram_type = 2;
+	else
+		sdram_type = 3;
 
-#if defined (CONFIG_DDR_32BIT)
-	/* in 32-Bit mode burst len is 8 beats */
-	tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
-	/*
-	 * sdram_cfg[3] = RD_EN - registered DIMM enable
-	 *   A value of 0x26 indicates micron registered DIMMS (micron.com)
-	 */
-	if (spd.mod_attr == 0x26) {
-		tmp |= 0x10000000;
-	}
+	sdram_cfg = (0
+		     | (1 << 31)			/* DDR enable */
+		     | (1 << 30)			/* Self refresh */
+		     | (sdram_type << 24)		/* SDRAM type */
+		     );
+
+	/* sdram_cfg[3] = RD_EN - registered DIMM enable */
+	if (spd.mod_attr & 0x02)
+		sdram_cfg |= 0x10000000;
+
+	/* The DIMM is 32bit width */
+	if (spd.dataw_lsb == 0x20)
+		sdram_cfg |= 0x000C0000;
+
+	ddrc_ecc_enable = 0;
 
 #if defined(CONFIG_DDR_ECC)
-	/*
-	 * If the user wanted ECC (enabled via sdram_cfg[2])
-	 */
+	/* Enable ECC with sdram_cfg[2] */
 	if (spd.config == 0x02) {
-		tmp |= SDRAM_CFG_ECC_EN;
+		sdram_cfg |= 0x20000000;
+		ddrc_ecc_enable = 1;
+		/* disable error detection */
+		ddr->err_disable = ~ECC_ERROR_ENABLE;
+		/* set single bit error threshold to maximum value,
+		 * reset counter to zero */
+		ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
+				(0 << ECC_ERROR_MAN_SBEC_SHIFT);
 	}
+
+	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
+	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
 #endif
+	printf("   DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
 
 #if defined(CONFIG_DDR_2T_TIMING)
 	/*
 	 * Enable 2T timing by setting sdram_cfg[16].
 	 */
-	tmp |= SDRAM_CFG_2T_EN;
+	sdram_cfg |= SDRAM_CFG_2T_EN;
 #endif
-
-	ddr->sdram_cfg = tmp;
+	/* Enable controller, and GO! */
+	ddr->sdram_cfg = sdram_cfg;
 	asm("sync;isync");
 	udelay(500);
 
@@ -392,8 +774,7 @@ long int spd_sdram()
 }
 #endif /* CONFIG_SPD_EEPROM */
 
-
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 /*
  * Use timebase counter, get_timer() is not availabe
  * at this point of initialization yet.
@@ -429,74 +810,48 @@ static __inline__ unsigned long get_tbms (void)
 /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
 void ddr_enable_ecc(unsigned int dram_size)
 {
-	uint *p;
-	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
-	volatile ddr8349_t *ddr = &immap->ddr;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ddr83xx_t *ddr= &immap->ddr;
 	unsigned long t_start, t_end;
+	register u64 *p;
+	register uint size;
+	unsigned int pattern[2];
 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
 	uint i;
 #endif
-
-	debug("Initialize a Cachline in DRAM\n");
 	icache_enable();
-
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
-	/* Initialise DMA for direct Transfers */
-	dma_init();
-#endif
-
 	t_start = get_tbms();
+	pattern[0] = 0xdeadbeef;
+	pattern[1] = 0xdeadbeef;
 
 #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
-	debug("DDR init: Cache flush method\n");
-	for (p = 0; p < (uint *)(dram_size); p++) {
-		if (((unsigned int)p & 0x1f) == 0) {
-			ppcDcbz((unsigned long) p);
-		}
-
-		/* write pattern to cache and flush */
-		*p = (unsigned int)0xdeadbeef;
-
-		if (((unsigned int)p & 0x1c) == 0x1c) {
-			ppcDcbf((unsigned long) p);
-		}
+	debug("ddr init: CPU FP write method\n");
+	size = dram_size;
+	for (p = 0; p < (u64*)(size); p++) {
+		ppcDWstore((u32*)p, pattern);
 	}
+	__asm__ __volatile__ ("sync");
 #else
-	printf("DDR init: DMA method\n");
-	for (p = 0; p < (uint *)(8 * 1024); p++) {
-		/* zero one data cache line */
-		if (((unsigned int)p & 0x1f) == 0) {
-			ppcDcbz((unsigned long)p);
-		}
-
-		/* write pattern to it and flush */
-		*p = (unsigned int)0xdeadbeef;
-
-		if (((unsigned int)p & 0x1c) == 0x1c) {
-			ppcDcbf((unsigned long)p);
-		}
+	debug("ddr init: DMA method\n");
+	size = 0x2000;
+	for (p = 0; p < (u64*)(size); p++) {
+		ppcDWstore((u32*)p, pattern);
 	}
+	__asm__ __volatile__ ("sync");
 
-	/* 8K */
-	dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
-	/* 16K */
-	dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
-	/* 32K */
-	dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
-	/* 64K */
-	dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
-	/* 128k */
-	dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
-	/* 256k */
-	dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
-	/* 512k */
-	dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
-	/* 1M */
-	dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
-	/* 2M */
-	dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
-	/* 4M */
-	dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
+	/* Initialise DMA for direct transfer */
+	dma_init();
+	/* Start DMA to transfer */
+	dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
+	dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
+	dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
+	dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
+	dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
+	dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
+	dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
+	dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
+	dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
+	dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
 
 	for (i = 1; i < dram_size / 0x800000; i++) {
 		dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index ad6b3f6..c759930 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright 2004 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -21,11 +21,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
- * Change log:
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- *           Initial file creating (porting from 85XX & 8260)
  */
 
 #include <common.h>
@@ -53,38 +48,38 @@ typedef enum {
 
 typedef struct {
 	mult_t core_csb_ratio;
-	mult_t  vco_divider;
+	mult_t vco_divider;
 } corecnf_t;
 
 corecnf_t corecnf_tab[] = {
-	{ _byp, _byp},	/* 0x00 */
-	{ _byp, _byp},	/* 0x01 */
-	{ _byp, _byp},	/* 0x02 */
-	{ _byp, _byp},	/* 0x03 */
-	{ _byp, _byp},	/* 0x04 */
-	{ _byp, _byp},	/* 0x05 */
-	{ _byp, _byp},	/* 0x06 */
-	{ _byp, _byp},	/* 0x07 */
-	{  _1x,  _x2},	/* 0x08 */
-	{  _1x,  _x4},	/* 0x09 */
-	{  _1x,  _x8},	/* 0x0A */
-	{  _1x,  _x8},	/* 0x0B */
-	{_1_5x,  _x2},	/* 0x0C */
-	{_1_5x,  _x4},	/* 0x0D */
-	{_1_5x,  _x8},	/* 0x0E */
-	{_1_5x,  _x8},	/* 0x0F */
-	{  _2x,  _x2},	/* 0x10 */
-	{  _2x,  _x4},	/* 0x11 */
-	{  _2x,  _x8},	/* 0x12 */
-	{  _2x,  _x8},	/* 0x13 */
-	{_2_5x,  _x2},	/* 0x14 */
-	{_2_5x,  _x4},	/* 0x15 */
-	{_2_5x,  _x8},	/* 0x16 */
-	{_2_5x,  _x8},	/* 0x17 */
-	{  _3x,  _x2},	/* 0x18 */
-	{  _3x,  _x4},	/* 0x19 */
-	{  _3x,  _x8},	/* 0x1A */
-	{  _3x,  _x8},	/* 0x1B */
+	{_byp, _byp},		/* 0x00 */
+	{_byp, _byp},		/* 0x01 */
+	{_byp, _byp},		/* 0x02 */
+	{_byp, _byp},		/* 0x03 */
+	{_byp, _byp},		/* 0x04 */
+	{_byp, _byp},		/* 0x05 */
+	{_byp, _byp},		/* 0x06 */
+	{_byp, _byp},		/* 0x07 */
+	{_1x, _x2},		/* 0x08 */
+	{_1x, _x4},		/* 0x09 */
+	{_1x, _x8},		/* 0x0A */
+	{_1x, _x8},		/* 0x0B */
+	{_1_5x, _x2},		/* 0x0C */
+	{_1_5x, _x4},		/* 0x0D */
+	{_1_5x, _x8},		/* 0x0E */
+	{_1_5x, _x8},		/* 0x0F */
+	{_2x, _x2},		/* 0x10 */
+	{_2x, _x4},		/* 0x11 */
+	{_2x, _x8},		/* 0x12 */
+	{_2x, _x8},		/* 0x13 */
+	{_2_5x, _x2},		/* 0x14 */
+	{_2_5x, _x4},		/* 0x15 */
+	{_2_5x, _x8},		/* 0x16 */
+	{_2_5x, _x8},		/* 0x17 */
+	{_3x, _x2},		/* 0x18 */
+	{_3x, _x4},		/* 0x19 */
+	{_3x, _x8},		/* 0x1A */
+	{_3x, _x8},		/* 0x1B */
 };
 
 /* ----------------------------------------------------------------- */
@@ -92,91 +87,68 @@ corecnf_t corecnf_tab[] = {
 /*
  *
  */
-int get_clocks (void)
+int get_clocks(void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
 	u32 pci_sync_in;
-	u8  spmf;
-	u8  clkin_div;
+	u8 spmf;
+	u8 clkin_div;
 	u32 sccr;
 	u32 corecnf_tab_index;
-	u8  corepll;
+	u8 corepll;
 	u32 lcrr;
 
 	u32 csb_clk;
+#if defined(CONFIG_MPC834X)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
-	u32 core_clk;
 	u32 usbmph_clk;
 	u32 usbdr_clk;
-	u32 i2c_clk;
+#endif
+	u32 core_clk;
+	u32 i2c1_clk;
+#if !defined(CONFIG_MPC832X)
+	u32 i2c2_clk;
+#endif
 	u32 enc_clk;
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 ddr_clk;
-
-	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+#if defined(CONFIG_MPC8360)
+	u32 ddr_sec_clk;
+#endif
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+	u32 qepmf;
+	u32 qepdf;
+	u32 qe_clk;
+	u32 brg_clk;
+#endif
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
 
-#ifndef CFG_HRCW_HIGH
-# error "CFG_HRCW_HIGH must be defined in board config file"
-#endif /* CFG_HCWD_HIGH */
-
-#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
-
-# ifndef CONFIG_83XX_CLKIN
-#  error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
-# endif /* CONFIG_83XX_CLKIN */
-# ifdef CONFIG_83XX_PCICLK
-#  warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
-# endif /* CONFIG_83XX_PCICLK */
-
-	/* PCI Host Mode */
-	if (!(im->reset.rcwh & RCWH_PCIHOST)) {
-		/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
-		 * the im->reset.rcwhr PCI Host Mode is disabled
-		 * FIXME: findout if there is a way to issue some warning */
-		return -2;
-	}
-	if (im->clk.spmr & SPMR_CKID) {
-		/* PCI Clock is half CONFIG_83XX_CLKIN */
-		pci_sync_in = CONFIG_83XX_CLKIN / 2;
-	}
-	else {
-		pci_sync_in = CONFIG_83XX_CLKIN;
-	}
-
-#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
-
-# ifdef CONFIG_83XX_CLKIN
-#  warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
-# endif /* CONFIG_83XX_CLKIN */
-# ifndef CONFIG_83XX_PCICLK
-#  error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
-# endif /* CONFIG_83XX_PCICLK */
-
-	/* PCI Agent Mode */
-	if (im->reset.rcwh & RCWH_PCIHOST) {
-		/* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
-		 * the im->reset.rcwhr PCI Host Mode is enabled */
-		return -3;
-	}
-	pci_sync_in = CONFIG_83XX_PCICLK;
-
-#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
-
-	/* we have up to date pci_sync_in */
-	spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
 	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 
-	if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
-		csb_clk	= (pci_sync_in * spmf * (1 + clkin_div)) / 2;
-	}
-	else {
-		csb_clk = pci_sync_in * spmf * (1 + clkin_div);
+	if (im->reset.rcwh & HRCWH_PCI_HOST) {
+#if defined(CONFIG_83XX_CLKIN)
+		pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
+#else
+		pci_sync_in = 0xDEADBEEF;
+#endif
+	} else {
+#if defined(CONFIG_83XX_PCICLK)
+		pci_sync_in = CONFIG_83XX_PCICLK;
+#else
+		pci_sync_in = 0xDEADBEEF;
+#endif
 	}
 
+	spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
+	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
+
 	sccr = im->clk.sccr;
+
+#if defined(CONFIG_MPC834X)
 	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 	case 0:
 		tsec1_clk = 0;
@@ -212,25 +184,8 @@ int get_clocks (void)
 		/* unkown SCCR_TSEC2CM value */
 		return -5;
 	}
-	i2c_clk = tsec2_clk;
 
-	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
-	case 0:
-		enc_clk = 0;
-		break;
-	case 1:
-		enc_clk = csb_clk;
-		break;
-	case 2:
-		enc_clk = csb_clk / 2;
-		break;
-	case 3:
-		enc_clk = csb_clk / 3;
-		break;
-	default:
-		/* unkown SCCR_ENCCM value */
-		return -6;
-	}
+	i2c1_clk = tsec2_clk;
 
 	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
 	case 0:
@@ -268,14 +223,41 @@ int get_clocks (void)
 		return -8;
 	}
 
-	if (usbmph_clk != 0
-		&& usbdr_clk != 0
-		&& usbmph_clk != usbdr_clk ) {
-		/* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
+	if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
+		/* if USB MPH clock is not disabled and
+		 * USB DR clock is not disabled then
+		 * USB MPH & USB DR must have the same rate
+		 */
 		return -9;
 	}
+#endif
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+	i2c1_clk = csb_clk;
+#endif
+#if !defined(CONFIG_MPC832X)
+	i2c2_clk = csb_clk;	/* i2c-2 clk is equal to csb clk */
+#endif
 
-	lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
+	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
+	case 0:
+		enc_clk = 0;
+		break;
+	case 1:
+		enc_clk = csb_clk;
+		break;
+	case 2:
+		enc_clk = csb_clk / 2;
+		break;
+	case 3:
+		enc_clk = csb_clk / 3;
+		break;
+	default:
+		/* unkown SCCR_ENCCM value */
+		return -6;
+	}
+
+	lbiu_clk = csb_clk *
+	           (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 	lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 	switch (lcrr) {
 	case 2:
@@ -288,11 +270,16 @@ int get_clocks (void)
 		return -10;
 	}
 
-	ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
+	ddr_clk = csb_clk *
+		  (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
+	corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
+#if defined(CONFIG_MPC8360)
+	ddr_sec_clk = csb_clk * (1 +
+		       ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
+#endif
 
-	corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
 	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
-	if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
+	if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
 		/* corecnf_tab_index is too high, possibly worng value */
 		return -11;
 	}
@@ -309,7 +296,7 @@ int get_clocks (void)
 		core_clk = 2 * csb_clk;
 		break;
 	case _2_5x:
-		core_clk = ( 5 * csb_clk) / 2;
+		core_clk = (5 * csb_clk) / 2;
 		break;
 	case _3x:
 		core_clk = 3 * csb_clk;
@@ -319,46 +306,76 @@ int get_clocks (void)
 		return -12;
 	}
 
-	gd->csb_clk    = csb_clk   ;
-	gd->tsec1_clk  = tsec1_clk ;
-	gd->tsec2_clk  = tsec2_clk ;
-	gd->core_clk   = core_clk  ;
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+	qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
+	qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
+	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
+	brg_clk = qe_clk / 2;
+#endif
+
+	gd->csb_clk = csb_clk;
+#if defined(CONFIG_MPC834X)
+	gd->tsec1_clk = tsec1_clk;
+	gd->tsec2_clk = tsec2_clk;
 	gd->usbmph_clk = usbmph_clk;
-	gd->usbdr_clk  = usbdr_clk ;
-	gd->i2c_clk    = i2c_clk   ;
-	gd->enc_clk    = enc_clk   ;
-	gd->lbiu_clk   = lbiu_clk  ;
-	gd->lclk_clk   = lclk_clk  ;
-	gd->ddr_clk    = ddr_clk   ;
-	gd->pci_clk    = pci_sync_in;
-
+	gd->usbdr_clk = usbdr_clk;
+#endif
+	gd->core_clk = core_clk;
+	gd->i2c1_clk = i2c1_clk;
+#if !defined(CONFIG_MPC832X)
+	gd->i2c2_clk = i2c2_clk;
+#endif
+	gd->enc_clk = enc_clk;
+	gd->lbiu_clk = lbiu_clk;
+	gd->lclk_clk = lclk_clk;
+	gd->ddr_clk = ddr_clk;
+#if defined(CONFIG_MPC8360)
+	gd->ddr_sec_clk = ddr_sec_clk;
+#endif
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+	gd->qe_clk = qe_clk;
+	gd->brg_clk = brg_clk;
+#endif
 	gd->cpu_clk = gd->core_clk;
-	gd->bus_clk = gd->lbiu_clk;
+	gd->bus_clk = gd->csb_clk;
 	return 0;
+
 }
 
 /********************************************
  * get_bus_freq
  * return system bus freq in Hz
  *********************************************/
-ulong get_bus_freq (ulong dummy)
+ulong get_bus_freq(ulong dummy)
 {
 	return gd->csb_clk;
 }
 
-int print_clock_conf (void)
+int print_clock_conf(void)
 {
 	printf("Clock configuration:\n");
-	printf("  Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
-	printf("  Core:                %4d MHz\n",gd->core_clk/1000000);
-	debug("  Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
-	printf("  Local Bus:           %4d MHz\n",gd->lclk_clk/1000000);
-	debug("  DDR:                 %4d MHz\n",gd->ddr_clk/1000000);
-	debug("  I2C:                 %4d MHz\n",gd->i2c_clk/1000000);
-	debug("  TSEC1:               %4d MHz\n",gd->tsec1_clk/1000000);
-	debug("  TSEC2:               %4d MHz\n",gd->tsec2_clk/1000000);
-	debug("  USB MPH:             %4d MHz\n",gd->usbmph_clk/1000000);
-	debug("  USB DR:              %4d MHz\n",gd->usbdr_clk/1000000);
-
+	printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
+	printf("  Core:                %4d MHz\n", gd->core_clk / 1000000);
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+	printf("  QE:                  %4d MHz\n", gd->qe_clk / 1000000);
+	printf("  BRG:                 %4d MHz\n", gd->brg_clk / 1000000);
+#endif
+	printf("  Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
+	printf("  Local Bus:           %4d MHz\n", gd->lclk_clk / 1000000);
+	printf("  DDR:                 %4d MHz\n", gd->ddr_clk / 1000000);
+#if defined(CONFIG_MPC8360)
+	printf("  DDR Secondary:       %4d MHz\n", gd->ddr_sec_clk / 1000000);
+#endif
+	printf("  SEC:                 %4d MHz\n", gd->enc_clk / 1000000);
+	printf("  I2C1:                %4d MHz\n", gd->i2c1_clk / 1000000);
+#if !defined(CONFIG_MPC832X)
+	printf("  I2C2:                %4d MHz\n", gd->i2c2_clk / 1000000);
+#endif
+#if defined(CONFIG_MPC834X)
+	printf("  TSEC1:               %4d MHz\n", gd->tsec1_clk / 1000000);
+	printf("  TSEC2:               %4d MHz\n", gd->tsec2_clk / 1000000);
+	printf("  USB MPH:             %4d MHz\n", gd->usbmph_clk / 1000000);
+	printf("  USB DR:              %4d MHz\n", gd->usbdr_clk / 1000000);
+#endif
 	return 0;
 }
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 6e02cce..6ee9ec9 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -2,7 +2,7 @@
  * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
  * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
- * Copyright 2004 Freescale Semiconductor, Inc.
+ * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -77,19 +77,11 @@
 	END_GOT
 
 /*
- * Version string - must be in data segment because MPC83xx uses the
- * first 256 bytes for the Hard Reset Configuration Word table (see
- * below).  Similarly, can't have the U-Boot Magic Number as the first
- * thing in the image - don't know how this will affect the image tools,
- * but I guess I'll find out soon.
+ * The Hard Reset Configuration Word (HRCW) table is in the first 64
+ * (0x40) bytes of flash.  It has 8 bytes, but each byte is repeated 8
+ * times so the processor can fetch it out of flash whether the flash
+ * is 8, 16, 32, or 64 bits wide (hardware trickery).
  */
-	.data
-	.globl	version_string
-version_string:
-	.ascii U_BOOT_VERSION
-	.ascii " (", __DATE__, " - ", __TIME__, ")"
-	.ascii " ", CONFIG_IDENT_STRING, "\0"
-
 	.text
 #define _HRCW_TABLE_ENTRY(w)		\
 	.fill	8,1,(((w)>>24)&0xff);	\
@@ -100,13 +92,25 @@ version_string:
 	_HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
 	_HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
 
+/*
+ * Magic number and version string - put it after the HRCW since it
+ * cannot be first in flash like it is in many other processors.
+ */
+	.long	0x27051956		/* U-Boot Magic Number */
+
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION
+	.ascii " (", __DATE__, " - ", __TIME__, ")"
+	.ascii " ", CONFIG_IDENT_STRING, "\0"
+
 
 #ifndef CONFIG_DEFAULT_IMMR
 #error CONFIG_DEFAULT_IMMR must be defined
 #endif /* CFG_DEFAULT_IMMR */
-#ifndef CFG_IMMRBAR
-#define CFG_IMMRBAR CONFIG_DEFAULT_IMMR
-#endif /* CFG_IMMRBAR */
+#ifndef CFG_IMMR
+#define CFG_IMMR CONFIG_DEFAULT_IMMR
+#endif /* CFG_IMMR */
 
 /*
  * After configuration, a system reset exception is executed using the
@@ -152,8 +156,8 @@ boot_cold: /* time t 3 */
 	nop
 boot_warm: /* time t 5 */
 	mfmsr	r5			/* save msr contents	*/
-	lis	r3, CFG_IMMRBAR@h
-	ori	r3, r3, CFG_IMMRBAR@l
+	lis	r3, CFG_IMMR@h
+	ori	r3, r3, CFG_IMMR@l
 	stw	r3, IMMRBAR(r4)
 
 	/* Initialise the E300 processor core		*/
@@ -226,7 +230,7 @@ in_flash:
 	GET_GOT			/* initialize GOT access	*/
 
 	/* r3: IMMR */
-	lis	r3, CFG_IMMRBAR@h
+	lis	r3, CFG_IMMR@h
 	/* run low-level CPU init code (in Flash)*/
 	bl	cpu_init_f
 
@@ -446,7 +450,7 @@ init_e300_core: /* time t 10 */
 	mtspr	SRR1, r3			/* Make SRR1 match MSR */
 
 
-	lis	r3, CFG_IMMRBAR@h
+	lis	r3, CFG_IMMR@h
 #if defined(CONFIG_WATCHDOG)
 	/* Initialise the Wathcdog values and reset it (if req) */
 	/*------------------------------------------------------*/
@@ -870,6 +874,18 @@ ppcDcbz:
 	dcbz	r0,r3
 	blr
 
+	.globl	ppcDWstore
+ppcDWstore:
+	lfd	1, 0(r4)
+	stfd	1, 0(r3)
+	blr
+
+	.globl	ppcDWload
+ppcDWload:
+	lfd	1, 0(r3)
+	stfd	1, 0(r4)
+	blr
+
 /*-------------------------------------------------------------------*/
 
 /*
@@ -1189,7 +1205,7 @@ map_flash_by_law1:
 	/* When booting from ROM (Flash or EPROM), clear the  */
 	/* Address Mask in OR0 so ROM appears everywhere      */
 	/*----------------------------------------------------*/
-	lis	r3, (CFG_IMMRBAR)@h  /* r3 <= CFG_IMMRBAR    */
+	lis	r3, (CFG_IMMR)@h  /* r3 <= CFG_IMMR    */
 	lwz	r4, OR0@l(r3)
 	li	r5, 0x7fff        /* r5 <= 0x00007FFFF */
 	and	r4, r4, r5
@@ -1214,8 +1230,15 @@ map_flash_by_law1:
 	lis r4, (CFG_FLASH_BASE)@h
 	ori r4, r4, (CFG_FLASH_BASE)@l
 	stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
-	lis r4, (0x80000016)@h
-	ori r4, r4, (0x80000016)@l
+
+	/* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */
+	lis r4, (0x80000012)@h
+	ori r4, r4, (0x80000012)@l
+	li r5, CFG_FLASH_SIZE
+1:	srawi. r5, r5, 1	/* r5 = r5 >> 1 */
+	addi r4, r4, 1
+	bne 1b
+
 	stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
 	blr
 
@@ -1234,17 +1257,23 @@ remap_flash_by_law0:
 	stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
 
 	lwz r4, OR0(r3)
-	lis r5, 0xFF80 /* 8M */
+	lis r5, ~((CFG_FLASH_SIZE << 4) - 1)
 	or r4, r4, r5
-	stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */
+	stw r4, OR0(r3)
 
 	lis r4, (CFG_FLASH_BASE)@h
 	ori r4, r4, (CFG_FLASH_BASE)@l
 	stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */
 
-	lis r4, (0x80000016)@h
-	ori r4, r4, (0x80000016)@l
-	stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */
+	/* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR0 */
+	lis r4, (0x80000012)@h
+	ori r4, r4, (0x80000012)@l
+	li r5, CFG_FLASH_SIZE
+1:	srawi. r5, r5, 1 /* r5 = r5 >> 1 */
+	addi r4, r4, 1
+	bne 1b
+	stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
+
 
 	xor r4, r4, r4
 	stw r4, LBLAWBAR1(r3)
diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c
index 44345af..152fa73 100644
--- a/cpu/mpc83xx/traps.c
+++ b/cpu/mpc83xx/traps.c
@@ -1,5 +1,8 @@
 /*
- * linux/arch/ppc/kernel/traps.c
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -15,19 +18,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
- * Change log:
- *
- * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
- *
- * Modified by Cort Dougan (cort@cs.nmt.edu)
- * and Paul Mackerras (paulus@cs.anu.edu.au)
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- *           Initial file creating (porting from 85XX & 8260)
  */
 
 /*
diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index 8ae584f..ffc898c 100644
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -227,8 +227,16 @@ static int smc_init (void)
 	sp->smc_smcm = 0;
 	sp->smc_smce = 0xff;
 
-#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */
-	*((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff;
+#ifdef CFG_SPC1920_SMC1_CLK4
+	/* clock source is PLD */
+
+	/* set freq to 19200 Baud */
+	*((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3;
+	/* configure clk4 as input */
+	im->im_ioport.iop_pdpar |= 0x800;
+	im->im_ioport.iop_pddir &= ~0x800;
+
+	cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
 #else
 	/* Set up the baud rate generator */
 	smc_setbrg ();
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 03128d3..7134355 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -380,7 +380,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
 	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
 }
 
-#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
+#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SOLIDCARD3))
 
 /*
  *As is these functs get called out of flash Not a horrible
@@ -475,7 +475,11 @@ void pci_440_init (struct pci_controller *hose)
 	pci_set_region(hose->regions + reg_num++,
 		       CFG_PCI_TARGBASE,
 		       CFG_PCI_MEMBASE,
+#ifdef CFG_PCI_MEMSIZE
+		       CFG_PCI_MEMSIZE,
+#else
 		       0x10000000,
+#endif
 		       PCI_REGION_MEM );
 
 #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c
new file mode 100644
index 0000000..19c4f76
--- /dev/null
+++ b/cpu/ppc4xx/40x_spd_sdram.c
@@ -0,0 +1,469 @@
+/*
+ * cpu/ppc4xx/40x_spd_sdram.c
+ * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
+ * SDRAM controller. Those are all current 405 PPC's.
+ *
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
+ *
+ * Based on code by:
+ *
+ * Kenneth Johansson ,Ericsson AB.
+ * kenneth.johansson@etx.ericsson.se
+ *
+ * hacked up by bill hunter. fixed so we could run before
+ * serial_init and console_init. previous version avoided this by
+ * running out of cache memory during serial/console init, then running
+ * this code later.
+ *
+ * (C) Copyright 2002
+ * Jun Gu, Artesyn Technology, jung@artesyncp.com
+ * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <ppc4xx.h>
+
+#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
+
+/*
+ * Set default values
+ */
+#ifndef CFG_I2C_SPEED
+#define CFG_I2C_SPEED	50000
+#endif
+
+#ifndef CFG_I2C_SLAVE
+#define CFG_I2C_SLAVE	0xFE
+#endif
+
+#define ONE_BILLION	1000000000
+
+#define	 SDRAM0_CFG_DCE		0x80000000
+#define	 SDRAM0_CFG_SRE		0x40000000
+#define	 SDRAM0_CFG_PME		0x20000000
+#define	 SDRAM0_CFG_MEMCHK	0x10000000
+#define	 SDRAM0_CFG_REGEN	0x08000000
+#define	 SDRAM0_CFG_ECCDD	0x00400000
+#define	 SDRAM0_CFG_EMDULR	0x00200000
+#define	 SDRAM0_CFG_DRW_SHIFT	(31-6)
+#define	 SDRAM0_CFG_BRPF_SHIFT	(31-8)
+
+#define	 SDRAM0_TR_CASL_SHIFT	(31-8)
+#define	 SDRAM0_TR_PTA_SHIFT	(31-13)
+#define	 SDRAM0_TR_CTP_SHIFT	(31-15)
+#define	 SDRAM0_TR_LDF_SHIFT	(31-17)
+#define	 SDRAM0_TR_RFTA_SHIFT	(31-29)
+#define	 SDRAM0_TR_RCD_SHIFT	(31-31)
+
+#define	 SDRAM0_RTR_SHIFT	(31-15)
+#define	 SDRAM0_ECCCFG_SHIFT	(31-11)
+
+/* SDRAM0_CFG enable macro  */
+#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
+
+#define SDRAM0_BXCR_SZ_MASK	0x000e0000
+#define SDRAM0_BXCR_AM_MASK	0x0000e000
+
+#define SDRAM0_BXCR_SZ_SHIFT	(31-14)
+#define SDRAM0_BXCR_AM_SHIFT	(31-18)
+
+#define SDRAM0_BXCR_SZ(x)	( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
+#define SDRAM0_BXCR_AM(x)	( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
+
+#ifdef CONFIG_SPDDRAM_SILENT
+# define SPD_ERR(x) do { return 0; } while (0)
+#else
+# define SPD_ERR(x) do { printf(x); return(0); } while (0)
+#endif
+
+#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
+
+/* function prototypes */
+int spd_read(uint addr);
+
+
+/*
+ * This function is reading data from the DIMM module EEPROM over the SPD bus
+ * and uses that to program the sdram controller.
+ *
+ * This works on boards that has the same schematics that the AMCC walnut has.
+ *
+ * Input: null for default I2C spd functions or a pointer to a custom function
+ * returning spd_data.
+ */
+
+long int spd_sdram(int(read_spd)(uint addr))
+{
+	int tmp,row,col;
+	int total_size,bank_size,bank_code;
+	int ecc_on;
+	int mode;
+	int bank_cnt;
+
+	int sdram0_pmit=0x07c00000;
+#ifndef CONFIG_405EP /* not on PPC405EP */
+	int sdram0_besr0=-1;
+	int sdram0_besr1=-1;
+	int sdram0_eccesr=-1;
+#endif
+	int sdram0_ecccfg;
+
+	int sdram0_rtr=0;
+	int sdram0_tr=0;
+
+	int sdram0_b0cr;
+	int sdram0_b1cr;
+	int sdram0_b2cr;
+	int sdram0_b3cr;
+
+	int sdram0_cfg=0;
+
+	int t_rp;
+	int t_rcd;
+	int t_ras;
+	int t_rc;
+	int min_cas;
+
+	PPC405_SYS_INFO sys_info;
+	unsigned long bus_period_x_10;
+
+	/*
+	 * get the board info
+	 */
+	get_sys_info(&sys_info);
+	bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
+
+	if (read_spd == 0){
+		read_spd=spd_read;
+		/*
+		 * Make sure I2C controller is initialized
+		 * before continuing.
+		 */
+		i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	}
+
+	/* Make shure we are using SDRAM */
+	if (read_spd(2) != 0x04) {
+		SPD_ERR("SDRAM - non SDRAM memory module found\n");
+	}
+
+	/* ------------------------------------------------------------------
+	 * configure memory timing register
+	 *
+	 * data from DIMM:
+	 * 27	IN Row Precharge Time ( t RP)
+	 * 29	MIN RAS to CAS Delay ( t RCD)
+	 * 127	 Component and Clock Detail ,clk0-clk3, junction temp, CAS
+	 * -------------------------------------------------------------------*/
+
+	/*
+	 * first figure out which cas latency mode to use
+	 * use the min supported mode
+	 */
+
+	tmp = read_spd(127) & 0x6;
+	if (tmp == 0x02) {		/* only cas = 2 supported */
+		min_cas = 2;
+/*		t_ck = read_spd(9); */
+/*		t_ac = read_spd(10); */
+	} else if (tmp == 0x04) {	/* only cas = 3 supported */
+		min_cas = 3;
+/*		t_ck = read_spd(9); */
+/*		t_ac = read_spd(10); */
+	} else if (tmp == 0x06) {	/* 2,3 supported, so use 2 */
+		min_cas = 2;
+/*		t_ck = read_spd(23); */
+/*		t_ac = read_spd(24); */
+	} else {
+		SPD_ERR("SDRAM - unsupported CAS latency \n");
+	}
+
+	/* get some timing values, t_rp,t_rcd,t_ras,t_rc
+	 */
+	t_rp = read_spd(27);
+	t_rcd = read_spd(29);
+	t_ras = read_spd(30);
+	t_rc = t_ras + t_rp;
+
+	/* The following timing calcs subtract 1 before deviding.
+	 * this has effect of using ceiling instead of floor rounding,
+	 * and also subtracting 1 to convert number to reg value
+	 */
+	/* set up CASL */
+	sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
+	/* set up PTA */
+	sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
+	/* set up CTP */
+	tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
+	if (tmp < 1)
+		tmp = 1;
+	sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
+	/* set LDF	= 2 cycles, reg value = 1 */
+	sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
+	/* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
+	tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
+	if (tmp < 0)
+		tmp = 0;
+	if (tmp > 6)
+		tmp = 6;
+	sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
+	/* set RCD = t_rcd/bus_period*/
+	sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
+
+
+	/*------------------------------------------------------------------
+	 * configure RTR register
+	 * -------------------------------------------------------------------*/
+	row = read_spd(3);
+	col = read_spd(4);
+	tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
+	switch (tmp) {
+	case 0x00:
+		tmp = 15625;
+		break;
+	case 0x01:
+		tmp = 15625 / 4;
+		break;
+	case 0x02:
+		tmp = 15625 / 2;
+		break;
+	case 0x03:
+		tmp = 15625 * 2;
+		break;
+	case 0x04:
+		tmp = 15625 * 4;
+		break;
+	case 0x05:
+		tmp = 15625 * 8;
+		break;
+	default:
+		SPD_ERR("SDRAM - Bad refresh period \n");
+	}
+	/* convert from nsec to bus cycles */
+	tmp = (tmp * 10) / bus_period_x_10;
+	sdram0_rtr = (tmp & 0x3ff8) <<	SDRAM0_RTR_SHIFT;
+
+	/*------------------------------------------------------------------
+	 * determine the number of banks used
+	 * -------------------------------------------------------------------*/
+	/* byte 7:6 is module data width */
+	if (read_spd(7) != 0)
+		SPD_ERR("SDRAM - unsupported module width\n");
+	tmp = read_spd(6);
+	if (tmp < 32)
+		SPD_ERR("SDRAM - unsupported module width\n");
+	else if (tmp < 64)
+		bank_cnt = 1;		/* one bank per sdram side */
+	else if (tmp < 73)
+		bank_cnt = 2;	/* need two banks per side */
+	else if (tmp < 161)
+		bank_cnt = 4;	/* need four banks per side */
+	else
+		SPD_ERR("SDRAM - unsupported module width\n");
+
+	/* byte 5 is the module row count (refered to as dimm "sides") */
+	tmp = read_spd(5);
+	if (tmp == 1)
+		;
+	else if (tmp==2)
+		bank_cnt *= 2;
+	else if (tmp==4)
+		bank_cnt *= 4;
+	else
+		bank_cnt = 8;		/* 8 is an error code */
+
+	if (bank_cnt > 4)	/* we only have 4 banks to work with */
+		SPD_ERR("SDRAM - unsupported module rows for this width\n");
+
+	/* now check for ECC ability of module. We only support ECC
+	 *   on 32 bit wide devices with 8 bit ECC.
+	 */
+	if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
+		sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
+		ecc_on = 1;
+	} else {
+		sdram0_ecccfg = 0;
+		ecc_on = 0;
+	}
+
+	/*------------------------------------------------------------------
+	 * calculate total size
+	 * -------------------------------------------------------------------*/
+	/* calculate total size and do sanity check */
+	tmp = read_spd(31);
+	total_size = 1 << 22;	/* total_size = 4MB */
+	/* now multiply 4M by the smallest device row density */
+	/* note that we don't support asymetric rows */
+	while (((tmp & 0x0001) == 0) && (tmp != 0)) {
+		total_size = total_size << 1;
+		tmp = tmp >> 1;
+	}
+	total_size *= read_spd(5);	/* mult by module rows (dimm sides) */
+
+	/*------------------------------------------------------------------
+	 * map	rows * cols * banks to a mode
+	 * -------------------------------------------------------------------*/
+
+	switch (row) {
+	case 11:
+		switch (col) {
+		case 8:
+			mode=4; /* mode 5 */
+			break;
+		case 9:
+		case 10:
+			mode=0; /* mode 1 */
+			break;
+		default:
+			SPD_ERR("SDRAM - unsupported mode\n");
+		}
+		break;
+	case 12:
+		switch (col) {
+		case 8:
+			mode=3; /* mode 4 */
+			break;
+		case 9:
+		case 10:
+			mode=1; /* mode 2 */
+			break;
+		default:
+			SPD_ERR("SDRAM - unsupported mode\n");
+		}
+		break;
+	case 13:
+		switch (col) {
+		case 8:
+			mode=5; /* mode 6 */
+			break;
+		case 9:
+		case 10:
+			if (read_spd(17) == 2)
+				mode = 6; /* mode 7 */
+			else
+				mode = 2; /* mode 3 */
+			break;
+		case 11:
+			mode = 2; /* mode 3 */
+			break;
+		default:
+			SPD_ERR("SDRAM - unsupported mode\n");
+		}
+		break;
+	default:
+		SPD_ERR("SDRAM - unsupported mode\n");
+	}
+
+	/*------------------------------------------------------------------
+	 * using the calculated values, compute the bank
+	 * config register values.
+	 * -------------------------------------------------------------------*/
+	sdram0_b1cr = 0;
+	sdram0_b2cr = 0;
+	sdram0_b3cr = 0;
+
+	/* compute the size of each bank */
+	bank_size = total_size / bank_cnt;
+	/* convert bank size to bank size code for ppc4xx
+	   by takeing log2(bank_size) - 22 */
+	tmp = bank_size;		/* start with tmp = bank_size */
+	bank_code = 0;			/* and bank_code = 0 */
+	while (tmp > 1) {		/* this takes log2 of tmp */
+		bank_code++;		/* and stores result in bank_code */
+		tmp = tmp >> 1;
+	}				/* bank_code is now log2(bank_size) */
+	bank_code -= 22;		/* subtract 22 to get the code */
+
+	tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
+	sdram0_b0cr = (bank_size * 0) | tmp;
+#ifndef CONFIG_405EP /* not on PPC405EP */
+	if (bank_cnt > 1)
+		sdram0_b2cr = (bank_size * 1) | tmp;
+	if (bank_cnt > 2)
+		sdram0_b1cr = (bank_size * 2) | tmp;
+	if (bank_cnt > 3)
+		sdram0_b3cr = (bank_size * 3) | tmp;
+#else
+	/* PPC405EP chip only supports two SDRAM banks */
+	if (bank_cnt > 1)
+		sdram0_b1cr = (bank_size * 1) | tmp;
+	if (bank_cnt > 2)
+		total_size = 2 * bank_size;
+#endif
+
+	/*
+	 *   enable sdram controller DCE=1
+	 *  enable burst read prefetch to 32 bytes BRPF=2
+	 *  leave other functions off
+	 */
+
+	/*------------------------------------------------------------------
+	 * now that we've done our calculations, we are ready to
+	 * program all the registers.
+	 * -------------------------------------------------------------------*/
+
+#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+	/* disable memcontroller so updates work */
+	mtsdram0( mem_mcopt1, 0 );
+
+#ifndef CONFIG_405EP /* not on PPC405EP */
+	mtsdram0( mem_besra , sdram0_besr0 );
+	mtsdram0( mem_besrb , sdram0_besr1 );
+	mtsdram0( mem_ecccf , sdram0_ecccfg );
+	mtsdram0( mem_eccerr, sdram0_eccesr );
+#endif
+	mtsdram0( mem_rtr   , sdram0_rtr );
+	mtsdram0( mem_pmit  , sdram0_pmit );
+	mtsdram0( mem_mb0cf , sdram0_b0cr );
+	mtsdram0( mem_mb1cf , sdram0_b1cr );
+#ifndef CONFIG_405EP /* not on PPC405EP */
+	mtsdram0( mem_mb2cf , sdram0_b2cr );
+	mtsdram0( mem_mb3cf , sdram0_b3cr );
+#endif
+	mtsdram0( mem_sdtr1 , sdram0_tr );
+
+	/* SDRAM have a power on delay,	 500 micro should do */
+	udelay(500);
+	sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
+	if (ecc_on)
+		sdram0_cfg |= SDRAM0_CFG_MEMCHK;
+	mtsdram0(mem_mcopt1, sdram0_cfg);
+
+	return (total_size);
+}
+
+int spd_read(uint addr)
+{
+	uchar data[2];
+
+	if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
+		return (int)data[0];
+	else
+		return 0;
+}
+
+#endif /* CONFIG_SPD_EEPROM */
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index 6130cd2..d6c4be5 100644
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -26,10 +26,9 @@
 #include <common.h>
 #include <pci.h>
 
-#include "440spe_pcie.h"
+#if defined(CONFIG_440SPE) && defined(CONFIG_PCI)
 
-#if defined(CONFIG_440SPE)
-#if defined(CONFIG_PCI)
+#include "440spe_pcie.h"
 
 enum {
 	PTYPE_ENDPOINT		= 0x0,
@@ -958,5 +957,4 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
 
 	return 0;
 }
-#endif /* CONFIG_PCI */
-#endif /* CONFIG_440SPE */
+#endif /* CONFIG_440SPE && CONFIG_PCI */
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/44x_spd_ddr.c
index c24456b..10b4c18 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -1,4 +1,8 @@
 /*
+ * cpu/ppc4xx/44x_spd_ddr.c
+ * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
+ * DDR controller. Those are 440GP/GX/EP/GR.
+ *
  * (C) Copyright 2001
  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
  *
@@ -42,8 +46,11 @@
 #include <asm/processor.h>
 #include <i2c.h>
 #include <ppc4xx.h>
+#include <asm/mmu.h>
 
-#ifdef CONFIG_SPD_EEPROM
+#if defined(CONFIG_SPD_EEPROM) &&					\
+	(defined(CONFIG_440GP) || defined(CONFIG_440GX) ||		\
+	 defined(CONFIG_440EP) || defined(CONFIG_440GR))
 
 /*
  * Set default values
@@ -58,414 +65,6 @@
 
 #define ONE_BILLION	1000000000
 
-#ifndef	 CONFIG_440		/* for 405 WALNUT/SYCAMORE/BUBINGA boards */
-
-#define	 SDRAM0_CFG_DCE		0x80000000
-#define	 SDRAM0_CFG_SRE		0x40000000
-#define	 SDRAM0_CFG_PME		0x20000000
-#define	 SDRAM0_CFG_MEMCHK	0x10000000
-#define	 SDRAM0_CFG_REGEN	0x08000000
-#define	 SDRAM0_CFG_ECCDD	0x00400000
-#define	 SDRAM0_CFG_EMDULR	0x00200000
-#define	 SDRAM0_CFG_DRW_SHIFT	(31-6)
-#define	 SDRAM0_CFG_BRPF_SHIFT	(31-8)
-
-#define	 SDRAM0_TR_CASL_SHIFT	(31-8)
-#define	 SDRAM0_TR_PTA_SHIFT	(31-13)
-#define	 SDRAM0_TR_CTP_SHIFT	(31-15)
-#define	 SDRAM0_TR_LDF_SHIFT	(31-17)
-#define	 SDRAM0_TR_RFTA_SHIFT	(31-29)
-#define	 SDRAM0_TR_RCD_SHIFT	(31-31)
-
-#define	 SDRAM0_RTR_SHIFT	(31-15)
-#define	 SDRAM0_ECCCFG_SHIFT	(31-11)
-
-/* SDRAM0_CFG enable macro  */
-#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
-
-#define SDRAM0_BXCR_SZ_MASK	0x000e0000
-#define SDRAM0_BXCR_AM_MASK	0x0000e000
-
-#define SDRAM0_BXCR_SZ_SHIFT	(31-14)
-#define SDRAM0_BXCR_AM_SHIFT	(31-18)
-
-#define SDRAM0_BXCR_SZ(x)	( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
-#define SDRAM0_BXCR_AM(x)	( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
-
-#ifdef CONFIG_SPDDRAM_SILENT
-# define SPD_ERR(x) do { return 0; } while (0)
-#else
-# define SPD_ERR(x) do { printf(x); return(0); } while (0)
-#endif
-
-#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
-
-/* function prototypes */
-int spd_read(uint addr);
-
-
-/*
- * This function is reading data from the DIMM module EEPROM over the SPD bus
- * and uses that to program the sdram controller.
- *
- * This works on boards that has the same schematics that the AMCC walnut has.
- *
- * Input: null for default I2C spd functions or a pointer to a custom function
- * returning spd_data.
- */
-
-long int spd_sdram(int(read_spd)(uint addr))
-{
-	int tmp,row,col;
-	int total_size,bank_size,bank_code;
-	int ecc_on;
-	int mode;
-	int bank_cnt;
-
-	int sdram0_pmit=0x07c00000;
-#ifndef CONFIG_405EP /* not on PPC405EP */
-	int sdram0_besr0=-1;
-	int sdram0_besr1=-1;
-	int sdram0_eccesr=-1;
-#endif
-	int sdram0_ecccfg;
-
-	int sdram0_rtr=0;
-	int sdram0_tr=0;
-
-	int sdram0_b0cr;
-	int sdram0_b1cr;
-	int sdram0_b2cr;
-	int sdram0_b3cr;
-
-	int sdram0_cfg=0;
-
-	int t_rp;
-	int t_rcd;
-	int t_ras;
-	int t_rc;
-	int min_cas;
-
-	PPC405_SYS_INFO sys_info;
-	unsigned long bus_period_x_10;
-
-	/*
-	 * get the board info
-	 */
-	get_sys_info(&sys_info);
-	bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
-
-	if (read_spd == 0){
-		read_spd=spd_read;
-		/*
-		 * Make sure I2C controller is initialized
-		 * before continuing.
-		 */
-		i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
-	}
-
-	/* Make shure we are using SDRAM */
-	if (read_spd(2) != 0x04) {
-		SPD_ERR("SDRAM - non SDRAM memory module found\n");
-	}
-
-	/* ------------------------------------------------------------------
-	 * configure memory timing register
-	 *
-	 * data from DIMM:
-	 * 27	IN Row Precharge Time ( t RP)
-	 * 29	MIN RAS to CAS Delay ( t RCD)
-	 * 127	 Component and Clock Detail ,clk0-clk3, junction temp, CAS
-	 * -------------------------------------------------------------------*/
-
-	/*
-	 * first figure out which cas latency mode to use
-	 * use the min supported mode
-	 */
-
-	tmp = read_spd(127) & 0x6;
-	if (tmp == 0x02) {		/* only cas = 2 supported */
-		min_cas = 2;
-/*		t_ck = read_spd(9); */
-/*		t_ac = read_spd(10); */
-	} else if (tmp == 0x04) {	/* only cas = 3 supported */
-		min_cas = 3;
-/*		t_ck = read_spd(9); */
-/*		t_ac = read_spd(10); */
-	} else if (tmp == 0x06) {	/* 2,3 supported, so use 2 */
-		min_cas = 2;
-/*		t_ck = read_spd(23); */
-/*		t_ac = read_spd(24); */
-	} else {
-		SPD_ERR("SDRAM - unsupported CAS latency \n");
-	}
-
-	/* get some timing values, t_rp,t_rcd,t_ras,t_rc
-	 */
-	t_rp = read_spd(27);
-	t_rcd = read_spd(29);
-	t_ras = read_spd(30);
-	t_rc = t_ras + t_rp;
-
-	/* The following timing calcs subtract 1 before deviding.
-	 * this has effect of using ceiling instead of floor rounding,
-	 * and also subtracting 1 to convert number to reg value
-	 */
-	/* set up CASL */
-	sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
-	/* set up PTA */
-	sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
-	/* set up CTP */
-	tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
-	if (tmp < 1)
-		tmp = 1;
-	sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
-	/* set LDF	= 2 cycles, reg value = 1 */
-	sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
-	/* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
-	tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
-	if (tmp < 0)
-		tmp = 0;
-	if (tmp > 6)
-		tmp = 6;
-	sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
-	/* set RCD = t_rcd/bus_period*/
-	sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
-
-
-	/*------------------------------------------------------------------
-	 * configure RTR register
-	 * -------------------------------------------------------------------*/
-	row = read_spd(3);
-	col = read_spd(4);
-	tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
-	switch (tmp) {
-	case 0x00:
-		tmp = 15625;
-		break;
-	case 0x01:
-		tmp = 15625 / 4;
-		break;
-	case 0x02:
-		tmp = 15625 / 2;
-		break;
-	case 0x03:
-		tmp = 15625 * 2;
-		break;
-	case 0x04:
-		tmp = 15625 * 4;
-		break;
-	case 0x05:
-		tmp = 15625 * 8;
-		break;
-	default:
-		SPD_ERR("SDRAM - Bad refresh period \n");
-	}
-	/* convert from nsec to bus cycles */
-	tmp = (tmp * 10) / bus_period_x_10;
-	sdram0_rtr = (tmp & 0x3ff8) <<	SDRAM0_RTR_SHIFT;
-
-	/*------------------------------------------------------------------
-	 * determine the number of banks used
-	 * -------------------------------------------------------------------*/
-	/* byte 7:6 is module data width */
-	if (read_spd(7) != 0)
-		SPD_ERR("SDRAM - unsupported module width\n");
-	tmp = read_spd(6);
-	if (tmp < 32)
-		SPD_ERR("SDRAM - unsupported module width\n");
-	else if (tmp < 64)
-		bank_cnt = 1;		/* one bank per sdram side */
-	else if (tmp < 73)
-		bank_cnt = 2;	/* need two banks per side */
-	else if (tmp < 161)
-		bank_cnt = 4;	/* need four banks per side */
-	else
-		SPD_ERR("SDRAM - unsupported module width\n");
-
-	/* byte 5 is the module row count (refered to as dimm "sides") */
-	tmp = read_spd(5);
-	if (tmp == 1)
-		;
-	else if (tmp==2)
-		bank_cnt *= 2;
-	else if (tmp==4)
-		bank_cnt *= 4;
-	else
-		bank_cnt = 8;		/* 8 is an error code */
-
-	if (bank_cnt > 4)	/* we only have 4 banks to work with */
-		SPD_ERR("SDRAM - unsupported module rows for this width\n");
-
-	/* now check for ECC ability of module. We only support ECC
-	 *   on 32 bit wide devices with 8 bit ECC.
-	 */
-	if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
-		sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
-		ecc_on = 1;
-	} else {
-		sdram0_ecccfg = 0;
-		ecc_on = 0;
-	}
-
-	/*------------------------------------------------------------------
-	 * calculate total size
-	 * -------------------------------------------------------------------*/
-	/* calculate total size and do sanity check */
-	tmp = read_spd(31);
-	total_size = 1 << 22;	/* total_size = 4MB */
-	/* now multiply 4M by the smallest device row density */
-	/* note that we don't support asymetric rows */
-	while (((tmp & 0x0001) == 0) && (tmp != 0)) {
-		total_size = total_size << 1;
-		tmp = tmp >> 1;
-	}
-	total_size *= read_spd(5);	/* mult by module rows (dimm sides) */
-
-	/*------------------------------------------------------------------
-	 * map	rows * cols * banks to a mode
-	 * -------------------------------------------------------------------*/
-
-	switch (row) {
-	case 11:
-		switch (col) {
-		case 8:
-			mode=4; /* mode 5 */
-			break;
-		case 9:
-		case 10:
-			mode=0; /* mode 1 */
-			break;
-		default:
-			SPD_ERR("SDRAM - unsupported mode\n");
-		}
-		break;
-	case 12:
-		switch (col) {
-		case 8:
-			mode=3; /* mode 4 */
-			break;
-		case 9:
-		case 10:
-			mode=1; /* mode 2 */
-			break;
-		default:
-			SPD_ERR("SDRAM - unsupported mode\n");
-		}
-		break;
-	case 13:
-		switch (col) {
-		case 8:
-			mode=5; /* mode 6 */
-			break;
-		case 9:
-		case 10:
-			if (read_spd(17) == 2)
-				mode = 6; /* mode 7 */
-			else
-				mode = 2; /* mode 3 */
-			break;
-		case 11:
-			mode = 2; /* mode 3 */
-			break;
-		default:
-			SPD_ERR("SDRAM - unsupported mode\n");
-		}
-		break;
-	default:
-		SPD_ERR("SDRAM - unsupported mode\n");
-	}
-
-	/*------------------------------------------------------------------
-	 * using the calculated values, compute the bank
-	 * config register values.
-	 * -------------------------------------------------------------------*/
-	sdram0_b1cr = 0;
-	sdram0_b2cr = 0;
-	sdram0_b3cr = 0;
-
-	/* compute the size of each bank */
-	bank_size = total_size / bank_cnt;
-	/* convert bank size to bank size code for ppc4xx
-	   by takeing log2(bank_size) - 22 */
-	tmp = bank_size;		/* start with tmp = bank_size */
-	bank_code = 0;			/* and bank_code = 0 */
-	while (tmp > 1) {		/* this takes log2 of tmp */
-		bank_code++;		/* and stores result in bank_code */
-		tmp = tmp >> 1;
-	}				/* bank_code is now log2(bank_size) */
-	bank_code -= 22;		/* subtract 22 to get the code */
-
-	tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
-	sdram0_b0cr = (bank_size * 0) | tmp;
-#ifndef CONFIG_405EP /* not on PPC405EP */
-	if (bank_cnt > 1)
-		sdram0_b2cr = (bank_size * 1) | tmp;
-	if (bank_cnt > 2)
-		sdram0_b1cr = (bank_size * 2) | tmp;
-	if (bank_cnt > 3)
-		sdram0_b3cr = (bank_size * 3) | tmp;
-#else
-	/* PPC405EP chip only supports two SDRAM banks */
-	if (bank_cnt > 1)
-		sdram0_b1cr = (bank_size * 1) | tmp;
-	if (bank_cnt > 2)
-		total_size = 2 * bank_size;
-#endif
-
-	/*
-	 *   enable sdram controller DCE=1
-	 *  enable burst read prefetch to 32 bytes BRPF=2
-	 *  leave other functions off
-	 */
-
-	/*------------------------------------------------------------------
-	 * now that we've done our calculations, we are ready to
-	 * program all the registers.
-	 * -------------------------------------------------------------------*/
-
-#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
-	/* disable memcontroller so updates work */
-	mtsdram0( mem_mcopt1, 0 );
-
-#ifndef CONFIG_405EP /* not on PPC405EP */
-	mtsdram0( mem_besra , sdram0_besr0 );
-	mtsdram0( mem_besrb , sdram0_besr1 );
-	mtsdram0( mem_ecccf , sdram0_ecccfg );
-	mtsdram0( mem_eccerr, sdram0_eccesr );
-#endif
-	mtsdram0( mem_rtr   , sdram0_rtr );
-	mtsdram0( mem_pmit  , sdram0_pmit );
-	mtsdram0( mem_mb0cf , sdram0_b0cr );
-	mtsdram0( mem_mb1cf , sdram0_b1cr );
-#ifndef CONFIG_405EP /* not on PPC405EP */
-	mtsdram0( mem_mb2cf , sdram0_b2cr );
-	mtsdram0( mem_mb3cf , sdram0_b3cr );
-#endif
-	mtsdram0( mem_sdtr1 , sdram0_tr );
-
-	/* SDRAM have a power on delay,	 500 micro should do */
-	udelay(500);
-	sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
-	if (ecc_on)
-		sdram0_cfg |= SDRAM0_CFG_MEMCHK;
-	mtsdram0(mem_mcopt1, sdram0_cfg);
-
-	return (total_size);
-}
-
-int spd_read(uint addr)
-{
-	uchar data[2];
-
-	if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
-		return (int)data[0];
-	else
-		return 0;
-}
-
-#else /* CONFIG_440 */
-
 /*-----------------------------------------------------------------------------
   |  Memory Controller Options 0
   +-----------------------------------------------------------------------------*/
@@ -631,6 +230,22 @@ int spd_read(uint addr)
 #define TRUE			1
 #define FALSE			0
 
+/*
+ * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
+ * region. Right now the cache should still be disabled in U-Boot because of the
+ * EMAC driver, that need it's buffer descriptor to be located in non cached
+ * memory.
+ *
+ * If at some time this restriction doesn't apply anymore, just define
+ * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * everything correctly.
+ */
+#ifdef CFG_ENABLE_SDRAM_CACHE
+#define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
+#else
+#define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
+#endif
+
 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 	{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 	 0xFFFFFFFF, 0xFFFFFFFF},
@@ -661,6 +276,7 @@ typedef struct bank_param BANKPARMS;
 #ifdef CFG_SIMULATE_SPD_EEPROM
 extern unsigned char cfg_simulate_spd_eeprom[128];
 #endif
+void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
 
 unsigned char spd_read(uchar chip, uint addr);
 
@@ -779,6 +395,11 @@ long int spd_sdram(void) {
 	total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 				  num_dimm_banks);
 
+#ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
+	/* and program tlb entries for this size (dynamic) */
+	program_tlb(0, total_size, MY_TLB_WORD2_I_ENABLE);
+#endif
+
 	/*
 	 * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 	 */
@@ -1732,11 +1353,11 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
 			 */
 			cr |= SDRAM_BXCR_SDBE;
 
-			for (i = 0; i < num_banks; i++) {
-				bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
+ 			for (i = 0; i < num_banks; i++) {
+				bank_parms[ctrl_bank_num[dimm_num]+i+dimm_num].bank_size_bytes =
 					(4 * 1024 * 1024) * bank_size_id;
-				bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
-			}
+				bank_parms[ctrl_bank_num[dimm_num]+i+dimm_num].cr = cr;
+ 			}
 		}
 	}
 
@@ -1825,7 +1446,4 @@ void program_ecc (unsigned long	 num_bytes)
 			SDRAM_CFG0_MCHK_CHK);
 	}
 }
-
-#endif /* CONFIG_440 */
-
 #endif /* CONFIG_SPD_EEPROM */
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
new file mode 100644
index 0000000..83c9911
--- /dev/null
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -0,0 +1,2954 @@
+/*
+ * cpu/ppc4xx/44x_spd_ddr2.c
+ * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
+ * DDR2 controller (non Denali Core). Those are 440SP/SPe.
+ *
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * COPYRIGHT   AMCC   CORPORATION 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <command.h>
+#include <ppc4xx.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+#if defined(CONFIG_SPD_EEPROM) &&				\
+	(defined(CONFIG_440SP) || defined(CONFIG_440SPE))
+
+/*-----------------------------------------------------------------------------+
+ * Defines
+ *-----------------------------------------------------------------------------*/
+#ifndef	TRUE
+#define TRUE		1
+#endif
+#ifndef FALSE
+#define FALSE		0
+#endif
+
+#define SDRAM_DDR1	1
+#define SDRAM_DDR2	2
+#define SDRAM_NONE	0
+
+#define MAXDIMMS 	2
+#define MAXRANKS 	4
+#define MAXBXCF		4
+#define MAX_SPD_BYTES	256   /* Max number of bytes on the DIMM's SPD EEPROM */
+
+#define ONE_BILLION	1000000000
+
+#define MULDIV64(m1, m2, d)	(u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
+
+#define CMD_NOP		(7 << 19)
+#define CMD_PRECHARGE	(2 << 19)
+#define CMD_REFRESH	(1 << 19)
+#define CMD_EMR		(0 << 19)
+#define CMD_READ	(5 << 19)
+#define CMD_WRITE	(4 << 19)
+
+#define SELECT_MR	(0 << 16)
+#define SELECT_EMR	(1 << 16)
+#define SELECT_EMR2	(2 << 16)
+#define SELECT_EMR3	(3 << 16)
+
+/* MR */
+#define DLL_RESET	0x00000100
+
+#define WRITE_RECOV_2	(1 << 9)
+#define WRITE_RECOV_3	(2 << 9)
+#define WRITE_RECOV_4	(3 << 9)
+#define WRITE_RECOV_5	(4 << 9)
+#define WRITE_RECOV_6	(5 << 9)
+
+#define BURST_LEN_4	0x00000002
+
+/* EMR */
+#define ODT_0_OHM	0x00000000
+#define ODT_50_OHM	0x00000044
+#define ODT_75_OHM	0x00000004
+#define ODT_150_OHM	0x00000040
+
+#define ODS_FULL	0x00000000
+#define ODS_REDUCED	0x00000002
+
+/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
+#define ODT_EB0R	(0x80000000 >> 8)
+#define ODT_EB0W	(0x80000000 >> 7)
+#define CALC_ODT_R(n)	(ODT_EB0R << (n << 1))
+#define CALC_ODT_W(n)	(ODT_EB0W << (n << 1))
+#define CALC_ODT_RW(n)	(CALC_ODT_R(n) | CALC_ODT_W(n))
+
+/* Defines for the Read Cycle Delay test */
+#define NUMMEMTESTS 8
+#define NUMMEMWORDS 8
+
+#define CONFIG_ECC_ERROR_RESET		/* test-only: see description below, at check_ecc() */
+
+/*
+ * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
+ * region. Right now the cache should still be disabled in U-Boot because of the
+ * EMAC driver, that need it's buffer descriptor to be located in non cached
+ * memory.
+ *
+ * If at some time this restriction doesn't apply anymore, just define
+ * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * everything correctly.
+ */
+#ifdef CFG_ENABLE_SDRAM_CACHE
+#define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
+#else
+#define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
+#endif
+
+/* Private Structure Definitions */
+
+/* enum only to ease code for cas latency setting */
+typedef enum ddr_cas_id {
+	DDR_CAS_2      = 20,
+	DDR_CAS_2_5    = 25,
+	DDR_CAS_3      = 30,
+	DDR_CAS_4      = 40,
+	DDR_CAS_5      = 50
+} ddr_cas_id_t;
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+static unsigned long sdram_memsize(void);
+void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
+static void get_spd_info(unsigned long *dimm_populated,
+			 unsigned char *iic0_dimm_addr,
+			 unsigned long num_dimm_banks);
+static void check_mem_type(unsigned long *dimm_populated,
+			   unsigned char *iic0_dimm_addr,
+			   unsigned long num_dimm_banks);
+static void check_frequency(unsigned long *dimm_populated,
+			    unsigned char *iic0_dimm_addr,
+			    unsigned long num_dimm_banks);
+static void check_rank_number(unsigned long *dimm_populated,
+			      unsigned char *iic0_dimm_addr,
+			      unsigned long num_dimm_banks);
+static void check_voltage_type(unsigned long *dimm_populated,
+			       unsigned char *iic0_dimm_addr,
+			       unsigned long num_dimm_banks);
+static void program_memory_queue(unsigned long *dimm_populated,
+				 unsigned char *iic0_dimm_addr,
+				 unsigned long num_dimm_banks);
+static void program_codt(unsigned long *dimm_populated,
+			 unsigned char *iic0_dimm_addr,
+			 unsigned long num_dimm_banks);
+static void program_mode(unsigned long *dimm_populated,
+			 unsigned char *iic0_dimm_addr,
+			 unsigned long num_dimm_banks,
+			 ddr_cas_id_t *selected_cas,
+			 int *write_recovery);
+static void program_tr(unsigned long *dimm_populated,
+		       unsigned char *iic0_dimm_addr,
+		       unsigned long num_dimm_banks);
+static void program_rtr(unsigned long *dimm_populated,
+			unsigned char *iic0_dimm_addr,
+			unsigned long num_dimm_banks);
+static void program_bxcf(unsigned long *dimm_populated,
+			 unsigned char *iic0_dimm_addr,
+			 unsigned long num_dimm_banks);
+static void program_copt1(unsigned long *dimm_populated,
+			  unsigned char *iic0_dimm_addr,
+			  unsigned long num_dimm_banks);
+static void program_initplr(unsigned long *dimm_populated,
+			    unsigned char *iic0_dimm_addr,
+			    unsigned long num_dimm_banks,
+			    ddr_cas_id_t selected_cas,
+			    int write_recovery);
+static unsigned long is_ecc_enabled(void);
+#ifdef CONFIG_DDR_ECC
+static void program_ecc(unsigned long *dimm_populated,
+			unsigned char *iic0_dimm_addr,
+			unsigned long num_dimm_banks,
+			unsigned long tlb_word2_i_value);
+static void program_ecc_addr(unsigned long start_address,
+			     unsigned long num_bytes,
+			     unsigned long tlb_word2_i_value);
+#endif
+static void program_DQS_calibration(unsigned long *dimm_populated,
+				    unsigned char *iic0_dimm_addr,
+				    unsigned long num_dimm_banks);
+#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
+static void	test(void);
+#else
+static void	DQS_calibration_process(void);
+#endif
+#if defined(DEBUG)
+static void ppc440sp_sdram_register_dump(void);
+#endif
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+void dcbz_area(u32 start_address, u32 num_bytes);
+void dflush(void);
+
+static u32 mfdcr_any(u32 dcr)
+{
+	u32 val;
+
+	switch (dcr) {
+	case SDRAM_R0BAS + 0:
+		val = mfdcr(SDRAM_R0BAS + 0);
+		break;
+	case SDRAM_R0BAS + 1:
+		val = mfdcr(SDRAM_R0BAS + 1);
+		break;
+	case SDRAM_R0BAS + 2:
+		val = mfdcr(SDRAM_R0BAS + 2);
+		break;
+	case SDRAM_R0BAS + 3:
+		val = mfdcr(SDRAM_R0BAS + 3);
+		break;
+	default:
+		printf("DCR %d not defined in case statement!!!\n", dcr);
+		val = 0; /* just to satisfy the compiler */
+	}
+
+	return val;
+}
+
+static void mtdcr_any(u32 dcr, u32 val)
+{
+	switch (dcr) {
+	case SDRAM_R0BAS + 0:
+		mtdcr(SDRAM_R0BAS + 0, val);
+		break;
+	case SDRAM_R0BAS + 1:
+		mtdcr(SDRAM_R0BAS + 1, val);
+		break;
+	case SDRAM_R0BAS + 2:
+		mtdcr(SDRAM_R0BAS + 2, val);
+		break;
+	case SDRAM_R0BAS + 3:
+		mtdcr(SDRAM_R0BAS + 3, val);
+		break;
+	default:
+		printf("DCR %d not defined in case statement!!!\n", dcr);
+	}
+}
+
+static unsigned char spd_read(uchar chip, uint addr)
+{
+	unsigned char data[2];
+
+	if (i2c_probe(chip) == 0)
+		if (i2c_read(chip, addr, 1, data, 1) == 0)
+			return data[0];
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------------+
+ * sdram_memsize
+ *-----------------------------------------------------------------------------*/
+static unsigned long sdram_memsize(void)
+{
+	unsigned long mem_size;
+	unsigned long mcopt2;
+	unsigned long mcstat;
+	unsigned long mb0cf;
+	unsigned long sdsz;
+	unsigned long i;
+
+	mem_size = 0;
+
+	mfsdram(SDRAM_MCOPT2, mcopt2);
+	mfsdram(SDRAM_MCSTAT, mcstat);
+
+	/* DDR controller must be enabled and not in self-refresh. */
+	/* Otherwise memsize is zero. */
+	if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
+	    && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
+	    && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
+		== (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
+		for (i = 0; i < MAXBXCF; i++) {
+			mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
+			/* Banks enabled */
+			if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
+				sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
+
+				switch(sdsz) {
+				case SDRAM_RXBAS_SDSZ_8:
+					mem_size+=8;
+					break;
+				case SDRAM_RXBAS_SDSZ_16:
+					mem_size+=16;
+					break;
+				case SDRAM_RXBAS_SDSZ_32:
+					mem_size+=32;
+					break;
+				case SDRAM_RXBAS_SDSZ_64:
+					mem_size+=64;
+					break;
+				case SDRAM_RXBAS_SDSZ_128:
+					mem_size+=128;
+					break;
+				case SDRAM_RXBAS_SDSZ_256:
+					mem_size+=256;
+					break;
+				case SDRAM_RXBAS_SDSZ_512:
+					mem_size+=512;
+					break;
+				case SDRAM_RXBAS_SDSZ_1024:
+					mem_size+=1024;
+					break;
+				case SDRAM_RXBAS_SDSZ_2048:
+					mem_size+=2048;
+					break;
+				case SDRAM_RXBAS_SDSZ_4096:
+					mem_size+=4096;
+					break;
+				default:
+					mem_size=0;
+					break;
+				}
+			}
+		}
+	}
+
+	mem_size *= 1024 * 1024;
+	return(mem_size);
+}
+
+/*-----------------------------------------------------------------------------+
+ * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
+ * Note: This routine runs from flash with a stack set up in the chip's
+ * sram space.  It is important that the routine does not require .sbss, .bss or
+ * .data sections.  It also cannot call routines that require these sections.
+ *-----------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------
+ * Function:	 initdram
+ * Description:  Configures SDRAM memory banks for DDR operation.
+ *		 Auto Memory Configuration option reads the DDR SDRAM EEPROMs
+ *		 via the IIC bus and then configures the DDR SDRAM memory
+ *		 banks appropriately. If Auto Memory Configuration is
+ *		 not used, it is assumed that no DIMM is plugged
+ *-----------------------------------------------------------------------------*/
+long int initdram(int board_type)
+{
+	unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
+	unsigned char spd0[MAX_SPD_BYTES];
+	unsigned char spd1[MAX_SPD_BYTES];
+	unsigned char *dimm_spd[MAXDIMMS];
+	unsigned long dimm_populated[MAXDIMMS];
+	unsigned long num_dimm_banks;		    /* on board dimm banks */
+	unsigned long val;
+	ddr_cas_id_t  selected_cas;
+	int write_recovery;
+	unsigned long dram_size = 0;
+
+	num_dimm_banks = sizeof(iic0_dimm_addr);
+
+	/*------------------------------------------------------------------
+	 * Set up an array of SPD matrixes.
+	 *-----------------------------------------------------------------*/
+	dimm_spd[0] = spd0;
+	dimm_spd[1] = spd1;
+
+	/*------------------------------------------------------------------
+	 * Reset the DDR-SDRAM controller.
+	 *-----------------------------------------------------------------*/
+	mtsdr(SDR0_SRST, (0x80000000 >> 10));
+	mtsdr(SDR0_SRST, 0x00000000);
+
+	/*
+	 * Make sure I2C controller is initialized
+	 * before continuing.
+	 */
+
+	/* switch to correct I2C bus */
+	I2C_SET_BUS(CFG_SPD_BUS_NUM);
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	/*------------------------------------------------------------------
+	 * Clear out the serial presence detect buffers.
+	 * Perform IIC reads from the dimm.  Fill in the spds.
+	 * Check to see if the dimm slots are populated
+	 *-----------------------------------------------------------------*/
+	get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Check the memory type for the dimms plugged.
+	 *-----------------------------------------------------------------*/
+	check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Check the frequency supported for the dimms plugged.
+	 *-----------------------------------------------------------------*/
+	check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Check the total rank number.
+	 *-----------------------------------------------------------------*/
+	check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Check the voltage type for the dimms plugged.
+	 *-----------------------------------------------------------------*/
+	check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Program SDRAM controller options 2 register
+	 * Except Enabling of the memory controller.
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_MCOPT2, val);
+	mtsdram(SDRAM_MCOPT2,
+		(val &
+		 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
+		   SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
+		   SDRAM_MCOPT2_ISIE_MASK))
+		| (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
+		   SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
+		   SDRAM_MCOPT2_ISIE_ENABLE));
+
+	/*------------------------------------------------------------------
+	 * Program SDRAM controller options 1 register
+	 * Note: Does not enable the memory controller.
+	 *-----------------------------------------------------------------*/
+	program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Set the SDRAM Controller On Die Termination Register
+	 *-----------------------------------------------------------------*/
+	program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Program SDRAM refresh register.
+	 *-----------------------------------------------------------------*/
+	program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Program SDRAM mode register.
+	 *-----------------------------------------------------------------*/
+	program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
+		     &selected_cas, &write_recovery);
+
+	/*------------------------------------------------------------------
+	 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_WRDTR, val);
+	mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
+		(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
+
+	/*------------------------------------------------------------------
+	 * Set the SDRAM Clock Timing Register
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_CLKTR, val);
+	mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
+
+	/*------------------------------------------------------------------
+	 * Program the BxCF registers.
+	 *-----------------------------------------------------------------*/
+	program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Program SDRAM timing registers.
+	 *-----------------------------------------------------------------*/
+	program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Set the Extended Mode register
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_MEMODE, val);
+	mtsdram(SDRAM_MEMODE,
+		(val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
+			 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
+		(SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
+		 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
+
+	/*------------------------------------------------------------------
+	 * Program Initialization preload registers.
+	 *-----------------------------------------------------------------*/
+	program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
+			selected_cas, write_recovery);
+
+	/*------------------------------------------------------------------
+	 * Delay to ensure 200usec have elapsed since reset.
+	 *-----------------------------------------------------------------*/
+	udelay(400);
+
+	/*------------------------------------------------------------------
+	 * Set the memory queue core base addr.
+	 *-----------------------------------------------------------------*/
+	program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+	/*------------------------------------------------------------------
+	 * Program SDRAM controller options 2 register
+	 * Enable the memory controller.
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_MCOPT2, val);
+	mtsdram(SDRAM_MCOPT2,
+		(val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
+			 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
+		(SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
+
+	/*------------------------------------------------------------------
+	 * Wait for SDRAM_CFG0_DC_EN to complete.
+	 *-----------------------------------------------------------------*/
+	do {
+		mfsdram(SDRAM_MCSTAT, val);
+	} while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
+
+	/* get installed memory size */
+	dram_size = sdram_memsize();
+
+	/* and program tlb entries for this size (dynamic) */
+	program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
+
+	/*------------------------------------------------------------------
+	 * DQS calibration.
+	 *-----------------------------------------------------------------*/
+	program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
+
+#ifdef CONFIG_DDR_ECC
+	/*------------------------------------------------------------------
+	 * If ecc is enabled, initialize the parity bits.
+	 *-----------------------------------------------------------------*/
+	program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
+#endif
+
+#ifdef DEBUG
+	ppc440sp_sdram_register_dump();
+#endif
+
+	return dram_size;
+}
+
+static void get_spd_info(unsigned long *dimm_populated,
+			 unsigned char *iic0_dimm_addr,
+			 unsigned long num_dimm_banks)
+{
+	unsigned long dimm_num;
+	unsigned long dimm_found;
+	unsigned char num_of_bytes;
+	unsigned char total_size;
+
+	dimm_found = FALSE;
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		num_of_bytes = 0;
+		total_size = 0;
+
+		num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
+		debug("\nspd_read(0x%x) returned %d\n",
+		      iic0_dimm_addr[dimm_num], num_of_bytes);
+		total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
+		debug("spd_read(0x%x) returned %d\n",
+		      iic0_dimm_addr[dimm_num], total_size);
+
+		if ((num_of_bytes != 0) && (total_size != 0)) {
+			dimm_populated[dimm_num] = TRUE;
+			dimm_found = TRUE;
+			debug("DIMM slot %lu: populated\n", dimm_num);
+		} else {
+			dimm_populated[dimm_num] = FALSE;
+			debug("DIMM slot %lu: Not populated\n", dimm_num);
+		}
+	}
+
+	if (dimm_found == FALSE) {
+		printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
+		hang();
+	}
+}
+
+#ifdef CONFIG_ADD_RAM_INFO
+void board_add_ram_info(int use_default)
+{
+	if (is_ecc_enabled())
+		puts(" (ECC enabled)");
+	else
+		puts(" (ECC not enabled)");
+}
+#endif
+
+/*------------------------------------------------------------------
+ * For the memory DIMMs installed, this routine verifies that they
+ * really are DDR specific DIMMs.
+ *-----------------------------------------------------------------*/
+static void check_mem_type(unsigned long *dimm_populated,
+			   unsigned char *iic0_dimm_addr,
+			   unsigned long num_dimm_banks)
+{
+	unsigned long dimm_num;
+	unsigned long dimm_type;
+
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		if (dimm_populated[dimm_num] == TRUE) {
+			dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
+			switch (dimm_type) {
+			case 1:
+				printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
+				       "slot %d.\n", (unsigned int)dimm_num);
+				printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
+				printf("Replace the DIMM module with a supported DIMM.\n\n");
+				hang();
+				break;
+			case 2:
+				printf("ERROR: EDO DIMM detected in slot %d.\n",
+				       (unsigned int)dimm_num);
+				printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
+				printf("Replace the DIMM module with a supported DIMM.\n\n");
+				hang();
+				break;
+			case 3:
+				printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
+				       (unsigned int)dimm_num);
+				printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
+				printf("Replace the DIMM module with a supported DIMM.\n\n");
+				hang();
+				break;
+			case 4:
+				printf("ERROR: SDRAM DIMM detected in slot %d.\n",
+				       (unsigned int)dimm_num);
+				printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
+				printf("Replace the DIMM module with a supported DIMM.\n\n");
+				hang();
+				break;
+			case 5:
+				printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
+				       (unsigned int)dimm_num);
+				printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
+				printf("Replace the DIMM module with a supported DIMM.\n\n");
+				hang();
+				break;
+			case 6:
+				printf("ERROR: SGRAM DIMM detected in slot %d.\n",
+				       (unsigned int)dimm_num);
+				printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
+				printf("Replace the DIMM module with a supported DIMM.\n\n");
+				hang();
+				break;
+			case 7:
+				debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
+				dimm_populated[dimm_num] = SDRAM_DDR1;
+				break;
+			case 8:
+				debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
+				dimm_populated[dimm_num] = SDRAM_DDR2;
+				break;
+			default:
+				printf("ERROR: Unknown DIMM detected in slot %d.\n",
+				       (unsigned int)dimm_num);
+				printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
+				printf("Replace the DIMM module with a supported DIMM.\n\n");
+				hang();
+				break;
+			}
+		}
+	}
+	for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
+		if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
+		    && (dimm_populated[dimm_num]   != SDRAM_NONE)
+		    && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
+			printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
+			hang();
+		}
+	}
+}
+
+/*------------------------------------------------------------------
+ * For the memory DIMMs installed, this routine verifies that
+ * frequency previously calculated is supported.
+ *-----------------------------------------------------------------*/
+static void check_frequency(unsigned long *dimm_populated,
+			    unsigned char *iic0_dimm_addr,
+			    unsigned long num_dimm_banks)
+{
+	unsigned long dimm_num;
+	unsigned long tcyc_reg;
+	unsigned long cycle_time;
+	unsigned long calc_cycle_time;
+	unsigned long sdram_freq;
+	unsigned long sdr_ddrpll;
+	PPC440_SYS_INFO board_cfg;
+
+	/*------------------------------------------------------------------
+	 * Get the board configuration info.
+	 *-----------------------------------------------------------------*/
+	get_sys_info(&board_cfg);
+
+	mfsdr(SDR0_DDR0, sdr_ddrpll);
+	sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
+
+	/*
+	 * calc_cycle_time is calculated from DDR frequency set by board/chip
+	 * and is expressed in multiple of 10 picoseconds
+	 * to match the way DIMM cycle time is calculated below.
+	 */
+	calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
+
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		if (dimm_populated[dimm_num] != SDRAM_NONE) {
+			tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
+			/*
+			 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
+			 * the higher order nibble (bits 4-7) designates the cycle time
+			 * to a granularity of 1ns;
+			 * the value presented by the lower order nibble (bits 0-3)
+			 * has a granularity of .1ns and is added to the value designated
+			 * by the higher nibble. In addition, four lines of the lower order
+			 * nibble are assigned to support +.25,+.33, +.66 and +.75.
+			 */
+			 /* Convert from hex to decimal */
+			if ((tcyc_reg & 0x0F) == 0x0D)
+				cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
+			else if ((tcyc_reg & 0x0F) == 0x0C)
+				cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
+			else if ((tcyc_reg & 0x0F) == 0x0B)
+				cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
+			else if ((tcyc_reg & 0x0F) == 0x0A)
+				cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
+			else
+				cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
+					((tcyc_reg & 0x0F)*10);
+
+			if  (cycle_time > (calc_cycle_time + 10)) {
+				/*
+				 * the provided sdram cycle_time is too small
+				 * for the available DIMM cycle_time.
+				 * The additionnal 100ps is here to accept a small incertainty.
+				 */
+				printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
+				       "slot %d \n while calculated cycle time is %d ps.\n",
+				       (unsigned int)(cycle_time*10),
+				       (unsigned int)dimm_num,
+				       (unsigned int)(calc_cycle_time*10));
+				printf("Replace the DIMM, or change DDR frequency via "
+				       "strapping bits.\n\n");
+				hang();
+			}
+		}
+	}
+}
+
+/*------------------------------------------------------------------
+ * For the memory DIMMs installed, this routine verifies two
+ * ranks/banks maximum are availables.
+ *-----------------------------------------------------------------*/
+static void check_rank_number(unsigned long *dimm_populated,
+			      unsigned char *iic0_dimm_addr,
+			      unsigned long num_dimm_banks)
+{
+	unsigned long dimm_num;
+	unsigned long dimm_rank;
+	unsigned long total_rank = 0;
+
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		if (dimm_populated[dimm_num] != SDRAM_NONE) {
+			dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
+			if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
+				dimm_rank = (dimm_rank & 0x0F) +1;
+			else
+				dimm_rank = dimm_rank & 0x0F;
+
+
+			if (dimm_rank > MAXRANKS) {
+				printf("ERROR: DRAM DIMM detected with %d ranks in "
+				       "slot %d is not supported.\n", dimm_rank, dimm_num);
+				printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
+				printf("Replace the DIMM module with a supported DIMM.\n\n");
+				hang();
+			} else
+				total_rank += dimm_rank;
+		}
+		if (total_rank > MAXRANKS) {
+			printf("ERROR: DRAM DIMM detected with a total of %d ranks "
+			       "for all slots.\n", (unsigned int)total_rank);
+			printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
+			printf("Remove one of the DIMM modules.\n\n");
+			hang();
+		}
+	}
+}
+
+/*------------------------------------------------------------------
+ * only support 2.5V modules.
+ * This routine verifies this.
+ *-----------------------------------------------------------------*/
+static void check_voltage_type(unsigned long *dimm_populated,
+			       unsigned char *iic0_dimm_addr,
+			       unsigned long num_dimm_banks)
+{
+	unsigned long dimm_num;
+	unsigned long voltage_type;
+
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		if (dimm_populated[dimm_num] != SDRAM_NONE) {
+			voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
+			switch (voltage_type) {
+			case 0x00:
+				printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
+				printf("This DIMM is 5.0 Volt/TTL.\n");
+				printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
+				       (unsigned int)dimm_num);
+				hang();
+				break;
+			case 0x01:
+				printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
+				printf("This DIMM is LVTTL.\n");
+				printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
+				       (unsigned int)dimm_num);
+				hang();
+				break;
+			case 0x02:
+				printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
+				printf("This DIMM is 1.5 Volt.\n");
+				printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
+				       (unsigned int)dimm_num);
+				hang();
+				break;
+			case 0x03:
+				printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
+				printf("This DIMM is 3.3 Volt/TTL.\n");
+				printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
+				       (unsigned int)dimm_num);
+				hang();
+				break;
+			case 0x04:
+				/* 2.5 Voltage only for DDR1 */
+				break;
+			case 0x05:
+				/* 1.8 Voltage only for DDR2 */
+				break;
+			default:
+				printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
+				printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
+				       (unsigned int)dimm_num);
+				hang();
+				break;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------------+
+ * program_copt1.
+ *-----------------------------------------------------------------------------*/
+static void program_copt1(unsigned long *dimm_populated,
+			  unsigned char *iic0_dimm_addr,
+			  unsigned long num_dimm_banks)
+{
+	unsigned long dimm_num;
+	unsigned long mcopt1;
+	unsigned long ecc_enabled;
+	unsigned long ecc = 0;
+	unsigned long data_width = 0;
+	unsigned long dimm_32bit;
+	unsigned long dimm_64bit;
+	unsigned long registered = 0;
+	unsigned long attribute = 0;
+	unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
+	unsigned long bankcount;
+	unsigned long ddrtype;
+	unsigned long val;
+
+#ifdef CONFIG_DDR_ECC
+	ecc_enabled = TRUE;
+#else
+	ecc_enabled = FALSE;
+#endif
+	dimm_32bit = FALSE;
+	dimm_64bit = FALSE;
+	buf0 = FALSE;
+	buf1 = FALSE;
+
+	/*------------------------------------------------------------------
+	 * Set memory controller options reg 1, SDRAM_MCOPT1.
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_MCOPT1, val);
+	mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
+			 SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
+			 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
+			 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
+			 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
+			 SDRAM_MCOPT1_DREF_MASK);
+
+	mcopt1 |= SDRAM_MCOPT1_QDEP;
+	mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
+	mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
+	mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
+	mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
+	mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
+
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		if (dimm_populated[dimm_num] != SDRAM_NONE) {
+			/* test ecc support */
+			ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
+			if (ecc != 0x02) /* ecc not supported */
+				ecc_enabled = FALSE;
+
+			/* test bank count */
+			bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
+			if (bankcount == 0x04) /* bank count = 4 */
+				mcopt1 |= SDRAM_MCOPT1_4_BANKS;
+			else /* bank count = 8 */
+				mcopt1 |= SDRAM_MCOPT1_8_BANKS;
+
+			/* test DDR type */
+			ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
+			/* test for buffered/unbuffered, registered, differential clocks */
+			registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
+			attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
+
+			/* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
+			if (dimm_num == 0) {
+				if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
+					mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
+				if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
+					mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
+				if (registered == 1) { /* DDR2 always buffered */
+					/* TODO: what about above  comments ? */
+					mcopt1 |= SDRAM_MCOPT1_RDEN;
+					buf0 = TRUE;
+				} else {
+					/* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
+					if ((attribute & 0x02) == 0x00) {
+						/* buffered not supported */
+						buf0 = FALSE;
+					} else {
+						mcopt1 |= SDRAM_MCOPT1_RDEN;
+						buf0 = TRUE;
+					}
+				}
+			}
+			else if (dimm_num == 1) {
+				if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
+					mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
+				if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
+					mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
+				if (registered == 1) {
+					/* DDR2 always buffered */
+					mcopt1 |= SDRAM_MCOPT1_RDEN;
+					buf1 = TRUE;
+				} else {
+					if ((attribute & 0x02) == 0x00) {
+						/* buffered not supported */
+						buf1 = FALSE;
+					} else {
+						mcopt1 |= SDRAM_MCOPT1_RDEN;
+						buf1 = TRUE;
+					}
+				}
+			}
+
+			/* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
+			data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
+				(((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
+
+			switch (data_width) {
+			case 72:
+			case 64:
+				dimm_64bit = TRUE;
+				break;
+			case 40:
+			case 32:
+				dimm_32bit = TRUE;
+				break;
+			default:
+				printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
+				       data_width);
+				printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
+				break;
+			}
+		}
+	}
+
+	/* verify matching properties */
+	if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
+		if (buf0 != buf1) {
+			printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
+			hang();
+		}
+	}
+
+	if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
+		printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
+		hang();
+	}
+	else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
+		mcopt1 |= SDRAM_MCOPT1_DMWD_64;
+	} else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
+		mcopt1 |= SDRAM_MCOPT1_DMWD_32;
+	} else {
+		printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
+		hang();
+	}
+
+	if (ecc_enabled == TRUE)
+		mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
+	else
+		mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
+
+	mtsdram(SDRAM_MCOPT1, mcopt1);
+}
+
+/*-----------------------------------------------------------------------------+
+ * program_codt.
+ *-----------------------------------------------------------------------------*/
+static void program_codt(unsigned long *dimm_populated,
+			 unsigned char *iic0_dimm_addr,
+			 unsigned long num_dimm_banks)
+{
+	unsigned long codt;
+	unsigned long modt0 = 0;
+	unsigned long modt1 = 0;
+	unsigned long modt2 = 0;
+	unsigned long modt3 = 0;
+	unsigned char dimm_num;
+	unsigned char dimm_rank;
+	unsigned char total_rank = 0;
+	unsigned char total_dimm = 0;
+	unsigned char dimm_type = 0;
+	unsigned char firstSlot = 0;
+
+	/*------------------------------------------------------------------
+	 * Set the SDRAM Controller On Die Termination Register
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_CODT, codt);
+	codt |= (SDRAM_CODT_IO_NMODE
+		 & (~SDRAM_CODT_DQS_SINGLE_END
+		    & ~SDRAM_CODT_CKSE_SINGLE_END
+		    & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
+		    & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
+
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		if (dimm_populated[dimm_num] != SDRAM_NONE) {
+			dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
+			if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
+				dimm_rank = (dimm_rank & 0x0F) + 1;
+				dimm_type = SDRAM_DDR2;
+			} else {
+				dimm_rank = dimm_rank & 0x0F;
+				dimm_type = SDRAM_DDR1;
+			}
+
+			total_rank += dimm_rank;
+			total_dimm++;
+			if ((dimm_num == 0) && (total_dimm == 1))
+				firstSlot = TRUE;
+			else
+				firstSlot = FALSE;
+		}
+	}
+	if (dimm_type == SDRAM_DDR2) {
+		codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
+		if ((total_dimm == 1) && (firstSlot == TRUE)) {
+			if (total_rank == 1) {
+				codt |= CALC_ODT_R(0);
+				modt0 = CALC_ODT_W(0);
+				modt1 = 0x00000000;
+				modt2 = 0x00000000;
+				modt3 = 0x00000000;
+			}
+			if (total_rank == 2) {
+				codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
+				modt0 = CALC_ODT_W(0);
+				modt1 = CALC_ODT_W(0);
+				modt2 = 0x00000000;
+				modt3 = 0x00000000;
+			}
+		} else if ((total_dimm == 1) && (firstSlot != TRUE)) {
+			if (total_rank == 1) {
+				codt |= CALC_ODT_R(2);
+				modt0 = 0x00000000;
+				modt1 = 0x00000000;
+				modt2 = CALC_ODT_W(2);
+				modt3 = 0x00000000;
+			}
+			if (total_rank == 2) {
+				codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
+				modt0 = 0x00000000;
+				modt1 = 0x00000000;
+				modt2 = CALC_ODT_W(2);
+				modt3 = CALC_ODT_W(2);
+			}
+		}
+		if (total_dimm == 2) {
+			if (total_rank == 2) {
+				codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
+				modt0 = CALC_ODT_RW(2);
+				modt1 = 0x00000000;
+				modt2 = CALC_ODT_RW(0);
+				modt3 = 0x00000000;
+			}
+			if (total_rank == 4) {
+				codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3);
+				modt0 = CALC_ODT_RW(2);
+				modt1 = 0x00000000;
+				modt2 = CALC_ODT_RW(0);
+				modt3 = 0x00000000;
+			}
+		}
+  	} else {
+		codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
+		modt0 = 0x00000000;
+		modt1 = 0x00000000;
+		modt2 = 0x00000000;
+		modt3 = 0x00000000;
+
+		if (total_dimm == 1) {
+			if (total_rank == 1)
+				codt |= 0x00800000;
+			if (total_rank == 2)
+				codt |= 0x02800000;
+		}
+		if (total_dimm == 2) {
+			if (total_rank == 2)
+				codt |= 0x08800000;
+			if (total_rank == 4)
+				codt |= 0x2a800000;
+		}
+	}
+
+	debug("nb of dimm %d\n", total_dimm);
+	debug("nb of rank %d\n", total_rank);
+	if (total_dimm == 1)
+		debug("dimm in slot %d\n", firstSlot);
+
+	mtsdram(SDRAM_CODT, codt);
+	mtsdram(SDRAM_MODT0, modt0);
+	mtsdram(SDRAM_MODT1, modt1);
+	mtsdram(SDRAM_MODT2, modt2);
+	mtsdram(SDRAM_MODT3, modt3);
+}
+
+/*-----------------------------------------------------------------------------+
+ * program_initplr.
+ *-----------------------------------------------------------------------------*/
+static void program_initplr(unsigned long *dimm_populated,
+			    unsigned char *iic0_dimm_addr,
+			    unsigned long num_dimm_banks,
+			    ddr_cas_id_t selected_cas,
+			    int write_recovery)
+{
+	u32 cas = 0;
+	u32 odt = 0;
+	u32 ods = 0;
+	u32 mr;
+	u32 wr;
+	u32 emr;
+	u32 emr2;
+	u32 emr3;
+	int dimm_num;
+	int total_dimm = 0;
+
+	/******************************************************
+	 ** Assumption: if more than one DIMM, all DIMMs are the same
+	 **		as already checked in check_memory_type
+	 ******************************************************/
+
+	if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
+		mtsdram(SDRAM_INITPLR0, 0x81B80000);
+		mtsdram(SDRAM_INITPLR1, 0x81900400);
+		mtsdram(SDRAM_INITPLR2, 0x81810000);
+		mtsdram(SDRAM_INITPLR3, 0xff800162);
+		mtsdram(SDRAM_INITPLR4, 0x81900400);
+		mtsdram(SDRAM_INITPLR5, 0x86080000);
+		mtsdram(SDRAM_INITPLR6, 0x86080000);
+		mtsdram(SDRAM_INITPLR7, 0x81000062);
+	} else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
+		switch (selected_cas) {
+		case DDR_CAS_3:
+			cas = 3 << 4;
+			break;
+		case DDR_CAS_4:
+			cas = 4 << 4;
+			break;
+		case DDR_CAS_5:
+			cas = 5 << 4;
+			break;
+		default:
+			printf("ERROR: ucode error on selected_cas value %d", selected_cas);
+			hang();
+			break;
+		}
+
+#if 0
+		/*
+		 * ToDo - Still a problem with the write recovery:
+		 * On the Corsair CM2X512-5400C4 module, setting write recovery
+		 * in the INITPLR reg to the value calculated in program_mode()
+		 * results in not correctly working DDR2 memory (crash after
+		 * relocation).
+		 *
+		 * So for now, set the write recovery to 3. This seems to work
+		 * on the Corair module too.
+		 *
+		 * 2007-03-01, sr
+		 */
+		switch (write_recovery) {
+		case 3:
+			wr = WRITE_RECOV_3;
+			break;
+		case 4:
+			wr = WRITE_RECOV_4;
+			break;
+		case 5:
+			wr = WRITE_RECOV_5;
+			break;
+		case 6:
+			wr = WRITE_RECOV_6;
+			break;
+		default:
+			printf("ERROR: write recovery not support (%d)", write_recovery);
+			hang();
+			break;
+		}
+#else
+		wr = WRITE_RECOV_3; /* test-only, see description above */
+#endif
+
+		for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
+			if (dimm_populated[dimm_num] != SDRAM_NONE)
+				total_dimm++;
+		if (total_dimm == 1) {
+			odt = ODT_150_OHM;
+			ods = ODS_FULL;
+		} else if (total_dimm == 2) {
+			odt = ODT_75_OHM;
+			ods = ODS_REDUCED;
+		} else {
+			printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
+			hang();
+		}
+
+		mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
+		emr = CMD_EMR | SELECT_EMR | odt | ods;
+		emr2 = CMD_EMR | SELECT_EMR2;
+		emr3 = CMD_EMR | SELECT_EMR3;
+		mtsdram(SDRAM_INITPLR0,  0xB5000000 | CMD_NOP);		/* NOP */
+		udelay(1000);
+		mtsdram(SDRAM_INITPLR1,  0x82000400 | CMD_PRECHARGE);	/* precharge 8 DDR clock cycle */
+		mtsdram(SDRAM_INITPLR2,  0x80800000 | emr2);		/* EMR2 */
+		mtsdram(SDRAM_INITPLR3,  0x80800000 | emr3);		/* EMR3 */
+		mtsdram(SDRAM_INITPLR4,  0x80800000 | emr);		/* EMR DLL ENABLE */
+		mtsdram(SDRAM_INITPLR5,  0x80800000 | mr | DLL_RESET);	/* MR w/ DLL reset */
+		udelay(1000);
+		mtsdram(SDRAM_INITPLR6,  0x82000400 | CMD_PRECHARGE);	/* precharge 8 DDR clock cycle */
+		mtsdram(SDRAM_INITPLR7,  0x8a000000 | CMD_REFRESH);	/* Refresh  50 DDR clock cycle */
+		mtsdram(SDRAM_INITPLR8,  0x8a000000 | CMD_REFRESH);	/* Refresh  50 DDR clock cycle */
+		mtsdram(SDRAM_INITPLR9,  0x8a000000 | CMD_REFRESH);	/* Refresh  50 DDR clock cycle */
+		mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH);	/* Refresh  50 DDR clock cycle */
+		mtsdram(SDRAM_INITPLR11, 0x80000000 | mr);		/* MR w/o DLL reset */
+		mtsdram(SDRAM_INITPLR12, 0x80800380 | emr);		/* EMR OCD Default */
+		mtsdram(SDRAM_INITPLR13, 0x80800000 | emr);		/* EMR OCD Exit */
+	} else {
+		printf("ERROR: ucode error as unknown DDR type in program_initplr");
+		hang();
+	}
+}
+
+/*------------------------------------------------------------------
+ * This routine programs the SDRAM_MMODE register.
+ * the selected_cas is an output parameter, that will be passed
+ * by caller to call the above program_initplr( )
+ *-----------------------------------------------------------------*/
+static void program_mode(unsigned long *dimm_populated,
+			 unsigned char *iic0_dimm_addr,
+			 unsigned long num_dimm_banks,
+			 ddr_cas_id_t *selected_cas,
+			 int *write_recovery)
+{
+	unsigned long dimm_num;
+	unsigned long sdram_ddr1;
+	unsigned long t_wr_ns;
+	unsigned long t_wr_clk;
+	unsigned long cas_bit;
+	unsigned long cas_index;
+	unsigned long sdram_freq;
+	unsigned long ddr_check;
+	unsigned long mmode;
+	unsigned long tcyc_reg;
+	unsigned long cycle_2_0_clk;
+	unsigned long cycle_2_5_clk;
+	unsigned long cycle_3_0_clk;
+	unsigned long cycle_4_0_clk;
+	unsigned long cycle_5_0_clk;
+	unsigned long max_2_0_tcyc_ns_x_100;
+	unsigned long max_2_5_tcyc_ns_x_100;
+	unsigned long max_3_0_tcyc_ns_x_100;
+	unsigned long max_4_0_tcyc_ns_x_100;
+	unsigned long max_5_0_tcyc_ns_x_100;
+	unsigned long cycle_time_ns_x_100[3];
+	PPC440_SYS_INFO board_cfg;
+	unsigned char cas_2_0_available;
+	unsigned char cas_2_5_available;
+	unsigned char cas_3_0_available;
+	unsigned char cas_4_0_available;
+	unsigned char cas_5_0_available;
+	unsigned long sdr_ddrpll;
+
+	/*------------------------------------------------------------------
+	 * Get the board configuration info.
+	 *-----------------------------------------------------------------*/
+	get_sys_info(&board_cfg);
+
+	mfsdr(SDR0_DDR0, sdr_ddrpll);
+	sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
+
+	/*------------------------------------------------------------------
+	 * Handle the timing.  We need to find the worst case timing of all
+	 * the dimm modules installed.
+	 *-----------------------------------------------------------------*/
+	t_wr_ns = 0;
+	cas_2_0_available = TRUE;
+	cas_2_5_available = TRUE;
+	cas_3_0_available = TRUE;
+	cas_4_0_available = TRUE;
+	cas_5_0_available = TRUE;
+	max_2_0_tcyc_ns_x_100 = 10;
+	max_2_5_tcyc_ns_x_100 = 10;
+	max_3_0_tcyc_ns_x_100 = 10;
+	max_4_0_tcyc_ns_x_100 = 10;
+	max_5_0_tcyc_ns_x_100 = 10;
+	sdram_ddr1 = TRUE;
+
+	/* loop through all the DIMM slots on the board */
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		/* If a dimm is installed in a particular slot ... */
+		if (dimm_populated[dimm_num] != SDRAM_NONE) {
+			if (dimm_populated[dimm_num] == SDRAM_DDR1)
+				sdram_ddr1 = TRUE;
+			else
+				sdram_ddr1 = FALSE;
+
+			/* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
+			cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
+
+			/* For a particular DIMM, grab the three CAS values it supports */
+			for (cas_index = 0; cas_index < 3; cas_index++) {
+				switch (cas_index) {
+				case 0:
+					tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
+					break;
+				case 1:
+					tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
+					break;
+				default:
+					tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
+					break;
+				}
+
+				if ((tcyc_reg & 0x0F) >= 10) {
+					if ((tcyc_reg & 0x0F) == 0x0D) {
+						/* Convert from hex to decimal */
+						cycle_time_ns_x_100[cas_index] = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
+					} else {
+						printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
+						       "in slot %d\n", (unsigned int)dimm_num);
+						hang();
+					}
+				} else {
+					/* Convert from hex to decimal */
+					cycle_time_ns_x_100[cas_index] = (((tcyc_reg & 0xF0) >> 4) * 100) +
+						((tcyc_reg & 0x0F)*10);
+				}
+			}
+
+			/* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
+			/* supported for a particular DIMM. */
+			cas_index = 0;
+
+			if (sdram_ddr1) {
+				/*
+				 * DDR devices use the following bitmask for CAS latency:
+				 *  Bit   7    6    5    4    3    2    1    0
+				 *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
+				 */
+				if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
+					max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
+					cas_index++;
+				} else {
+					if (cas_index != 0)
+						cas_index++;
+					cas_4_0_available = FALSE;
+				}
+
+				if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
+					max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
+					cas_index++;
+				} else {
+					if (cas_index != 0)
+						cas_index++;
+					cas_3_0_available = FALSE;
+				}
+
+				if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
+					max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
+					cas_index++;
+				} else {
+					if (cas_index != 0)
+						cas_index++;
+					cas_2_5_available = FALSE;
+				}
+
+				if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
+					max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
+					cas_index++;
+				} else {
+					if (cas_index != 0)
+						cas_index++;
+					cas_2_0_available = FALSE;
+				}
+			} else {
+				/*
+				 * DDR2 devices use the following bitmask for CAS latency:
+				 *  Bit   7    6    5    4    3    2    1    0
+				 *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
+				 */
+				if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
+					max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
+					cas_index++;
+				} else {
+					if (cas_index != 0)
+						cas_index++;
+					cas_5_0_available = FALSE;
+				}
+
+				if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
+					max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
+					cas_index++;
+				} else {
+					if (cas_index != 0)
+						cas_index++;
+					cas_4_0_available = FALSE;
+				}
+
+				if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && (cycle_time_ns_x_100[cas_index] != 0)) {
+					max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, cycle_time_ns_x_100[cas_index]);
+					cas_index++;
+				} else {
+					if (cas_index != 0)
+						cas_index++;
+					cas_3_0_available = FALSE;
+				}
+			}
+		}
+	}
+
+	/*------------------------------------------------------------------
+	 * Set the SDRAM mode, SDRAM_MMODE
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_MMODE, mmode);
+	mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
+
+	/* add 10 here because of rounding problems */
+	cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
+	cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
+	cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
+	cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
+	cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
+
+	if (sdram_ddr1 == TRUE) { /* DDR1 */
+		if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
+			mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
+			*selected_cas = DDR_CAS_2;
+		} else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
+			mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
+			*selected_cas = DDR_CAS_2_5;
+		} else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
+			mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
+			*selected_cas = DDR_CAS_3;
+		} else {
+			printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
+			printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
+			printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
+			hang();
+		}
+	} else { /* DDR2 */
+		if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
+			mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
+			*selected_cas = DDR_CAS_3;
+		} else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
+			mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
+			*selected_cas = DDR_CAS_4;
+		} else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
+			mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
+			*selected_cas = DDR_CAS_5;
+		} else {
+			printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
+			printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
+			printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
+			printf("cas3=%d cas4=%d cas5=%d\n",
+			       cas_3_0_available, cas_4_0_available, cas_5_0_available);
+			printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
+			       sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
+			hang();
+		}
+	}
+
+	if (sdram_ddr1 == TRUE)
+		mmode |= SDRAM_MMODE_WR_DDR1;
+	else {
+
+		/* loop through all the DIMM slots on the board */
+		for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+			/* If a dimm is installed in a particular slot ... */
+			if (dimm_populated[dimm_num] != SDRAM_NONE)
+				t_wr_ns = max(t_wr_ns,
+					      spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
+		}
+
+		/*
+		 * convert from nanoseconds to ddr clocks
+		 * round up if necessary
+		 */
+		t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
+		ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
+		if (sdram_freq != ddr_check)
+			t_wr_clk++;
+
+		switch (t_wr_clk) {
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+			mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
+			break;
+		case 4:
+			mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
+			break;
+		case 5:
+			mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
+			break;
+		default:
+			mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
+			break;
+		}
+		*write_recovery = t_wr_clk;
+	}
+
+	debug("CAS latency = %d\n", *selected_cas);
+	debug("Write recovery = %d\n", *write_recovery);
+
+	mtsdram(SDRAM_MMODE, mmode);
+}
+
+/*-----------------------------------------------------------------------------+
+ * program_rtr.
+ *-----------------------------------------------------------------------------*/
+static void program_rtr(unsigned long *dimm_populated,
+			unsigned char *iic0_dimm_addr,
+			unsigned long num_dimm_banks)
+{
+	PPC440_SYS_INFO board_cfg;
+	unsigned long max_refresh_rate;
+	unsigned long dimm_num;
+	unsigned long refresh_rate_type;
+	unsigned long refresh_rate;
+	unsigned long rint;
+	unsigned long sdram_freq;
+	unsigned long sdr_ddrpll;
+	unsigned long val;
+
+	/*------------------------------------------------------------------
+	 * Get the board configuration info.
+	 *-----------------------------------------------------------------*/
+	get_sys_info(&board_cfg);
+
+	/*------------------------------------------------------------------
+	 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
+	 *-----------------------------------------------------------------*/
+	mfsdr(SDR0_DDR0, sdr_ddrpll);
+	sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
+
+	max_refresh_rate = 0;
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		if (dimm_populated[dimm_num] != SDRAM_NONE) {
+
+			refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
+			refresh_rate_type &= 0x7F;
+			switch (refresh_rate_type) {
+			case 0:
+				refresh_rate =  15625;
+				break;
+			case 1:
+				refresh_rate =   3906;
+				break;
+			case 2:
+				refresh_rate =   7812;
+				break;
+			case 3:
+				refresh_rate =  31250;
+				break;
+			case 4:
+				refresh_rate =  62500;
+				break;
+			case 5:
+				refresh_rate = 125000;
+				break;
+			default:
+				refresh_rate = 0;
+				printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
+				       (unsigned int)dimm_num);
+				printf("Replace the DIMM module with a supported DIMM.\n\n");
+				hang();
+				break;
+			}
+
+			max_refresh_rate = max(max_refresh_rate, refresh_rate);
+		}
+	}
+
+	rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
+	mfsdram(SDRAM_RTR, val);
+	mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
+		(SDRAM_RTR_RINT_ENCODE(rint)));
+}
+
+/*------------------------------------------------------------------
+ * This routine programs the SDRAM_TRx registers.
+ *-----------------------------------------------------------------*/
+static void program_tr(unsigned long *dimm_populated,
+		       unsigned char *iic0_dimm_addr,
+		       unsigned long num_dimm_banks)
+{
+	unsigned long dimm_num;
+	unsigned long sdram_ddr1;
+	unsigned long t_rp_ns;
+	unsigned long t_rcd_ns;
+	unsigned long t_rrd_ns;
+	unsigned long t_ras_ns;
+	unsigned long t_rc_ns;
+	unsigned long t_rfc_ns;
+	unsigned long t_wpc_ns;
+	unsigned long t_wtr_ns;
+	unsigned long t_rpc_ns;
+	unsigned long t_rp_clk;
+	unsigned long t_rcd_clk;
+	unsigned long t_rrd_clk;
+	unsigned long t_ras_clk;
+	unsigned long t_rc_clk;
+	unsigned long t_rfc_clk;
+	unsigned long t_wpc_clk;
+	unsigned long t_wtr_clk;
+	unsigned long t_rpc_clk;
+	unsigned long sdtr1, sdtr2, sdtr3;
+	unsigned long ddr_check;
+	unsigned long sdram_freq;
+	unsigned long sdr_ddrpll;
+
+	PPC440_SYS_INFO board_cfg;
+
+	/*------------------------------------------------------------------
+	 * Get the board configuration info.
+	 *-----------------------------------------------------------------*/
+	get_sys_info(&board_cfg);
+
+	mfsdr(SDR0_DDR0, sdr_ddrpll);
+	sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
+
+	/*------------------------------------------------------------------
+	 * Handle the timing.  We need to find the worst case timing of all
+	 * the dimm modules installed.
+	 *-----------------------------------------------------------------*/
+	t_rp_ns = 0;
+	t_rrd_ns = 0;
+	t_rcd_ns = 0;
+	t_ras_ns = 0;
+	t_rc_ns = 0;
+	t_rfc_ns = 0;
+	t_wpc_ns = 0;
+	t_wtr_ns = 0;
+	t_rpc_ns = 0;
+	sdram_ddr1 = TRUE;
+
+	/* loop through all the DIMM slots on the board */
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		/* If a dimm is installed in a particular slot ... */
+		if (dimm_populated[dimm_num] != SDRAM_NONE) {
+			if (dimm_populated[dimm_num] == SDRAM_DDR2)
+				sdram_ddr1 = TRUE;
+			else
+				sdram_ddr1 = FALSE;
+
+			t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
+			t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
+			t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
+			t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
+			t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
+			t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
+		}
+	}
+
+	/*------------------------------------------------------------------
+	 * Set the SDRAM Timing Reg 1, SDRAM_TR1
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_SDTR1, sdtr1);
+	sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
+		   SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
+
+	/* default values */
+	sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
+	sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
+
+	/* normal operations */
+	sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
+	sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
+
+	mtsdram(SDRAM_SDTR1, sdtr1);
+
+	/*------------------------------------------------------------------
+	 * Set the SDRAM Timing Reg 2, SDRAM_TR2
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_SDTR2, sdtr2);
+	sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
+		   SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
+		   SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
+		   SDRAM_SDTR2_RRD_MASK);
+
+	/*
+	 * convert t_rcd from nanoseconds to ddr clocks
+	 * round up if necessary
+	 */
+	t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
+	ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
+	if (sdram_freq != ddr_check)
+		t_rcd_clk++;
+
+	switch (t_rcd_clk) {
+	case 0:
+	case 1:
+		sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
+		break;
+	case 2:
+		sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
+		break;
+	case 3:
+		sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
+		break;
+	case 4:
+		sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
+		break;
+	default:
+		sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
+		break;
+	}
+
+	if (sdram_ddr1 == TRUE) { /* DDR1 */
+		if (sdram_freq < 200000000) {
+			sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
+			sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
+			sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
+		} else {
+			sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
+			sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
+			sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
+		}
+	} else { /* DDR2 */
+		/* loop through all the DIMM slots on the board */
+		for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+			/* If a dimm is installed in a particular slot ... */
+			if (dimm_populated[dimm_num] != SDRAM_NONE) {
+				t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
+				t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
+				t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
+			}
+		}
+
+		/*
+		 * convert from nanoseconds to ddr clocks
+		 * round up if necessary
+		 */
+		t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
+		ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
+		if (sdram_freq != ddr_check)
+			t_wpc_clk++;
+
+		switch (t_wpc_clk) {
+		case 0:
+		case 1:
+		case 2:
+			sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
+			break;
+		case 3:
+			sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
+			break;
+		case 4:
+			sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
+			break;
+		case 5:
+			sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
+			break;
+		default:
+			sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
+			break;
+		}
+
+		/*
+		 * convert from nanoseconds to ddr clocks
+		 * round up if necessary
+		 */
+		t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
+		ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
+		if (sdram_freq != ddr_check)
+			t_wtr_clk++;
+
+		switch (t_wtr_clk) {
+		case 0:
+		case 1:
+			sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
+			break;
+		case 2:
+			sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
+			break;
+		case 3:
+			sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
+			break;
+		default:
+			sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
+			break;
+		}
+
+		/*
+		 * convert from nanoseconds to ddr clocks
+		 * round up if necessary
+		 */
+		t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
+		ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
+		if (sdram_freq != ddr_check)
+			t_rpc_clk++;
+
+		switch (t_rpc_clk) {
+		case 0:
+		case 1:
+		case 2:
+			sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
+			break;
+		case 3:
+			sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
+			break;
+		default:
+			sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
+			break;
+		}
+	}
+
+	/* default value */
+	sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
+
+	/*
+	 * convert t_rrd from nanoseconds to ddr clocks
+	 * round up if necessary
+	 */
+	t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
+	ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
+	if (sdram_freq != ddr_check)
+		t_rrd_clk++;
+
+	if (t_rrd_clk == 3)
+		sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
+	else
+		sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
+
+	/*
+	 * convert t_rp from nanoseconds to ddr clocks
+	 * round up if necessary
+	 */
+	t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
+	ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
+	if (sdram_freq != ddr_check)
+		t_rp_clk++;
+
+	switch (t_rp_clk) {
+	case 0:
+	case 1:
+	case 2:
+	case 3:
+		sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
+		break;
+	case 4:
+		sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
+		break;
+	case 5:
+		sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
+		break;
+	case 6:
+		sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
+		break;
+	default:
+		sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
+		break;
+	}
+
+	mtsdram(SDRAM_SDTR2, sdtr2);
+
+	/*------------------------------------------------------------------
+	 * Set the SDRAM Timing Reg 3, SDRAM_TR3
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_SDTR3, sdtr3);
+	sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
+		   SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
+
+	/*
+	 * convert t_ras from nanoseconds to ddr clocks
+	 * round up if necessary
+	 */
+	t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
+	ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
+	if (sdram_freq != ddr_check)
+		t_ras_clk++;
+
+	sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
+
+	/*
+	 * convert t_rc from nanoseconds to ddr clocks
+	 * round up if necessary
+	 */
+	t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
+	ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
+	if (sdram_freq != ddr_check)
+		t_rc_clk++;
+
+	sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
+
+	/* default xcs value */
+	sdtr3 |= SDRAM_SDTR3_XCS;
+
+	/*
+	 * convert t_rfc from nanoseconds to ddr clocks
+	 * round up if necessary
+	 */
+	t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
+	ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
+	if (sdram_freq != ddr_check)
+		t_rfc_clk++;
+
+	sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
+
+	mtsdram(SDRAM_SDTR3, sdtr3);
+}
+
+/*-----------------------------------------------------------------------------+
+ * program_bxcf.
+ *-----------------------------------------------------------------------------*/
+static void program_bxcf(unsigned long *dimm_populated,
+			 unsigned char *iic0_dimm_addr,
+			 unsigned long num_dimm_banks)
+{
+	unsigned long dimm_num;
+	unsigned long num_col_addr;
+	unsigned long num_ranks;
+	unsigned long num_banks;
+	unsigned long mode;
+	unsigned long ind_rank;
+	unsigned long ind;
+	unsigned long ind_bank;
+	unsigned long bank_0_populated;
+
+	/*------------------------------------------------------------------
+	 * Set the BxCF regs.  First, wipe out the bank config registers.
+	 *-----------------------------------------------------------------*/
+	mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
+	mtdcr(SDRAMC_CFGDATA, 0x00000000);
+	mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
+	mtdcr(SDRAMC_CFGDATA, 0x00000000);
+	mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
+	mtdcr(SDRAMC_CFGDATA, 0x00000000);
+	mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
+	mtdcr(SDRAMC_CFGDATA, 0x00000000);
+
+	mode = SDRAM_BXCF_M_BE_ENABLE;
+
+	bank_0_populated = 0;
+
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		if (dimm_populated[dimm_num] != SDRAM_NONE) {
+			num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
+			num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
+			if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
+				num_ranks = (num_ranks & 0x0F) +1;
+			else
+				num_ranks = num_ranks & 0x0F;
+
+			num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
+
+			for (ind_bank = 0; ind_bank < 2; ind_bank++) {
+				if (num_banks == 4)
+					ind = 0;
+				else
+					ind = 5;
+				switch (num_col_addr) {
+				case 0x08:
+					mode |= (SDRAM_BXCF_M_AM_0 + ind);
+					break;
+				case 0x09:
+					mode |= (SDRAM_BXCF_M_AM_1 + ind);
+					break;
+				case 0x0A:
+					mode |= (SDRAM_BXCF_M_AM_2 + ind);
+					break;
+				case 0x0B:
+					mode |= (SDRAM_BXCF_M_AM_3 + ind);
+					break;
+				case 0x0C:
+					mode |= (SDRAM_BXCF_M_AM_4 + ind);
+					break;
+				default:
+					printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
+					       (unsigned int)dimm_num);
+					printf("ERROR: Unsupported value for number of "
+					       "column addresses: %d.\n", (unsigned int)num_col_addr);
+					printf("Replace the DIMM module with a supported DIMM.\n\n");
+					hang();
+				}
+			}
+
+			if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
+				bank_0_populated = 1;
+
+			for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
+				mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
+				mtdcr(SDRAMC_CFGDATA, mode);
+			}
+		}
+	}
+}
+
+/*------------------------------------------------------------------
+ * program memory queue.
+ *-----------------------------------------------------------------*/
+static void program_memory_queue(unsigned long *dimm_populated,
+				 unsigned char *iic0_dimm_addr,
+				 unsigned long num_dimm_banks)
+{
+	unsigned long dimm_num;
+	unsigned long rank_base_addr;
+	unsigned long rank_reg;
+	unsigned long rank_size_bytes;
+	unsigned long rank_size_id;
+	unsigned long num_ranks;
+	unsigned long baseadd_size;
+	unsigned long i;
+	unsigned long bank_0_populated = 0;
+
+	/*------------------------------------------------------------------
+	 * Reset the rank_base_address.
+	 *-----------------------------------------------------------------*/
+	rank_reg   = SDRAM_R0BAS;
+
+	rank_base_addr = 0x00000000;
+
+	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
+		if (dimm_populated[dimm_num] != SDRAM_NONE) {
+			num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
+			if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
+				num_ranks = (num_ranks & 0x0F) + 1;
+			else
+				num_ranks = num_ranks & 0x0F;
+
+			rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
+
+			/*------------------------------------------------------------------
+			 * Set the sizes
+			 *-----------------------------------------------------------------*/
+			baseadd_size = 0;
+			rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
+			switch (rank_size_id) {
+			case 0x02:
+				baseadd_size |= SDRAM_RXBAS_SDSZ_8;
+				break;
+			case 0x04:
+				baseadd_size |= SDRAM_RXBAS_SDSZ_16;
+				break;
+			case 0x08:
+				baseadd_size |= SDRAM_RXBAS_SDSZ_32;
+				break;
+			case 0x10:
+				baseadd_size |= SDRAM_RXBAS_SDSZ_64;
+				break;
+			case 0x20:
+				baseadd_size |= SDRAM_RXBAS_SDSZ_128;
+				break;
+			case 0x40:
+				baseadd_size |= SDRAM_RXBAS_SDSZ_256;
+				break;
+			case 0x80:
+				baseadd_size |= SDRAM_RXBAS_SDSZ_512;
+				break;
+			default:
+				printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
+				       (unsigned int)dimm_num);
+				printf("ERROR: Unsupported value for the banksize: %d.\n",
+				       (unsigned int)rank_size_id);
+				printf("Replace the DIMM module with a supported DIMM.\n\n");
+				hang();
+			}
+
+			if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
+				bank_0_populated = 1;
+
+			for (i = 0; i < num_ranks; i++)	{
+				mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
+					  (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
+					   baseadd_size));
+				rank_base_addr += rank_size_bytes;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------------+
+ * is_ecc_enabled.
+ *-----------------------------------------------------------------------------*/
+static unsigned long is_ecc_enabled(void)
+{
+	unsigned long dimm_num;
+	unsigned long ecc;
+	unsigned long val;
+
+	ecc = 0;
+	/* loop through all the DIMM slots on the board */
+	for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
+		mfsdram(SDRAM_MCOPT1, val);
+		ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
+	}
+
+	return ecc;
+}
+
+#ifdef CONFIG_DDR_ECC
+/*-----------------------------------------------------------------------------+
+ * program_ecc.
+ *-----------------------------------------------------------------------------*/
+static void program_ecc(unsigned long *dimm_populated,
+			unsigned char *iic0_dimm_addr,
+			unsigned long num_dimm_banks,
+			unsigned long tlb_word2_i_value)
+{
+	unsigned long mcopt1;
+	unsigned long mcopt2;
+	unsigned long mcstat;
+	unsigned long dimm_num;
+	unsigned long ecc;
+
+	ecc = 0;
+	/* loop through all the DIMM slots on the board */
+	for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
+		/* If a dimm is installed in a particular slot ... */
+		if (dimm_populated[dimm_num] != SDRAM_NONE)
+			ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
+	}
+	if (ecc == 0)
+		return;
+
+	mfsdram(SDRAM_MCOPT1, mcopt1);
+	mfsdram(SDRAM_MCOPT2, mcopt2);
+
+	if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
+		/* DDR controller must be enabled and not in self-refresh. */
+		mfsdram(SDRAM_MCSTAT, mcstat);
+		if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
+		    && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
+		    && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
+			== (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
+
+			program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
+		}
+	}
+
+	return;
+}
+
+#ifdef CONFIG_ECC_ERROR_RESET
+/*
+ * Check for ECC errors and reset board upon any error here
+ *
+ * On the Katmai 440SPe eval board, from time to time, the first
+ * lword write access after DDR2 initializazion with ECC checking
+ * enabled, leads to an ECC error. I couldn't find a configuration
+ * without this happening. On my board with the current setup it
+ * happens about 1 from 10 times.
+ *
+ * The ECC modules used for testing are:
+ * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
+ *
+ * This has to get fixed for the Katmai and tested for the other
+ * board (440SP/440SPe) that will eventually use this code in the
+ * future.
+ *
+ * 2007-03-01, sr
+ */
+static void check_ecc(void)
+{
+	u32 val;
+
+	mfsdram(SDRAM_ECCCR, val);
+	if (val != 0) {
+		printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
+		       val, mfdcr(0x4c), mfdcr(0x4e));
+		printf("ECC error occured, resetting board...\n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+}
+#endif
+
+static void wait_ddr_idle(void)
+{
+	u32 val;
+
+	do {
+		mfsdram(SDRAM_MCSTAT, val);
+	} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
+}
+
+/*-----------------------------------------------------------------------------+
+ * program_ecc_addr.
+ *-----------------------------------------------------------------------------*/
+static void program_ecc_addr(unsigned long start_address,
+			     unsigned long num_bytes,
+			     unsigned long tlb_word2_i_value)
+{
+	unsigned long current_address;
+	unsigned long end_address;
+	unsigned long address_increment;
+	unsigned long mcopt1;
+	char str[] = "ECC generation...";
+	int i;
+
+	current_address = start_address;
+	mfsdram(SDRAM_MCOPT1, mcopt1);
+	if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
+		mtsdram(SDRAM_MCOPT1,
+			(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
+		sync();
+		eieio();
+		wait_ddr_idle();
+
+		puts(str);
+		if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
+			/* ECC bit set method for non-cached memory */
+			if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
+				address_increment = 4;
+			else
+				address_increment = 8;
+			end_address = current_address + num_bytes;
+
+			while (current_address < end_address) {
+				*((unsigned long *)current_address) = 0x00000000;
+				current_address += address_increment;
+			}
+		} else {
+			/* ECC bit set method for cached memory */
+			dcbz_area(start_address, num_bytes);
+			dflush();
+		}
+		for (i=0; i<strlen(str); i++)
+			putc('\b');
+
+		sync();
+		eieio();
+		wait_ddr_idle();
+
+		/* clear ECC error repoting registers */
+		mtsdram(SDRAM_ECCCR, 0xffffffff);
+		mtdcr(0x4c, 0xffffffff);
+
+		mtsdram(SDRAM_MCOPT1,
+			(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
+		sync();
+		eieio();
+		wait_ddr_idle();
+
+#ifdef CONFIG_ECC_ERROR_RESET
+		/*
+		 * One write to 0 is enough to trigger this ECC error
+		 * (see description above)
+		 */
+		out_be32(0, 0x12345678);
+		check_ecc();
+#endif
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------------+
+ * program_DQS_calibration.
+ *-----------------------------------------------------------------------------*/
+static void program_DQS_calibration(unsigned long *dimm_populated,
+				    unsigned char *iic0_dimm_addr,
+				    unsigned long num_dimm_banks)
+{
+	unsigned long val;
+
+#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
+	mtsdram(SDRAM_RQDC, 0x80000037);
+	mtsdram(SDRAM_RDCC, 0x40000000);
+	mtsdram(SDRAM_RFDC, 0x000001DF);
+
+	test();
+#else
+	/*------------------------------------------------------------------
+	 * Program RDCC register
+	 * Read sample cycle auto-update enable
+	 *-----------------------------------------------------------------*/
+
+	/*
+	 * Modified for the Katmai platform:  with some DIMMs, the DDR2
+	 * controller automatically selects the T2 read cycle, but this
+	 * proves unreliable.  Go ahead and force the DDR2 controller
+	 * to use the T4 sample and disable the automatic update of the
+	 * RDSS field.
+	 */
+	mfsdram(SDRAM_RDCC, val);
+	mtsdram(SDRAM_RDCC,
+		(val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
+		| (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
+
+	/*------------------------------------------------------------------
+	 * Program RQDC register
+	 * Internal DQS delay mechanism enable
+	 *-----------------------------------------------------------------*/
+	mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
+
+	/*------------------------------------------------------------------
+	 * Program RFDC register
+	 * Set Feedback Fractional Oversample
+	 * Auto-detect read sample cycle enable
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_RFDC, val);
+	mtsdram(SDRAM_RFDC,
+		(val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
+			 SDRAM_RFDC_RFFD_MASK))
+		| (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
+		   SDRAM_RFDC_RFFD_ENCODE(0)));
+
+	DQS_calibration_process();
+#endif
+}
+
+static u32 short_mem_test(void)
+{
+	u32 *membase;
+	u32 bxcr_num;
+	u32 bxcf;
+	int i;
+	int j;
+	u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
+		{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
+		{0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
+		{0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
+		{0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
+		{0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
+		{0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
+		{0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
+		{0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
+
+	for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
+		mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
+
+		/* Banks enabled */
+		if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
+
+			/* Bank is enabled */
+			membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
+
+			/*------------------------------------------------------------------
+			 * Run the short memory test.
+			 *-----------------------------------------------------------------*/
+			for (i = 0; i < NUMMEMTESTS; i++) {
+				for (j = 0; j < NUMMEMWORDS; j++) {
+					membase[j] = test[i][j];
+					ppcDcbf((u32)&(membase[j]));
+				}
+				sync();
+				for (j = 0; j < NUMMEMWORDS; j++) {
+					if (membase[j] != test[i][j]) {
+						ppcDcbf((u32)&(membase[j]));
+						break;
+					}
+					ppcDcbf((u32)&(membase[j]));
+				}
+				sync();
+				if (j < NUMMEMWORDS)
+					break;
+			}
+			if (i < NUMMEMTESTS)
+				break;
+		}	/* if bank enabled */
+	}		/* for bxcf_num */
+
+	return bxcr_num;
+}
+
+#ifndef HARD_CODED_DQS
+/*-----------------------------------------------------------------------------+
+ * DQS_calibration_process.
+ *-----------------------------------------------------------------------------*/
+static void DQS_calibration_process(void)
+{
+	unsigned long ecc_temp;
+	unsigned long rfdc_reg;
+	unsigned long rffd;
+	unsigned long rqdc_reg;
+	unsigned long rqfd;
+	unsigned long bxcr_num;
+	unsigned long val;
+	long rqfd_average;
+	long rffd_average;
+	long max_start;
+	long min_end;
+	unsigned long begin_rqfd[MAXRANKS];
+	unsigned long begin_rffd[MAXRANKS];
+	unsigned long end_rqfd[MAXRANKS];
+	unsigned long end_rffd[MAXRANKS];
+	char window_found;
+	unsigned long dlycal;
+	unsigned long dly_val;
+	unsigned long max_pass_length;
+	unsigned long current_pass_length;
+	unsigned long current_fail_length;
+	unsigned long current_start;
+	long max_end;
+	unsigned char fail_found;
+	unsigned char pass_found;
+
+	/*------------------------------------------------------------------
+	 * Test to determine the best read clock delay tuning bits.
+	 *
+	 * Before the DDR controller can be used, the read clock delay needs to be
+	 * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
+	 * This value cannot be hardcoded into the program because it changes
+	 * depending on the board's setup and environment.
+	 * To do this, all delay values are tested to see if they
+	 * work or not.  By doing this, you get groups of fails with groups of
+	 * passing values.  The idea is to find the start and end of a passing
+	 * window and take the center of it to use as the read clock delay.
+	 *
+	 * A failure has to be seen first so that when we hit a pass, we know
+	 * that it is truely the start of the window.  If we get passing values
+	 * to start off with, we don't know if we are at the start of the window.
+	 *
+	 * The code assumes that a failure will always be found.
+	 * If a failure is not found, there is no easy way to get the middle
+	 * of the passing window.  I guess we can pretty much pick any value
+	 * but some values will be better than others.  Since the lowest speed
+	 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
+	 * from experimentation it is safe to say you will always have a failure.
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_MCOPT1, ecc_temp);
+	ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
+	mfsdram(SDRAM_MCOPT1, val);
+	mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
+		SDRAM_MCOPT1_MCHK_NON);
+
+	max_start = 0;
+	min_end = 0;
+	begin_rqfd[0] = 0;
+	begin_rffd[0] = 0;
+	begin_rqfd[1] = 0;
+	begin_rffd[1] = 0;
+	end_rqfd[0] = 0;
+	end_rffd[0] = 0;
+	end_rqfd[1] = 0;
+	end_rffd[1] = 0;
+	window_found = FALSE;
+
+	max_pass_length = 0;
+	max_start = 0;
+	max_end = 0;
+	current_pass_length = 0;
+	current_fail_length = 0;
+	current_start = 0;
+	window_found = FALSE;
+	fail_found = FALSE;
+	pass_found = FALSE;
+
+	/* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
+	/* rqdc_reg = mfsdram(SDRAM_RQDC) & ~(SDRAM_RQDC_RQFD_MASK); */
+
+	/*
+	 * get the delay line calibration register value
+	 */
+	mfsdram(SDRAM_DLCR, dlycal);
+	dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
+
+	for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
+		mfsdram(SDRAM_RFDC, rfdc_reg);
+		rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
+
+		/*------------------------------------------------------------------
+		 * Set the timing reg for the test.
+		 *-----------------------------------------------------------------*/
+		mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
+
+		/* do the small memory test */
+		bxcr_num = short_mem_test();
+
+		/*------------------------------------------------------------------
+		 * See if the rffd value passed.
+		 *-----------------------------------------------------------------*/
+		if (bxcr_num == MAXBXCF) {
+			if (fail_found == TRUE) {
+				pass_found = TRUE;
+				if (current_pass_length == 0)
+					current_start = rffd;
+
+				current_fail_length = 0;
+				current_pass_length++;
+
+				if (current_pass_length > max_pass_length) {
+					max_pass_length = current_pass_length;
+					max_start = current_start;
+					max_end = rffd;
+				}
+			}
+		} else {
+			current_pass_length = 0;
+			current_fail_length++;
+
+			if (current_fail_length >= (dly_val >> 2)) {
+				if (fail_found == FALSE) {
+					fail_found = TRUE;
+				} else if (pass_found == TRUE) {
+					window_found = TRUE;
+					break;
+				}
+			}
+		}
+	}		/* for rffd */
+
+	/*------------------------------------------------------------------
+	 * Set the average RFFD value
+	 *-----------------------------------------------------------------*/
+	rffd_average = ((max_start + max_end) >> 1);
+
+	if (rffd_average < 0)
+		rffd_average = 0;
+
+	if (rffd_average > SDRAM_RFDC_RFFD_MAX)
+		rffd_average = SDRAM_RFDC_RFFD_MAX;
+	/* now fix RFDC[RFFD] found and find RQDC[RQFD] */
+	mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
+
+	max_pass_length = 0;
+	max_start = 0;
+	max_end = 0;
+	current_pass_length = 0;
+	current_fail_length = 0;
+	current_start = 0;
+	window_found = FALSE;
+	fail_found = FALSE;
+	pass_found = FALSE;
+
+	for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
+		mfsdram(SDRAM_RQDC, rqdc_reg);
+		rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
+
+		/*------------------------------------------------------------------
+		 * Set the timing reg for the test.
+		 *-----------------------------------------------------------------*/
+		mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
+
+		/* do the small memory test */
+		bxcr_num = short_mem_test();
+
+		/*------------------------------------------------------------------
+		 * See if the rffd value passed.
+		 *-----------------------------------------------------------------*/
+		if (bxcr_num == MAXBXCF) {
+			if (fail_found == TRUE) {
+				pass_found = TRUE;
+				if (current_pass_length == 0)
+					current_start = rqfd;
+
+				current_fail_length = 0;
+				current_pass_length++;
+
+				if (current_pass_length > max_pass_length) {
+					max_pass_length = current_pass_length;
+					max_start = current_start;
+					max_end = rqfd;
+				}
+			}
+		} else {
+			current_pass_length = 0;
+			current_fail_length++;
+
+			if (fail_found == FALSE) {
+				fail_found = TRUE;
+			} else if (pass_found == TRUE) {
+				window_found = TRUE;
+				break;
+			}
+		}
+	}
+
+	/*------------------------------------------------------------------
+	 * Make sure we found the valid read passing window.  Halt if not
+	 *-----------------------------------------------------------------*/
+	if (window_found == FALSE) {
+		printf("ERROR: Cannot determine a common read delay for the "
+		       "DIMM(s) installed.\n");
+		debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
+		hang();
+	}
+
+	rqfd_average = ((max_start + max_end) >> 1);
+
+	if (rqfd_average < 0)
+		rqfd_average = 0;
+
+	if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
+		rqfd_average = SDRAM_RQDC_RQFD_MAX;
+
+	/*------------------------------------------------------------------
+	 * Restore the ECC variable to what it originally was
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_MCOPT1, val);
+	mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | ecc_temp);
+
+	mtsdram(SDRAM_RQDC,
+		(rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
+		SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
+
+	mfsdram(SDRAM_DLCR, val);
+	debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
+	mfsdram(SDRAM_RQDC, val);
+	debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
+	mfsdram(SDRAM_RFDC, val);
+	debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
+}
+#else /* calibration test with hardvalues */
+/*-----------------------------------------------------------------------------+
+ * DQS_calibration_process.
+ *-----------------------------------------------------------------------------*/
+static void test(void)
+{
+	unsigned long dimm_num;
+	unsigned long ecc_temp;
+	unsigned long i, j;
+	unsigned long *membase;
+	unsigned long bxcf[MAXRANKS];
+	unsigned long val;
+	char window_found;
+	char begin_found[MAXDIMMS];
+	char end_found[MAXDIMMS];
+	char search_end[MAXDIMMS];
+	unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
+		{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
+		{0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
+		{0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
+		{0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
+		{0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
+		{0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
+		{0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
+		{0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
+
+	/*------------------------------------------------------------------
+	 * Test to determine the best read clock delay tuning bits.
+	 *
+	 * Before the DDR controller can be used, the read clock delay needs to be
+	 * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
+	 * This value cannot be hardcoded into the program because it changes
+	 * depending on the board's setup and environment.
+	 * To do this, all delay values are tested to see if they
+	 * work or not.  By doing this, you get groups of fails with groups of
+	 * passing values.  The idea is to find the start and end of a passing
+	 * window and take the center of it to use as the read clock delay.
+	 *
+	 * A failure has to be seen first so that when we hit a pass, we know
+	 * that it is truely the start of the window.  If we get passing values
+	 * to start off with, we don't know if we are at the start of the window.
+	 *
+	 * The code assumes that a failure will always be found.
+	 * If a failure is not found, there is no easy way to get the middle
+	 * of the passing window.  I guess we can pretty much pick any value
+	 * but some values will be better than others.  Since the lowest speed
+	 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
+	 * from experimentation it is safe to say you will always have a failure.
+	 *-----------------------------------------------------------------*/
+	mfsdram(SDRAM_MCOPT1, ecc_temp);
+	ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
+	mfsdram(SDRAM_MCOPT1, val);
+	mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
+		SDRAM_MCOPT1_MCHK_NON);
+
+	window_found = FALSE;
+	begin_found[0] = FALSE;
+	end_found[0] = FALSE;
+	search_end[0] = FALSE;
+	begin_found[1] = FALSE;
+	end_found[1] = FALSE;
+	search_end[1] = FALSE;
+
+	for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
+		mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
+
+		/* Banks enabled */
+		if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
+
+			/* Bank is enabled */
+			membase =
+				(unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
+
+			/*------------------------------------------------------------------
+			 * Run the short memory test.
+			 *-----------------------------------------------------------------*/
+			for (i = 0; i < NUMMEMTESTS; i++) {
+				for (j = 0; j < NUMMEMWORDS; j++) {
+					membase[j] = test[i][j];
+					ppcDcbf((u32)&(membase[j]));
+				}
+				sync();
+				for (j = 0; j < NUMMEMWORDS; j++) {
+					if (membase[j] != test[i][j]) {
+						ppcDcbf((u32)&(membase[j]));
+						break;
+					}
+					ppcDcbf((u32)&(membase[j]));
+				}
+				sync();
+				if (j < NUMMEMWORDS)
+					break;
+			}
+
+			/*------------------------------------------------------------------
+			 * See if the rffd value passed.
+			 *-----------------------------------------------------------------*/
+			if (i < NUMMEMTESTS) {
+				if ((end_found[dimm_num] == FALSE) &&
+				    (search_end[dimm_num] == TRUE)) {
+					end_found[dimm_num] = TRUE;
+				}
+				if ((end_found[0] == TRUE) &&
+				    (end_found[1] == TRUE))
+					break;
+			} else {
+				if (begin_found[dimm_num] == FALSE) {
+					begin_found[dimm_num] = TRUE;
+					search_end[dimm_num] = TRUE;
+				}
+			}
+		} else {
+			begin_found[dimm_num] = TRUE;
+			end_found[dimm_num] = TRUE;
+		}
+	}
+
+	if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
+		window_found = TRUE;
+
+	/*------------------------------------------------------------------
+	 * Make sure we found the valid read passing window.  Halt if not
+	 *-----------------------------------------------------------------*/
+	if (window_found == FALSE) {
+		printf("ERROR: Cannot determine a common read delay for the "
+		       "DIMM(s) installed.\n");
+		hang();
+	}
+
+	/*------------------------------------------------------------------
+	 * Restore the ECC variable to what it originally was
+	 *-----------------------------------------------------------------*/
+	mtsdram(SDRAM_MCOPT1,
+		(ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
+		| ecc_temp);
+}
+#endif
+
+#if defined(DEBUG)
+static void ppc440sp_sdram_register_dump(void)
+{
+	unsigned int sdram_reg;
+	unsigned int sdram_data;
+	unsigned int dcr_data;
+
+	printf("\n  Register Dump:\n");
+	sdram_reg = SDRAM_MCSTAT;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MCSTAT    = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_MCOPT1;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MCOPT1    = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_MCOPT2;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MCOPT2    = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_MODT0;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MODT0     = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_MODT1;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MODT1     = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_MODT2;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MODT2     = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_MODT3;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MODT3     = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_CODT;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_CODT      = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_VVPR;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_VVPR      = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_OPARS;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_OPARS     = 0x%08X\n", sdram_data);
+	/*
+	 * OPAR2 is only used as a trigger register.
+	 * No data is contained in this register, and reading or writing
+	 * to is can cause bad things to happen (hangs).  Just skip it
+	 * and report NA
+	 * sdram_reg = SDRAM_OPAR2;
+	 * mfsdram(sdram_reg, sdram_data);
+	 * printf("        SDRAM_OPAR2     = 0x%08X\n", sdram_data);
+	 */
+	printf("        SDRAM_OPART     = N/A       ");
+	sdram_reg = SDRAM_RTR;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_RTR       = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_MB0CF;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MB0CF     = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_MB1CF;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MB1CF     = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_MB2CF;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MB2CF     = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_MB3CF;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MB3CF     = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_INITPLR0;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR0  = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_INITPLR1;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR1  = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_INITPLR2;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR2  = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_INITPLR3;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR3  = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_INITPLR4;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR4  = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_INITPLR5;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR5  = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_INITPLR6;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR6  = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_INITPLR7;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR7  = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_INITPLR8;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR8  = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_INITPLR9;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR9  = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_INITPLR10;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR10 = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_INITPLR11;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_INITPLR12;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR12 = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_INITPLR13;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_INITPLR14;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR14 = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_INITPLR15;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_RQDC;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_RQDC      = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_RFDC;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_RFDC      = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_RDCC;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_RDCC      = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_DLCR;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_DLCR      = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_CLKTR;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_CLKTR     = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_WRDTR;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_WRDTR     = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_SDTR1;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_SDTR1     = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_SDTR2;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_SDTR2     = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_SDTR3;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_SDTR3     = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_MMODE;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MMODE     = 0x%08X\n", sdram_data);
+	sdram_reg = SDRAM_MEMODE;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_MEMODE    = 0x%08X", sdram_data);
+	sdram_reg = SDRAM_ECCCR;
+	mfsdram(sdram_reg, sdram_data);
+	printf("        SDRAM_ECCCR     = 0x%08X\n\n", sdram_data);
+
+	dcr_data = mfdcr(SDRAM_R0BAS);
+	printf("        MQ0_B0BAS       = 0x%08X", dcr_data);
+	dcr_data = mfdcr(SDRAM_R1BAS);
+	printf("        MQ1_B0BAS       = 0x%08X\n", dcr_data);
+	dcr_data = mfdcr(SDRAM_R2BAS);
+	printf("        MQ2_B0BAS       = 0x%08X", dcr_data);
+	dcr_data = mfdcr(SDRAM_R3BAS);
+	printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
+}
+#endif
+#endif /* CONFIG_SPD_EEPROM */
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 81d49ff..cf56581 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -166,6 +166,11 @@ struct eth_device *emac0_dev = NULL;
 #define LAST_EMAC_NUM	1
 #endif
 
+/* normal boards start with EMAC0 */
+#if !defined(CONFIG_EMAC_NR_START)
+#define CONFIG_EMAC_NR_START	0
+#endif
+
 /*-----------------------------------------------------------------------------+
  * Prototypes and externals.
  *-----------------------------------------------------------------------------*/
@@ -264,10 +269,10 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 		bis->bi_phymode[3] = BI_PHYMODE_ZMII;
 		break;
 	case 2:
-		zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
-		zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
-		zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
-		zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
+		zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
 		bis->bi_phymode[0] = BI_PHYMODE_ZMII;
 		bis->bi_phymode[1] = BI_PHYMODE_ZMII;
 		bis->bi_phymode[2] = BI_PHYMODE_ZMII;
@@ -470,8 +475,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #else
 	if ((devnum == 0) || (devnum == 1)) {
 		out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
-	}
-	else { /* ((devnum == 2) || (devnum == 3)) */
+	} else { /* ((devnum == 2) || (devnum == 3)) */
 		out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
 		out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
 				   (RGMII_FER_RGMII << RGMII_FER_V (3))));
@@ -561,22 +565,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	 * otherwise, just check the speeds & feeds
 	 */
 	if (hw_p->first_init == 0) {
-#if defined(CONFIG_88E1111_CLK_DELAY)
-		/*
-		 * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
-		 * the "RGMII transmit timing control" and "RGMII receive
-		 * timing control" bits set, so that Gbit communication works
-		 * without problems.
-		 * Also set the "Transmitter disable" to 1 to enable the
-		 * transmitter.
-		 * After setting these bits a soft-reset must occur for this
-		 * change to become active.
-		 */
-		miiphy_read (dev->name, reg, 0x14, &reg_short);
-		reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
-		miiphy_write (dev->name, reg, 0x14, reg_short);
-#endif
-#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */
+#if defined(CONFIG_M88E1111_PHY)
 		miiphy_write (dev->name, reg, 0x14, 0x0ce3);
 		miiphy_write (dev->name, reg, 0x18, 0x4101);
 		miiphy_write (dev->name, reg, 0x09, 0x0e00);
@@ -617,6 +606,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 			/* end Vitesse/Cicada errata */
 		}
 #endif
+
+#if defined(CONFIG_ET1011C_PHY)
+		/*
+		 * Agere ET1011c PHY needs to have an extended register whacked
+		 * for RGMII mode.
+		 */
+		if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
+			miiphy_read (dev->name, reg, 0x16, &reg_short);
+			reg_short &= ~(0x7);
+			reg_short |= 0x6;	/* RGMII DLL Delay*/
+			miiphy_write (dev->name, reg, 0x16, reg_short);
+
+			miiphy_read (dev->name, reg, 0x17, &reg_short);
+			reg_short &= ~(0x40);
+			miiphy_write (dev->name, reg, 0x17, reg_short);
+
+			miiphy_write(dev->name, reg, 0x1c, 0x74f0);
+		}
+#endif
+
 #endif
 		/* Start/Restart autonegotiation */
 		phy_setup_aneg (dev->name, reg);
@@ -659,8 +668,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
 	if (hw_p->print_speed) {
 		hw_p->print_speed = 0;
-		printf ("ENET Speed is %d Mbps - %s duplex connection\n",
-			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
+		printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
+			(int) speed, (duplex == HALF) ? "HALF" : "FULL",
+			hw_p->devnum);
 	}
 
 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
@@ -808,7 +818,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
 		hw_p->rx_ready[i] = -1;
 #if 0
-		printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
+		printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr);
 #endif
 	}
 
@@ -1323,6 +1333,9 @@ int enetInt (struct eth_device *dev)
 			}
 		}
 		mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1);	/* Clear */
+#if defined(CONFIG_405EZ)
+		mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
+#endif	/* defined(CONFIG_405EZ) */
 	}
 	while (serviced);
 
@@ -1509,6 +1522,8 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 	struct eth_device *dev;
 	int eth_num = 0;
 	EMAC_4XX_HW_PST hw = NULL;
+	u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
+	u32 hw_addr[4];
 
 #if defined(CONFIG_440GX)
 	unsigned long pfc1;
@@ -1518,59 +1533,69 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 	pfc1 |= 0x01200000;
 	mtsdr (sdr_pfc1, pfc1);
 #endif
-	/* set phy num and mode */
-	bis->bi_phynum[0] = CONFIG_PHY_ADDR;
-	bis->bi_phymode[0] = 0;
-
-#if defined(CONFIG_PHY1_ADDR)
-	bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
-	bis->bi_phymode[1] = 0;
-#endif
-#if defined(CONFIG_440GX)
-	bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
-	bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
-	bis->bi_phymode[2] = 2;
-	bis->bi_phymode[3] = 2;
 
-	ppc_4xx_eth_setup_bridge(0, bis);
-#endif
+	/* first clear all mac-addresses */
+	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
+		memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
 
 	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
-
-		/* See if we can actually bring up the interface, otherwise, skip it */
 		switch (eth_num) {
 		default:		/* fall through */
 		case 0:
-			if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enetaddr, 6);
+			hw_addr[eth_num] = 0x0;
 			break;
 #ifdef CONFIG_HAS_ETH1
 		case 1:
-			if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enet1addr, 6);
+			hw_addr[eth_num] = 0x100;
 			break;
 #endif
 #ifdef CONFIG_HAS_ETH2
 		case 2:
-			if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enet2addr, 6);
+			hw_addr[eth_num] = 0x400;
 			break;
 #endif
 #ifdef CONFIG_HAS_ETH3
 		case 3:
-			if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
-				bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
-				continue;
-			}
+			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
+			       bis->bi_enet3addr, 6);
+			hw_addr[eth_num] = 0x600;
 			break;
 #endif
 		}
+	}
+
+	/* set phy num and mode */
+	bis->bi_phynum[0] = CONFIG_PHY_ADDR;
+	bis->bi_phymode[0] = 0;
+
+#if defined(CONFIG_PHY1_ADDR)
+	bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
+	bis->bi_phymode[1] = 0;
+#endif
+#if defined(CONFIG_440GX)
+	bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
+	bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
+	bis->bi_phymode[2] = 2;
+	bis->bi_phymode[3] = 2;
+
+	ppc_4xx_eth_setup_bridge(0, bis);
+#endif
+
+	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
+		/*
+		 * See if we can actually bring up the interface,
+		 * otherwise, skip it
+		 */
+		if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
+			bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
+			continue;
+		}
 
 		/* Allocate device structure */
 		dev = (struct eth_device *) malloc (sizeof (*dev));
@@ -1592,36 +1617,12 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 		}
 		memset(hw, 0, sizeof(*hw));
 
-		switch (eth_num) {
-		default:		/* fall through */
-		case 0:
-			hw->hw_addr = 0;
-			memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
-			break;
-#ifdef CONFIG_HAS_ETH1
-		case 1:
-			hw->hw_addr = 0x100;
-			memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
-			break;
-#endif
-#ifdef CONFIG_HAS_ETH2
-		case 2:
-			hw->hw_addr = 0x400;
-			memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
-			break;
-#endif
-#ifdef CONFIG_HAS_ETH3
-		case 3:
-			hw->hw_addr = 0x600;
-			memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
-			break;
-#endif
-		}
-
+		hw->hw_addr = hw_addr[eth_num];
+		memcpy (dev->enetaddr, ethaddr[eth_num], 6);
 		hw->devnum = eth_num;
 		hw->print_speed = 1;
 
-		sprintf (dev->name, "ppc_4xx_eth%d", eth_num);
+		sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
 		dev->priv = (void *) hw;
 		dev->init = ppc_4xx_eth_init;
 		dev->halt = ppc_4xx_eth_halt;
@@ -1679,7 +1680,6 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 	return (1);
 }
 
-
 #if !defined(CONFIG_NET_MULTI)
 void eth_halt (void) {
 	if (emac0_dev) {
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 87c6230..1347e0f 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -31,7 +31,9 @@ COBJS	= 405gp_pci.o 440spe_pcie.o 4xx_enet.o \
 	  bedbug_405.o commproc.o \
 	  cpu.o cpu_init.o i2c.o interrupts.o \
 	  miiphy.o ndfc.o sdram.o serial.o \
-	  spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o usb.o
+	  40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o speed.o \
+	  tlb.o traps.o usb_ohci.o usbdev.o usb.o \
+	  440spe_pcie.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index f4a7208..2d8740c 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -41,8 +41,15 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
+#if defined(CONFIG_BOARD_RESET)
+void board_reset(void);
+#endif
+
 #if defined(CONFIG_440)
 #define FREQ_EBC		(sys_info.freqEPB)
+#elif defined(CONFIG_405EZ)
+#define FREQ_EBC		((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \
+				 sys_info.pllExtBusDiv)
 #else
 #define FREQ_EBC		(sys_info.freqPLB / sys_info.pllExtBusDiv)
 #endif
@@ -84,14 +91,18 @@ int pci_arbiter_enabled(void)
 	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
 #endif
 
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long val;
 
-	mfsdr(sdr_sdstp1, val);
-	return (val & SDR0_SDSTP1_PAE_MASK);
+	mfsdr(sdr_xcr, val);
+	return (val & 0x80000000);
+#endif
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	unsigned long val;
+
+	mfsdr(sdr_pci0, val);
+	return (val & 0x80000000);
 #endif
 }
 #endif
@@ -201,7 +212,8 @@ int checkcpu (void)
 
 	puts("AMCC PowerPC 4");
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+    defined(CONFIG_405EP) || defined(CONFIG_405EZ)
 	puts("05");
 #endif
 #if defined(CONFIG_440)
@@ -249,6 +261,10 @@ int checkcpu (void)
 		puts("EP Rev. B");
 		break;
 
+	case PVR_405EZ_RA:
+		puts("EZ Rev. A");
+		break;
+
 #if defined(CONFIG_440)
 	case PVR_440GP_RB:
 		puts("GP Rev. B");
@@ -308,40 +324,68 @@ int checkcpu (void)
 #endif /* CONFIG_440GR */
 #endif /* CONFIG_440 */
 
-	case PVR_440EPX1_RA:
+#ifdef CONFIG_440EPX
+	case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 		puts("EPx Rev. A");
 		strcpy(addstr, "Security/Kasumi support");
 		break;
 
-	case PVR_440EPX2_RA:
+	case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 		puts("EPx Rev. A");
 		strcpy(addstr, "No Security/Kasumi support");
 		break;
+#endif /* CONFIG_440EPX */
 
-	case PVR_440GRX1_RA:
+#ifdef CONFIG_440GRX
+	case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 		puts("GRx Rev. A");
 		strcpy(addstr, "Security/Kasumi support");
 		break;
 
-	case PVR_440GRX2_RA:
+	case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 		puts("GRx Rev. A");
 		strcpy(addstr, "No Security/Kasumi support");
 		break;
+#endif /* CONFIG_440GRX */
+
+	case PVR_440SP_6_RAB:
+		puts("SP Rev. A/B");
+		strcpy(addstr, "RAID 6 support");
+		break;
 
-	case PVR_440SP_RA:
-		puts("SP Rev. A");
+	case PVR_440SP_RAB:
+		puts("SP Rev. A/B");
+		strcpy(addstr, "No RAID 6 support");
 		break;
 
-	case PVR_440SP_RB:
-		puts("SP Rev. B");
+	case PVR_440SP_6_RC:
+		puts("SP Rev. C");
+		strcpy(addstr, "RAID 6 support");
+		break;
+
+	case PVR_440SP_RC:
+		puts("SP Rev. C");
+		strcpy(addstr, "No RAID 6 support");
+		break;
+
+	case PVR_440SPe_6_RA:
+		puts("SPe Rev. A");
+		strcpy(addstr, "RAID 6 support");
 		break;
 
 	case PVR_440SPe_RA:
 		puts("SPe Rev. A");
+		strcpy(addstr, "No RAID 6 support");
+		break;
+
+	case PVR_440SPe_6_RB:
+		puts("SPe Rev. B");
+		strcpy(addstr, "RAID 6 support");
 		break;
 
 	case PVR_440SPe_RB:
 		puts("SPe Rev. B");
+		strcpy(addstr, "No RAID 6 support");
 		break;
 
 	default:
@@ -350,9 +394,9 @@ int checkcpu (void)
 	}
 
 	printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
-	       sys_info.freqPLB / 1000000,
-	       sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
-	       FREQ_EBC / 1000000);
+		sys_info.freqPLB / 1000000,
+		get_OPB_freq() / 1000000,
+		FREQ_EBC / 1000000);
 
 	if (addstr[0] != 0)
 		printf("       %s\n", addstr);
@@ -382,7 +426,7 @@ int checkcpu (void)
 	putc('\n');
 #endif
 
-#if defined(CONFIG_405EP)
+#if defined(CONFIG_405EP) || defined(CONFIG_405EZ)
 	printf ("       16 kB I-Cache 16 kB D-Cache");
 #elif defined(CONFIG_440)
 	printf ("       32 kB I-Cache 32 kB D-Cache");
@@ -411,7 +455,7 @@ int ppc440spe_revB() {
 	unsigned int pvr;
 
 	pvr = get_pvr();
-	if (pvr == PVR_440SPe_RB)
+	if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
 		return 1;
 	else
 		return 0;
@@ -422,23 +466,19 @@ int ppc440spe_revB() {
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
-	/*give reset to BCSR*/
-	*(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
-
+#if defined(CONFIG_BOARD_RESET)
+	board_reset();
+#else
+#if defined(CFG_4xx_RESET_TYPE)
+	mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
 #else
-
 	/*
 	 * Initiate system reset in debug control register DBCR
 	 */
-	__asm__ __volatile__("lis   3, 0x3000" ::: "r3");
-#if defined(CONFIG_440)
-	__asm__ __volatile__("mtspr 0x134, 3");
-#else
-	__asm__ __volatile__("mtspr 0x3f2, 3");
-#endif
+	mtspr(dbcr0, 0x30000000);
+#endif /* defined(CFG_4xx_RESET_TYPE) */
+#endif /* defined(CONFIG_BOARD_RESET) */
 
-#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
 	return 1;
 }
 
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index def46f1..9d1cd13 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -31,9 +31,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-
-#define mtebc(reg, data)  mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
-
 #ifdef CFG_INIT_DCACHE_CS
 # if (CFG_INIT_DCACHE_CS == 0)
 #  define PBxAP pb0ap
@@ -222,6 +219,10 @@ void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_M
 void
 cpu_init_f (void)
 {
+#if defined(CONFIG_WATCHDOG)
+	unsigned long val;
+#endif
+
 #if defined(CONFIG_405EP)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
@@ -255,7 +256,8 @@ cpu_init_f (void)
 	 */
 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
-     defined(CONFIG_405EP) || defined(CONFIG_405))
+     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+     defined(CONFIG_405))
 	/*
 	 * Move the next instructions into icache, since these modify the flash
 	 * we are running from!
@@ -312,15 +314,21 @@ cpu_init_f (void)
 	mtebc(pb7cr, CFG_EBC_PB7CR);
 #endif
 
-#if defined(CONFIG_WATCHDOG)
-	unsigned long val;
+#if defined (CFG_EBC_CFG)
+	mtebc(EBC0_CFG, CFG_EBC_CFG);
+#endif
 
+#if defined(CONFIG_WATCHDOG)
 	val = mfspr(tcr);
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
 #else
 	val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
 #endif
+#if defined(CFG_4xx_RESET_TYPE)
+	val &= ~0x30000000;			/* clear WRC bits */
+	val |= CFG_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
+#endif
 	mtspr(tcr, val);
 
 	val = mfspr(tsr);
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index 7db1cd8..8f4da86 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -1,91 +1,100 @@
-/*****************************************************************************/
-/* I2C Bus interface initialisation and I2C Commands                         */
-/* for PPC405GP		                                                     */
-/* Author : AS HARNOIS                                                       */
-/* Date   : 13.Dec.00                                                        */
-/*****************************************************************************/
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
+ *
+ * (C) Copyright 2001
+ * Bill Hunter,  Wave 7 Optics, williamhunter@mediaone.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
 
 #include <common.h>
 #include <ppc4xx.h>
-#if defined(CONFIG_440)
-#   include <440_i2c.h>
-#else
-#   include <405gp_i2c.h>
-#endif
+#include <4xx_i2c.h>
 #include <i2c.h>
+#include <asm-ppc/io.h>
 
 #ifdef CONFIG_HARD_I2C
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define IIC_OK		0
-#define IIC_NOK		1
-#define IIC_NOK_LA	2		/* Lost arbitration */
-#define IIC_NOK_ICT	3		/* Incomplete transfer */
-#define IIC_NOK_XFRA	4		/* Transfer aborted */
-#define IIC_NOK_DATA	5		/* No data in buffer */
-#define IIC_NOK_TOUT	6		/* Transfer timeout */
-
-#define IIC_TIMEOUT 1			/* 1 seconde */
-
+#if defined(CONFIG_I2C_MULTI_BUS)
+/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
+ * Default is bus 0.  This is necessary because the DDR initialization
+ * runs from ROM, and we can't switch buses because we can't modify
+ * the global variables.
+ */
+#ifdef CFG_SPD_BUS_NUM
+static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
+#else
+static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
+#endif
+#endif /* CONFIG_I2C_MULTI_BUS */
 
-static void _i2c_bus_reset (void)
+static void _i2c_bus_reset(void)
 {
-	int i, status;
+	int i;
+	u8 dc;
 
 	/* Reset status register */
 	/* write 1 in SCMP and IRQA to clear these fields */
-	out8 (IIC_STS, 0x0A);
+	out_8((u8 *)IIC_STS, 0x0A);
 
 	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
-	out8 (IIC_EXTSTS, 0x8F);
-	__asm__ volatile ("eieio");
-
-	/*
-	 * Get current state, reset bus
-	 * only if no transfers are pending.
-	 */
-	i = 10;
-	do {
-		/* Get status */
-		status = in8 (IIC_STS);
-		udelay (500);			/* 500us */
-		i--;
-	} while ((status & IIC_STS_PT) && (i > 0));
-	/* Soft reset controller */
-	status = in8 (IIC_XTCNTLSS);
-	out8 (IIC_XTCNTLSS, (status | IIC_XTCNTLSS_SRST));
-	__asm__ volatile ("eieio");
-
-	/* make sure where in initial state, data hi, clock hi */
-	out8 (IIC_DIRECTCNTL, 0xC);
-	for (i = 0; i < 10; i++) {
-		if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) {
-			/* clock until we get to known state */
-			out8 (IIC_DIRECTCNTL, 0x8);	/* clock lo */
-			udelay (100);		/* 100us */
-			out8 (IIC_DIRECTCNTL, 0xC);	/* clock hi */
-			udelay (100);		/* 100us */
-		} else {
-			break;
+	out_8((u8 *)IIC_EXTSTS, 0x8F);
+
+    	/* Place chip in the reset state */
+	out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST);
+
+	/* Check if bus is free */
+	dc = in_8((u8 *)IIC_DIRECTCNTL);
+	if (!DIRCTNL_FREE(dc)){
+		/* Try to set bus free state */
+		out_8((u8 *)IIC_DIRECTCNTL, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
+
+		/* Wait until we regain bus control */
+		for (i = 0; i < 100; ++i) {
+			dc = in_8((u8 *)IIC_DIRECTCNTL);
+			if (DIRCTNL_FREE(dc))
+				break;
+
+			/* Toggle SCL line */
+			dc ^= IIC_DIRCNTL_SCC;
+			out_8((u8 *)IIC_DIRECTCNTL, dc);
+			udelay(10);
+			dc ^= IIC_DIRCNTL_SCC;
+			out_8((u8 *)IIC_DIRECTCNTL, dc);
 		}
 	}
-	/* send start condition */
-	out8 (IIC_DIRECTCNTL, 0x4);
-	udelay (1000);				/* 1ms */
-	/* send stop condition */
-	out8 (IIC_DIRECTCNTL, 0xC);
-	udelay (1000);				/* 1ms */
-	/* Unreset controller */
-	out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST));
-	udelay (1000);				/* 1ms */
+
+	/* Remove reset */
+	out_8((u8 *)IIC_XTCNTLSS, 0);
 }
 
-void i2c_init (int speed, int slaveadd)
+void i2c_init(int speed, int slaveadd)
 {
 	sys_info_t sysInfo;
 	unsigned long freqOPB;
 	int val, divisor;
+	int bus;
 
 #ifdef CFG_I2C_INIT_BOARD
 	/* call board specific i2c bus reset routine before accessing the   */
@@ -94,101 +103,100 @@ void i2c_init (int speed, int slaveadd)
 	i2c_init_board();
 #endif
 
-	/* Handle possible failed I2C state */
-	/* FIXME: put this into i2c_init_board()? */
-	_i2c_bus_reset ();
+	for (bus = 0; bus < CFG_MAX_I2C_BUS; bus++) {
+		I2C_SET_BUS(bus);
 
-	/* clear lo master address */
-	out8 (IIC_LMADR, 0);
+		/* Handle possible failed I2C state */
+		/* FIXME: put this into i2c_init_board()? */
+		_i2c_bus_reset();
 
-	/* clear hi master address */
-	out8 (IIC_HMADR, 0);
+		/* clear lo master address */
+		out_8((u8 *)IIC_LMADR, 0);
 
-	/* clear lo slave address */
-	out8 (IIC_LSADR, 0);
+		/* clear hi master address */
+		out_8((u8 *)IIC_HMADR, 0);
 
-	/* clear hi slave address */
-	out8 (IIC_HSADR, 0);
+		/* clear lo slave address */
+		out_8((u8 *)IIC_LSADR, 0);
 
-	/* Clock divide Register */
-	/* get OPB frequency */
-	get_sys_info (&sysInfo);
-	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
-	/* set divisor according to freqOPB */
-	divisor = (freqOPB - 1) / 10000000;
-	if (divisor == 0)
-		divisor = 1;
-	out8 (IIC_CLKDIV, divisor);
+		/* clear hi slave address */
+		out_8((u8 *)IIC_HSADR, 0);
 
-	/* no interrupts */
-	out8 (IIC_INTRMSK, 0);
+		/* Clock divide Register */
+		/* get OPB frequency */
+		get_sys_info(&sysInfo);
+		freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
+		/* set divisor according to freqOPB */
+		divisor = (freqOPB - 1) / 10000000;
+		if (divisor == 0)
+			divisor = 1;
+		out_8((u8 *)IIC_CLKDIV, divisor);
 
-	/* clear transfer count */
-	out8 (IIC_XFRCNT, 0);
+		/* no interrupts */
+		out_8((u8 *)IIC_INTRMSK, 0);
 
-	/* clear extended control & stat */
-	/* write 1 in SRC SRS SWC SWS to clear these fields */
-	out8 (IIC_XTCNTLSS, 0xF0);
+		/* clear transfer count */
+		out_8((u8 *)IIC_XFRCNT, 0);
 
-	/* Mode Control Register
-	   Flush Slave/Master data buffer */
-	out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
-	__asm__ volatile ("eieio");
+		/* clear extended control & stat */
+		/* write 1 in SRC SRS SWC SWS to clear these fields */
+		out_8((u8 *)IIC_XTCNTLSS, 0xF0);
 
+		/* Mode Control Register
+		   Flush Slave/Master data buffer */
+		out_8((u8 *)IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
 
-	val = in8(IIC_MDCNTL);
-	__asm__ volatile ("eieio");
+		val = in_8((u8 *)IIC_MDCNTL);
 
-	/* Ignore General Call, slave transfers are ignored,
-	   disable interrupts, exit unknown bus state, enable hold
-	   SCL
-	   100kHz normaly or FastMode for 400kHz and above
-	*/
+		/* Ignore General Call, slave transfers are ignored,
+		 * disable interrupts, exit unknown bus state, enable hold
+		 * SCL 100kHz normaly or FastMode for 400kHz and above
+		 */
 
-	val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
-	if( speed >= 400000 ){
-		val |= IIC_MDCNTL_FSM;
-	}
-	out8 (IIC_MDCNTL, val);
+		val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
+		if (speed >= 400000)
+			val |= IIC_MDCNTL_FSM;
+		out_8((u8 *)IIC_MDCNTL, val);
 
-	/* clear control reg */
-	out8 (IIC_CNTL, 0x00);
-	__asm__ volatile ("eieio");
+		/* clear control reg */
+		out_8((u8 *)IIC_CNTL, 0x00);
+	}
 
+	/* set to SPD bus as default bus upon powerup */
+	I2C_SET_BUS(CFG_SPD_BUS_NUM);
 }
 
 /*
-  This code tries to use the features of the 405GP i2c
-  controller. It will transfer up to 4 bytes in one pass
-  on the loop. It only does out8(lbz) to the buffer when it
-  is possible to do out16(lhz) transfers.
-
-  cmd_type is 0 for write 1 for read.
-
-  addr_len can take any value from 0-255, it is only limited
-  by the char, we could make it larger if needed. If it is
-  0 we skip the address write cycle.
-
-  Typical case is a Write of an addr followd by a Read. The
-  IBM FAQ does not cover this. On the last byte of the write
-  we don't set the creg CHT bit, and on the first bytes of the
-  read we set the RPST bit.
-
-  It does not support address only transfers, there must be
-  a data part. If you want to write the address yourself, put
-  it in the data pointer.
-
-  It does not support transfer to/from address 0.
-
-  It does not check XFRCNT.
-*/
-static
-int i2c_transfer(unsigned char cmd_type,
-		 unsigned char chip,
-		 unsigned char addr[],
-		 unsigned char addr_len,
-		 unsigned char data[],
-		 unsigned short data_len )
+ * This code tries to use the features of the 405GP i2c
+ * controller. It will transfer up to 4 bytes in one pass
+ * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
+ * is possible to do out16(lhz) transfers.
+ *
+ * cmd_type is 0 for write 1 for read.
+ *
+ * addr_len can take any value from 0-255, it is only limited
+ * by the char, we could make it larger if needed. If it is
+ * 0 we skip the address write cycle.
+ *
+ * Typical case is a Write of an addr followd by a Read. The
+ * IBM FAQ does not cover this. On the last byte of the write
+ * we don't set the creg CHT bit, and on the first bytes of the
+ * read we set the RPST bit.
+ *
+ * It does not support address only transfers, there must be
+ * a data part. If you want to write the address yourself, put
+ * it in the data pointer.
+ *
+ * It does not support transfer to/from address 0.
+ *
+ * It does not check XFRCNT.
+ */
+static int i2c_transfer(unsigned char cmd_type,
+			unsigned char chip,
+			unsigned char addr[],
+			unsigned char addr_len,
+			unsigned char data[],
+			unsigned short data_len)
 {
 	unsigned char* ptr;
 	int reading;
@@ -198,97 +206,88 @@ int i2c_transfer(unsigned char cmd_type,
 	int i;
 	uchar creg;
 
-	if( data == 0 || data_len == 0 ){
-		/*Don't support data transfer of no length or to address 0*/
+	if (data == 0 || data_len == 0) {
+		/* Don't support data transfer of no length or to address 0 */
 		printf( "i2c_transfer: bad call\n" );
 		return IIC_NOK;
 	}
-	if( addr && addr_len ){
+	if (addr && addr_len) {
 		ptr = addr;
 		cnt = addr_len;
 		reading = 0;
-	}else{
+	} else {
 		ptr = data;
 		cnt = data_len;
 		reading = cmd_type;
 	}
 
-	/*Clear Stop Complete Bit*/
-	out8(IIC_STS,IIC_STS_SCMP);
+	/* Clear Stop Complete Bit */
+	out_8((u8 *)IIC_STS, IIC_STS_SCMP);
 	/* Check init */
-	i=10;
+	i = 10;
 	do {
 		/* Get status */
-		status = in8(IIC_STS);
-		__asm__ volatile("eieio");
+		status = in_8((u8 *)IIC_STS);
 		i--;
-	} while ((status & IIC_STS_PT) && (i>0));
+	} while ((status & IIC_STS_PT) && (i > 0));
 
 	if (status & IIC_STS_PT) {
 		result = IIC_NOK_TOUT;
 		return(result);
 	}
-	/*flush the Master/Slave Databuffers*/
-	out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
-	/*need to wait 4 OPB clocks? code below should take that long*/
+	/* flush the Master/Slave Databuffers */
+	out_8((u8 *)IIC_MDCNTL, ((in_8((u8 *)IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
+	/* need to wait 4 OPB clocks? code below should take that long */
 
 	/* 7-bit adressing */
-	out8(IIC_HMADR,0);
-	out8(IIC_LMADR, chip);
-	__asm__ volatile("eieio");
+	out_8((u8 *)IIC_HMADR, 0);
+	out_8((u8 *)IIC_LMADR, chip);
 
 	tran = 0;
 	result = IIC_OK;
 	creg = 0;
 
-	while ( tran != cnt && (result == IIC_OK)) {
+	while (tran != cnt && (result == IIC_OK)) {
 		int  bc,j;
 
 		/* Control register =
-		   Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
-		   Transfer is a sequence of transfers
-		*/
+		 * Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
+		 * Transfer is a sequence of transfers
+		 */
 		creg |= IIC_CNTL_PT;
 
-		bc = (cnt - tran) > 4 ? 4 :
-			cnt - tran;
-		creg |= (bc-1)<<4;
-		/* if the real cmd type is write continue trans*/
-		if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
+		bc = (cnt - tran) > 4 ? 4 : cnt - tran;
+		creg |= (bc - 1) << 4;
+		/* if the real cmd type is write continue trans */
+		if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
 			creg |= IIC_CNTL_CHT;
 
 		if (reading)
 			creg |= IIC_CNTL_READ;
-		else {
-			for(j=0; j<bc; j++) {
+		else
+			for(j=0; j < bc; j++)
 				/* Set buffer */
-				out8(IIC_MDBUF,ptr[tran+j]);
-				__asm__ volatile("eieio");
-			}
-		}
-		out8(IIC_CNTL, creg );
-		__asm__ volatile("eieio");
+				out_8((u8 *)IIC_MDBUF, ptr[tran+j]);
+		out_8((u8 *)IIC_CNTL, creg);
 
 		/* Transfer is in progress
-		   we have to wait for upto 5 bytes of data
-		   1 byte chip address+r/w bit then bc bytes
-		   of data.
-		   udelay(10) is 1 bit time at 100khz
-		   Doubled for slop. 20 is too small.
-		*/
-		i=2*5*8;
+		 * we have to wait for upto 5 bytes of data
+		 * 1 byte chip address+r/w bit then bc bytes
+		 * of data.
+		 * udelay(10) is 1 bit time at 100khz
+		 * Doubled for slop. 20 is too small.
+		 */
+		i = 2*5*8;
 		do {
 			/* Get status */
-			status = in8(IIC_STS);
-			__asm__ volatile("eieio");
-			udelay (10);
+			status = in_8((u8 *)IIC_STS);
+			udelay(10);
 			i--;
-		} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
-			 && (i>0));
+		} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && (i > 0));
 
 		if (status & IIC_STS_ERR) {
 			result = IIC_NOK;
-			status = in8 (IIC_EXTSTS);
+			status = in_8((u8 *)IIC_EXTSTS);
 			/* Lost arbitration? */
 			if (status & IIC_EXTSTS_LA)
 				result = IIC_NOK_LA;
@@ -306,34 +305,32 @@ int i2c_transfer(unsigned char cmd_type,
 			/* Are there data in buffer */
 			if (status & IIC_STS_MDBS) {
 				/*
-				  even if we have data we have to wait 4OPB clocks
-				  for it to hit the front of the FIFO, after that
-				  we can just read. We should check XFCNT here and
-				  if the FIFO is full there is no need to wait.
-				*/
-				udelay (1);
-				for(j=0;j<bc;j++) {
-					ptr[tran+j] = in8(IIC_MDBUF);
-					__asm__ volatile("eieio");
-				}
+				 * even if we have data we have to wait 4OPB clocks
+				 * for it to hit the front of the FIFO, after that
+				 * we can just read. We should check XFCNT here and
+				 * if the FIFO is full there is no need to wait.
+				 */
+				udelay(1);
+				for (j=0; j<bc; j++)
+					ptr[tran+j] = in_8((u8 *)IIC_MDBUF);
 			} else
 				result = IIC_NOK_DATA;
 		}
 		creg = 0;
-		tran+=bc;
-		if( ptr == addr && tran == cnt ) {
+		tran += bc;
+		if (ptr == addr && tran == cnt) {
 			ptr = data;
 			cnt = data_len;
 			tran = 0;
 			reading = cmd_type;
-			if( reading )
+			if (reading)
 				creg = IIC_CNTL_RPST;
 		}
 	}
 	return (result);
 }
 
-int i2c_probe (uchar chip)
+int i2c_probe(uchar chip)
 {
 	uchar buf[1];
 
@@ -344,21 +341,21 @@ int i2c_probe (uchar chip)
 	 * address was <ACK>ed (i.e. there was a chip at that address which
 	 * drove the data line low).
 	 */
-	return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
+	return (i2c_transfer(1, chip << 1, 0,0, buf, 1) != 0);
 }
 
 
-int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
+int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
 {
 	uchar xaddr[4];
 	int ret;
 
-	if ( alen > 4 ) {
+	if (alen > 4) {
 		printf ("I2C read: addr len %d not supported\n", alen);
 		return 1;
 	}
 
-	if ( alen > 0 ) {
+	if (alen > 0) {
 		xaddr[0] = (addr >> 24) & 0xFF;
 		xaddr[1] = (addr >> 16) & 0xFF;
 		xaddr[2] = (addr >> 8) & 0xFF;
@@ -378,10 +375,10 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
 	 * still be one byte because the extra address bits are
 	 * hidden in the chip address.
 	 */
-	if( alen > 0 )
+	if (alen > 0)
 		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
-	if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
+	if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) {
 		if (gd->have_console)
 			printf( "I2c read: failed %d\n", ret);
 		return 1;
@@ -389,16 +386,17 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
 	return 0;
 }
 
-int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
+int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
 {
 	uchar xaddr[4];
 
-	if ( alen > 4 ) {
+	if (alen > 4) {
 		printf ("I2C write: addr len %d not supported\n", alen);
 		return 1;
 
 	}
-	if ( alen > 0 ) {
+
+	if (alen > 0) {
 		xaddr[0] = (addr >> 24) & 0xFF;
 		xaddr[1] = (addr >> 16) & 0xFF;
 		xaddr[2] = (addr >> 8) & 0xFF;
@@ -417,11 +415,11 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
 	 * still be one byte because the extra address bits are
 	 * hidden in the chip address.
 	 */
-	if( alen > 0 )
+	if (alen > 0)
 		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
 
-	return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
+	return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
 }
 
 /*-----------------------------------------------------------------------
@@ -433,7 +431,7 @@ uchar i2c_reg_read(uchar i2c_addr, uchar reg)
 
 	i2c_read(i2c_addr, reg, 1, &buf, 1);
 
-	return(buf);
+	return (buf);
 }
 
 /*-----------------------------------------------------------------------
@@ -443,4 +441,38 @@ void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
 {
 	i2c_write(i2c_addr, reg, 1, &val, 1);
 }
+
+#if defined(CONFIG_I2C_MULTI_BUS)
+/*
+ * Functions for multiple I2C bus handling
+ */
+unsigned int i2c_get_bus_num(void)
+{
+	return i2c_bus_num;
+}
+
+int i2c_set_bus_num(unsigned int bus)
+{
+	if (bus >= CFG_MAX_I2C_BUS)
+		return -1;
+
+	i2c_bus_num = bus;
+
+	return 0;
+}
+#endif	/* CONFIG_I2C_MULTI_BUS */
+
+/* TODO: add 100/400k switching */
+unsigned int i2c_get_bus_speed(void)
+{
+	return CFG_I2C_SPEED;
+}
+
+int i2c_set_bus_speed(unsigned int speed)
+{
+	if (speed != CFG_I2C_SPEED)
+		return -1;
+
+	return 0;
+}
 #endif	/* CONFIG_HARD_I2C */
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index 3521731..b198ff4 100644
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -156,7 +156,7 @@ void board_nand_select_device(struct nand_chip *nand, int chip)
 	out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
 }
 
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
 	ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
@@ -188,6 +188,7 @@ void board_nand_init(struct nand_chip *nand)
 	 */
 	board_nand_select_device(nand, cs);
 	out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
+	return 0;
 }
 
 #endif
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index faeea5c..d520cd3 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005-2006
+ * (C) Copyright 2005-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2006
@@ -32,9 +32,9 @@
 #include <asm/processor.h>
 #include "sdram.h"
 
-
 #ifdef CONFIG_SDRAM_BANK0
 
+#ifndef CONFIG_440
 
 #ifndef CFG_SDRAM_TABLE
 sdram_conf_t mb0cf[] = {
@@ -50,9 +50,6 @@ sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
 
 #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
 
-
-#ifndef CONFIG_440
-
 #ifdef CFG_SDRAM_CASL
 static ulong ns2clks(ulong ns)
 {
@@ -221,6 +218,26 @@ void sdram_init(void)
 
 #else /* CONFIG_440 */
 
+/*
+ * Define some default values. Those can be overwritten in the
+ * board config file.
+ */
+
+#ifndef CFG_SDRAM_TABLE
+sdram_conf_t mb0cf[] = {
+	{(256 << 20), 13, 0x000C4001},	/* 256MB mode 3, 13x10(4)	*/
+	{(64 << 20),  12, 0x00082001}	/* 64MB mode 2, 12x9(4)		*/
+};
+#else
+sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE;
+#endif
+
+#ifndef CFG_SDRAM0_TR0
+#define	CFG_SDRAM0_TR0		0x41094012
+#endif
+
+#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+
 #define NUM_TRIES 64
 #define NUM_READS 10
 
@@ -295,7 +312,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
 	*tr1_value = (first_good + last_bad) / 2;
 }
 
-
 #ifdef CONFIG_SDRAM_ECC
 static void ecc_init(ulong start, ulong size)
 {
@@ -351,6 +367,15 @@ long int initdram(int board_type)
 	int i;
 	int tr1_bank1;
 
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+    defined(CONFIG_440GR) || defined(CONFIG_440SP)
+	/*
+	 * Soft-reset SDRAM controller.
+	 */
+	mtsdr(sdr_srst, SDR0_SRST_DMC);
+	mtsdr(sdr_srst, 0x00000000);
+#endif
+
 	for (i=0; i<N_MB0CF; i++) {
 		/*
 		 * Disable memory controller.
@@ -370,9 +395,9 @@ long int initdram(int board_type)
 		 * Following for CAS Latency = 2.5 @ 133 MHz PLB
 		 */
 		mtsdram(mem_b0cr, mb0cf[i].reg);
-		mtsdram(mem_tr0, 0x41094012);
+		mtsdram(mem_tr0, CFG_SDRAM0_TR0);
 		mtsdram(mem_tr1, 0x80800800);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
-		mtsdram(mem_rtr, 0x7e000000);	/* Interval 15.20µs @ 133MHz PLB*/
+		mtsdram(mem_rtr, 0x04100000);	/* Interval 7.8µs @ 133MHz PLB	*/
 		mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM*/
 		udelay(400);			/* Delay 200 usecs (min)	*/
 
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index fab0d95..e62dd9d 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -264,7 +264,8 @@ int serial_tstc ()
 #endif	/* CONFIG_IOP480 */
 
 /*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
     defined(CONFIG_440)
 
 #if defined(CONFIG_440)
@@ -309,7 +310,7 @@ int serial_tstc ()
 #define MFREG(a, d)	mfsdr(a, d)
 #define MTREG(a, d)	mtsdr(a, d)
 #endif /* #if defined(CONFIG_440GP) */
-#elif defined(CONFIG_405EP)
+#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
 #define UART0_BASE      0xef600300
 #define UART1_BASE      0xef600400
 #define UCR0_MASK       0x0000007f
@@ -392,47 +393,95 @@ volatile static serial_buffer_t buf_info;
 
 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
 static void serial_divs (int baudrate, unsigned long *pudiv,
-			 unsigned short *pbdiv )
+			 unsigned short *pbdiv)
 {
-	sys_info_t	sysinfo;
+	sys_info_t sysinfo;
 	unsigned long div;		/* total divisor udiv * bdiv */
 	unsigned long umin;		/* minimum udiv	*/
-	unsigned short diff;    /* smallest diff */
-	unsigned long udiv;     /* best udiv */
-
-	unsigned short idiff;   /* current diff */
-	unsigned short ibdiv;   /* current bdiv */
+	unsigned short diff;		/* smallest diff */
+	unsigned long udiv;		/* best udiv */
+	unsigned short idiff;		/* current diff */
+	unsigned short ibdiv;		/* current bdiv */
 	unsigned long i;
-	unsigned long est;      /* current estimate */
+	unsigned long est;		/* current estimate */
 
-	get_sys_info( &sysinfo );
+	get_sys_info(&sysinfo);
 
-	udiv = 32;     /* Assume lowest possible serial clk */
-	div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
-	umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
-	diff = 32;      /* highest possible */
+	udiv = 32;			/* Assume lowest possible serial clk */
+	div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
+	umin = sysinfo.pllOpbDiv << 1;	/* 2 x OPB divisor */
+	diff = 32;			/* highest possible */
 
 	/* i is the test udiv value -- start with the largest
 	 * possible (32) to minimize serial clock and constrain
 	 * search to umin.
 	 */
-	for( i = 32; i > umin; i-- ){
-		ibdiv = div/i;
+	for (i = 32; i > umin; i--) {
+		ibdiv = div / i;
 		est = i * ibdiv;
 		idiff = (est > div) ? (est-div) : (div-est);
-		if( idiff == 0 ){
+		if (idiff == 0) {
 			udiv = i;
 			break;      /* can't do better */
-		}
-		else if( idiff < diff ){
+		} else if (idiff < diff) {
 			udiv = i;       /* best so far */
 			diff = idiff;   /* update lowest diff*/
 		}
 	}
 
 	*pudiv = udiv;
-	*pbdiv = div/udiv;
+	*pbdiv = div / udiv;
+}
+
+#elif defined(CONFIG_405EZ)
+
+static void serial_divs (int baudrate, unsigned long *pudiv,
+			 unsigned short *pbdiv)
+{
+	sys_info_t sysinfo;
+	unsigned long div;		/* total divisor udiv * bdiv */
+	unsigned long umin;		/* minimum udiv	*/
+	unsigned short diff;		/* smallest diff */
+	unsigned long udiv;		/* best udiv */
+	unsigned short idiff;		/* current diff */
+	unsigned short ibdiv;		/* current bdiv */
+	unsigned long i;
+	unsigned long est;		/* current estimate */
+	unsigned long plloutb;
+	u32 reg;
+
+	get_sys_info(&sysinfo);
 
+	plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv)
+		   / sysinfo.pllFwdDivB);
+	udiv = 256;			/* Assume lowest possible serial clk */
+	div = plloutb / (16 * baudrate); /* total divisor */
+	umin = (plloutb / get_OPB_freq()) << 1;	/* 2 x OPB divisor */
+	diff = 256;			/* highest possible */
+
+	/* i is the test udiv value -- start with the largest
+	 * possible (256) to minimize serial clock and constrain
+	 * search to umin.
+	 */
+	for (i = 256; i > umin; i--) {
+		ibdiv = div / i;
+		est = i * ibdiv;
+		idiff = (est > div) ? (est-div) : (div-est);
+		if (idiff == 0) {
+			udiv = i;
+			break;      /* can't do better */
+		} else if (idiff < diff) {
+			udiv = i;       /* best so far */
+			diff = idiff;   /* update lowest diff*/
+		}
+	}
+
+	*pudiv = udiv;
+	mfcpr(cprperd0, reg);
+	reg &= ~0x0000ffff;
+	reg |= ((udiv - 0) << 8) | (udiv - 0);
+	mtcpr(cprperd0, reg);
+	*pbdiv = div / udiv;
 }
 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
 
@@ -518,6 +567,10 @@ int serial_init (void)
 	unsigned short bdiv;
 	volatile char val;
 
+#if defined(CONFIG_405EZ)
+	serial_divs(gd->baudrate, &udiv, &bdiv);
+	clk = tmp = reg = 0;
+#else
 #ifdef CONFIG_405EP
 	reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
 	clk = gd->cpu_clk;
@@ -548,9 +601,9 @@ int serial_init (void)
 	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
 	mtdcr (cntrl0, reg);
 #endif /* CONFIG_405EP */
-
 	tmp = gd->baudrate * udiv * 16;
 	bdiv = (clk + tmp / 2) / tmp;
+#endif /* CONFIG_405EZ */
 
 	out8(UART_BASE + UART_LCR, 0x80);	/* set DLAB bit */
 	out8(UART_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 2d16a83..028b11a 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -331,7 +331,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	unsigned long m;
 	unsigned long prbdv0;
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_YUCCA)
 	unsigned long sys_freq;
 	unsigned long sys_per=0;
 	unsigned long msr;
@@ -348,7 +348,7 @@ void get_sys_info (sys_info_t * sysInfo)
 	/*-------------------------------------------------------------------------+
 	 | Calculate the system clock speed from the period.
 	 +-------------------------------------------------------------------------*/
-	sys_freq=(ONE_BILLION/sys_per)*1000;
+	sys_freq = (ONE_BILLION / sys_per) * 1000;
 #endif
 
 	/* Extract configured divisors */
@@ -385,17 +385,17 @@ void get_sys_info (sys_info_t * sysInfo)
 		m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
 
 	/* Now calculate the individual clocks */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_YUCCA)
 	sysInfo->freqVCOMhz = (m * sys_freq) ;
 #else
-	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
+	sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m >> 1);
 #endif
 	sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
 	sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
 	sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 	sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_YUCCA)
 	/* Determine PCI Clock Period */
 	pci_clock_per = determine_pci_clock_per();
 	sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
@@ -408,7 +408,7 @@ void get_sys_info (sys_info_t * sysInfo)
 
 #endif
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_YUCCA)
 unsigned long determine_sysper(void)
 {
 	unsigned int fpga_clocking_reg;
@@ -583,7 +583,6 @@ unsigned long determine_sysper(void)
 	}
 
 	return(sys_per);
-
 }
 
 /*-------------------------------------------------------------------------+
@@ -768,11 +767,119 @@ ulong get_PCI_freq (void)
 	return val;
 }
 
+#elif defined(CONFIG_405EZ)
+void get_sys_info (PPC405_SYS_INFO * sysInfo)
+{
+	unsigned long cpr_plld;
+	unsigned long cpr_primad;
+	unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000);
+	unsigned long primad_cpudv;
+	unsigned long m;
+
+	/*
+	 * Read PLL Mode registers
+	 */
+	mfcpr(cprplld, cpr_plld);
+
+	/*
+	 * Determine forward divider A
+	 */
+	sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
+
+	/*
+	 * Determine forward divider B (should be equal to A)
+	 */
+	sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
+	if (sysInfo->pllFwdDivB == 0) {
+		sysInfo->pllFwdDivB = 8;
+	}
+
+	/*
+	 * Determine FBK_DIV.
+	 */
+	sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
+	if (sysInfo->pllFbkDiv == 0) {
+		sysInfo->pllFbkDiv = 256;
+	}
+
+	/*
+	 * Read CPR_PRIMAD register
+	 */
+	mfcpr(cprprimad, cpr_primad);
+	/*
+	 * Determine PLB_DIV.
+	 */
+	sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
+	if (sysInfo->pllPlbDiv == 0) {
+		sysInfo->pllPlbDiv = 16;
+	}
+
+	/*
+	 * Determine EXTBUS_DIV.
+	 */
+	sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
+	if (sysInfo->pllExtBusDiv == 0) {
+		sysInfo->pllExtBusDiv = 16;
+	}
+
+	/*
+	 * Determine OPB_DIV.
+	 */
+	sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
+	if (sysInfo->pllOpbDiv == 0) {
+		sysInfo->pllOpbDiv = 16;
+	}
+
+	/*
+	 * Determine the M factor
+	 */
+	m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
+
+	/*
+	 * Determine VCO clock frequency
+	 */
+	sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
+		(unsigned long long)sysClkPeriodPs;
+
+	/*
+	 * Determine CPU clock frequency
+	 */
+	primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
+	if (primad_cpudv == 0) {
+		primad_cpudv = 16;
+	}
+
+	sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv;
+
+	/*
+	 * Determine PLB clock frequency
+	 */
+	sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv;
+}
+
+/********************************************
+ * get_OPB_freq
+ * return OPB bus freq in Hz
+ *********************************************/
+ulong get_OPB_freq (void)
+{
+	ulong val = 0;
+
+	PPC405_SYS_INFO sys_info;
+
+	get_sys_info (&sys_info);
+	val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv;
+
+	return val;
+}
+
 #endif
 
 int get_clocks (void)
 {
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+    defined(CONFIG_440) || defined(CONFIG_405)
 	sys_info_t sys_info;
 
 	get_sys_info (&sys_info);
@@ -797,7 +904,9 @@ ulong get_bus_freq (ulong dummy)
 {
 	ulong val;
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+    defined(CONFIG_440) || defined(CONFIG_405)
 	sys_info_t sys_info;
 
 	get_sys_info (&sys_info);
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 8e000d3..d918b3e 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -699,7 +699,9 @@ _start:
 #endif	/* CONFIG_IOP480 */
 
 /*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+    defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+    defined(CONFIG_405)
 	/*----------------------------------------------------------------------- */
 	/* Clear and set up some registers. */
 	/*----------------------------------------------------------------------- */
@@ -727,13 +729,13 @@ _start:
 	/*----------------------------------------------------------------------- */
 	/* Enable two 128MB cachable regions. */
 	/*----------------------------------------------------------------------- */
-	addis	r4,r0,0x8000
-	addi	r4,r4,0x0001
+	lis	r4,0x8000
+	ori	r4,r4,0x0001
 	mticcr	r4			/* instruction cache */
 	isync
 
-	addis	r4,r0,0x0000
-	addi	r4,r4,0x0000
+	lis	r4,0x0000
+	ori	r4,r4,0x0000
 	mtdccr	r4			/* data cache */
 
 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
@@ -755,6 +757,70 @@ _start:
 #endif /* CONFIG_405EP */
 
 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
+/* test-only... (clean up later when NAND booting is supported) */
+#if defined(CONFIG_405EZ)
+	/********************************************************************
+	 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
+	 *******************************************************************/
+	/*
+	 * We can map the OCM on the PLB3, so map it at
+	 * CFG_OCM_DATA_ADDR + 0x8000
+	 */
+	lis	r3,CFG_OCM_DATA_ADDR@h	/* OCM location */
+	ori	r3,r3,CFG_OCM_DATA_ADDR@l
+	ori	r3,r3,0x8270	/* 32K Offset, 16K for Bank 1, R/W/Enable */
+	mtdcr	ocmplb3cr1,r3		/* Set PLB Access */
+	ori	r3,r3,0x4000		/* Add 0x4000 for bank 2 */
+	mtdcr	ocmplb3cr2,r3		/* Set PLB Access */
+	isync
+
+	lis	r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
+	ori	r3,r3,CFG_OCM_DATA_ADDR@l
+	ori	r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
+	mtdcr	ocmdscr1, r3            /* Set Data Side */
+	mtdcr	ocmiscr1, r3            /* Set Instruction Side */
+	ori	r3,r3,0x4000		/* Add 0x4000 for bank 2 */
+	mtdcr	ocmdscr2, r3            /* Set Data Side */
+	mtdcr	ocmiscr2, r3            /* Set Instruction Side */
+	addis	r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
+	mtdcr	ocmdsisdpc,r4
+
+	isync
+
+#if defined(CONFIG_NAND_SPL)
+	/*
+	 * 405EZ can boot from NAND Flash.
+	 * If we are booting the SPL (Pre-loader), copy code from
+	 * the mapped 4K NAND Flash to the OCM
+	 */
+	li	r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
+	mtctr	r4
+	lis	r2,CFG_NAND_BOOT_SPL_SRC@h
+	ori	r2,r2,CFG_NAND_BOOT_SPL_SRC@l
+	lis	r3,CFG_NAND_BOOT_SPL_DST@h
+	ori	r3,r3,CFG_NAND_BOOT_SPL_DST@l
+spl_loop:
+	lwzu	r4,4(r2)
+	stwu	r4,4(r3)
+	bdnz	spl_loop
+
+	/*
+	 * Jump to code in OCM Ram
+	 */
+	bl 	00f
+00:	mflr	r10
+	lis	r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
+	ori	r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
+	sub	r10,r10,r3
+	addi	r10,r10,28
+	mtlr	r10
+	blr
+start_ram:
+	sync
+	isync
+#endif
+#else
+/* ...test-only */
 	/********************************************************************
 	 * Setup OCM - On Chip Memory
 	 *******************************************************************/
@@ -774,6 +840,7 @@ _start:
 	addis	r4, 0, 0xC000		/* OCM data area enabled */
 	mtdcr	ocmdscntl, r4
 	isync
+#endif /* CONFIG_405EZ */
 #endif
 
 	/*----------------------------------------------------------------------- */
@@ -1361,7 +1428,7 @@ ppcSync:
 relocate_code:
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_440SPE)
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	/*
 	 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
 	 * to speed up the boot process. Now this cache needs to be disabled.
@@ -1856,3 +1923,103 @@ pll_wait:
 				     /* execution will continue from the poweron */
 				     /* vector of 0xfffffffc */
 #endif /* CONFIG_405EP */
+
+#if defined(CONFIG_440)
+#define function_prolog(func_name)      .text; \
+					.align 2; \
+					.globl func_name; \
+					func_name:
+#define function_epilog(func_name)      .type func_name,@function; \
+					.size func_name,.-func_name
+
+/*----------------------------------------------------------------------------+
+| mttlb3.
++----------------------------------------------------------------------------*/
+	function_prolog(mttlb3)
+	TLBWE(4,3,2)
+	blr
+	function_epilog(mttlb3)
+
+/*----------------------------------------------------------------------------+
+| mftlb3.
++----------------------------------------------------------------------------*/
+	function_prolog(mftlb3)
+	TLBRE(3,3,2)
+	blr
+	function_epilog(mftlb3)
+
+/*----------------------------------------------------------------------------+
+| mttlb2.
++----------------------------------------------------------------------------*/
+	function_prolog(mttlb2)
+	TLBWE(4,3,1)
+	blr
+	function_epilog(mttlb2)
+
+/*----------------------------------------------------------------------------+
+| mftlb2.
++----------------------------------------------------------------------------*/
+	function_prolog(mftlb2)
+	TLBRE(3,3,1)
+	blr
+	function_epilog(mftlb2)
+
+/*----------------------------------------------------------------------------+
+| mttlb1.
++----------------------------------------------------------------------------*/
+	function_prolog(mttlb1)
+	TLBWE(4,3,0)
+	blr
+	function_epilog(mttlb1)
+
+/*----------------------------------------------------------------------------+
+| mftlb1.
++----------------------------------------------------------------------------*/
+	function_prolog(mftlb1)
+	TLBRE(3,3,0)
+	blr
+	function_epilog(mftlb1)
+
+/*----------------------------------------------------------------------------+
+| dcbz_area.
++----------------------------------------------------------------------------*/
+	function_prolog(dcbz_area)
+	rlwinm. r5,r4,0,27,31
+	rlwinm  r5,r4,27,5,31
+	beq     ..d_ra2
+	addi    r5,r5,0x0001
+..d_ra2:mtctr   r5
+..d_ag2:dcbz    r0,r3
+	addi    r3,r3,32
+	bdnz    ..d_ag2
+	sync
+	blr
+	function_epilog(dcbz_area)
+
+/*----------------------------------------------------------------------------+
+| dflush.  Assume 32K at vector address is cachable.
++----------------------------------------------------------------------------*/
+	function_prolog(dflush)
+	mfmsr   r9
+	rlwinm  r8,r9,0,15,13
+	rlwinm  r8,r8,0,17,15
+	mtmsr   r8
+	addi    r3,r0,0x0000
+	mtspr   dvlim,r3
+	mfspr   r3,ivpr
+	addi    r4,r0,1024
+	mtctr   r4
+..dflush_loop:
+	lwz     r6,0x0(r3)
+	addi    r3,r3,32
+	bdnz    ..dflush_loop
+	addi    r3,r3,-32
+	mtctr   r4
+..ag:   dcbf    r0,r3
+	addi    r3,r3,-32
+	bdnz    ..ag
+	sync
+	mtmsr   r9
+	blr
+	function_epilog(dflush)
+#endif /* CONFIG_440 */
diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c
new file mode 100644
index 0000000..50344a4
--- /dev/null
+++ b/cpu/ppc4xx/tlb.c
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_440)
+
+#include <ppc4xx.h>
+#include <ppc440.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+
+typedef struct region {
+	unsigned long base;
+	unsigned long size;
+	unsigned long tlb_word2_i_value;
+} region_t;
+
+static int add_tlb_entry(unsigned long base_addr,
+			 unsigned long tlb_word0_size_value,
+			 unsigned long tlb_word2_i_value)
+{
+	int i;
+	unsigned long tlb_word0_value;
+	unsigned long tlb_word1_value;
+	unsigned long tlb_word2_value;
+
+	/* First, find the index of a TLB entry not being used */
+	for (i=0; i<PPC4XX_TLB_SIZE; i++) {
+		tlb_word0_value = mftlb1(i);
+		if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
+			break;
+	}
+	if (i >= PPC4XX_TLB_SIZE)
+		return -1;
+
+	/* Second, create the TLB entry */
+	tlb_word0_value = TLB_WORD0_EPN_ENCODE(base_addr) | TLB_WORD0_V_ENABLE |
+		TLB_WORD0_TS_0 | tlb_word0_size_value;
+	tlb_word1_value = TLB_WORD1_RPN_ENCODE(base_addr) | TLB_WORD1_ERPN_ENCODE(0);
+	tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
+		TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
+		TLB_WORD2_W_DISABLE | tlb_word2_i_value |
+		TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
+		TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
+		TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
+		TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
+		TLB_WORD2_SR_ENABLE;
+
+	/* Wait for all memory accesses to complete */
+	sync();
+
+	/* Third, add the TLB entries */
+	mttlb1(i, tlb_word0_value);
+	mttlb2(i, tlb_word1_value);
+	mttlb3(i, tlb_word2_value);
+
+	/* Execute an ISYNC instruction so that the new TLB entry takes effect */
+	asm("isync");
+
+	return 0;
+}
+
+static void program_tlb_addr(unsigned long base_addr, unsigned long mem_size,
+			     unsigned long tlb_word2_i_value)
+{
+	int rc;
+	int tlb_i;
+
+	tlb_i = tlb_word2_i_value;
+	while (mem_size != 0) {
+		rc = 0;
+		/* Add the TLB entries in to map the region. */
+		if (((base_addr & TLB_256MB_ALIGN_MASK) == base_addr) &&
+		    (mem_size >= TLB_256MB_SIZE)) {
+			/* Add a 256MB TLB entry */
+			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
+				mem_size -= TLB_256MB_SIZE;
+				base_addr += TLB_256MB_SIZE;
+			}
+		} else if (((base_addr & TLB_16MB_ALIGN_MASK) == base_addr) &&
+			   (mem_size >= TLB_16MB_SIZE)) {
+			/* Add a 16MB TLB entry */
+			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
+				mem_size -= TLB_16MB_SIZE;
+				base_addr += TLB_16MB_SIZE;
+			}
+		} else if (((base_addr & TLB_1MB_ALIGN_MASK) == base_addr) &&
+			   (mem_size >= TLB_1MB_SIZE)) {
+			/* Add a 1MB TLB entry */
+			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
+				mem_size -= TLB_1MB_SIZE;
+				base_addr += TLB_1MB_SIZE;
+			}
+		} else if (((base_addr & TLB_256KB_ALIGN_MASK) == base_addr) &&
+			   (mem_size >= TLB_256KB_SIZE)) {
+			/* Add a 256KB TLB entry */
+			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
+				mem_size -= TLB_256KB_SIZE;
+				base_addr += TLB_256KB_SIZE;
+			}
+		} else if (((base_addr & TLB_64KB_ALIGN_MASK) == base_addr) &&
+			   (mem_size >= TLB_64KB_SIZE)) {
+			/* Add a 64KB TLB entry */
+			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
+				mem_size -= TLB_64KB_SIZE;
+				base_addr += TLB_64KB_SIZE;
+			}
+		} else if (((base_addr & TLB_16KB_ALIGN_MASK) == base_addr) &&
+			   (mem_size >= TLB_16KB_SIZE)) {
+			/* Add a 16KB TLB entry */
+			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
+				mem_size -= TLB_16KB_SIZE;
+				base_addr += TLB_16KB_SIZE;
+			}
+		} else if (((base_addr & TLB_4KB_ALIGN_MASK) == base_addr) &&
+			   (mem_size >= TLB_4KB_SIZE)) {
+			/* Add a 4KB TLB entry */
+			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
+				mem_size -= TLB_4KB_SIZE;
+				base_addr += TLB_4KB_SIZE;
+			}
+		} else if (((base_addr & TLB_1KB_ALIGN_MASK) == base_addr) &&
+			   (mem_size >= TLB_1KB_SIZE)) {
+			/* Add a 1KB TLB entry */
+			if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
+				mem_size -= TLB_1KB_SIZE;
+				base_addr += TLB_1KB_SIZE;
+			}
+		} else {
+			printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
+				base_addr);
+		}
+
+		if (rc != 0)
+			printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
+				base_addr);
+	}
+
+	return;
+}
+
+/*
+ * Program one (or multiple) TLB entries for one memory region
+ *
+ * Common usage for boards with SDRAM DIMM modules to dynamically
+ * configure the TLB's for the SDRAM
+ */
+void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value)
+{
+	region_t region_array;
+
+	region_array.base = start;
+	region_array.size = size;
+	region_array.tlb_word2_i_value = tlb_word2_i_value;	/* en-/disable cache */
+
+	/* Call the routine to add in the tlb entries for the memory regions */
+	program_tlb_addr(region_array.base, region_array.size,
+			 region_array.tlb_word2_i_value);
+
+	return;
+}
+
+#endif /* CONFIG_440 */
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c
index ab852c5..c71a6a9 100644
--- a/cpu/ppc4xx/usb_ohci.c
+++ b/cpu/ppc4xx/usb_ohci.c
@@ -76,7 +76,7 @@
 #define m16_swap(x) swap_16(x)
 #define m32_swap(x) swap_32(x)
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
+#if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX)
 #define ohci_cpu_to_le16(x) (x)
 #define ohci_cpu_to_le32(x) (x)
 #else
@@ -1601,7 +1601,7 @@ int usb_lowlevel_init(void)
 	gohci.irq = -1;
 #if defined(CONFIG_440EP)
  	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
-#elif defined(CONFIG_440EPX)
+#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST)
 	gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
 #endif
 
@@ -1625,8 +1625,10 @@ int usb_lowlevel_init(void)
 	ohci_inited = 1;
 	urb_finished = 1;
 
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
 	/* init the device driver */
 	usb_dev_init();
+#endif
 
 	return 0;
 }
diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h
index 685d48b..bddf9e5 100644
--- a/cpu/ppc4xx/vecnum.h
+++ b/cpu/ppc4xx/vecnum.h
@@ -231,6 +231,47 @@
 
 #else /* !defined(CONFIG_440) */
 
+#if defined(CONFIG_405EZ)
+#define VECNUM_D0		0	/* DMA channel 0		*/
+#define VECNUM_D1		1	/* DMA channel 1		*/
+#define VECNUM_D2		2	/* DMA channel 2		*/
+#define VECNUM_D3		3	/* DMA channel 3		*/
+#define VECNUM_1588		4	/* IEEE 1588 network synchronization */
+#define VECNUM_U0		5	/* UART0			*/
+#define VECNUM_U1		6	/* UART1			*/
+#define VECNUM_CAN0		7	/* CAN 0			*/
+#define VECNUM_CAN1		8	/* CAN 1			*/
+#define VECNUM_SPI		9	/* SPI				*/
+#define VECNUM_IIC0		10	/* I2C				*/
+#define VECNUM_CHT0		11	/* Chameleon timer high pri interrupt */
+#define VECNUM_CHT1		12	/* Chameleon timer high pri interrupt */
+#define VECNUM_USBH1		13	/* USB Host 1			*/
+#define VECNUM_USBH2		14	/* USB Host 2			*/
+#define VECNUM_USBDEV		15	/* USB Device			*/
+#define VECNUM_ETH0		16	/* 10/100 Ethernet interrupt status */
+#define VECNUM_EWU0		17	/* Ethernet wakeup sequence detected */
+
+#define VECNUM_MADMAL		18	/* Logical OR of following MadMAL int */
+#define VECNUM_MS		18	/*	MAL_SERR_INT 		*/
+#define VECNUM_TXDE		18	/* 	MAL_TXDE_INT 		*/
+#define VECNUM_RXDE		18	/*	MAL_RXDE_INT 		*/
+
+#define VECNUM_MTE		19	/* MAL TXEOB			*/
+#define VECNUM_MTE1		20	/* MAL TXEOB1			*/
+#define VECNUM_MRE		21	/* MAL RXEOB			*/
+#define VECNUM_NAND		22	/* NAND Flash controller	*/
+#define VECNUM_ADC		23	/* ADC				*/
+#define VECNUM_DAC		24	/* DAC				*/
+#define VECNUM_OPB2PLB		25	/* OPB to PLB bridge interrupt	*/
+#define VECNUM_RESERVED0	26	/* Reserved			*/
+#define VECNUM_EIR0		27	/* External interrupt 0		*/
+#define VECNUM_EIR1		28	/* External interrupt 1		*/
+#define VECNUM_EIR2		29	/* External interrupt 2		*/
+#define VECNUM_EIR3		30	/* External interrupt 3		*/
+#define VECNUM_EIR4		31	/* External interrupt 4		*/
+
+#else	/* !CONFIG_405EZ */
+
 #define VECNUM_U0           0           /* UART0                        */
 #define VECNUM_U1           1           /* UART1                        */
 #define VECNUM_D0           5           /* DMA channel 0                */
@@ -251,6 +292,7 @@
 #define VECNUM_EIR4         29          /* External interrupt 4         */
 #define VECNUM_EIR5         30          /* External interrupt 5         */
 #define VECNUM_EIR6         31          /* External interrupt 6         */
+#endif	/* defined(CONFIG_405EZ) */
 
 #endif /* defined(CONFIG_440) */
 
diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c
index f7020ee..0fbaa16 100644
--- a/cpu/pxa/mmc.c
+++ b/cpu/pxa/mmc.c
@@ -37,7 +37,7 @@ static block_dev_desc_t mmc_dev;
 
 block_dev_desc_t * mmc_get_dev(int dev)
 {
-	return ((block_dev_desc_t *)&mmc_dev);
+	return (dev == 0) ? &mmc_dev : NULL;
 }
 
 /*
@@ -363,7 +363,7 @@ mmc_write(uchar *src, ulong dst, int size)
 
 ulong
 /****************************************************/
-mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst)
+mmc_bread(int dev_num, ulong blknr, ulong blkcnt, void *dst)
 /****************************************************/
 {
 	int mmc_block_size = MMC_BLOCK_SIZE;
diff --git a/disk/part.c b/disk/part.c
index 2255e72..9e8bd4f 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -24,6 +24,7 @@
 #include <common.h>
 #include <command.h>
 #include <ide.h>
+#include <part.h>
 
 #undef	PART_DEBUG
 
@@ -39,6 +40,58 @@
      defined(CONFIG_MMC) || \
      defined(CONFIG_SYSTEMACE) )
 
+struct block_drvr {
+	char *name;
+	block_dev_desc_t* (*get_dev)(int dev);
+};
+
+static const struct block_drvr block_drvr[] = {
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+	{ .name = "ide", .get_dev = ide_get_dev, },
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_SCSI)
+	{ .name = "scsi", .get_dev = scsi_get_dev, },
+#endif
+#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE))
+	{ .name = "usb", .get_dev = usb_stor_get_dev, },
+#endif
+#if defined(CONFIG_MMC)
+	{ .name = "mmc", .get_dev = mmc_get_dev, },
+#endif
+#if defined(CONFIG_SYSTEMACE)
+	{ .name = "ace", .get_dev = systemace_get_dev, },
+#endif
+	{ },
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+block_dev_desc_t *get_dev(char* ifname, int dev)
+{
+	const struct block_drvr *drvr = block_drvr;
+	block_dev_desc_t* (*reloc_get_dev)(int dev);
+
+	while (drvr->name) {
+		reloc_get_dev = drvr->get_dev + gd->reloc_off;
+		if (strncmp(ifname, drvr->name, strlen(drvr->name)) == 0)
+			return reloc_get_dev(dev);
+		drvr++;
+	}
+	return NULL;
+}
+#else
+block_dev_desc_t *get_dev(char* ifname, int dev)
+{
+	return NULL;
+}
+#endif
+
+#if ((CONFIG_COMMANDS & CFG_CMD_IDE)	|| \
+     (CONFIG_COMMANDS & CFG_CMD_SCSI)	|| \
+     (CONFIG_COMMANDS & CFG_CMD_USB)	|| \
+     defined(CONFIG_MMC) || \
+     defined(CONFIG_SYSTEMACE) )
+
 /* ------------------------------------------------------------------------- */
 /*
  * reports device info to the user
diff --git a/doc/README.mpc832xemds b/doc/README.mpc832xemds
new file mode 100644
index 0000000..b63cc79
--- /dev/null
+++ b/doc/README.mpc832xemds
@@ -0,0 +1,128 @@
+Freescale MPC832XEMDS Board
+-----------------------------------------
+1. Board Switches and Jumpers
+1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
+	For some reason, the HW designers describe the switch settings
+	in terms of 0 and 1, and then map that to physical switches where
+	the label "On" refers to logic 0 and "Off" is logic 1.
+
+	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+	bits may contribute to signals that are numbered based at 0,
+	and some of those signals may be high-bit-number-0 too.  Heed
+	well the names and labels and do not get confused.
+
+		"Off" == 1
+		"On"  == 0
+
+	SW3 is switch 18 as silk-screened onto the board.
+	SW4[8] is the bit labled 8 on Switch 4.
+	SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
+	SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
+	SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
+		and bits labeled 8 is set as "Off".
+
+1.1 For the MPC832XEMDS PROTO Board
+
+	First, make sure the board default setting is consistent with the document
+		 shipped with your board. Then apply the following setting:
+	SW3[1-8]= 0000_1000  (core PLL setting, core enable)
+	SW4[1-8]= 0001_0010  (Flash boot on local bus, system PLL setting)
+	SW5[1-8]= 0010_0110  (Boot from high end)
+	SW6[1-8]= 0011_0100  (Flash boot on 16 bit local bus)
+	SW7[1-8]= 1000_0011  (QE PLL setting)
+
+	ENET3/4 MII mode settings:
+	J1 1-2 (ETH3_TXER)
+	J2 2-3 (MII mode)
+	J3 2-3 (MII mode)
+	J4 2-3 (ADSL clockOscillator)
+	J5 1-2 (ETH4_TXER)
+	J6 2-3 (ClockOscillator)
+	JP1 removed (don't force PORESET)
+	JP2 mounted (ETH4/2 MII)
+	JP3 mounted (ETH3 MII)
+	JP4 mounted (HRCW from BCSR)
+
+	ENET3/4 RMII mode settings:
+	J1 1-2 (ETH3_TXER)
+	J2 1-2 (RMII mode)
+	J3 1-2 (RMII mode)
+	J4 2-3 (ADSL clockOscillator)
+	J5 1-2 (ETH4_TXER)
+	J6 2-3 (ClockOscillator)
+	JP1 removed (don't force PORESET)
+	JP2 removed (ETH4/2 RMII)
+	JP3 removed (ETH3 RMII)
+	JP4 removed (HRCW from FLASH)
+
+	on board Oscillator: 66M
+
+
+2. Memory Map
+
+2.1 The memory map should look pretty much like this:
+
+	0x0000_0000	0x7fff_ffff	DDR			2G
+	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
+	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
+	0xc000_0000	0xdfff_ffff	Empty			512M
+	0xe000_0000	0xe01f_ffff	Int Mem Reg Space	2M
+	0xe020_0000	0xe02f_ffff	Empty			1M
+	0xe030_0000	0xe03f_ffff	PCI IO			1M
+	0xe040_0000	0xefff_ffff	Empty			252M
+	0xf400_0000	0xf7ff_ffff	Empty			64M
+	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
+	0xf800_8000	0xf800_ffff	PIB CS2			32K
+	0xf801_0000	0xf801_7fff	PIB CS3			32K
+	0xfe00_0000	0xfeff_ffff	FLASH on CS0		16M
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+	include/configs/MPC832XEPB.h
+
+    CONFIG_MPC83XX	MPC83XX family for MPC8349, MPC8360 and MPC832X
+    CONFIG_MPC832X	MPC832X specific
+    CONFIG_MPC832XEMDS	MPC832XEMDS board specific
+
+4. Compilation
+
+	Assuming you're using BASH shell:
+
+		export CROSS_COMPILE=your-cross-compile-prefix
+		cd u-boot
+		make distclean
+		make MPC832XEMDS_config
+		make
+
+	MPC832X support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
+
+		1)Make sure the DIP SW support PCI mode as described in Section 1.1.
+
+		2)To Make U-Boot image support PCI 33MHz, use
+			Make MPC832XEMDS_HOST_33_config
+
+		3)To Make U-Boot image support PCI 66MHz, use
+			Make MPC832XEMDS_HOST_66M_config
+
+5. Downloading and Flashing Images
+
+5.0 Download over network:
+
+	tftp 10000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+	tftp 20000 u-boot.bin
+	protect off fe000000 fe0fffff
+	erase fe000000 fe0fffff
+	cp.b 20000 fe000000 xxxx
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+Maybe 3ffff will work too, that corresponds to the erased sectors.
+
+
+6. Notes
+	1) The console baudrate for MPC832XEMDS is 115200bps.
diff --git a/doc/README.mpc8349itx b/doc/README.mpc8349itx
new file mode 100644
index 0000000..4ae03ae
--- /dev/null
+++ b/doc/README.mpc8349itx
@@ -0,0 +1,187 @@
+Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
+---------------------------------------------------
+
+1.	Board Description
+
+	The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
+	the Freescale MPC8349E processor in a Mini-ITX form factor.
+
+	The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
+
+	A) One 8MB on-board flash EEPROM chip, instead of two.
+	B) No SATA controller
+	C) No Compact Flash slot
+	D) No Mini-PCI slot
+	E) No Vitesse 7385 5-port Ethernet switch
+	F) No 4-port USB Type-A interface
+
+2.	Board Switches and Jumpers
+
+2.0 	Descriptions for all of the board jumpers can be found in the User
+	Guide.  Of particular interest to U-Boot developers is jumper J22:
+
+	Pos.	Name		Default		Description
+	-----------------------------------------------------------------------
+	A	LGPL0		ON (0)          HRCW source, bit 0
+	B       LGPL1           ON (0)          HRCW source, bit 1
+	C       LGPL3           ON (0)		HRCW source, bit 2
+	D       LGPL5           OFF (1)         PCI_SYNC_OUT frequency
+	E       BOOT1           ON (0)          Flash EEPROM boot device
+	F       PCI_M66EN       ON (0)          PCI 66MHz enable
+	G       I2C-WP          ON (0)          I2C EEPROM write protection
+	H       F_WP            OFF (1)         Flash EEPROM write protection
+
+	Jumper J22.E is only for the ITX, and it decides the configuration
+	of the flash chips.  If J22.E is ON (i.e. jumpered), then flash chip
+	U4 is located at address FE000000 and flash chip U7 is at FE800000.
+	If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
+
+	For U-Boot development, J22.E can be used to switch back-and-forth
+	between two U-Boot images.
+
+3.	Memory Map
+
+3.1.	The memory map should look pretty much like this:
+
+	0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
+	0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
+	0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
+	0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
+	0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
+	0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
+	0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
+	0xF001_0000 - 0xF001_FFFF Local bus expansion slot
+	0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
+	0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
+	0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
+
+3.2	Flash EEPROM layout.
+
+	On the ITX, jumper J22.E is used to determine which flash chips are
+	at which address.  When J22.E is switched, addresses from FE000000
+	to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
+
+	On the ITX, at the normal boot address (aka HIGHBOOT):
+
+	FE00_0000	HRCW
+	FE70_0000	Alternative U-Boot image
+	FE80_0000	Alternative HRCW
+	FEF0_0000	U-Boot image
+	FEFF_FFFF	End of flash
+
+	On the ITX, at the low boot address (LOWBOOT)
+
+	FE00_0000	HRCW and U-Boot image
+	FE04_0000	U-Boot environment variables
+	FE80_0000	Alternative HRCW and U-Boot image
+	FEFF_FFFF	End of flash
+
+	On the ITX-GP, the only option is LOWBOOT and there is only one chip
+
+	FE00_0000	HRCW and U-Boot image
+	FE04_0000	U-Boot environment variables
+	F7FF_FFFF	End of flash
+
+4. Definitions
+
+4.1 Explanation of NEW definitions in:
+
+	include/configs/MPC8349ITX.h
+
+	CONFIG_MPC83XX	    	MPC83xx family
+	CONFIG_MPC8349	    	MPC8349 specific
+	CONFIG_MPC8349ITX		MPC8349E-mITX
+	CONFIG_MPC8349ITXGP		MPC8349E-mITX-GP
+
+5. Compilation
+
+	Assuming you're using BASH shell:
+
+		export CROSS_COMPILE=your-cross-compile-prefix
+		cd u-boot
+		make distclean
+
+		make MPC8349ITX_config
+	or:
+		make MPC8349ITXGP_config
+	or:
+		make MPC8349ITX_LOWBOOT_config
+
+		make
+
+6. Downloading and Flashing Images
+
+6.1 Download via tftp:
+
+	tftp $loadaddr <uboot>
+
+	where "<uboot>" is the path and filename, on the TFTP server, of
+	the U-Boot image.
+
+6.1 Reflash U-Boot Image using U-Boot
+
+	setenv uboot <uboot>
+	run tftpflash
+
+	where "<uboot>" is the path and filename, on the TFTP server, of
+	the U-Boot image.
+
+6.2 Using the HRCW to switch between two different U-Boot images on the ITX
+
+	Because the ITX has 16MB of flash, it is possible to keep two U-Boot
+	images in flash, and use the HRCW to specify which one is to be used
+	when the board boots.  This trick is especially effective with a
+	hardware debugger that can override the HRCW, such as the BDI-2000.
+
+	When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
+	at address FE000000.  When the BMS bit is 1, the ITX will boot the
+	image at address FEF00000.
+
+	Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
+	change the BMS bit whenever you want to boot the other image.
+
+	Step-by-step instructions:
+
+	1) Build an ITX image to be loaded at FEF00000
+
+		make distclean
+		make MPC8349ITX_config
+		make
+
+	2) Take the u-boot.bin image and flash it at FEF00000.
+
+		tftp $loadaddr u-boot.bin
+		protect off all
+		erase FEF00000 +$filesize
+		cp.b $loadaddr FEF00000 $filesize
+
+	3) Build an ITX image to be loaded at FE000000
+
+		make distclean
+		make MPC8349ITX_LOWBOOT_config
+		make
+
+	4) Take the u-boot.bin image and flash it at FE000000.
+
+		tftp $loadaddr u-boot.bin
+		protect off FE000000 +$filesize
+		erase FE000000 +$filesize
+		cp.b $loadaddr FE000000 $filesize
+
+	The HRCW in flash is currently set to boot the image at FE000000.
+
+	If you have a hardware debugger, configure it to set the HRCW to
+	B460A000 04040000 if you want to boot the image at FEF00000, or set
+	it to B060A000 04040000 if you want to boot the image at FE000000.
+
+	To change the HRCW in flash to boot the image at FEF00000, use these
+	U-Boot commands:
+
+		cp.b FE000000 1000 10000	; copy 1st flash sector to 1000
+		mw.b 1020 b4 8			; modify BMS bit
+		protect off FE000000 +10000
+		erase FE000000 +10000
+		cp.b 1000 FE000000 10000
+
+7. Notes
+	1) The console baudrate for MPC8349EITX is 115200bps.
diff --git a/doc/README.mpc8360emds b/doc/README.mpc8360emds
new file mode 100644
index 0000000..c87469f
--- /dev/null
+++ b/doc/README.mpc8360emds
@@ -0,0 +1,126 @@
+Freescale MPC8360EMDS Board
+-----------------------------------------
+1.	Board Switches and Jumpers
+1.0 	There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
+	For some reason, the HW designers describe the switch settings
+	in terms of 0 and 1, and then map that to physical switches where
+	the label "On" refers to logic 0 and "Off" is logic 1.
+
+	Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+	bits may contribute to signals that are numbered based at 0,
+	and some of those signals may be high-bit-number-0 too.  Heed
+	well the names and labels and do not get confused.
+
+		"Off" == 1
+		"On"  == 0
+
+	SW18 is switch 18 as silk-screened onto the board.
+	SW4[8] is the bit labled 8 on Switch 4.
+	SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
+	SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
+	SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
+		and bits labeled 8 is set as "Off".
+
+1.1	For the MPC8360E PB PROTO Board
+
+	First, make sure the board default setting is consistent with the
+	document shipped with your board. Then apply the following setting:
+	SW3[1-8]= 0000_0100  (HRCW setting value is performed on local bus)
+	SW4[1-8]= 0011_0000  (Flash boot on local bus)
+	SW9[1-8]= 0110_0110  (PCI Mode enabled. HRCW is read from FLASH)
+	SW10[1-8]= 0000_1000  (core PLL setting)
+	SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
+	JP6 1-2
+	on board Oscillator: 66M
+
+
+2.	Memory Map
+
+2.1.	The memory map should look pretty much like this:
+
+	0x0000_0000	0x7fff_ffff	DDR			2G
+	0x8000_0000	0x8fff_ffff	PCI MEM prefetch	256M
+	0x9000_0000	0x9fff_ffff	PCI MEM non-prefetch	256M
+	0xc000_0000	0xdfff_ffff	Empty			512M
+	0xe000_0000	0xe01f_ffff	Int Mem Reg Space	2M
+	0xe020_0000	0xe02f_ffff	Empty			1M
+	0xe030_0000	0xe03f_ffff	PCI IO			1M
+	0xe040_0000	0xefff_ffff	Empty			252M
+	0xf000_0000	0xf3ff_ffff	Local Bus SDRAM		64M
+	0xf400_0000	0xf7ff_ffff	Empty			64M
+	0xf800_0000	0xf800_7fff	BCSR on CS1		32K
+	0xf800_8000	0xf800_ffff	PIB CS4			32K
+	0xf801_0000	0xf801_7fff	PIB CS5			32K
+	0xfe00_0000	0xfeff_ffff	FLASH on CS0		16M
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+	include/configs/MPC8360EMDS.h
+
+    CONFIG_MPC83XX	    MPC83xx family for both MPC8349 and MPC8360
+    CONFIG_MPC8360	    MPC8360 specific
+    CONFIG_MPC8360EMDS	    MPC8360EMDS board specific
+
+4. Compilation
+
+	Assuming you're using BASH shell:
+
+		export CROSS_COMPILE=your-cross-compile-prefix
+		cd u-boot
+		make distclean
+		make MPC8360EMDS_config
+		make
+
+	MPC8360 support PCI in host and slave mode.
+
+	To make u-boot support PCI host 66M :
+	1) DIP SW support PCI mode as described in Section 1.1.
+	2) Make MPC8360EMDS_HOST_66_config
+
+	To make u-boot support PCI host 33M :
+	1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
+	2) Make MPC8360EMDS_HOST_33_config
+
+	To make u-boot support PCI slave 66M :
+	1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
+	2) Make MPC8360EMDS_SLAVE_config
+
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+	loadb
+	[Drop to kermit:
+	    ^\c
+	    send <u-boot-bin-image>
+	    c
+	]
+
+
+    Or via tftp:
+
+	tftp 10000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+	tftp 20000 u-boot.bin
+	protect off fef00000 fef3ffff
+	erase fef00000 fef3ffff
+
+	cp.b 20000 fef00000 xxxx
+
+	or
+
+	cp.b 20000 fef00000 3ffff
+
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+Maybe 3ffff will work too, that corresponds to the erased sectors.
+
+
+6. Notes
+	1) The console baudrate for MPC8360EMDS is 115200bps.
diff --git a/doc/README.sbc8349 b/doc/README.sbc8349
new file mode 100644
index 0000000..a0ac638
--- /dev/null
+++ b/doc/README.sbc8349
@@ -0,0 +1,99 @@
+
+
+	U-Boot for Wind River SBC834x Boards
+	====================================
+
+
+The Wind River SBC834x board is a 6U form factor (not CPCI) reference
+design that uses the MPC8347E or MPC8349E processor.  U-Boot support
+for this board is heavily based on the existing U-Boot support for
+Freescale MPC8349 reference boards.
+
+Support has been primarily tested on the SBC8349 version of the board,
+although earlier versions were also tested on the SBC8347.  The primary
+difference in the two is the level of PCI functionality.
+
+	http://www.windriver.com/products/OCD/SBC8347E_49E/
+
+
+Flash Details:
+==============
+
+The flash type is intel 28F640Jx (4096x16) [one device].  Base address
+is 0xFF80_0000 which is also where the Hardware Reset Configuration
+Word (HRCW) is stored.  Caution should be used to not overwrite the
+HRCW, or "CF RCW" with a Wind River ICE will be required to restore
+the HRCW and allow the board to enter background mode for further
+steps in the flash process.
+
+
+Restoring a corrupted or missing flash image:
+=============================================
+
+Details for storing U-boot to flash using a Wind River ICE can be found
+on page 19 of the board manual (request ERG-00328-001).  The following
+is a summary of that information:
+
+  - Connect ICE and establish connection to it from WorkBench/OCD.
+  - Ensure you have background mode (BKM) in the OCD terminal window.
+  - Select the appropriate flash type (listed above)
+  - Prepare a u-boot image by using the Wind River Convert utility;
+    by using "Convert and Add file" on the ELF file from your build.
+    Convert from FFF0_0000 to FFFF_FFFF (or to FFF3_FFFF if you are
+    trying to preserve your old environment settings).
+  - Set the start address of the erase/flash process to FFF0_0000
+  - Set the target RAM required to 64kB.
+  - Select sectors for erasing (see note on enviroment below)
+  - Select Erase and Reprogram.
+
+Note that some versions of the register files used with Workbench
+would zero some TSEC registers, which inhibits ethernet operation
+by u-boot when this register file is played to the target.  Using
+"INN" in the OCD terminal window instead of "IN" before the "GO"
+will not play the register file, and allow u-boot to use the TSEC
+interface while executed from the ICE "GO" command.
+
+Alternatively, you can locate the register file which will be named
+WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines
+beginning with "SCGA TSEC1" and "SCGA TSEC2".  This allows you to
+use all the remaining register file content.
+
+If you wish to preserve your prior U-Boot environment settings,
+then convert (and erase to) 0xFFF3FFFF instead of 0xFFFFFFFF.
+The size for converting (and erasing) must be at least as large
+as u-boot.bin.
+
+
+Updating U-Boot with U-Boot:
+============================
+
+This procedure is very similar to other boards that have u-boot installed.
+Assuming that the network has been configured, and that the new u-boot.bin
+has been copied to the TFTP server, the commands are:
+
+	tftp 200000 u-boot.bin
+	protect off all
+	erase fff00000 fff3ffff
+	cp.b 200000 fff00000 3ffff
+	protect on all
+
+
+PCI:
+====
+
+This board and U-Boot have been tested with PCI built in, on a SBC8349
+and confirmed that the "pci" command showed the intel e1000 that was
+present in the PCI slot.  Note that if a 33MHz 32bit card is inserted
+in the slot, then the whole board will clock down to a 33MHz base
+clock instead of the default 66MHz.  This will change the baud clocks
+and mess up your serial console output.  If you want to use a 33MHz PCI
+card, then you should build a U-Boot with #undef PCI_66M in the
+include/configs/sbc8349.h and store this to flash prior to powering down
+the board and inserting the 33MHz PCI card.
+
+By default PCI support is disabled to better support very early
+revision MPC834x chips with possible PCI issues.  Also PCI support is
+untested on the sbc8347 variants at this point in time.
+
+
+						Paul Gortmaker, 01/2007
diff --git a/drivers/Makefile b/drivers/Makefile
index b89b06f..0ca400c 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -44,7 +44,7 @@ COBJS	= 3c589.o 5701rls.o ali512x.o atmel_usart.o \
 	  serial.o serial_max3100.o \
 	  serial_pl010.o serial_pl011.o serial_xuartlite.o \
 	  sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
-	  status_led.o sym53c8xx.o ahci.o \
+	  status_led.o sym53c8xx.o systemace.o ahci.o \
 	  ti_pci1410a.o tigon3.o tsec.o \
 	  usb_ohci.o \
 	  usbdcore.o usbdcore_ep0.o usbdcore_mpc8xx.o usbdcore_omap1510.o \
diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index 9b10220..5579a1e 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -36,6 +36,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <asm/byteorder.h>
 #include <environment.h>
 #ifdef	CFG_FLASH_CFI_DRIVER
@@ -54,6 +55,8 @@
  * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
  *   Device IDs, Publication Number 25538 Revision A, November 8, 2001
  *
+ * define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
+ * reading and writing ... (yes there is such a Hardware).
  */
 
 #ifndef CFG_FLASH_BANKS_LIST
@@ -104,6 +107,7 @@
 #define FLASH_OFFSET_DEVICE_ID2		0x0E
 #define FLASH_OFFSET_DEVICE_ID3		0x0F
 #define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_ALT		0x555
 #define FLASH_OFFSET_CFI_RESP		0x10
 #define FLASH_OFFSET_PRIMARY_VENDOR	0x13
 #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR	0x15	/* extended query table primary addr */
@@ -154,6 +158,8 @@ typedef union {
 
 #define NUM_ERASE_REGIONS	4 /* max. number of erase regions */
 
+static uint flash_offset_cfi[2]={FLASH_OFFSET_CFI,FLASH_OFFSET_CFI_ALT};
+
 /* use CFG_MAX_FLASH_BANKS_DETECT if defined */
 #ifdef CFG_MAX_FLASH_BANKS_DETECT
 static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
@@ -253,7 +259,7 @@ inline uchar flash_read_uchar (flash_info_t * info, uint offset)
 	uchar *cp;
 
 	cp = flash_make_addr (info, 0, offset);
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
 	return (cp[0]);
 #else
 	return (cp[info->portwidth - 1]);
@@ -280,7 +286,7 @@ ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
 		debug ("addr[%x] = 0x%x\n", x, addr[x]);
 	}
 #endif
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
 	retval = ((addr[(info->portwidth)] << 8) | addr[0]);
 #else
 	retval = ((addr[(2 * info->portwidth) - 1] << 8) |
@@ -312,7 +318,7 @@ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
 		debug ("addr[%x] = 0x%x\n", x, addr[x]);
 	}
 #endif
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
 	retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
 		(addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
 #else
@@ -343,7 +349,7 @@ unsigned long flash_init (void)
 		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
 #ifndef CFG_FLASH_QUIET_TEST
 			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
-				i, flash_info[i].size, flash_info[i].size << 20);
+				i+1, flash_info[i].size, flash_info[i].size << 20);
 #endif /* CFG_FLASH_QUIET_TEST */
 		}
 #ifdef CFG_FLASH_PROTECTION
@@ -853,7 +859,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
  */
 static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
 {
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
 	unsigned short	w;
 	unsigned int	l;
 	unsigned long long ll;
@@ -864,7 +870,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
 		cword->c = c;
 		break;
 	case FLASH_CFI_16BIT:
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
 		w = c;
 		w <<= 8;
 		cword->w = (cword->w >> 8) | w;
@@ -873,7 +879,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
 #endif
 		break;
 	case FLASH_CFI_32BIT:
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
 		l = c;
 		l <<= 24;
 		cword->l = (cword->l >> 8) | l;
@@ -882,7 +888,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
 #endif
 		break;
 	case FLASH_CFI_64BIT:
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
 		ll = c;
 		ll <<= 56;
 		cword->ll = (cword->ll >> 8) | ll;
@@ -902,7 +908,7 @@ static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
 	int i;
 	uchar *cp = (uchar *) cmdbuf;
 
-#if defined(__LITTLE_ENDIAN)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
 	for (i = info->portwidth; i > 0; i--)
 #else
 	for (i = 1; i <= info->portwidth; i++)
@@ -926,27 +932,18 @@ static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset
 		debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
 		       cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
 		*addr.cp = cword.c;
-#ifdef CONFIG_BLACKFIN
-		asm("ssync;");
-#endif
 		break;
 	case FLASH_CFI_16BIT:
 		debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
 		       cmd, cword.w,
 		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
 		*addr.wp = cword.w;
-#ifdef CONFIG_BLACKFIN
-		asm("ssync;");
-#endif
 		break;
 	case FLASH_CFI_32BIT:
 		debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
 		       cmd, cword.l,
 		       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
 		*addr.lp = cword.l;
-#ifdef CONFIG_BLACKFIN
-		asm("ssync;");
-#endif
 		break;
 	case FLASH_CFI_64BIT:
 #ifdef DEBUG
@@ -961,11 +958,11 @@ static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset
 		}
 #endif
 		*addr.llp = cword.ll;
-#ifdef CONFIG_BLACKFIN
-		asm("ssync;");
-#endif
 		break;
 	}
+
+	/* Ensure all the instructions are fully finished */
+	sync();
 }
 
 static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
@@ -1136,6 +1133,7 @@ static void flash_read_jedec_ids (flash_info_t * info)
 */
 static int flash_detect_cfi (flash_info_t * info)
 {
+	int cfi_offset;
 	debug ("flash detect cfi\n");
 
 	for (info->portwidth = CFG_FLASH_CFI_WIDTH;
@@ -1144,19 +1142,22 @@ static int flash_detect_cfi (flash_info_t * info)
 		     info->chipwidth <= info->portwidth;
 		     info->chipwidth <<= 1) {
 			flash_write_cmd (info, 0, 0, info->cmd_reset);
-			flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
-			if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
-			    && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
-			    && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
-				info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
-				debug ("device interface is %d\n",
-				       info->interface);
-				debug ("found port %d chip %d ",
-				       info->portwidth, info->chipwidth);
-				debug ("port %d bits chip %d bits\n",
-				       info->portwidth << CFI_FLASH_SHIFT_WIDTH,
-				       info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
-				return 1;
+			for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi)/sizeof(uint); cfi_offset++) {
+				flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI);
+				if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+				 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
+				 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
+					info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
+					info->cfi_offset=flash_offset_cfi[cfi_offset];
+					debug ("device interface is %d\n",
+						info->interface);
+					debug ("found port %d chip %d ",
+						info->portwidth, info->chipwidth);
+					debug ("port %d bits chip %d bits\n",
+						info->portwidth << CFI_FLASH_SHIFT_WIDTH,
+						info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
+					return 1;
+				}
 			}
 		}
 	}
@@ -1193,7 +1194,7 @@ ulong flash_get_size (ulong base, int banknum)
 		info->vendor = flash_read_ushort (info, 0,
 					FLASH_OFFSET_PRIMARY_VENDOR);
 		flash_read_jedec_ids (info);
-		flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+		flash_write_cmd (info, 0, info->cfi_offset, FLASH_CMD_CFI);
 		num_erase_regions = flash_read_uchar (info,
 					FLASH_OFFSET_NUM_ERASE_REGIONS);
 		info->ext_addr = flash_read_ushort (info, 0,
@@ -1352,7 +1353,6 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
 	ctladdr.cp = flash_make_addr (info, 0, 0);
 	cptr.cp = (uchar *) dest;
 
-
 	/* Check if Flash is (sufficiently) erased */
 	switch (info->portwidth) {
 	case FLASH_CFI_8BIT:
@@ -1524,4 +1524,5 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
 	}
 }
 #endif /* CFG_FLASH_USE_BUFFER_WRITE */
+
 #endif /* CFG_FLASH_CFI */
diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c
index 65c2743..ebae5af 100644
--- a/drivers/fsl_i2c.c
+++ b/drivers/fsl_i2c.c
@@ -28,29 +28,53 @@
 #include <asm/fsl_i2c.h>	/* HW definitions */
 
 #define I2C_TIMEOUT	(CFG_HZ / 4)
-#define I2C		((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET))
 
+#define I2C_READ_BIT  1
+#define I2C_WRITE_BIT 0
+
+/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
+ * Default is bus 0.  This is necessary because the DDR initialization
+ * runs from ROM, and we can't switch buses because we can't modify
+ * the global variables.
+ */
+#ifdef CFG_SPD_BUS_NUM
+static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
+#else
+static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
+#endif
+
+static volatile struct fsl_i2c *i2c_dev[2] = {
+	(struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
+#ifdef CFG_I2C2_OFFSET
+	(struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
+#endif
+};
 
 void
 i2c_init(int speed, int slaveadd)
 {
-	/* stop I2C controller */
-	writeb(0x0, &I2C->cr);
-
-	/* set clock */
-	writeb(0x3f, &I2C->fdr);
-
-	/* set default filter */
-	writeb(0x10, &I2C->dfsrr);
-
-	/* write slave address */
-	writeb(slaveadd, &I2C->adr);
-
-	/* clear status register */
-	writeb(0x0, &I2C->sr);
-
-	/* start I2C controller */
-	writeb(I2C_CR_MEN, &I2C->cr);
+	volatile struct fsl_i2c *dev;
+
+	dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
+
+	writeb(0, &dev->cr);			/* stop I2C controller */
+	udelay(5);				/* let it shutdown in peace */
+	writeb(0x3F, &dev->fdr);		/* set bus speed */
+	writeb(0x3F, &dev->dfsrr);		/* set default filter */
+	writeb(slaveadd << 1, &dev->adr);	/* write slave address */
+	writeb(0x0, &dev->sr);			/* clear status register */
+	writeb(I2C_CR_MEN, &dev->cr);		/* start I2C controller */
+
+#ifdef	CFG_I2C2_OFFSET
+	dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
+
+	writeb(0, &dev->cr);			/* stop I2C controller */
+	writeb(0x3F, &dev->fdr);		/* set bus speed */
+	writeb(0x3F, &dev->dfsrr);		/* set default filter */
+	writeb(slaveadd, &dev->adr);		/* write slave address */
+	writeb(0x0, &dev->sr);			/* clear status register */
+	writeb(I2C_CR_MEN, &dev->cr);		/* start I2C controller */
+#endif	/* CFG_I2C2_OFFSET */
 }
 
 static __inline__ int
@@ -58,7 +82,7 @@ i2c_wait4bus(void)
 {
 	ulong timeval = get_timer(0);
 
-	while (readb(&I2C->sr) & I2C_SR_MBB) {
+	while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
 		if (get_timer(timeval) > I2C_TIMEOUT) {
 			return -1;
 		}
@@ -74,11 +98,11 @@ i2c_wait(int write)
 	ulong timeval = get_timer(0);
 
 	do {
-		csr = readb(&I2C->sr);
+		csr = readb(&i2c_dev[i2c_bus_num]->sr);
 		if (!(csr & I2C_SR_MIF))
 			continue;
 
-		writeb(0x0, &I2C->sr);
+		writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
 
 		if (csr & I2C_SR_MAL) {
 			debug("i2c_wait: MAL\n");
@@ -90,7 +114,7 @@ i2c_wait(int write)
 			return -1;
 		}
 
-		if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
+		if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
 			debug("i2c_wait: No RXACK\n");
 			return -1;
 		}
@@ -107,11 +131,11 @@ i2c_write_addr (u8 dev, u8 dir, int rsta)
 {
 	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
 	       | (rsta ? I2C_CR_RSTA : 0),
-	       &I2C->cr);
+	       &i2c_dev[i2c_bus_num]->cr);
 
-	writeb((dev << 1) | dir, &I2C->dr);
+	writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
 
-	if (i2c_wait(I2C_WRITE) < 0)
+	if (i2c_wait(I2C_WRITE_BIT) < 0)
 		return 0;
 
 	return 1;
@@ -123,12 +147,12 @@ __i2c_write(u8 *data, int length)
 	int i;
 
 	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
-	       &I2C->cr);
+	       &i2c_dev[i2c_bus_num]->cr);
 
 	for (i = 0; i < length; i++) {
-		writeb(data[i], &I2C->dr);
+		writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
 
-		if (i2c_wait(I2C_WRITE) < 0)
+		if (i2c_wait(I2C_WRITE_BIT) < 0)
 			break;
 	}
 
@@ -141,25 +165,25 @@ __i2c_read(u8 *data, int length)
 	int i;
 
 	writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
-	       &I2C->cr);
+	       &i2c_dev[i2c_bus_num]->cr);
 
 	/* dummy read */
-	readb(&I2C->dr);
+	readb(&i2c_dev[i2c_bus_num]->dr);
 
 	for (i = 0; i < length; i++) {
-		if (i2c_wait(I2C_READ) < 0)
+		if (i2c_wait(I2C_READ_BIT) < 0)
 			break;
 
 		/* Generate ack on last next to last byte */
 		if (i == length - 2)
 			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
-			       &I2C->cr);
+			       &i2c_dev[i2c_bus_num]->cr);
 
 		/* Generate stop on last byte */
 		if (i == length - 1)
-			writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr);
+			writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
 
-		data[i] = readb(&I2C->dr);
+		data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
 	}
 
 	return i;
@@ -168,17 +192,19 @@ __i2c_read(u8 *data, int length)
 int
 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
 {
-	int i = 0;
+	int i = -1; /* signal error */
 	u8 *a = (u8*)&addr;
 
 	if (i2c_wait4bus() >= 0
-	    && i2c_write_addr(dev, I2C_WRITE, 0) != 0
-	    && __i2c_write(&a[4 - alen], alen) == alen
-	    && i2c_write_addr(dev, I2C_READ, 1) != 0) {
+	    && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
+	    && __i2c_write(&a[4 - alen], alen) == alen)
+		i = 0; /* No error so far */
+
+	if (length
+	    && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
 		i = __i2c_read(data, length);
-	}
 
-	writeb(I2C_CR_MEN, &I2C->cr);
+	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
 
 	if (i == length)
 	    return 0;
@@ -189,16 +215,16 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
 int
 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
 {
-	int i = 0;
+	int i = -1; /* signal error */
 	u8 *a = (u8*)&addr;
 
 	if (i2c_wait4bus() >= 0
-	    && i2c_write_addr(dev, I2C_WRITE, 0) != 0
+	    && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
 	    && __i2c_write(&a[4 - alen], alen) == alen) {
 		i = __i2c_write(data, length);
 	}
 
-	writeb(I2C_CR_MEN, &I2C->cr);
+	writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
 
 	if (i == length)
 	    return 0;
@@ -209,16 +235,14 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
 int
 i2c_probe(uchar chip)
 {
-	int tmp;
-
-	/*
-	 * Try to read the first location of the chip.  The underlying
-	 * driver doesn't appear to support sending just the chip address
-	 * and looking for an <ACK> back.
+	/* For unknow reason the controller will ACK when
+	 * probing for a slave with the same address, so skip
+	 * it.
 	 */
-	udelay(10000);
+	if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
+		return -1;
 
-	return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
+	return i2c_read(chip, 0, 0, NULL, 0);
 }
 
 uchar
@@ -237,5 +261,34 @@ i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
 	i2c_write(i2c_addr, reg, 1, &val, 1);
 }
 
+int i2c_set_bus_num(unsigned int bus)
+{
+#ifdef CFG_I2C2_OFFSET
+	if (bus > 1) {
+#else
+	if (bus > 0) {
+#endif
+		return -1;
+	}
+
+	i2c_bus_num = bus;
+
+	return 0;
+}
+
+int i2c_set_bus_speed(unsigned int speed)
+{
+	return -1;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+	return i2c_bus_num;
+}
+
+unsigned int i2c_get_bus_speed(void)
+{
+	return 0;
+}
 #endif /* CONFIG_HARD_I2C */
 #endif /* CONFIG_FSL_I2C */
diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c
index 3899045..9fef71d 100644
--- a/drivers/nand/nand.c
+++ b/drivers/nand/nand.c
@@ -39,7 +39,7 @@ static ulong base_address[CFG_MAX_NAND_DEVICE] = CFG_NAND_BASE_LIST;
 
 static const char default_nand_name[] = "nand";
 
-extern void board_nand_init(struct nand_chip *nand);
+extern int board_nand_init(struct nand_chip *nand);
 
 static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
 			   ulong base_addr)
@@ -47,13 +47,16 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand,
 	mtd->priv = nand;
 
 	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
-	board_nand_init(nand);
-
-	if (nand_scan(mtd, 1) == 0) {
-		if (!mtd->name)
-			mtd->name = (char *)default_nand_name;
-	} else
+	if (board_nand_init(nand) == 0) {
+		if (nand_scan(mtd, 1) == 0) {
+			if (!mtd->name)
+				mtd->name = (char *)default_nand_name;
+		} else
+			mtd->name = NULL;
+	} else {
 		mtd->name = NULL;
+		mtd->size = 0;
+	}
 
 }
 
diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c
index b7a5d32..8495829 100644
--- a/drivers/nand/nand_base.c
+++ b/drivers/nand/nand_base.c
@@ -838,9 +838,9 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
 	unsigned long	timeo;
 
 	if (state == FL_ERASING)
-		timeo = CFG_HZ * 400;
+ 		timeo = (CFG_HZ * 400) / 1000;
 	else
-		timeo = CFG_HZ * 20;
+		timeo = (CFG_HZ * 20) / 1000;
 
 	if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 		this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
@@ -852,8 +852,8 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
 	while (1) {
 		if (get_timer(0) > timeo) {
 			printf("Timeout!");
-			return 0;
-			}
+			return 0x01;
+		}
 
 		if (this->dev_ready) {
 			if (this->dev_ready(mtd))
@@ -1713,6 +1713,7 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
 				goto out;
 			}
 			*retlen = written;
+			bufstart = (u_char*) &buf[written];
 
 			ofs = autoplace ? mtd->oobavail : mtd->oobsize;
 			if (eccbuf)
@@ -2337,7 +2338,7 @@ int nand_scan (struct mtd_info *mtd, int maxchips)
 			mtd->oobblock = 1024 << (extid & 0x3);
 			extid >>= 2;
 			/* Calc oobsize */
-			mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512);
+			mtd->oobsize = (8 << (extid & 0x01)) * (mtd->oobblock / 512);
 			extid >>= 2;
 			/* Calc blocksize. Blocksize is multiples of 64KiB */
 			mtd->erasesize = (64 * 1024)  << (extid & 0x03);
@@ -2407,7 +2408,9 @@ int nand_scan (struct mtd_info *mtd, int maxchips)
 	}
 
 	if (!nand_flash_ids[i].name) {
+#ifndef CFG_NAND_QUIET_TEST
 		printk (KERN_WARNING "No NAND device found!!!\n");
+#endif
 		this->select_chip(mtd, -1);
 		return 1;
 	}
diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile
new file mode 100644
index 0000000..4844181
--- /dev/null
+++ b/drivers/qe/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2006 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB 	:= $(obj)qe.a
+
+COBJS 	:= qe.o uccf.o uec.o uec_phy.o
+
+SRCS 	:= $(COBJS:.o=.c)
+OBJS 	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
new file mode 100644
index 0000000..5f20962
--- /dev/null
+++ b/drivers/qe/qe.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "common.h"
+#include "asm/errno.h"
+#include "asm/io.h"
+#include "asm/immap_qe.h"
+#include "qe.h"
+
+#if defined(CONFIG_QE)
+qe_map_t		*qe_immr = NULL;
+static qe_snum_t	snums[QE_NUM_OF_SNUM];
+
+void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
+{
+	u32           cecr;
+
+	if (cmd == QE_RESET) {
+		out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
+	} else {
+		out_be32(&qe_immr->cp.cecdr, cmd_data);
+		out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
+			 ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
+	}
+	/* Wait for the QE_CR_FLG to clear */
+	do {
+		cecr = in_be32(&qe_immr->cp.cecr);
+	} while (cecr & QE_CR_FLG);
+
+	return;
+}
+
+uint qe_muram_alloc(uint size, uint align)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	uint	retloc;
+	uint	align_mask, off;
+	uint	savebase;
+
+	align_mask = align - 1;
+	savebase = gd->mp_alloc_base;
+
+	if ((off = (gd->mp_alloc_base & align_mask)) != 0)
+		gd->mp_alloc_base += (align - off);
+
+	if ((off = size & align_mask) != 0)
+		size += (align - off);
+
+	if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) {
+		gd->mp_alloc_base = savebase;
+		printf("%s: ran out of ram.\n",  __FUNCTION__);
+	}
+
+	retloc = gd->mp_alloc_base;
+	gd->mp_alloc_base += size;
+
+	memset((void *)&qe_immr->muram[retloc], 0, size);
+
+	__asm__ __volatile__("sync");
+
+	return retloc;
+}
+
+void *qe_muram_addr(uint offset)
+{
+	return (void *)&qe_immr->muram[offset];
+}
+
+static void qe_sdma_init(void)
+{
+	volatile sdma_t	*p;
+	uint		sdma_buffer_base;
+
+	p = (volatile sdma_t *)&qe_immr->sdma;
+
+	/* All of DMA transaction in bus 1 */
+	out_be32(&p->sdaqr, 0);
+	out_be32(&p->sdaqmr, 0);
+
+	/* Allocate 2KB temporary buffer for sdma */
+	sdma_buffer_base = qe_muram_alloc(2048, 64);
+	out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
+
+	/* Clear sdma status */
+	out_be32(&p->sdsr, 0x03000000);
+
+	/* Enable global mode on bus 1, and 2KB buffer size */
+	out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
+}
+
+static u8 thread_snum[QE_NUM_OF_SNUM] = {
+	0x04, 0x05, 0x0c, 0x0d,
+	0x14, 0x15, 0x1c, 0x1d,
+	0x24, 0x25, 0x2c, 0x2d,
+	0x34, 0x35, 0x88, 0x89,
+	0x98, 0x99, 0xa8, 0xa9,
+	0xb8, 0xb9, 0xc8, 0xc9,
+	0xd8, 0xd9, 0xe8, 0xe9
+};
+
+static void qe_snums_init(void)
+{
+	int	i;
+
+	for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+		snums[i].state = QE_SNUM_STATE_FREE;
+		snums[i].num   = thread_snum[i];
+	}
+}
+
+int qe_get_snum(void)
+{
+	int	snum = -EBUSY;
+	int	i;
+
+	for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+		if (snums[i].state == QE_SNUM_STATE_FREE) {
+			snums[i].state = QE_SNUM_STATE_USED;
+			snum = snums[i].num;
+			break;
+		}
+	}
+
+	return snum;
+}
+
+void qe_put_snum(u8 snum)
+{
+	int	i;
+
+	for (i = 0; i < QE_NUM_OF_SNUM; i++) {
+		if (snums[i].num == snum) {
+			snums[i].state = QE_SNUM_STATE_FREE;
+			break;
+		}
+	}
+}
+
+void qe_init(uint qe_base)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Init the QE IMMR base */
+	qe_immr = (qe_map_t *)qe_base;
+
+	gd->mp_alloc_base = QE_DATAONLY_BASE;
+	gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE;
+
+	qe_sdma_init();
+	qe_snums_init();
+}
+
+void qe_reset(void)
+{
+	qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
+			 (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
+}
+
+void qe_assign_page(uint snum, uint para_ram_base)
+{
+	u32	cecr;
+
+	out_be32(&qe_immr->cp.cecdr, para_ram_base);
+	out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
+					 | QE_CR_FLG | QE_ASSIGN_PAGE);
+
+	/* Wait for the QE_CR_FLG to clear */
+	do {
+		cecr = in_be32(&qe_immr->cp.cecr);
+	} while (cecr & QE_CR_FLG );
+
+	return;
+}
+
+/*
+ * brg: 0~15 as BRG1~BRG16
+   rate: baud rate
+ * BRG input clock comes from the BRGCLK (internal clock generated from
+   the QE clock, it is one-half of the QE clock), If need the clock source
+   from CLKn pin, we have te change the function.
+ */
+
+#define BRG_CLK		(gd->brg_clk)
+
+int qe_set_brg(uint brg, uint rate)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	volatile uint	*bp;
+	u32		divisor;
+	int		div16 = 0;
+
+	if (brg >= QE_NUM_OF_BRGS)
+		return -EINVAL;
+	bp = (uint *)&qe_immr->brg.brgc1;
+	bp += brg;
+
+	divisor = (BRG_CLK / rate);
+	if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
+		div16 = 1;
+		divisor /= 16;
+	}
+
+	*bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
+	__asm__ __volatile__("sync");
+
+	if (div16) {
+		*bp |= QE_BRGC_DIV16;
+		__asm__ __volatile__("sync");
+	}
+
+	return 0;
+}
+
+/* Set ethernet MII clock master
+*/
+int qe_set_mii_clk_src(int ucc_num)
+{
+	u32	cmxgcr;
+
+	/* check if the UCC number is in range. */
+	if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
+		printf("%s: ucc num not in ranges\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
+	cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
+	cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
+	out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
+
+	return 0;
+}
+
+#endif /* CONFIG_QE */
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
new file mode 100644
index 0000000..0bcd0a9
--- /dev/null
+++ b/drivers/qe/qe.h
@@ -0,0 +1,237 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __QE_H__
+#define __QE_H__
+
+#include "common.h"
+
+#define QE_NUM_OF_SNUM	28
+#define QE_NUM_OF_BRGS	16
+#define UCC_MAX_NUM	8
+
+#define QE_DATAONLY_BASE	(uint)(128)
+#define QE_DATAONLY_SIZE	(QE_MURAM_SIZE - QE_DATAONLY_BASE)
+
+/* QE threads SNUM
+*/
+typedef enum qe_snum_state {
+	QE_SNUM_STATE_USED,   /* used */
+	QE_SNUM_STATE_FREE    /* free */
+} qe_snum_state_e;
+
+typedef struct qe_snum {
+	u8		num;   /* snum  */
+	qe_snum_state_e	state; /* state */
+} qe_snum_t;
+
+/* QE RISC allocation
+*/
+typedef enum qe_risc_allocation {
+	QE_RISC_ALLOCATION_RISC1		= 1,  /* RISC 1 */
+	QE_RISC_ALLOCATION_RISC2		= 2,  /* RISC 2 */
+	QE_RISC_ALLOCATION_RISC1_AND_RISC2	= 3   /* RISC 1 or RISC 2 */
+} qe_risc_allocation_e;
+
+/* QE CECR commands for UCC fast.
+*/
+#define QE_CR_FLG			0x00010000
+#define QE_RESET			0x80000000
+#define QE_INIT_TX_RX			0x00000000
+#define QE_INIT_RX			0x00000001
+#define QE_INIT_TX			0x00000002
+#define QE_ENTER_HUNT_MODE		0x00000003
+#define QE_STOP_TX			0x00000004
+#define QE_GRACEFUL_STOP_TX		0x00000005
+#define QE_RESTART_TX			0x00000006
+#define QE_SWITCH_COMMAND		0x00000007
+#define QE_SET_GROUP_ADDRESS		0x00000008
+#define QE_INSERT_CELL			0x00000009
+#define QE_ATM_TRANSMIT			0x0000000a
+#define QE_CELL_POOL_GET		0x0000000b
+#define QE_CELL_POOL_PUT		0x0000000c
+#define QE_IMA_HOST_CMD			0x0000000d
+#define QE_ATM_MULTI_THREAD_INIT	0x00000011
+#define QE_ASSIGN_PAGE			0x00000012
+#define QE_START_FLOW_CONTROL		0x00000014
+#define QE_STOP_FLOW_CONTROL		0x00000015
+#define QE_ASSIGN_PAGE_TO_DEVICE	0x00000016
+#define QE_GRACEFUL_STOP_RX		0x0000001a
+#define QE_RESTART_RX			0x0000001b
+
+/* QE CECR Sub Block Code - sub block code of QE command.
+*/
+#define QE_CR_SUBBLOCK_INVALID		0x00000000
+#define QE_CR_SUBBLOCK_USB		0x03200000
+#define QE_CR_SUBBLOCK_UCCFAST1		0x02000000
+#define QE_CR_SUBBLOCK_UCCFAST2		0x02200000
+#define QE_CR_SUBBLOCK_UCCFAST3		0x02400000
+#define QE_CR_SUBBLOCK_UCCFAST4		0x02600000
+#define QE_CR_SUBBLOCK_UCCFAST5		0x02800000
+#define QE_CR_SUBBLOCK_UCCFAST6		0x02a00000
+#define QE_CR_SUBBLOCK_UCCFAST7		0x02c00000
+#define QE_CR_SUBBLOCK_UCCFAST8		0x02e00000
+#define QE_CR_SUBBLOCK_UCCSLOW1		0x00000000
+#define QE_CR_SUBBLOCK_UCCSLOW2		0x00200000
+#define QE_CR_SUBBLOCK_UCCSLOW3		0x00400000
+#define QE_CR_SUBBLOCK_UCCSLOW4		0x00600000
+#define QE_CR_SUBBLOCK_UCCSLOW5		0x00800000
+#define QE_CR_SUBBLOCK_UCCSLOW6		0x00a00000
+#define QE_CR_SUBBLOCK_UCCSLOW7		0x00c00000
+#define QE_CR_SUBBLOCK_UCCSLOW8		0x00e00000
+#define QE_CR_SUBBLOCK_MCC1		0x03800000
+#define QE_CR_SUBBLOCK_MCC2		0x03a00000
+#define QE_CR_SUBBLOCK_MCC3		0x03000000
+#define QE_CR_SUBBLOCK_IDMA1		0x02800000
+#define QE_CR_SUBBLOCK_IDMA2		0x02a00000
+#define QE_CR_SUBBLOCK_IDMA3		0x02c00000
+#define QE_CR_SUBBLOCK_IDMA4		0x02e00000
+#define QE_CR_SUBBLOCK_HPAC		0x01e00000
+#define QE_CR_SUBBLOCK_SPI1		0x01400000
+#define QE_CR_SUBBLOCK_SPI2		0x01600000
+#define QE_CR_SUBBLOCK_RAND		0x01c00000
+#define QE_CR_SUBBLOCK_TIMER		0x01e00000
+#define QE_CR_SUBBLOCK_GENERAL		0x03c00000
+
+/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
+*/
+#define QE_CR_PROTOCOL_UNSPECIFIED	0x00 /* For all other protocols */
+#define QE_CR_PROTOCOL_HDLC_TRANSPARENT	0x00
+#define QE_CR_PROTOCOL_ATM_POS		0x0A
+#define QE_CR_PROTOCOL_ETHERNET		0x0C
+#define QE_CR_PROTOCOL_L2_SWITCH	0x0D
+#define QE_CR_PROTOCOL_SHIFT		6
+
+/* QE ASSIGN PAGE command
+*/
+#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT	17
+
+/* Communication Direction.
+*/
+typedef enum comm_dir {
+	COMM_DIR_NONE		= 0,
+	COMM_DIR_RX		= 1,
+	COMM_DIR_TX		= 2,
+	COMM_DIR_RX_AND_TX	= 3
+} comm_dir_e;
+
+/* Clocks and BRG's
+*/
+typedef enum qe_clock {
+	QE_CLK_NONE = 0,
+	QE_BRG1,     /* Baud Rate Generator  1 */
+	QE_BRG2,     /* Baud Rate Generator  2 */
+	QE_BRG3,     /* Baud Rate Generator  3 */
+	QE_BRG4,     /* Baud Rate Generator  4 */
+	QE_BRG5,     /* Baud Rate Generator  5 */
+	QE_BRG6,     /* Baud Rate Generator  6 */
+	QE_BRG7,     /* Baud Rate Generator  7 */
+	QE_BRG8,     /* Baud Rate Generator  8 */
+	QE_BRG9,     /* Baud Rate Generator  9 */
+	QE_BRG10,    /* Baud Rate Generator 10 */
+	QE_BRG11,    /* Baud Rate Generator 11 */
+	QE_BRG12,    /* Baud Rate Generator 12 */
+	QE_BRG13,    /* Baud Rate Generator 13 */
+	QE_BRG14,    /* Baud Rate Generator 14 */
+	QE_BRG15,    /* Baud Rate Generator 15 */
+	QE_BRG16,    /* Baud Rate Generator 16 */
+	QE_CLK1,     /* Clock  1               */
+	QE_CLK2,     /* Clock  2               */
+	QE_CLK3,     /* Clock  3               */
+	QE_CLK4,     /* Clock  4               */
+	QE_CLK5,     /* Clock  5               */
+	QE_CLK6,     /* Clock  6               */
+	QE_CLK7,     /* Clock  7               */
+	QE_CLK8,     /* Clock  8               */
+	QE_CLK9,     /* Clock  9               */
+	QE_CLK10,    /* Clock 10               */
+	QE_CLK11,    /* Clock 11               */
+	QE_CLK12,    /* Clock 12               */
+	QE_CLK13,    /* Clock 13               */
+	QE_CLK14,    /* Clock 14               */
+	QE_CLK15,    /* Clock 15               */
+	QE_CLK16,    /* Clock 16               */
+	QE_CLK17,    /* Clock 17               */
+	QE_CLK18,    /* Clock 18               */
+	QE_CLK19,    /* Clock 19               */
+	QE_CLK20,    /* Clock 20               */
+	QE_CLK21,    /* Clock 21               */
+	QE_CLK22,    /* Clock 22               */
+	QE_CLK23,    /* Clock 23               */
+	QE_CLK24,    /* Clock 24               */
+	QE_CLK_DUMMY
+} qe_clock_e;
+
+/* QE CMXGCR register
+*/
+#define QE_CMXGCR_MII_ENET_MNG_MASK	0x00007000
+#define QE_CMXGCR_MII_ENET_MNG_SHIFT	12
+
+/* QE CMXUCR registers
+ */
+#define QE_CMXUCR_TX_CLK_SRC_MASK	0x0000000F
+
+/* QE BRG configuration register
+*/
+#define QE_BRGC_ENABLE			0x00010000
+#define QE_BRGC_DIVISOR_SHIFT		1
+#define QE_BRGC_DIVISOR_MAX		0xFFF
+#define QE_BRGC_DIV16			1
+
+/* QE SDMA registers
+*/
+#define QE_SDSR_BER1			0x02000000
+#define QE_SDSR_BER2			0x01000000
+
+#define QE_SDMR_GLB_1_MSK		0x80000000
+#define QE_SDMR_ADR_SEL			0x20000000
+#define QE_SDMR_BER1_MSK		0x02000000
+#define QE_SDMR_BER2_MSK		0x01000000
+#define QE_SDMR_EB1_MSK			0x00800000
+#define QE_SDMR_ER1_MSK			0x00080000
+#define QE_SDMR_ER2_MSK			0x00040000
+#define QE_SDMR_CEN_MASK		0x0000E000
+#define QE_SDMR_SBER_1			0x00000200
+#define QE_SDMR_SBER_2			0x00000200
+#define QE_SDMR_EB1_PR_MASK		0x000000C0
+#define QE_SDMR_ER1_PR			0x00000008
+
+#define QE_SDMR_CEN_SHIFT		13
+#define QE_SDMR_EB1_PR_SHIFT		6
+
+#define QE_SDTM_MSNUM_SHIFT		24
+
+#define QE_SDEBCR_BA_MASK		0x01FFFFFF
+
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
+void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
+uint qe_muram_alloc(uint size, uint align);
+void *qe_muram_addr(uint offset);
+int qe_get_snum(void);
+void qe_put_snum(u8 snum);
+void qe_init(uint qe_base);
+void qe_reset(void);
+void qe_assign_page(uint snum, uint para_ram_base);
+int qe_set_brg(uint brg, uint rate);
+int qe_set_mii_clk_src(int ucc_num);
+
+#endif /* __QE_H__ */
diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c
new file mode 100644
index 0000000..c5477e0
--- /dev/null
+++ b/drivers/qe/uccf.c
@@ -0,0 +1,404 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "common.h"
+#include "malloc.h"
+#include "asm/errno.h"
+#include "asm/io.h"
+#include "asm/immap_qe.h"
+#include "qe.h"
+#include "uccf.h"
+
+#if defined(CONFIG_QE)
+void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
+{
+	out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
+}
+
+u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
+{
+	switch (ucc_num) {
+		case 0:	return QE_CR_SUBBLOCK_UCCFAST1;
+		case 1:	return QE_CR_SUBBLOCK_UCCFAST2;
+		case 2:	return QE_CR_SUBBLOCK_UCCFAST3;
+		case 3:	return QE_CR_SUBBLOCK_UCCFAST4;
+		case 4:	return QE_CR_SUBBLOCK_UCCFAST5;
+		case 5:	return QE_CR_SUBBLOCK_UCCFAST6;
+		case 6:	return QE_CR_SUBBLOCK_UCCFAST7;
+		case 7:	return QE_CR_SUBBLOCK_UCCFAST8;
+		default:	return QE_CR_SUBBLOCK_INVALID;
+	}
+}
+
+static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr,
+				 u8 *reg_num, u8 *shift)
+{
+	switch (ucc_num) {
+		case 0:	/* UCC1 */
+			*p_cmxucr  = &(qe_immr->qmx.cmxucr1);
+			*reg_num = 1;
+			*shift  = 16;
+			break;
+		case 2:	/* UCC3 */
+			*p_cmxucr  = &(qe_immr->qmx.cmxucr1);
+			*reg_num = 1;
+			*shift  = 0;
+			break;
+		case 4:	/* UCC5 */
+			*p_cmxucr  = &(qe_immr->qmx.cmxucr2);
+			*reg_num = 2;
+			*shift  = 16;
+			break;
+		case 6:	/* UCC7 */
+			*p_cmxucr  = &(qe_immr->qmx.cmxucr2);
+			*reg_num = 2;
+			*shift  = 0;
+			break;
+		case 1:	/* UCC2 */
+			*p_cmxucr  = &(qe_immr->qmx.cmxucr3);
+			*reg_num = 3;
+			*shift  = 16;
+			break;
+		case 3:	/* UCC4 */
+			*p_cmxucr  = &(qe_immr->qmx.cmxucr3);
+			*reg_num = 3;
+			*shift  = 0;
+			break;
+		case 5:	/* UCC6 */
+			*p_cmxucr  = &(qe_immr->qmx.cmxucr4);
+			*reg_num = 4;
+			*shift  = 16;
+			break;
+		case 7:	/* UCC8 */
+			*p_cmxucr  = &(qe_immr->qmx.cmxucr4);
+			*reg_num = 4;
+			*shift  = 0;
+			break;
+		default:
+			break;
+	}
+}
+
+static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
+{
+	volatile u32	*p_cmxucr = NULL;
+	u8		reg_num = 0;
+	u8		shift = 0;
+	u32		clockBits;
+	u32		clockMask;
+	int		source = -1;
+
+	/* check if the UCC number is in range. */
+	if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+		return -EINVAL;
+
+	if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
+		printf("%s: bad comm mode type passed\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
+
+	switch (reg_num) {
+		case 1:
+			switch (clock) {
+				case QE_BRG1:	source = 1; break;
+				case QE_BRG2:	source = 2; break;
+				case QE_BRG7:	source = 3; break;
+				case QE_BRG8:	source = 4; break;
+				case QE_CLK9:	source = 5; break;
+				case QE_CLK10:	source = 6; break;
+				case QE_CLK11:	source = 7; break;
+				case QE_CLK12:	source = 8; break;
+				case QE_CLK15:	source = 9; break;
+				case QE_CLK16:	source = 10; break;
+				default:	source = -1; break;
+			}
+			break;
+		case 2:
+			switch (clock) {
+				case QE_BRG5:	source = 1; break;
+				case QE_BRG6:	source = 2; break;
+				case QE_BRG7:	source = 3; break;
+				case QE_BRG8:	source = 4; break;
+				case QE_CLK13:	source = 5; break;
+				case QE_CLK14:	source = 6; break;
+				case QE_CLK19:	source = 7; break;
+				case QE_CLK20:	source = 8; break;
+				case QE_CLK15:	source = 9; break;
+				case QE_CLK16:	source = 10; break;
+				default:	source = -1; break;
+			}
+			break;
+		case 3:
+			switch (clock) {
+				case QE_BRG9:	source = 1; break;
+				case QE_BRG10:	source = 2; break;
+				case QE_BRG15:	source = 3; break;
+				case QE_BRG16:	source = 4; break;
+				case QE_CLK3:	source = 5; break;
+				case QE_CLK4:	source = 6; break;
+				case QE_CLK17:	source = 7; break;
+				case QE_CLK18:	source = 8; break;
+				case QE_CLK7:	source = 9; break;
+				case QE_CLK8:	source = 10; break;
+				case QE_CLK16:	source = 11; break;
+				default:	source = -1; break;
+			}
+			break;
+		case 4:
+			switch (clock) {
+				case QE_BRG13:	source = 1; break;
+				case QE_BRG14:	source = 2; break;
+				case QE_BRG15:	source = 3; break;
+				case QE_BRG16:	source = 4; break;
+				case QE_CLK5:	source = 5; break;
+				case QE_CLK6:	source = 6; break;
+				case QE_CLK21:	source = 7; break;
+				case QE_CLK22:	source = 8; break;
+				case QE_CLK7:	source = 9; break;
+				case QE_CLK8:	source = 10; break;
+				case QE_CLK16:	source = 11; break;
+				default:	source = -1; break;
+			}
+			break;
+		default:
+			source = -1;
+			break;
+	}
+
+	if (source == -1) {
+		printf("%s: Bad combination of clock and UCC\n", __FUNCTION__);
+		return -ENOENT;
+	}
+
+	clockBits = (u32) source;
+	clockMask = QE_CMXUCR_TX_CLK_SRC_MASK;
+	if (mode == COMM_DIR_RX) {
+		clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */
+		clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */
+	}
+	clockBits <<= shift;
+	clockMask <<= shift;
+
+	out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits);
+
+	return 0;
+}
+
+static uint ucc_get_reg_baseaddr(int ucc_num)
+{
+	uint base = 0;
+
+	/* check if the UCC number is in range */
+	if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
+		printf("%s: the UCC num not in ranges\n", __FUNCTION__);
+		return 0;
+	}
+
+	switch (ucc_num) {
+		case 0:	base = 0x00002000; break;
+		case 1:	base = 0x00003000; break;
+		case 2:	base = 0x00002200; break;
+		case 3:	base = 0x00003200; break;
+		case 4:	base = 0x00002400; break;
+		case 5:	base = 0x00003400; break;
+		case 6:	base = 0x00002600; break;
+		case 7:	base = 0x00003600; break;
+		default: break;
+	}
+
+	base = (uint)qe_immr + base;
+	return base;
+}
+
+void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode)
+{
+	ucc_fast_t	*uf_regs;
+	u32		gumr;
+
+	uf_regs = uccf->uf_regs;
+
+	/* Enable reception and/or transmission on this UCC. */
+	gumr = in_be32(&uf_regs->gumr);
+	if (mode & COMM_DIR_TX) {
+		gumr |= UCC_FAST_GUMR_ENT;
+		uccf->enabled_tx = 1;
+	}
+	if (mode & COMM_DIR_RX) {
+		gumr |= UCC_FAST_GUMR_ENR;
+		uccf->enabled_rx = 1;
+	}
+	out_be32(&uf_regs->gumr, gumr);
+}
+
+void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode)
+{
+	ucc_fast_t	*uf_regs;
+	u32		gumr;
+
+	uf_regs = uccf->uf_regs;
+
+	/* Disable reception and/or transmission on this UCC. */
+	gumr = in_be32(&uf_regs->gumr);
+	if (mode & COMM_DIR_TX) {
+		gumr &= ~UCC_FAST_GUMR_ENT;
+		uccf->enabled_tx = 0;
+	}
+	if (mode & COMM_DIR_RX) {
+		gumr &= ~UCC_FAST_GUMR_ENR;
+		uccf->enabled_rx = 0;
+	}
+	out_be32(&uf_regs->gumr, gumr);
+}
+
+int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t  **uccf_ret)
+{
+	ucc_fast_private_t	*uccf;
+	ucc_fast_t		*uf_regs;
+
+	if (!uf_info)
+		return -EINVAL;
+
+	if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
+		printf("%s: Illagal UCC number!\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t));
+	if (!uccf) {
+		printf("%s: No memory for UCC fast data structure!\n",
+			 __FUNCTION__);
+		return -ENOMEM;
+	}
+	memset(uccf, 0, sizeof(ucc_fast_private_t));
+
+	/* Save fast UCC structure */
+	uccf->uf_info	= uf_info;
+	uccf->uf_regs	= (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
+
+	if (uccf->uf_regs == NULL) {
+		printf("%s: No memory map for UCC fast controller!\n",
+			 __FUNCTION__);
+		return -ENOMEM;
+	}
+
+	uccf->enabled_tx	= 0;
+	uccf->enabled_rx	= 0;
+
+	uf_regs			= uccf->uf_regs;
+	uccf->p_ucce		= (u32 *) &(uf_regs->ucce);
+	uccf->p_uccm		= (u32 *) &(uf_regs->uccm);
+
+	/* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
+	out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
+				 | UCC_GUEMR_MODE_FAST_TX);
+
+	/* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
+	out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
+
+	/* Set the Giga ethernet VFIFO stuff */
+	if (uf_info->eth_type == GIGA_ETH) {
+		/* Allocate memory for Tx Virtual Fifo */
+		uccf->ucc_fast_tx_virtual_fifo_base_offset =
+		qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
+				 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+
+		/* Allocate memory for Rx Virtual Fifo */
+		uccf->ucc_fast_rx_virtual_fifo_base_offset =
+		qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
+				 UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
+				UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+
+		/* utfb, urfb are offsets from MURAM base */
+		out_be32(&uf_regs->utfb,
+			 uccf->ucc_fast_tx_virtual_fifo_base_offset);
+		out_be32(&uf_regs->urfb,
+			 uccf->ucc_fast_rx_virtual_fifo_base_offset);
+
+		/* Set Virtual Fifo registers */
+		out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
+		out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
+		out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
+		out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
+		out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
+		out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
+	}
+
+	/* Set the Fast ethernet VFIFO stuff */
+	if (uf_info->eth_type == FAST_ETH) {
+		/* Allocate memory for Tx Virtual Fifo */
+		uccf->ucc_fast_tx_virtual_fifo_base_offset =
+		qe_muram_alloc(UCC_GETH_UTFS_INIT,
+				 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+
+		/* Allocate memory for Rx Virtual Fifo */
+		uccf->ucc_fast_rx_virtual_fifo_base_offset =
+		qe_muram_alloc(UCC_GETH_URFS_INIT +
+				 UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
+				UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+
+		/* utfb, urfb are offsets from MURAM base */
+		out_be32(&uf_regs->utfb,
+			 uccf->ucc_fast_tx_virtual_fifo_base_offset);
+		out_be32(&uf_regs->urfb,
+			 uccf->ucc_fast_rx_virtual_fifo_base_offset);
+
+		/* Set Virtual Fifo registers */
+		out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
+		out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
+		out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
+		out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
+		out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
+ 		out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
+	}
+
+	/* Rx clock routing */
+	if (uf_info->rx_clock != QE_CLK_NONE) {
+		if (ucc_set_clk_src(uf_info->ucc_num,
+			 uf_info->rx_clock, COMM_DIR_RX)) {
+			printf("%s: Illegal value for parameter 'RxClock'.\n",
+				 __FUNCTION__);
+			return -EINVAL;
+		}
+	}
+
+	/* Tx clock routing */
+	if (uf_info->tx_clock != QE_CLK_NONE) {
+		if (ucc_set_clk_src(uf_info->ucc_num,
+			 uf_info->tx_clock, COMM_DIR_TX)) {
+			printf("%s: Illegal value for parameter 'TxClock'.\n",
+				 __FUNCTION__);
+			return -EINVAL;
+		}
+	}
+
+	/* Clear interrupt mask register to disable all of interrupts */
+	out_be32(&uf_regs->uccm, 0x0);
+
+	/* Writing '1' to clear all of envents */
+	out_be32(&uf_regs->ucce, 0xffffffff);
+
+	*uccf_ret = uccf;
+	return 0;
+}
+#endif /* CONFIG_QE */
diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h
new file mode 100644
index 0000000..1ff9e1d
--- /dev/null
+++ b/drivers/qe/uccf.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __UCCF_H__
+#define __UCCF_H__
+
+#include "common.h"
+#include "qe.h"
+
+/* Fast or Giga ethernet
+*/
+typedef enum enet_type {
+	FAST_ETH,
+	GIGA_ETH,
+} enet_type_e;
+
+/* General UCC Extended Mode Register
+*/
+#define UCC_GUEMR_MODE_MASK_RX		0x02
+#define UCC_GUEMR_MODE_MASK_TX		0x01
+#define UCC_GUEMR_MODE_FAST_RX		0x02
+#define UCC_GUEMR_MODE_FAST_TX		0x01
+#define UCC_GUEMR_MODE_SLOW_RX		0x00
+#define UCC_GUEMR_MODE_SLOW_TX		0x00
+#define UCC_GUEMR_SET_RESERVED3		0x10 /* Bit 3 must be set 1 */
+
+/* General UCC FAST Mode Register
+*/
+#define UCC_FAST_GUMR_TCI		0x20000000
+#define UCC_FAST_GUMR_TRX		0x10000000
+#define UCC_FAST_GUMR_TTX		0x08000000
+#define UCC_FAST_GUMR_CDP		0x04000000
+#define UCC_FAST_GUMR_CTSP		0x02000000
+#define UCC_FAST_GUMR_CDS		0x01000000
+#define UCC_FAST_GUMR_CTSS		0x00800000
+#define UCC_FAST_GUMR_TXSY		0x00020000
+#define UCC_FAST_GUMR_RSYN		0x00010000
+#define UCC_FAST_GUMR_RTSM		0x00002000
+#define UCC_FAST_GUMR_REVD		0x00000400
+#define UCC_FAST_GUMR_ENR		0x00000020
+#define UCC_FAST_GUMR_ENT		0x00000010
+
+/* GUMR [MODE] bit maps
+*/
+#define UCC_FAST_GUMR_HDLC		0x00000000
+#define UCC_FAST_GUMR_QMC		0x00000002
+#define UCC_FAST_GUMR_UART		0x00000004
+#define UCC_FAST_GUMR_BISYNC		0x00000008
+#define UCC_FAST_GUMR_ATM		0x0000000a
+#define UCC_FAST_GUMR_ETH		0x0000000c
+
+/* Transmit On Demand (UTORD)
+*/
+#define UCC_SLOW_TOD			0x8000
+#define UCC_FAST_TOD			0x8000
+
+/* Fast Ethernet (10/100 Mbps)
+*/
+#define UCC_GETH_URFS_INIT		512        /* Rx virtual FIFO size */
+#define UCC_GETH_URFET_INIT		256        /* 1/2 urfs */
+#define UCC_GETH_URFSET_INIT		384        /* 3/4 urfs */
+#define UCC_GETH_UTFS_INIT		512        /* Tx virtual FIFO size */
+#define UCC_GETH_UTFET_INIT		256        /* 1/2 utfs */
+#define UCC_GETH_UTFTT_INIT		128
+
+/* Gigabit Ethernet (1000 Mbps)
+*/
+#define UCC_GETH_URFS_GIGA_INIT		4096/*2048*/    /* Rx virtual FIFO size */
+#define UCC_GETH_URFET_GIGA_INIT	2048/*1024*/    /* 1/2 urfs */
+#define UCC_GETH_URFSET_GIGA_INIT	3072/*1536*/    /* 3/4 urfs */
+#define UCC_GETH_UTFS_GIGA_INIT		8192/*2048*/    /* Tx virtual FIFO size */
+#define UCC_GETH_UTFET_GIGA_INIT	4096/*1024*/    /* 1/2 utfs */
+#define UCC_GETH_UTFTT_GIGA_INIT	0x400/*0x40*/   /*  */
+
+/* UCC fast alignment
+*/
+#define UCC_FAST_RX_ALIGN			4
+#define UCC_FAST_MRBLR_ALIGNMENT		4
+#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT	8
+
+/* Sizes
+*/
+#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD	8
+
+/* UCC fast structure.
+*/
+typedef struct ucc_fast_info {
+	int		ucc_num;
+	qe_clock_e	rx_clock;
+	qe_clock_e	tx_clock;
+	enet_type_e	eth_type;
+} ucc_fast_info_t;
+
+typedef struct ucc_fast_private {
+	ucc_fast_info_t	*uf_info;
+	ucc_fast_t	*uf_regs; /* a pointer to memory map of UCC regs */
+	u32		*p_ucce; /* a pointer to the event register */
+	u32		*p_uccm; /* a pointer to the mask register */
+	int		enabled_tx; /* whether UCC is enabled for Tx (ENT) */
+	int		enabled_rx; /* whether UCC is enabled for Rx (ENR) */
+	u32		ucc_fast_tx_virtual_fifo_base_offset;
+	u32		ucc_fast_rx_virtual_fifo_base_offset;
+} ucc_fast_private_t;
+
+void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf);
+u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
+void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode);
+void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode);
+int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret);
+
+#endif /* __UCCF_H__ */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
new file mode 100644
index 0000000..c416a67
--- /dev/null
+++ b/drivers/qe/uec.c
@@ -0,0 +1,1271 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "common.h"
+#include "net.h"
+#include "malloc.h"
+#include "asm/errno.h"
+#include "asm/io.h"
+#include "asm/immap_qe.h"
+#include "qe.h"
+#include "uccf.h"
+#include "uec.h"
+#include "uec_phy.h"
+
+#if defined(CONFIG_QE)
+
+#ifdef CONFIG_UEC_ETH1
+static uec_info_t eth1_uec_info = {
+	.uf_info		= {
+		.ucc_num	= CFG_UEC1_UCC_NUM,
+		.rx_clock	= CFG_UEC1_RX_CLK,
+		.tx_clock	= CFG_UEC1_TX_CLK,
+		.eth_type	= CFG_UEC1_ETH_TYPE,
+	},
+	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
+	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.tx_bd_ring_len		= 16,
+	.rx_bd_ring_len		= 16,
+	.phy_address		= CFG_UEC1_PHY_ADDR,
+	.enet_interface		= CFG_UEC1_INTERFACE_MODE,
+};
+#endif
+#ifdef CONFIG_UEC_ETH2
+static uec_info_t eth2_uec_info = {
+	.uf_info		= {
+		.ucc_num	= CFG_UEC2_UCC_NUM,
+		.rx_clock	= CFG_UEC2_RX_CLK,
+		.tx_clock	= CFG_UEC2_TX_CLK,
+		.eth_type	= CFG_UEC2_ETH_TYPE,
+	},
+	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
+	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
+	.riscTx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.riscRx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+	.tx_bd_ring_len		= 16,
+	.rx_bd_ring_len		= 16,
+	.phy_address		= CFG_UEC2_PHY_ADDR,
+	.enet_interface		= CFG_UEC2_INTERFACE_MODE,
+};
+#endif
+
+static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
+{
+	uec_t		*uec_regs;
+	u32		maccfg1;
+
+	if (!uec) {
+		printf("%s: uec not initial\n", __FUNCTION__);
+		return -EINVAL;
+	}
+	uec_regs = uec->uec_regs;
+
+	maccfg1 = in_be32(&uec_regs->maccfg1);
+
+	if (mode & COMM_DIR_TX)	{
+		maccfg1 |= MACCFG1_ENABLE_TX;
+		out_be32(&uec_regs->maccfg1, maccfg1);
+		uec->mac_tx_enabled = 1;
+	}
+
+	if (mode & COMM_DIR_RX)	{
+		maccfg1 |= MACCFG1_ENABLE_RX;
+		out_be32(&uec_regs->maccfg1, maccfg1);
+		uec->mac_rx_enabled = 1;
+	}
+
+	return 0;
+}
+
+static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
+{
+	uec_t		*uec_regs;
+	u32		maccfg1;
+
+	if (!uec) {
+		printf("%s: uec not initial\n", __FUNCTION__);
+		return -EINVAL;
+	}
+	uec_regs = uec->uec_regs;
+
+	maccfg1 = in_be32(&uec_regs->maccfg1);
+
+	if (mode & COMM_DIR_TX)	{
+		maccfg1 &= ~MACCFG1_ENABLE_TX;
+		out_be32(&uec_regs->maccfg1, maccfg1);
+		uec->mac_tx_enabled = 0;
+	}
+
+	if (mode & COMM_DIR_RX)	{
+		maccfg1 &= ~MACCFG1_ENABLE_RX;
+		out_be32(&uec_regs->maccfg1, maccfg1);
+		uec->mac_rx_enabled = 0;
+	}
+
+	return 0;
+}
+
+static int uec_graceful_stop_tx(uec_private_t *uec)
+{
+	ucc_fast_t		*uf_regs;
+	u32			cecr_subblock;
+	u32			ucce;
+
+	if (!uec || !uec->uccf) {
+		printf("%s: No handle passed.\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	uf_regs = uec->uccf->uf_regs;
+
+	/* Clear the grace stop event */
+	out_be32(&uf_regs->ucce, UCCE_GRA);
+
+	/* Issue host command */
+	cecr_subblock =
+		 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
+	qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
+			 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+
+	/* Wait for command to complete */
+	do {
+		ucce = in_be32(&uf_regs->ucce);
+	} while (! (ucce & UCCE_GRA));
+
+	uec->grace_stopped_tx = 1;
+
+	return 0;
+}
+
+static int uec_graceful_stop_rx(uec_private_t *uec)
+{
+	u32		cecr_subblock;
+	u8		ack;
+
+	if (!uec) {
+		printf("%s: No handle passed.\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	if (!uec->p_rx_glbl_pram) {
+		printf("%s: No init rx global parameter\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	/* Clear acknowledge bit */
+	ack = uec->p_rx_glbl_pram->rxgstpack;
+	ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
+	uec->p_rx_glbl_pram->rxgstpack = ack;
+
+	/* Keep issuing cmd and checking ack bit until it is asserted */
+	do {
+		/* Issue host command */
+		cecr_subblock =
+		 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
+		qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
+				 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+		ack = uec->p_rx_glbl_pram->rxgstpack;
+	} while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
+
+	uec->grace_stopped_rx = 1;
+
+	return 0;
+}
+
+static int uec_restart_tx(uec_private_t *uec)
+{
+	u32		cecr_subblock;
+
+	if (!uec || !uec->uec_info) {
+		printf("%s: No handle passed.\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	cecr_subblock =
+	 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
+	qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
+			 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+
+	uec->grace_stopped_tx = 0;
+
+	return 0;
+}
+
+static int uec_restart_rx(uec_private_t *uec)
+{
+	u32		cecr_subblock;
+
+	if (!uec || !uec->uec_info) {
+		printf("%s: No handle passed.\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	cecr_subblock =
+	 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
+	qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
+			 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
+
+	uec->grace_stopped_rx = 0;
+
+	return 0;
+}
+
+static int uec_open(uec_private_t *uec, comm_dir_e mode)
+{
+	ucc_fast_private_t	*uccf;
+
+	if (!uec || !uec->uccf) {
+		printf("%s: No handle passed.\n", __FUNCTION__);
+		return -EINVAL;
+	}
+	uccf = uec->uccf;
+
+	/* check if the UCC number is in range. */
+	if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
+		printf("%s: ucc_num out of range.\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	/* Enable MAC */
+	uec_mac_enable(uec, mode);
+
+	/* Enable UCC fast */
+	ucc_fast_enable(uccf, mode);
+
+	/* RISC microcode start */
+	if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
+		uec_restart_tx(uec);
+	}
+	if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
+		uec_restart_rx(uec);
+	}
+
+	return 0;
+}
+
+static int uec_stop(uec_private_t *uec, comm_dir_e mode)
+{
+	ucc_fast_private_t	*uccf;
+
+	if (!uec || !uec->uccf) {
+		printf("%s: No handle passed.\n", __FUNCTION__);
+		return -EINVAL;
+	}
+	uccf = uec->uccf;
+
+	/* check if the UCC number is in range. */
+	if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
+		printf("%s: ucc_num out of range.\n", __FUNCTION__);
+		return -EINVAL;
+	}
+	/* Stop any transmissions */
+	if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
+		uec_graceful_stop_tx(uec);
+	}
+	/* Stop any receptions */
+	if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
+		uec_graceful_stop_rx(uec);
+	}
+
+	/* Disable the UCC fast */
+	ucc_fast_disable(uec->uccf, mode);
+
+	/* Disable the MAC */
+	uec_mac_disable(uec, mode);
+
+	return 0;
+}
+
+static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
+{
+	uec_t		*uec_regs;
+	u32		maccfg2;
+
+	if (!uec) {
+		printf("%s: uec not initial\n", __FUNCTION__);
+		return -EINVAL;
+	}
+	uec_regs = uec->uec_regs;
+
+	if (duplex == DUPLEX_HALF) {
+		maccfg2 = in_be32(&uec_regs->maccfg2);
+		maccfg2 &= ~MACCFG2_FDX;
+		out_be32(&uec_regs->maccfg2, maccfg2);
+	}
+
+	if (duplex == DUPLEX_FULL) {
+		maccfg2 = in_be32(&uec_regs->maccfg2);
+		maccfg2 |= MACCFG2_FDX;
+		out_be32(&uec_regs->maccfg2, maccfg2);
+	}
+
+	return 0;
+}
+
+static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
+{
+	enet_interface_e	enet_if_mode;
+	uec_info_t 		*uec_info;
+	uec_t			*uec_regs;
+	u32			upsmr;
+	u32			maccfg2;
+
+	if (!uec) {
+		printf("%s: uec not initial\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	uec_info = uec->uec_info;
+	uec_regs = uec->uec_regs;
+	enet_if_mode = if_mode;
+
+	maccfg2 = in_be32(&uec_regs->maccfg2);
+	maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
+
+	upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
+	upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
+
+	switch (enet_if_mode) {
+		case ENET_100_MII:
+		case ENET_10_MII:
+			maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+			break;
+		case ENET_1000_GMII:
+			maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+			break;
+		case ENET_1000_TBI:
+			maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+			upsmr |= UPSMR_TBIM;
+			break;
+		case ENET_1000_RTBI:
+			maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+			upsmr |= (UPSMR_RPM | UPSMR_TBIM);
+			break;
+		case ENET_1000_RGMII:
+			maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+			upsmr |= UPSMR_RPM;
+			break;
+		case ENET_100_RGMII:
+			maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+			upsmr |= UPSMR_RPM;
+			break;
+		case ENET_10_RGMII:
+			maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+			upsmr |= (UPSMR_RPM | UPSMR_R10M);
+			break;
+		case ENET_100_RMII:
+			maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+			upsmr |= UPSMR_RMM;
+			break;
+		case ENET_10_RMII:
+			maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
+			upsmr |= (UPSMR_R10M | UPSMR_RMM);
+			break;
+		default:
+			return -EINVAL;
+			break;
+	}
+	out_be32(&uec_regs->maccfg2, maccfg2);
+	out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
+
+	return 0;
+}
+
+static int init_mii_management_configuration(uec_t *uec_regs)
+{
+	uint		timeout = 0x1000;
+	u32		miimcfg = 0;
+
+	miimcfg = in_be32(&uec_regs->miimcfg);
+	miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
+	out_be32(&uec_regs->miimcfg, miimcfg);
+
+	/* Wait until the bus is free */
+	while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
+	if (timeout <= 0) {
+		printf("%s: The MII Bus is stuck!", __FUNCTION__);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int init_phy(struct eth_device *dev)
+{
+	uec_private_t		*uec;
+	uec_t			*uec_regs;
+	struct uec_mii_info	*mii_info;
+	struct phy_info		*curphy;
+	int			err;
+
+	uec = (uec_private_t *)dev->priv;
+	uec_regs = uec->uec_regs;
+
+	uec->oldlink = 0;
+	uec->oldspeed = 0;
+	uec->oldduplex = -1;
+
+	mii_info = malloc(sizeof(*mii_info));
+	if (!mii_info) {
+		printf("%s: Could not allocate mii_info", dev->name);
+		return -ENOMEM;
+	}
+	memset(mii_info, 0, sizeof(*mii_info));
+
+	if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
+		mii_info->speed = SPEED_1000;
+	} else {
+		mii_info->speed = SPEED_100;
+	}
+
+	mii_info->duplex = DUPLEX_FULL;
+	mii_info->pause = 0;
+	mii_info->link = 1;
+
+	mii_info->advertising = (ADVERTISED_10baseT_Half |
+				ADVERTISED_10baseT_Full |
+				ADVERTISED_100baseT_Half |
+				ADVERTISED_100baseT_Full |
+				ADVERTISED_1000baseT_Full);
+	mii_info->autoneg = 1;
+	mii_info->mii_id = uec->uec_info->phy_address;
+	mii_info->dev = dev;
+
+	mii_info->mdio_read = &read_phy_reg;
+	mii_info->mdio_write = &write_phy_reg;
+
+	uec->mii_info = mii_info;
+
+	if (init_mii_management_configuration(uec_regs)) {
+		printf("%s: The MII Bus is stuck!", dev->name);
+		err = -1;
+		goto bus_fail;
+	}
+
+	/* get info for this PHY */
+	curphy = get_phy_info(uec->mii_info);
+	if (!curphy) {
+		printf("%s: No PHY found", dev->name);
+		err = -1;
+		goto no_phy;
+	}
+
+	mii_info->phyinfo = curphy;
+
+	/* Run the commands which initialize the PHY */
+	if (curphy->init) {
+		err = curphy->init(uec->mii_info);
+		if (err)
+			goto phy_init_fail;
+	}
+
+	return 0;
+
+phy_init_fail:
+no_phy:
+bus_fail:
+	free(mii_info);
+	return err;
+}
+
+static void adjust_link(struct eth_device *dev)
+{
+	uec_private_t		*uec = (uec_private_t *)dev->priv;
+	uec_t			*uec_regs;
+	struct uec_mii_info	*mii_info = uec->mii_info;
+
+	extern void change_phy_interface_mode(struct eth_device *dev,
+					 enet_interface_e mode);
+	uec_regs = uec->uec_regs;
+
+	if (mii_info->link) {
+		/* Now we make sure that we can be in full duplex mode.
+		* If not, we operate in half-duplex mode. */
+		if (mii_info->duplex != uec->oldduplex) {
+			if (!(mii_info->duplex)) {
+				uec_set_mac_duplex(uec, DUPLEX_HALF);
+				printf("%s: Half Duplex\n", dev->name);
+			} else {
+				uec_set_mac_duplex(uec, DUPLEX_FULL);
+				printf("%s: Full Duplex\n", dev->name);
+			}
+			uec->oldduplex = mii_info->duplex;
+		}
+
+		if (mii_info->speed != uec->oldspeed) {
+			if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
+				switch (mii_info->speed) {
+				case 1000:
+					break;
+				case 100:
+					printf ("switching to rgmii 100\n");
+					/* change phy to rgmii 100 */
+					change_phy_interface_mode(dev,
+								ENET_100_RGMII);
+					/* change the MAC interface mode */
+					uec_set_mac_if_mode(uec,ENET_100_RGMII);
+					break;
+				case 10:
+					printf ("switching to rgmii 10\n");
+					/* change phy to rgmii 10 */
+					change_phy_interface_mode(dev,
+								ENET_10_RGMII);
+					/* change the MAC interface mode */
+					uec_set_mac_if_mode(uec,ENET_10_RGMII);
+					break;
+				default:
+					printf("%s: Ack,Speed(%d)is illegal\n",
+						dev->name, mii_info->speed);
+					break;
+				}
+			}
+
+			printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
+			uec->oldspeed = mii_info->speed;
+		}
+
+		if (!uec->oldlink) {
+			printf("%s: Link is up\n", dev->name);
+			uec->oldlink = 1;
+		}
+
+	} else { /* if (mii_info->link) */
+		if (uec->oldlink) {
+			printf("%s: Link is down\n", dev->name);
+			uec->oldlink = 0;
+			uec->oldspeed = 0;
+			uec->oldduplex = -1;
+		}
+	}
+}
+
+static void phy_change(struct eth_device *dev)
+{
+	uec_private_t	*uec = (uec_private_t *)dev->priv;
+	uec_t		*uec_regs;
+	int		result = 0;
+
+	uec_regs = uec->uec_regs;
+
+	/* Delay 5s to give the PHY a chance to change the register state */
+	udelay(5000000);
+
+	/* Update the link, speed, duplex */
+	result = uec->mii_info->phyinfo->read_status(uec->mii_info);
+
+	/* Adjust the interface according to speed */
+	if ((0 == result) || (uec->mii_info->link == 0)) {
+		adjust_link(dev);
+	}
+}
+
+static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
+{
+	uec_t		*uec_regs;
+	u32		mac_addr1;
+	u32		mac_addr2;
+
+	if (!uec) {
+		printf("%s: uec not initial\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	uec_regs = uec->uec_regs;
+
+	/* if a station address of 0x12345678ABCD, perform a write to
+	MACSTNADDR1 of 0xCDAB7856,
+	MACSTNADDR2 of 0x34120000 */
+
+	mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
+			(mac_addr[3] << 8)  | (mac_addr[2]);
+	out_be32(&uec_regs->macstnaddr1, mac_addr1);
+
+	mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
+	out_be32(&uec_regs->macstnaddr2, mac_addr2);
+
+	return 0;
+}
+
+static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
+					 int *threads_num_ret)
+{
+	int	num_threads_numerica;
+
+	switch (threads_num) {
+		case UEC_NUM_OF_THREADS_1:
+			num_threads_numerica = 1;
+			break;
+		case UEC_NUM_OF_THREADS_2:
+			num_threads_numerica = 2;
+			break;
+		case UEC_NUM_OF_THREADS_4:
+			num_threads_numerica = 4;
+			break;
+		case UEC_NUM_OF_THREADS_6:
+			num_threads_numerica = 6;
+			break;
+		case UEC_NUM_OF_THREADS_8:
+			num_threads_numerica = 8;
+			break;
+		default:
+			printf("%s: Bad number of threads value.",
+				 __FUNCTION__);
+			return -EINVAL;
+	}
+
+	*threads_num_ret = num_threads_numerica;
+
+	return 0;
+}
+
+static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
+{
+	uec_info_t	*uec_info;
+	u32		end_bd;
+	u8		bmrx = 0;
+	int		i;
+
+	uec_info = uec->uec_info;
+
+	/* Alloc global Tx parameter RAM page */
+	uec->tx_glbl_pram_offset = qe_muram_alloc(
+				sizeof(uec_tx_global_pram_t),
+				 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
+	uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
+				qe_muram_addr(uec->tx_glbl_pram_offset);
+
+	/* Zero the global Tx prameter RAM */
+	memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
+
+	/* Init global Tx parameter RAM */
+
+	/* TEMODER, RMON statistics disable, one Tx queue */
+	out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
+
+	/* SQPTR */
+	uec->send_q_mem_reg_offset = qe_muram_alloc(
+				sizeof(uec_send_queue_qd_t),
+				 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
+	uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
+				qe_muram_addr(uec->send_q_mem_reg_offset);
+	out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
+
+	/* Setup the table with TxBDs ring */
+	end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
+					 * SIZEOFBD;
+	out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
+				 (u32)(uec->p_tx_bd_ring));
+	out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
+						 end_bd);
+
+	/* Scheduler Base Pointer, we have only one Tx queue, no need it */
+	out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
+
+	/* TxRMON Base Pointer, TxRMON disable, we don't need it */
+	out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
+
+	/* TSTATE, global snooping, big endian, the CSB bus selected */
+	bmrx = BMR_INIT_VALUE;
+	out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
+
+	/* IPH_Offset */
+	for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
+		out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
+	}
+
+	/* VTAG table */
+	for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
+		out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
+	}
+
+	/* TQPTR */
+	uec->thread_dat_tx_offset = qe_muram_alloc(
+		num_threads_tx * sizeof(uec_thread_data_tx_t) +
+		 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
+
+	uec->p_thread_data_tx = (uec_thread_data_tx_t *)
+				qe_muram_addr(uec->thread_dat_tx_offset);
+	out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
+}
+
+static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
+{
+	u8	bmrx = 0;
+	int	i;
+	uec_82xx_address_filtering_pram_t	*p_af_pram;
+
+	/* Allocate global Rx parameter RAM page */
+	uec->rx_glbl_pram_offset = qe_muram_alloc(
+		sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
+	uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
+				qe_muram_addr(uec->rx_glbl_pram_offset);
+
+	/* Zero Global Rx parameter RAM */
+	memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
+
+	/* Init global Rx parameter RAM */
+	/* REMODER, Extended feature mode disable, VLAN disable,
+	 LossLess flow control disable, Receive firmware statisic disable,
+	 Extended address parsing mode disable, One Rx queues,
+	 Dynamic maximum/minimum frame length disable, IP checksum check
+	 disable, IP address alignment disable
+	*/
+	out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
+
+	/* RQPTR */
+	uec->thread_dat_rx_offset = qe_muram_alloc(
+			num_threads_rx * sizeof(uec_thread_data_rx_t),
+			 UEC_THREAD_DATA_ALIGNMENT);
+	uec->p_thread_data_rx = (uec_thread_data_rx_t *)
+				qe_muram_addr(uec->thread_dat_rx_offset);
+	out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
+
+	/* Type_or_Len */
+	out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
+
+	/* RxRMON base pointer, we don't need it */
+	out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
+
+	/* IntCoalescingPTR, we don't need it, no interrupt */
+	out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
+
+	/* RSTATE, global snooping, big endian, the CSB bus selected */
+	bmrx = BMR_INIT_VALUE;
+	out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
+
+	/* MRBLR */
+	out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
+
+	/* RBDQPTR */
+	uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
+				sizeof(uec_rx_bd_queues_entry_t) + \
+				sizeof(uec_rx_prefetched_bds_t),
+				 UEC_RX_BD_QUEUES_ALIGNMENT);
+	uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
+				qe_muram_addr(uec->rx_bd_qs_tbl_offset);
+
+	/* Zero it */
+	memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
+					sizeof(uec_rx_prefetched_bds_t));
+	out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
+	out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
+		 (u32)uec->p_rx_bd_ring);
+
+	/* MFLR */
+	out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
+	/* MINFLR */
+	out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
+	/* MAXD1 */
+	out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
+	/* MAXD2 */
+	out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
+	/* ECAM_PTR */
+	out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
+	/* L2QT */
+	out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
+	/* L3QT */
+	for (i = 0; i < 8; i++)	{
+		out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
+	}
+
+	/* VLAN_TYPE */
+	out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
+	/* TCI */
+	out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
+
+	/* Clear PQ2 style address filtering hash table */
+	p_af_pram = (uec_82xx_address_filtering_pram_t *) \
+			uec->p_rx_glbl_pram->addressfiltering;
+
+	p_af_pram->iaddr_h = 0;
+	p_af_pram->iaddr_l = 0;
+	p_af_pram->gaddr_h = 0;
+	p_af_pram->gaddr_l = 0;
+}
+
+static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
+					 int thread_tx, int thread_rx)
+{
+	uec_init_cmd_pram_t		*p_init_enet_param;
+	u32				init_enet_param_offset;
+	uec_info_t			*uec_info;
+	int				i;
+	int				snum;
+	u32				init_enet_offset;
+	u32				entry_val;
+	u32				command;
+	u32				cecr_subblock;
+
+	uec_info = uec->uec_info;
+
+	/* Allocate init enet command parameter */
+	uec->init_enet_param_offset = qe_muram_alloc(
+					sizeof(uec_init_cmd_pram_t), 4);
+	init_enet_param_offset = uec->init_enet_param_offset;
+	uec->p_init_enet_param = (uec_init_cmd_pram_t *)
+				qe_muram_addr(uec->init_enet_param_offset);
+
+	/* Zero init enet command struct */
+	memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
+
+	/* Init the command struct */
+	p_init_enet_param = uec->p_init_enet_param;
+	p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
+	p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
+	p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
+	p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
+	p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
+	p_init_enet_param->largestexternallookupkeysize = 0;
+
+	p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
+					 << ENET_INIT_PARAM_RGF_SHIFT;
+	p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
+					 << ENET_INIT_PARAM_TGF_SHIFT;
+
+	/* Init Rx global parameter pointer */
+	p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
+						 (u32)uec_info->riscRx;
+
+	/* Init Rx threads */
+	for (i = 0; i < (thread_rx + 1); i++) {
+		if ((snum = qe_get_snum()) < 0) {
+			printf("%s can not get snum\n", __FUNCTION__);
+			return -ENOMEM;
+		}
+
+		if (i==0) {
+			init_enet_offset = 0;
+		} else {
+			init_enet_offset = qe_muram_alloc(
+					sizeof(uec_thread_rx_pram_t),
+					 UEC_THREAD_RX_PRAM_ALIGNMENT);
+		}
+
+		entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
+				 init_enet_offset | (u32)uec_info->riscRx;
+		p_init_enet_param->rxthread[i] = entry_val;
+	}
+
+	/* Init Tx global parameter pointer */
+	p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
+					 (u32)uec_info->riscTx;
+
+	/* Init Tx threads */
+	for (i = 0; i < thread_tx; i++) {
+		if ((snum = qe_get_snum()) < 0)	{
+			printf("%s can not get snum\n", __FUNCTION__);
+			return -ENOMEM;
+		}
+
+		init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
+						 UEC_THREAD_TX_PRAM_ALIGNMENT);
+
+		entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
+				 init_enet_offset | (u32)uec_info->riscTx;
+		p_init_enet_param->txthread[i] = entry_val;
+	}
+
+	__asm__ __volatile__("sync");
+
+	/* Issue QE command */
+	command = QE_INIT_TX_RX;
+	cecr_subblock =	ucc_fast_get_qe_cr_subblock(
+				uec->uec_info->uf_info.ucc_num);
+	qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
+						 init_enet_param_offset);
+
+	return 0;
+}
+
+static int uec_startup(uec_private_t *uec)
+{
+	uec_info_t			*uec_info;
+	ucc_fast_info_t			*uf_info;
+	ucc_fast_private_t		*uccf;
+	ucc_fast_t			*uf_regs;
+	uec_t				*uec_regs;
+	int				num_threads_tx;
+	int				num_threads_rx;
+	u32				utbipar;
+	enet_interface_e		enet_interface;
+	u32				length;
+	u32				align;
+	qe_bd_t				*bd;
+	u8				*buf;
+	int				i;
+
+	if (!uec || !uec->uec_info) {
+		printf("%s: uec or uec_info not initial\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	uec_info = uec->uec_info;
+	uf_info = &(uec_info->uf_info);
+
+	/* Check if Rx BD ring len is illegal */
+	if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
+		(uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
+		printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
+			 __FUNCTION__);
+		return -EINVAL;
+	}
+
+	/* Check if Tx BD ring len is illegal */
+	if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
+		printf("%s: Tx BD ring length must not be smaller than 2.\n",
+			 __FUNCTION__);
+		return -EINVAL;
+	}
+
+	/* Check if MRBLR is illegal */
+	if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN  % UEC_MRBLR_ALIGNMENT)) {
+		printf("%s: max rx buffer length must be mutliple of 128.\n",
+			 __FUNCTION__);
+		return -EINVAL;
+	}
+
+	/* Both Rx and Tx are stopped */
+	uec->grace_stopped_rx = 1;
+	uec->grace_stopped_tx = 1;
+
+	/* Init UCC fast */
+	if (ucc_fast_init(uf_info, &uccf)) {
+		printf("%s: failed to init ucc fast\n", __FUNCTION__);
+		return -ENOMEM;
+	}
+
+	/* Save uccf */
+	uec->uccf = uccf;
+
+	/* Convert the Tx threads number */
+	if (uec_convert_threads_num(uec_info->num_threads_tx,
+					 &num_threads_tx)) {
+		return -EINVAL;
+	}
+
+	/* Convert the Rx threads number */
+	if (uec_convert_threads_num(uec_info->num_threads_rx,
+					 &num_threads_rx)) {
+		return -EINVAL;
+	}
+
+	uf_regs = uccf->uf_regs;
+
+	/* UEC register is following UCC fast registers */
+	uec_regs = (uec_t *)(&uf_regs->ucc_eth);
+
+	/* Save the UEC register pointer to UEC private struct */
+	uec->uec_regs = uec_regs;
+
+	/* Init UPSMR, enable hardware statistics (UCC) */
+	out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
+
+	/* Init MACCFG1, flow control disable, disable Tx and Rx */
+	out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
+
+	/* Init MACCFG2, length check, MAC PAD and CRC enable */
+	out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
+
+	/* Setup MAC interface mode */
+	uec_set_mac_if_mode(uec, uec_info->enet_interface);
+
+	/* Setup MII master clock source */
+	qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
+
+	/* Setup UTBIPAR */
+	utbipar = in_be32(&uec_regs->utbipar);
+	utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
+	enet_interface = uec->uec_info->enet_interface;
+	if (enet_interface == ENET_1000_TBI ||
+		 enet_interface == ENET_1000_RTBI) {
+		utbipar |=  (uec_info->phy_address + uec_info->uf_info.ucc_num)
+						 << UTBIPAR_PHY_ADDRESS_SHIFT;
+	} else {
+		utbipar |=  (0x10 + uec_info->uf_info.ucc_num)
+						 << UTBIPAR_PHY_ADDRESS_SHIFT;
+	}
+
+	out_be32(&uec_regs->utbipar, utbipar);
+
+	/* Allocate Tx BDs */
+	length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
+		 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
+		 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
+	if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
+		 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
+		length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
+	}
+
+	align = UEC_TX_BD_RING_ALIGNMENT;
+	uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
+	if (uec->tx_bd_ring_offset != 0) {
+		uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
+						 & ~(align - 1));
+	}
+
+	/* Zero all of Tx BDs */
+	memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
+
+	/* Allocate Rx BDs */
+	length = uec_info->rx_bd_ring_len * SIZEOFBD;
+	align = UEC_RX_BD_RING_ALIGNMENT;
+	uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
+	if (uec->rx_bd_ring_offset != 0) {
+		uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
+							 & ~(align - 1));
+	}
+
+	/* Zero all of Rx BDs */
+	memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
+
+	/* Allocate Rx buffer */
+	length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
+	align = UEC_RX_DATA_BUF_ALIGNMENT;
+	uec->rx_buf_offset = (u32)malloc(length + align);
+	if (uec->rx_buf_offset != 0) {
+		uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
+						 & ~(align - 1));
+	}
+
+	/* Zero all of the Rx buffer */
+	memset((void *)(uec->rx_buf_offset), 0, length + align);
+
+	/* Init TxBD ring */
+	bd = (qe_bd_t *)uec->p_tx_bd_ring;
+	uec->txBd = bd;
+
+	for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
+		BD_DATA_CLEAR(bd);
+		BD_STATUS_SET(bd, 0);
+		BD_LENGTH_SET(bd, 0);
+		bd ++;
+	}
+	BD_STATUS_SET((--bd), TxBD_WRAP);
+
+	/* Init RxBD ring */
+	bd = (qe_bd_t *)uec->p_rx_bd_ring;
+	uec->rxBd = bd;
+	buf = uec->p_rx_buf;
+	for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
+		BD_DATA_SET(bd, buf);
+		BD_LENGTH_SET(bd, 0);
+		BD_STATUS_SET(bd, RxBD_EMPTY);
+		buf += MAX_RXBUF_LEN;
+		bd ++;
+	}
+	BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
+
+	/* Init global Tx parameter RAM */
+	uec_init_tx_parameter(uec, num_threads_tx);
+
+	/* Init global Rx parameter RAM */
+	uec_init_rx_parameter(uec, num_threads_rx);
+
+	/* Init ethernet Tx and Rx parameter command */
+	if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
+					 num_threads_rx)) {
+		printf("%s issue init enet cmd failed\n", __FUNCTION__);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int uec_init(struct eth_device* dev, bd_t *bd)
+{
+	uec_private_t		*uec;
+	int			err;
+
+	uec = (uec_private_t *)dev->priv;
+
+	if (uec->the_first_run == 0) {
+		/* Set up the MAC address */
+		if (dev->enetaddr[0] & 0x01) {
+			printf("%s: MacAddress is multcast address\n",
+				 __FUNCTION__);
+			return -EINVAL;
+		}
+		uec_set_mac_address(uec, dev->enetaddr);
+		uec->the_first_run = 1;
+	}
+
+	err = uec_open(uec, COMM_DIR_RX_AND_TX);
+	if (err) {
+		printf("%s: cannot enable UEC device\n", dev->name);
+		return err;
+	}
+
+	return 0;
+}
+
+static void uec_halt(struct eth_device* dev)
+{
+	uec_private_t	*uec = (uec_private_t *)dev->priv;
+	uec_stop(uec, COMM_DIR_RX_AND_TX);
+}
+
+static int uec_send(struct eth_device* dev, volatile void *buf, int len)
+{
+	uec_private_t		*uec;
+	ucc_fast_private_t	*uccf;
+	volatile qe_bd_t	*bd;
+	u16			status;
+	int			i;
+	int			result = 0;
+
+	uec = (uec_private_t *)dev->priv;
+	uccf = uec->uccf;
+	bd = uec->txBd;
+
+	/* Find an empty TxBD */
+	for (i = 0; bd->status & TxBD_READY; i++) {
+		if (i > 0x100000) {
+			printf("%s: tx buffer not ready\n", dev->name);
+			return result;
+		}
+	}
+
+	/* Init TxBD */
+	BD_DATA_SET(bd, buf);
+	BD_LENGTH_SET(bd, len);
+	status = bd->status;
+	status &= BD_WRAP;
+	status |= (TxBD_READY | TxBD_LAST);
+	BD_STATUS_SET(bd, status);
+
+	/* Tell UCC to transmit the buffer */
+	ucc_fast_transmit_on_demand(uccf);
+
+	/* Wait for buffer to be transmitted */
+	for (i = 0; bd->status & TxBD_READY; i++) {
+		if (i > 0x100000) {
+			printf("%s: tx error\n", dev->name);
+			return result;
+		}
+	}
+
+	/* Ok, the buffer be transimitted */
+	BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
+	uec->txBd = bd;
+	result = 1;
+
+	return result;
+}
+
+static int uec_recv(struct eth_device* dev)
+{
+	uec_private_t		*uec = dev->priv;
+	volatile qe_bd_t	*bd;
+	u16			status;
+	u16			len;
+	u8			*data;
+
+	bd = uec->rxBd;
+	status = bd->status;
+
+	while (!(status & RxBD_EMPTY)) {
+		if (!(status & RxBD_ERROR)) {
+			data = BD_DATA(bd);
+			len = BD_LENGTH(bd);
+			NetReceive(data, len);
+		} else {
+			printf("%s: Rx error\n", dev->name);
+		}
+		status &= BD_CLEAN;
+		BD_LENGTH_SET(bd, 0);
+		BD_STATUS_SET(bd, status | RxBD_EMPTY);
+		BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
+		status = bd->status;
+	}
+	uec->rxBd = bd;
+
+	return 1;
+}
+
+int uec_initialize(int index)
+{
+	struct eth_device	*dev;
+	int			i;
+	uec_private_t		*uec;
+	uec_info_t		*uec_info;
+	int			err;
+
+	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
+	if (!dev)
+		return 0;
+	memset(dev, 0, sizeof(struct eth_device));
+
+	/* Allocate the UEC private struct */
+	uec = (uec_private_t *)malloc(sizeof(uec_private_t));
+	if (!uec) {
+		return -ENOMEM;
+	}
+	memset(uec, 0, sizeof(uec_private_t));
+
+	/* Init UEC private struct, they come from board.h */
+	if (index == 0) {
+#ifdef CONFIG_UEC_ETH1
+		uec_info = &eth1_uec_info;
+#endif
+	} else if (index == 1) {
+#ifdef CONFIG_UEC_ETH2
+		uec_info = &eth2_uec_info;
+#endif
+	} else {
+		printf("%s: index is illegal.\n", __FUNCTION__);
+		return -EINVAL;
+	}
+
+	uec->uec_info = uec_info;
+
+	sprintf(dev->name, "FSL UEC%d", index);
+	dev->iobase = 0;
+	dev->priv = (void *)uec;
+	dev->init = uec_init;
+	dev->halt = uec_halt;
+	dev->send = uec_send;
+	dev->recv = uec_recv;
+
+	/* Clear the ethnet address */
+	for (i = 0; i < 6; i++)
+		dev->enetaddr[i] = 0;
+
+	eth_register(dev);
+
+	err = uec_startup(uec);
+	if (err) {
+		printf("%s: Cannot configure net device, aborting.",dev->name);
+		return err;
+	}
+
+	err = init_phy(dev);
+	if (err) {
+		printf("%s: Cannot initialize PHY, aborting.\n", dev->name);
+		return err;
+	}
+
+	phy_change(dev);
+
+	return 1;
+}
+#endif /* CONFIG_QE */
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
new file mode 100644
index 0000000..0495026
--- /dev/null
+++ b/drivers/qe/uec.h
@@ -0,0 +1,716 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __UEC_H__
+#define __UEC_H__
+
+#define MAX_TX_THREADS				8
+#define MAX_RX_THREADS				8
+#define MAX_TX_QUEUES				8
+#define MAX_RX_QUEUES				8
+#define MAX_PREFETCHED_BDS			4
+#define MAX_IPH_OFFSET_ENTRY			8
+#define MAX_ENET_INIT_PARAM_ENTRIES_RX		9
+#define MAX_ENET_INIT_PARAM_ENTRIES_TX		8
+
+/* UEC UPSMR (Protocol Specific Mode Register)
+ */
+#define UPSMR_ECM	0x04000000 /* Enable CAM Miss               */
+#define UPSMR_HSE	0x02000000 /* Hardware Statistics Enable    */
+#define UPSMR_PRO	0x00400000 /* Promiscuous                   */
+#define UPSMR_CAP	0x00200000 /* CAM polarity                  */
+#define UPSMR_RSH	0x00100000 /* Receive Short Frames          */
+#define UPSMR_RPM	0x00080000 /* Reduced Pin Mode interfaces   */
+#define UPSMR_R10M	0x00040000 /* RGMII/RMII 10 Mode            */
+#define UPSMR_RLPB	0x00020000 /* RMII Loopback Mode            */
+#define UPSMR_TBIM	0x00010000 /* Ten-bit Interface Mode        */
+#define UPSMR_RMM	0x00001000 /* RMII/RGMII Mode               */
+#define UPSMR_CAM	0x00000400 /* CAM Address Matching          */
+#define UPSMR_BRO	0x00000200 /* Broadcast Address             */
+#define UPSMR_RES1	0x00002000 /* Reserved feild - must be 1    */
+
+#define UPSMR_INIT_VALUE	(UPSMR_HSE | UPSMR_RES1)
+
+/* UEC MACCFG1 (MAC Configuration 1 Register)
+ */
+#define MACCFG1_FLOW_RX			0x00000020 /* Flow Control Rx */
+#define MACCFG1_FLOW_TX			0x00000010 /* Flow Control Tx */
+#define MACCFG1_ENABLE_SYNCHED_RX	0x00000008 /* Enable Rx Sync  */
+#define MACCFG1_ENABLE_RX		0x00000004 /* Enable Rx       */
+#define MACCFG1_ENABLE_SYNCHED_TX	0x00000002 /* Enable Tx Sync  */
+#define MACCFG1_ENABLE_TX		0x00000001 /* Enable Tx       */
+
+#define MACCFG1_INIT_VALUE		(0)
+
+/* UEC MACCFG2 (MAC Configuration 2 Register)
+ */
+#define MACCFG2_PREL				0x00007000
+#define MACCFG2_PREL_SHIFT			(31 - 19)
+#define MACCFG2_PREL_MASK			0x0000f000
+#define MACCFG2_SRP				0x00000080
+#define MACCFG2_STP				0x00000040
+#define MACCFG2_RESERVED_1			0x00000020 /* must be set  */
+#define MACCFG2_LC				0x00000010 /* Length Check */
+#define MACCFG2_MPE				0x00000008
+#define MACCFG2_FDX				0x00000001 /* Full Duplex  */
+#define MACCFG2_FDX_MASK			0x00000001
+#define MACCFG2_PAD_CRC				0x00000004
+#define MACCFG2_CRC_EN				0x00000002
+#define MACCFG2_PAD_AND_CRC_MODE_NONE		0x00000000
+#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY	0x00000002
+#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC	0x00000004
+#define MACCFG2_INTERFACE_MODE_NIBBLE		0x00000100
+#define MACCFG2_INTERFACE_MODE_BYTE		0x00000200
+#define MACCFG2_INTERFACE_MODE_MASK		0x00000300
+
+#define MACCFG2_INIT_VALUE	(MACCFG2_PREL | MACCFG2_RESERVED_1 | \
+				 MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
+
+/* UEC Event Register
+*/
+#define UCCE_MPD				0x80000000
+#define UCCE_SCAR				0x40000000
+#define UCCE_GRA				0x20000000
+#define UCCE_CBPR				0x10000000
+#define UCCE_BSY				0x08000000
+#define UCCE_RXC				0x04000000
+#define UCCE_TXC				0x02000000
+#define UCCE_TXE				0x01000000
+#define UCCE_TXB7				0x00800000
+#define UCCE_TXB6				0x00400000
+#define UCCE_TXB5				0x00200000
+#define UCCE_TXB4				0x00100000
+#define UCCE_TXB3				0x00080000
+#define UCCE_TXB2				0x00040000
+#define UCCE_TXB1				0x00020000
+#define UCCE_TXB0				0x00010000
+#define UCCE_RXB7				0x00008000
+#define UCCE_RXB6				0x00004000
+#define UCCE_RXB5				0x00002000
+#define UCCE_RXB4				0x00001000
+#define UCCE_RXB3				0x00000800
+#define UCCE_RXB2				0x00000400
+#define UCCE_RXB1				0x00000200
+#define UCCE_RXB0				0x00000100
+#define UCCE_RXF7				0x00000080
+#define UCCE_RXF6				0x00000040
+#define UCCE_RXF5				0x00000020
+#define UCCE_RXF4				0x00000010
+#define UCCE_RXF3				0x00000008
+#define UCCE_RXF2				0x00000004
+#define UCCE_RXF1				0x00000002
+#define UCCE_RXF0				0x00000001
+
+#define UCCE_TXB	(UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
+			 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
+#define UCCE_RXB	(UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
+			 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
+#define UCCE_RXF	(UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
+			 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
+#define UCCE_OTHER	(UCCE_SCAR | UCCE_GRA  | UCCE_CBPR | UCCE_BSY  | \
+			 UCCE_RXC  | UCCE_TXC  | UCCE_TXE)
+
+/* UEC TEMODR Register
+*/
+#define TEMODER_SCHEDULER_ENABLE		0x2000
+#define TEMODER_IP_CHECKSUM_GENERATE		0x0400
+#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1	0x0200
+#define TEMODER_RMON_STATISTICS			0x0100
+#define TEMODER_NUM_OF_QUEUES_SHIFT		(15-15)
+
+#define TEMODER_INIT_VALUE			0xc000
+
+/* UEC REMODR Register
+*/
+#define REMODER_RX_RMON_STATISTICS_ENABLE	0x00001000
+#define REMODER_RX_EXTENDED_FEATURES		0x80000000
+#define REMODER_VLAN_OPERATION_TAGGED_SHIFT	(31-9 )
+#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT	(31-10)
+#define REMODER_RX_QOS_MODE_SHIFT		(31-15)
+#define REMODER_RMON_STATISTICS			0x00001000
+#define REMODER_RX_EXTENDED_FILTERING		0x00000800
+#define REMODER_NUM_OF_QUEUES_SHIFT		(31-23)
+#define REMODER_DYNAMIC_MAX_FRAME_LENGTH	0x00000008
+#define REMODER_DYNAMIC_MIN_FRAME_LENGTH	0x00000004
+#define REMODER_IP_CHECKSUM_CHECK		0x00000002
+#define REMODER_IP_ADDRESS_ALIGNMENT		0x00000001
+
+#define REMODER_INIT_VALUE			0
+
+/* BMRx - Bus Mode Register */
+#define BMR_GLB					0x20
+#define BMR_BO_BE				0x10
+#define BMR_DTB_SECONDARY_BUS			0x02
+#define BMR_BDB_SECONDARY_BUS			0x01
+
+#define BMR_SHIFT				24
+#define BMR_INIT_VALUE				(BMR_GLB | BMR_BO_BE)
+
+/* UEC UCCS (Ethernet Status Register)
+ */
+#define UCCS_BPR				0x02
+#define UCCS_PAU				0x02
+#define UCCS_MPD				0x01
+
+/* UEC MIIMCFG (MII Management Configuration Register)
+ */
+#define MIIMCFG_RESET_MANAGEMENT		0x80000000
+#define MIIMCFG_NO_PREAMBLE			0x00000010
+#define MIIMCFG_CLOCK_DIVIDE_SHIFT		(31 - 31)
+#define MIIMCFG_CLOCK_DIVIDE_MASK		0x0000000f
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4	0x00000001
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6	0x00000002
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8	0x00000003
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10	0x00000004
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14	0x00000005
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20	0x00000006
+#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28	0x00000007
+
+#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE	\
+	MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
+
+/* UEC MIIMCOM (MII Management Command Register)
+ */
+#define MIIMCOM_SCAN_CYCLE			0x00000002 /* Scan cycle */
+#define MIIMCOM_READ_CYCLE			0x00000001 /* Read cycle */
+
+/* UEC MIIMADD (MII Management Address Register)
+ */
+#define MIIMADD_PHY_ADDRESS_SHIFT		(31 - 23)
+#define MIIMADD_PHY_REGISTER_SHIFT		(31 - 31)
+
+/* UEC MIIMCON (MII Management Control Register)
+ */
+#define MIIMCON_PHY_CONTROL_SHIFT		(31 - 31)
+#define MIIMCON_PHY_STATUS_SHIFT		(31 - 31)
+
+/* UEC MIIMIND (MII Management Indicator Register)
+ */
+#define MIIMIND_NOT_VALID			0x00000004
+#define MIIMIND_SCAN				0x00000002
+#define MIIMIND_BUSY				0x00000001
+
+/* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
+ */
+#define UTBIPAR_PHY_ADDRESS_SHIFT		(31 - 31)
+#define UTBIPAR_PHY_ADDRESS_MASK		0x0000001f
+
+/* UEC UESCR (Ethernet Statistics Control Register)
+ */
+#define UESCR_AUTOZ				0x8000
+#define UESCR_CLRCNT				0x4000
+#define UESCR_MAXCOV_SHIFT			(15 -  7)
+#define UESCR_SCOV_SHIFT			(15 - 15)
+
+/****** Tx data struct collection ******/
+/* Tx thread data, each Tx thread has one this struct.
+*/
+typedef struct uec_thread_data_tx {
+	u8   res0[136];
+} __attribute__ ((packed)) uec_thread_data_tx_t;
+
+/* Tx thread parameter, each Tx thread has one this struct.
+*/
+typedef struct uec_thread_tx_pram {
+	u8   res0[64];
+} __attribute__ ((packed)) uec_thread_tx_pram_t;
+
+/* Send queue queue-descriptor, each Tx queue has one this QD
+*/
+typedef struct uec_send_queue_qd {
+	u32    bd_ring_base; /* pointer to BD ring base address */
+	u8     res0[0x8];
+	u32    last_bd_completed_address; /* last entry in BD ring */
+	u8     res1[0x30];
+} __attribute__ ((packed)) uec_send_queue_qd_t;
+
+/* Send queue memory region */
+typedef struct uec_send_queue_mem_region {
+	uec_send_queue_qd_t   sqqd[MAX_TX_QUEUES];
+} __attribute__ ((packed)) uec_send_queue_mem_region_t;
+
+/* Scheduler struct
+*/
+typedef struct uec_scheduler {
+	u16  cpucount0;        /* CPU packet counter */
+	u16  cpucount1;        /* CPU packet counter */
+	u16  cecount0;         /* QE  packet counter */
+	u16  cecount1;         /* QE  packet counter */
+	u16  cpucount2;        /* CPU packet counter */
+	u16  cpucount3;        /* CPU packet counter */
+	u16  cecount2;         /* QE  packet counter */
+	u16  cecount3;         /* QE  packet counter */
+	u16  cpucount4;        /* CPU packet counter */
+	u16  cpucount5;        /* CPU packet counter */
+	u16  cecount4;         /* QE  packet counter */
+	u16  cecount5;         /* QE  packet counter */
+	u16  cpucount6;        /* CPU packet counter */
+	u16  cpucount7;        /* CPU packet counter */
+	u16  cecount6;         /* QE  packet counter */
+	u16  cecount7;         /* QE  packet counter */
+	u32  weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
+	u32  rtsrshadow;       /* temporary variable handled by QE */
+	u32  time;             /* temporary variable handled by QE */
+	u32  ttl;              /* temporary variable handled by QE */
+	u32  mblinterval;      /* max burst length interval        */
+	u16  nortsrbytetime;   /* normalized value of byte time in tsr units */
+	u8   fracsiz;
+	u8   res0[1];
+	u8   strictpriorityq;  /* Strict Priority Mask register */
+	u8   txasap;           /* Transmit ASAP register        */
+	u8   extrabw;          /* Extra BandWidth register      */
+	u8   oldwfqmask;       /* temporary variable handled by QE */
+	u8   weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
+	u32  minw;             /* temporary variable handled by QE */
+	u8   res1[0x70-0x64];
+} __attribute__ ((packed)) uec_scheduler_t;
+
+/* Tx firmware counters
+*/
+typedef struct uec_tx_firmware_statistics_pram {
+	u32  sicoltx;            /* single collision */
+	u32  mulcoltx;           /* multiple collision */
+	u32  latecoltxfr;        /* late collision */
+	u32  frabortduecol;      /* frames aborted due to tx collision */
+	u32  frlostinmactxer;    /* frames lost due to internal MAC error tx */
+	u32  carriersenseertx;   /* carrier sense error */
+	u32  frtxok;             /* frames transmitted OK */
+	u32  txfrexcessivedefer;
+	u32  txpkts256;          /* total packets(including bad) 256~511 B */
+	u32  txpkts512;          /* total packets(including bad) 512~1023B */
+	u32  txpkts1024;         /* total packets(including bad) 1024~1518B */
+	u32  txpktsjumbo;        /* total packets(including bad)  >1024 */
+} __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
+
+/* Tx global parameter table
+*/
+typedef struct uec_tx_global_pram {
+	u16  temoder;
+	u8   res0[0x38-0x02];
+	u32  sqptr;
+	u32  schedulerbasepointer;
+	u32  txrmonbaseptr;
+	u32  tstate;
+	u8   iphoffset[MAX_IPH_OFFSET_ENTRY];
+	u32  vtagtable[0x8];
+	u32  tqptr;
+	u8   res2[0x80-0x74];
+} __attribute__ ((packed)) uec_tx_global_pram_t;
+
+
+/****** Rx data struct collection ******/
+/* Rx thread data, each Rx thread has one this struct.
+*/
+typedef struct uec_thread_data_rx {
+	u8   res0[40];
+} __attribute__ ((packed)) uec_thread_data_rx_t;
+
+/* Rx thread parameter, each Rx thread has one this struct.
+*/
+typedef struct uec_thread_rx_pram {
+	u8   res0[128];
+} __attribute__ ((packed)) uec_thread_rx_pram_t;
+
+/* Rx firmware counters
+*/
+typedef struct uec_rx_firmware_statistics_pram {
+	u32   frrxfcser;         /* frames with crc error */
+	u32   fraligner;         /* frames with alignment error */
+	u32   inrangelenrxer;    /* in range length error */
+	u32   outrangelenrxer;   /* out of range length error */
+	u32   frtoolong;         /* frame too long */
+	u32   runt;              /* runt */
+	u32   verylongevent;     /* very long event */
+	u32   symbolerror;       /* symbol error */
+	u32   dropbsy;           /* drop because of BD not ready */
+	u8    res0[0x8];
+	u32   mismatchdrop;      /* drop because of MAC filtering */
+	u32   underpkts;         /* total frames less than 64 octets */
+	u32   pkts256;           /* total frames(including bad)256~511 B */
+	u32   pkts512;           /* total frames(including bad)512~1023 B */
+	u32   pkts1024;          /* total frames(including bad)1024~1518 B */
+	u32   pktsjumbo;         /* total frames(including bad) >1024 B */
+	u32   frlossinmacer;
+	u32   pausefr;           /* pause frames */
+	u8    res1[0x4];
+	u32   removevlan;
+	u32   replacevlan;
+	u32   insertvlan;
+} __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
+
+/* Rx interrupt coalescing entry, each Rx queue has one this entry.
+*/
+typedef struct uec_rx_interrupt_coalescing_entry {
+	u32   maxvalue;
+	u32   counter;
+} __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
+
+typedef struct uec_rx_interrupt_coalescing_table {
+	uec_rx_interrupt_coalescing_entry_t   entry[MAX_RX_QUEUES];
+} __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
+
+/* RxBD queue entry, each Rx queue has one this entry.
+*/
+typedef struct uec_rx_bd_queues_entry {
+	u32   bdbaseptr;         /* BD base pointer          */
+	u32   bdptr;             /* BD pointer               */
+	u32   externalbdbaseptr; /* external BD base pointer */
+	u32   externalbdptr;     /* external BD pointer      */
+} __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
+
+/* Rx global paramter table
+*/
+typedef struct uec_rx_global_pram {
+	u32  remoder;             /* ethernet mode reg. */
+	u32  rqptr;               /* base pointer to the Rx Queues */
+	u32  res0[0x1];
+	u8   res1[0x20-0xC];
+	u16  typeorlen;
+	u8   res2[0x1];
+	u8   rxgstpack;           /* ack on GRACEFUL STOP RX command */
+	u32  rxrmonbaseptr;       /* Rx RMON statistics base */
+	u8   res3[0x30-0x28];
+	u32  intcoalescingptr;    /* Interrupt coalescing table pointer */
+	u8   res4[0x36-0x34];
+	u8   rstate;
+	u8   res5[0x46-0x37];
+	u16  mrblr;               /* max receive buffer length reg. */
+	u32  rbdqptr;             /* RxBD parameter table description */
+	u16  mflr;                /* max frame length reg. */
+	u16  minflr;              /* min frame length reg. */
+	u16  maxd1;               /* max dma1 length reg. */
+	u16  maxd2;               /* max dma2 length reg. */
+	u32  ecamptr;             /* external CAM address */
+	u32  l2qt;                /* VLAN priority mapping table. */
+	u32  l3qt[0x8];           /* IP   priority mapping table. */
+	u16  vlantype;            /* vlan type */
+	u16  vlantci;             /* default vlan tci */
+	u8   addressfiltering[64];/* address filtering data structure */
+	u32  exfGlobalParam;      /* extended filtering global parameters */
+	u8   res6[0x100-0xC4];    /* Initialize to zero */
+} __attribute__ ((packed)) uec_rx_global_pram_t;
+
+#define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
+
+
+/****** UEC common ******/
+/* UCC statistics - hardware counters
+*/
+typedef struct uec_hardware_statistics {
+	u32 tx64;
+	u32 tx127;
+	u32 tx255;
+	u32 rx64;
+	u32 rx127;
+	u32 rx255;
+	u32 txok;
+	u16 txcf;
+	u32 tmca;
+	u32 tbca;
+	u32 rxfok;
+	u32 rxbok;
+	u32 rbyt;
+	u32 rmca;
+	u32 rbca;
+} __attribute__ ((packed)) uec_hardware_statistics_t;
+
+/* InitEnet command parameter
+*/
+typedef struct uec_init_cmd_pram {
+	u8   resinit0;
+	u8   resinit1;
+	u8   resinit2;
+	u8   resinit3;
+	u16  resinit4;
+	u8   res1[0x1];
+	u8   largestexternallookupkeysize;
+	u32  rgftgfrxglobal;
+	u32  rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
+	u8   res2[0x38 - 0x30];
+	u32  txglobal;				   /* tx global  */
+	u32  txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
+	u8   res3[0x1];
+} __attribute__ ((packed)) uec_init_cmd_pram_t;
+
+#define ENET_INIT_PARAM_RGF_SHIFT		(32 - 4)
+#define ENET_INIT_PARAM_TGF_SHIFT		(32 - 8)
+
+#define ENET_INIT_PARAM_RISC_MASK		0x0000003f
+#define ENET_INIT_PARAM_PTR_MASK		0x00ffffc0
+#define ENET_INIT_PARAM_SNUM_MASK		0xff000000
+#define ENET_INIT_PARAM_SNUM_SHIFT		24
+
+#define ENET_INIT_PARAM_MAGIC_RES_INIT0		0x06
+#define ENET_INIT_PARAM_MAGIC_RES_INIT1		0x30
+#define ENET_INIT_PARAM_MAGIC_RES_INIT2		0xff
+#define ENET_INIT_PARAM_MAGIC_RES_INIT3		0x00
+#define ENET_INIT_PARAM_MAGIC_RES_INIT4		0x0400
+
+/* structure representing 82xx Address Filtering Enet Address in PRAM
+*/
+typedef struct uec_82xx_enet_address {
+	u8   res1[0x2];
+	u16  h;       /* address (MSB) */
+	u16  m;       /* address       */
+	u16  l;       /* address (LSB) */
+} __attribute__ ((packed)) uec_82xx_enet_address_t;
+
+/* structure representing 82xx Address Filtering PRAM
+*/
+typedef struct uec_82xx_address_filtering_pram {
+	u32  iaddr_h;        /* individual address filter, high */
+	u32  iaddr_l;        /* individual address filter, low  */
+	u32  gaddr_h;        /* group address filter, high      */
+	u32  gaddr_l;        /* group address filter, low       */
+	uec_82xx_enet_address_t    taddr;
+	uec_82xx_enet_address_t    paddr[4];
+	u8                         res0[0x40-0x38];
+} __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
+
+/* Buffer Descriptor
+*/
+typedef struct buffer_descriptor {
+	u16 status;
+	u16 len;
+	u32 data;
+} __attribute__ ((packed)) qe_bd_t, *p_bd_t;
+
+#define	SIZEOFBD		sizeof(qe_bd_t)
+
+/* Common BD flags
+*/
+#define BD_WRAP			0x2000
+#define BD_INT			0x1000
+#define BD_LAST			0x0800
+#define BD_CLEAN		0x3000
+
+/* TxBD status flags
+*/
+#define TxBD_READY		0x8000
+#define TxBD_PADCRC		0x4000
+#define TxBD_WRAP		BD_WRAP
+#define TxBD_INT		BD_INT
+#define TxBD_LAST		BD_LAST
+#define TxBD_TXCRC		0x0400
+#define TxBD_DEF		0x0200
+#define TxBD_PP			0x0100
+#define TxBD_LC			0x0080
+#define TxBD_RL			0x0040
+#define TxBD_RC			0x003C
+#define TxBD_UNDERRUN		0x0002
+#define TxBD_TRUNC		0x0001
+
+#define TxBD_ERROR		(TxBD_UNDERRUN | TxBD_TRUNC)
+
+/* RxBD status flags
+*/
+#define RxBD_EMPTY		0x8000
+#define RxBD_OWNER		0x4000
+#define RxBD_WRAP		BD_WRAP
+#define RxBD_INT		BD_INT
+#define RxBD_LAST		BD_LAST
+#define RxBD_FIRST		0x0400
+#define RxBD_CMR		0x0200
+#define RxBD_MISS		0x0100
+#define RxBD_BCAST		0x0080
+#define RxBD_MCAST		0x0040
+#define RxBD_LG			0x0020
+#define RxBD_NO			0x0010
+#define RxBD_SHORT		0x0008
+#define RxBD_CRCERR		0x0004
+#define RxBD_OVERRUN		0x0002
+#define RxBD_IPCH		0x0001
+
+#define RxBD_ERROR		(RxBD_LG | RxBD_NO | RxBD_SHORT | \
+				 RxBD_CRCERR | RxBD_OVERRUN)
+
+/* BD access macros
+*/
+#define BD_STATUS(_bd)			(((p_bd_t)(_bd))->status)
+#define BD_STATUS_SET(_bd, _val)	(((p_bd_t)(_bd))->status = _val)
+#define BD_LENGTH(_bd)			(((p_bd_t)(_bd))->len)
+#define BD_LENGTH_SET(_bd, _val)	(((p_bd_t)(_bd))->len = _val)
+#define BD_DATA_CLEAR(_bd)		(((p_bd_t)(_bd))->data = 0)
+#define BD_IS_DATA(_bd)			(((p_bd_t)(_bd))->data)
+#define BD_DATA(_bd)			((u8 *)(((p_bd_t)(_bd))->data))
+#define BD_DATA_SET(_bd, _data)		(((p_bd_t)(_bd))->data = (u32)(_data))
+#define BD_ADVANCE(_bd,_status,_base)	\
+	(((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
+
+/* Rx Prefetched BDs
+*/
+typedef struct uec_rx_prefetched_bds {
+    qe_bd_t   bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
+} __attribute__ ((packed)) uec_rx_prefetched_bds_t;
+
+/* Alignments
+ */
+#define UEC_RX_GLOBAL_PRAM_ALIGNMENT				64
+#define UEC_TX_GLOBAL_PRAM_ALIGNMENT				64
+#define UEC_THREAD_RX_PRAM_ALIGNMENT				128
+#define UEC_THREAD_TX_PRAM_ALIGNMENT				64
+#define UEC_THREAD_DATA_ALIGNMENT				256
+#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT		32
+#define UEC_SCHEDULER_ALIGNMENT					4
+#define UEC_TX_STATISTICS_ALIGNMENT				4
+#define UEC_RX_STATISTICS_ALIGNMENT				4
+#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT			4
+#define UEC_RX_BD_QUEUES_ALIGNMENT				8
+#define UEC_RX_PREFETCHED_BDS_ALIGNMENT				128
+#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT	4
+#define UEC_RX_BD_RING_ALIGNMENT				32
+#define UEC_TX_BD_RING_ALIGNMENT				32
+#define UEC_MRBLR_ALIGNMENT					128
+#define UEC_RX_BD_RING_SIZE_ALIGNMENT				4
+#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT			32
+#define UEC_RX_DATA_BUF_ALIGNMENT				64
+
+#define UEC_VLAN_PRIORITY_MAX					8
+#define UEC_IP_PRIORITY_MAX					64
+#define UEC_TX_VTAG_TABLE_ENTRY_MAX				8
+#define UEC_RX_BD_RING_SIZE_MIN					8
+#define UEC_TX_BD_RING_SIZE_MIN					2
+
+/* Ethernet speed
+*/
+typedef enum enet_speed {
+	ENET_SPEED_10BT,   /* 10 Base T */
+	ENET_SPEED_100BT,  /* 100 Base T */
+	ENET_SPEED_1000BT  /* 1000 Base T */
+} enet_speed_e;
+
+/* Ethernet Address Type.
+*/
+typedef enum enet_addr_type {
+	ENET_ADDR_TYPE_INDIVIDUAL,
+	ENET_ADDR_TYPE_GROUP,
+	ENET_ADDR_TYPE_BROADCAST
+} enet_addr_type_e;
+
+/* TBI / MII Set Register
+*/
+typedef enum enet_tbi_mii_reg {
+	ENET_TBI_MII_CR        = 0x00,
+	ENET_TBI_MII_SR        = 0x01,
+	ENET_TBI_MII_ANA       = 0x04,
+	ENET_TBI_MII_ANLPBPA   = 0x05,
+	ENET_TBI_MII_ANEX      = 0x06,
+	ENET_TBI_MII_ANNPT     = 0x07,
+	ENET_TBI_MII_ANLPANP   = 0x08,
+	ENET_TBI_MII_EXST      = 0x0F,
+	ENET_TBI_MII_JD        = 0x10,
+	ENET_TBI_MII_TBICON    = 0x11
+} enet_tbi_mii_reg_e;
+
+/* UEC number of threads
+*/
+typedef enum uec_num_of_threads {
+	UEC_NUM_OF_THREADS_1  = 0x1,  /* 1 */
+	UEC_NUM_OF_THREADS_2  = 0x2,  /* 2 */
+	UEC_NUM_OF_THREADS_4  = 0x0,  /* 4 */
+	UEC_NUM_OF_THREADS_6  = 0x3,  /* 6 */
+	UEC_NUM_OF_THREADS_8  = 0x4   /* 8 */
+} uec_num_of_threads_e;
+
+/* UEC ethernet interface type
+*/
+typedef enum enet_interface {
+	ENET_10_MII,
+	ENET_10_RMII,
+	ENET_10_RGMII,
+	ENET_100_MII,
+	ENET_100_RMII,
+	ENET_100_RGMII,
+	ENET_1000_GMII,
+	ENET_1000_RGMII,
+	ENET_1000_TBI,
+	ENET_1000_RTBI
+} enet_interface_e;
+
+/* UEC initialization info struct
+*/
+typedef struct uec_info {
+	ucc_fast_info_t			uf_info;
+	uec_num_of_threads_e		num_threads_tx;
+	uec_num_of_threads_e		num_threads_rx;
+	qe_risc_allocation_e		riscTx;
+	qe_risc_allocation_e		riscRx;
+	u16				rx_bd_ring_len;
+	u16				tx_bd_ring_len;
+	u8				phy_address;
+	enet_interface_e		enet_interface;
+} uec_info_t;
+
+/* UEC driver initialized info
+*/
+#define MAX_RXBUF_LEN			1536
+#define MAX_FRAME_LEN			1518
+#define MIN_FRAME_LEN			64
+#define MAX_DMA1_LEN			1520
+#define MAX_DMA2_LEN			1520
+
+/* UEC driver private struct
+*/
+typedef struct uec_private {
+	uec_info_t			*uec_info;
+	ucc_fast_private_t		*uccf;
+	struct eth_device		*dev;
+	uec_t				*uec_regs;
+	/* enet init command parameter */
+	uec_init_cmd_pram_t		*p_init_enet_param;
+	u32				init_enet_param_offset;
+	/* Rx and Tx paramter */
+	uec_rx_global_pram_t		*p_rx_glbl_pram;
+	u32				rx_glbl_pram_offset;
+	uec_tx_global_pram_t		*p_tx_glbl_pram;
+	u32				tx_glbl_pram_offset;
+	uec_send_queue_mem_region_t	*p_send_q_mem_reg;
+	u32				send_q_mem_reg_offset;
+	uec_thread_data_tx_t		*p_thread_data_tx;
+	u32				thread_dat_tx_offset;
+	uec_thread_data_rx_t		*p_thread_data_rx;
+	u32				thread_dat_rx_offset;
+	uec_rx_bd_queues_entry_t	*p_rx_bd_qs_tbl;
+	u32				rx_bd_qs_tbl_offset;
+	/* BDs specific */
+	u8				*p_tx_bd_ring;
+	u32				tx_bd_ring_offset;
+	u8				*p_rx_bd_ring;
+	u32				rx_bd_ring_offset;
+	u8				*p_rx_buf;
+	u32				rx_buf_offset;
+	volatile qe_bd_t		*txBd;
+	volatile qe_bd_t		*rxBd;
+	/* Status */
+	int				mac_tx_enabled;
+	int				mac_rx_enabled;
+	int				grace_stopped_tx;
+	int				grace_stopped_rx;
+	int				the_first_run;
+	/* PHY specific */
+	struct uec_mii_info 		*mii_info;
+	int				oldspeed;
+	int				oldduplex;
+	int				oldlink;
+} uec_private_t;
+
+#endif /* __UEC_H__ */
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
new file mode 100644
index 0000000..76fd388
--- /dev/null
+++ b/drivers/qe/uec_phy.c
@@ -0,0 +1,607 @@
+/*
+ * Copyright (C) 2005 Freescale Semiconductor, Inc.
+ *
+ * Author: Shlomi Gridish
+ *
+ * Description: UCC GETH Driver -- PHY handling
+ *		Driver for UEC on QE
+ *		Based on 8260_io/fcc_enet.c
+ *
+ * This program is free software; you can redistribute	it and/or modify it
+ * under  the terms of	the GNU General	 Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include "common.h"
+#include "net.h"
+#include "malloc.h"
+#include "asm/errno.h"
+#include "asm/immap_qe.h"
+#include "asm/io.h"
+#include "qe.h"
+#include "uccf.h"
+#include "uec.h"
+#include "uec_phy.h"
+#include "miiphy.h"
+
+#if defined(CONFIG_QE)
+
+#define UEC_VERBOSE_DEBUG
+#define ugphy_printk(format, arg...)  \
+	printf(format "\n", ## arg)
+
+#define ugphy_dbg(format, arg...)	     \
+	ugphy_printk(format , ## arg)
+#define ugphy_err(format, arg...)	     \
+	ugphy_printk(format , ## arg)
+#define ugphy_info(format, arg...)	     \
+	ugphy_printk(format , ## arg)
+#define ugphy_warn(format, arg...)	     \
+	ugphy_printk(format , ## arg)
+
+#ifdef UEC_VERBOSE_DEBUG
+#define ugphy_vdbg ugphy_dbg
+#else
+#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
+#endif /* UEC_VERBOSE_DEBUG */
+
+static void config_genmii_advert (struct uec_mii_info *mii_info);
+static void genmii_setup_forced (struct uec_mii_info *mii_info);
+static void genmii_restart_aneg (struct uec_mii_info *mii_info);
+static int gbit_config_aneg (struct uec_mii_info *mii_info);
+static int genmii_config_aneg (struct uec_mii_info *mii_info);
+static int genmii_update_link (struct uec_mii_info *mii_info);
+static int genmii_read_status (struct uec_mii_info *mii_info);
+u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
+void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
+
+/* Write value to the PHY for this device to the register at regnum, */
+/* waiting until the write is done before it returns.  All PHY */
+/* configuration has to be done through the TSEC1 MIIM regs */
+void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
+{
+	uec_private_t *ugeth = (uec_private_t *) dev->priv;
+	uec_t *ug_regs;
+	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
+	u32 tmp_reg;
+
+	ug_regs = ugeth->uec_regs;
+
+	/* Stop the MII management read cycle */
+	out_be32 (&ug_regs->miimcom, 0);
+	/* Setting up the MII Mangement Address Register */
+	tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
+	out_be32 (&ug_regs->miimadd, tmp_reg);
+
+	/* Setting up the MII Mangement Control Register with the value */
+	out_be32 (&ug_regs->miimcon, (u32) value);
+
+	/* Wait till MII management write is complete */
+	while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
+
+	udelay (100000);
+}
+
+/* Reads from register regnum in the PHY for device dev, */
+/* returning the value.  Clears miimcom first.  All PHY */
+/* configuration has to be done through the TSEC1 MIIM regs */
+int read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
+{
+	uec_private_t *ugeth = (uec_private_t *) dev->priv;
+	uec_t *ug_regs;
+	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
+	u32 tmp_reg;
+	u16 value;
+
+	ug_regs = ugeth->uec_regs;
+
+	/* Setting up the MII Mangement Address Register */
+	tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
+	out_be32 (&ug_regs->miimadd, tmp_reg);
+
+	/* Perform an MII management read cycle */
+	out_be32 (&ug_regs->miimcom, 0);
+	out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
+
+	/* Wait till MII management write is complete */
+	while ((in_be32 (&ug_regs->miimind)) &
+	       (MIIMIND_NOT_VALID | MIIMIND_BUSY));
+
+	udelay (100000);
+
+	/* Read MII management status  */
+	value = (u16) in_be32 (&ug_regs->miimstat);
+	if (value == 0xffff)
+		ugphy_warn
+			("read wrong value : mii_id %d,mii_reg %d, base %08x",
+			 mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
+
+	return (value);
+}
+
+void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
+{
+	if (mii_info->phyinfo->ack_interrupt)
+		mii_info->phyinfo->ack_interrupt (mii_info);
+}
+
+void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
+				  u32 interrupts)
+{
+	mii_info->interrupts = interrupts;
+	if (mii_info->phyinfo->config_intr)
+		mii_info->phyinfo->config_intr (mii_info);
+}
+
+/* Writes MII_ADVERTISE with the appropriate values, after
+ * sanitizing advertise to make sure only supported features
+ * are advertised
+ */
+static void config_genmii_advert (struct uec_mii_info *mii_info)
+{
+	u32 advertise;
+	u16 adv;
+
+	/* Only allow advertising what this PHY supports */
+	mii_info->advertising &= mii_info->phyinfo->features;
+	advertise = mii_info->advertising;
+
+	/* Setup standard advertisement */
+	adv = phy_read (mii_info, PHY_ANAR);
+	adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
+	if (advertise & ADVERTISED_10baseT_Half)
+		adv |= ADVERTISE_10HALF;
+	if (advertise & ADVERTISED_10baseT_Full)
+		adv |= ADVERTISE_10FULL;
+	if (advertise & ADVERTISED_100baseT_Half)
+		adv |= ADVERTISE_100HALF;
+	if (advertise & ADVERTISED_100baseT_Full)
+		adv |= ADVERTISE_100FULL;
+	phy_write (mii_info, PHY_ANAR, adv);
+}
+
+static void genmii_setup_forced (struct uec_mii_info *mii_info)
+{
+	u16 ctrl;
+	u32 features = mii_info->phyinfo->features;
+
+	ctrl = phy_read (mii_info, PHY_BMCR);
+
+	ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
+		  PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
+	ctrl |= PHY_BMCR_RESET;
+
+	switch (mii_info->speed) {
+	case SPEED_1000:
+		if (features & (SUPPORTED_1000baseT_Half
+				| SUPPORTED_1000baseT_Full)) {
+			ctrl |= PHY_BMCR_1000_MBPS;
+			break;
+		}
+		mii_info->speed = SPEED_100;
+	case SPEED_100:
+		if (features & (SUPPORTED_100baseT_Half
+				| SUPPORTED_100baseT_Full)) {
+			ctrl |= PHY_BMCR_100_MBPS;
+			break;
+		}
+		mii_info->speed = SPEED_10;
+	case SPEED_10:
+		if (features & (SUPPORTED_10baseT_Half
+				| SUPPORTED_10baseT_Full))
+			break;
+	default:		/* Unsupported speed! */
+		ugphy_err ("%s: Bad speed!", mii_info->dev->name);
+		break;
+	}
+
+	phy_write (mii_info, PHY_BMCR, ctrl);
+}
+
+/* Enable and Restart Autonegotiation */
+static void genmii_restart_aneg (struct uec_mii_info *mii_info)
+{
+	u16 ctl;
+
+	ctl = phy_read (mii_info, PHY_BMCR);
+	ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+	phy_write (mii_info, PHY_BMCR, ctl);
+}
+
+static int gbit_config_aneg (struct uec_mii_info *mii_info)
+{
+	u16 adv;
+	u32 advertise;
+
+	if (mii_info->autoneg) {
+		/* Configure the ADVERTISE register */
+		config_genmii_advert (mii_info);
+		advertise = mii_info->advertising;
+
+		adv = phy_read (mii_info, MII_1000BASETCONTROL);
+		adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
+			 MII_1000BASETCONTROL_HALFDUPLEXCAP);
+		if (advertise & SUPPORTED_1000baseT_Half)
+			adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
+		if (advertise & SUPPORTED_1000baseT_Full)
+			adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
+		phy_write (mii_info, MII_1000BASETCONTROL, adv);
+
+		/* Start/Restart aneg */
+		genmii_restart_aneg (mii_info);
+	} else
+		genmii_setup_forced (mii_info);
+
+	return 0;
+}
+
+static int marvell_config_aneg (struct uec_mii_info *mii_info)
+{
+	/* The Marvell PHY has an errata which requires
+	 * that certain registers get written in order
+	 * to restart autonegotiation */
+	phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
+
+	phy_write (mii_info, 0x1d, 0x1f);
+	phy_write (mii_info, 0x1e, 0x200c);
+	phy_write (mii_info, 0x1d, 0x5);
+	phy_write (mii_info, 0x1e, 0);
+	phy_write (mii_info, 0x1e, 0x100);
+
+	gbit_config_aneg (mii_info);
+
+	return 0;
+}
+
+static int genmii_config_aneg (struct uec_mii_info *mii_info)
+{
+	if (mii_info->autoneg) {
+		config_genmii_advert (mii_info);
+		genmii_restart_aneg (mii_info);
+	} else
+		genmii_setup_forced (mii_info);
+
+	return 0;
+}
+
+static int genmii_update_link (struct uec_mii_info *mii_info)
+{
+	u16 status;
+
+	/* Do a fake read */
+	phy_read (mii_info, PHY_BMSR);
+
+	/* Read link and autonegotiation status */
+	status = phy_read (mii_info, PHY_BMSR);
+	if ((status & PHY_BMSR_LS) == 0)
+		mii_info->link = 0;
+	else
+		mii_info->link = 1;
+
+	/* If we are autonegotiating, and not done,
+	 * return an error */
+	if (mii_info->autoneg && !(status & PHY_BMSR_AUTN_COMP))
+		return -EAGAIN;
+
+	return 0;
+}
+
+static int genmii_read_status (struct uec_mii_info *mii_info)
+{
+	u16 status;
+	int err;
+
+	/* Update the link, but return if there
+	 * was an error */
+	err = genmii_update_link (mii_info);
+	if (err)
+		return err;
+
+	if (mii_info->autoneg) {
+		status = phy_read (mii_info, PHY_ANLPAR);
+
+		if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
+			mii_info->duplex = DUPLEX_FULL;
+		else
+			mii_info->duplex = DUPLEX_HALF;
+		if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
+			mii_info->speed = SPEED_100;
+		else
+			mii_info->speed = SPEED_10;
+		mii_info->pause = 0;
+	}
+	/* On non-aneg, we assume what we put in BMCR is the speed,
+	 * though magic-aneg shouldn't prevent this case from occurring
+	 */
+
+	return 0;
+}
+
+static int marvell_read_status (struct uec_mii_info *mii_info)
+{
+	u16 status;
+	int err;
+
+	/* Update the link, but return if there
+	 * was an error */
+	err = genmii_update_link (mii_info);
+	if (err)
+		return err;
+
+	/* If the link is up, read the speed and duplex */
+	/* If we aren't autonegotiating, assume speeds
+	 * are as set */
+	if (mii_info->autoneg && mii_info->link) {
+		int speed;
+
+		status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
+
+		/* Get the duplexity */
+		if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
+			mii_info->duplex = DUPLEX_FULL;
+		else
+			mii_info->duplex = DUPLEX_HALF;
+
+		/* Get the speed */
+		speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
+		switch (speed) {
+		case MII_M1011_PHY_SPEC_STATUS_1000:
+			mii_info->speed = SPEED_1000;
+			break;
+		case MII_M1011_PHY_SPEC_STATUS_100:
+			mii_info->speed = SPEED_100;
+			break;
+		default:
+			mii_info->speed = SPEED_10;
+			break;
+		}
+		mii_info->pause = 0;
+	}
+
+	return 0;
+}
+
+static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
+{
+	/* Clear the interrupts by reading the reg */
+	phy_read (mii_info, MII_M1011_IEVENT);
+
+	return 0;
+}
+
+static int marvell_config_intr (struct uec_mii_info *mii_info)
+{
+	if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
+		phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
+	else
+		phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
+
+	return 0;
+}
+
+static int dm9161_init (struct uec_mii_info *mii_info)
+{
+	/* Reset the PHY */
+	phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
+		   PHY_BMCR_RESET);
+	/* PHY and MAC connect */
+	phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
+		   ~PHY_BMCR_ISO);
+#ifdef CONFIG_RMII_MODE
+	phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT);
+#else
+	phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
+#endif
+	config_genmii_advert (mii_info);
+	/* Start/restart aneg */
+	genmii_config_aneg (mii_info);
+	/* Delay to wait the aneg compeleted */
+	udelay (3000000);
+
+	return 0;
+}
+
+static int dm9161_config_aneg (struct uec_mii_info *mii_info)
+{
+	return 0;
+}
+
+static int dm9161_read_status (struct uec_mii_info *mii_info)
+{
+	u16 status;
+	int err;
+
+	/* Update the link, but return if there was an error */
+	err = genmii_update_link (mii_info);
+	if (err)
+		return err;
+	/* If the link is up, read the speed and duplex
+	   If we aren't autonegotiating assume speeds are as set */
+	if (mii_info->autoneg && mii_info->link) {
+		status = phy_read (mii_info, MII_DM9161_SCSR);
+		if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
+			mii_info->speed = SPEED_100;
+		else
+			mii_info->speed = SPEED_10;
+
+		if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
+			mii_info->duplex = DUPLEX_FULL;
+		else
+			mii_info->duplex = DUPLEX_HALF;
+	}
+
+	return 0;
+}
+
+static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
+{
+	/* Clear the interrupt by reading the reg */
+	phy_read (mii_info, MII_DM9161_INTR);
+
+	return 0;
+}
+
+static int dm9161_config_intr (struct uec_mii_info *mii_info)
+{
+	if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
+		phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
+	else
+		phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
+
+	return 0;
+}
+
+static void dm9161_close (struct uec_mii_info *mii_info)
+{
+}
+
+static struct phy_info phy_info_dm9161 = {
+	.phy_id = 0x0181b880,
+	.phy_id_mask = 0x0ffffff0,
+	.name = "Davicom DM9161E",
+	.init = dm9161_init,
+	.config_aneg = dm9161_config_aneg,
+	.read_status = dm9161_read_status,
+	.close = dm9161_close,
+};
+
+static struct phy_info phy_info_dm9161a = {
+	.phy_id = 0x0181b8a0,
+	.phy_id_mask = 0x0ffffff0,
+	.name = "Davicom DM9161A",
+	.features = MII_BASIC_FEATURES,
+	.init = dm9161_init,
+	.config_aneg = dm9161_config_aneg,
+	.read_status = dm9161_read_status,
+	.ack_interrupt = dm9161_ack_interrupt,
+	.config_intr = dm9161_config_intr,
+	.close = dm9161_close,
+};
+
+static struct phy_info phy_info_marvell = {
+	.phy_id = 0x01410c00,
+	.phy_id_mask = 0xffffff00,
+	.name = "Marvell 88E11x1",
+	.features = MII_GBIT_FEATURES,
+	.config_aneg = &marvell_config_aneg,
+	.read_status = &marvell_read_status,
+	.ack_interrupt = &marvell_ack_interrupt,
+	.config_intr = &marvell_config_intr,
+};
+
+static struct phy_info phy_info_genmii = {
+	.phy_id = 0x00000000,
+	.phy_id_mask = 0x00000000,
+	.name = "Generic MII",
+	.features = MII_BASIC_FEATURES,
+	.config_aneg = genmii_config_aneg,
+	.read_status = genmii_read_status,
+};
+
+static struct phy_info *phy_info[] = {
+	&phy_info_dm9161,
+	&phy_info_dm9161a,
+	&phy_info_marvell,
+	&phy_info_genmii,
+	NULL
+};
+
+u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
+{
+	return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
+}
+
+void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
+{
+	mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
+}
+
+/* Use the PHY ID registers to determine what type of PHY is attached
+ * to device dev.  return a struct phy_info structure describing that PHY
+ */
+struct phy_info *get_phy_info (struct uec_mii_info *mii_info)
+{
+	u16 phy_reg;
+	u32 phy_ID;
+	int i;
+	struct phy_info *theInfo = NULL;
+
+	/* Grab the bits from PHYIR1, and put them in the upper half */
+	phy_reg = phy_read (mii_info, PHY_PHYIDR1);
+	phy_ID = (phy_reg & 0xffff) << 16;
+
+	/* Grab the bits from PHYIR2, and put them in the lower half */
+	phy_reg = phy_read (mii_info, PHY_PHYIDR2);
+	phy_ID |= (phy_reg & 0xffff);
+
+	/* loop through all the known PHY types, and find one that */
+	/* matches the ID we read from the PHY. */
+	for (i = 0; phy_info[i]; i++)
+		if (phy_info[i]->phy_id ==
+		    (phy_ID & phy_info[i]->phy_id_mask)) {
+			theInfo = phy_info[i];
+			break;
+		}
+
+	/* This shouldn't happen, as we have generic PHY support */
+	if (theInfo == NULL) {
+		ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
+		return NULL;
+	} else {
+		ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
+	}
+
+	return theInfo;
+}
+
+void marvell_phy_interface_mode (struct eth_device *dev,
+				 enet_interface_e mode)
+{
+	uec_private_t *uec = (uec_private_t *) dev->priv;
+	struct uec_mii_info *mii_info;
+
+	if (!uec->mii_info) {
+		printf ("%s: the PHY not intialized\n", __FUNCTION__);
+		return;
+	}
+	mii_info = uec->mii_info;
+
+	if (mode == ENET_100_RGMII) {
+		phy_write (mii_info, 0x00, 0x9140);
+		phy_write (mii_info, 0x1d, 0x001f);
+		phy_write (mii_info, 0x1e, 0x200c);
+		phy_write (mii_info, 0x1d, 0x0005);
+		phy_write (mii_info, 0x1e, 0x0000);
+		phy_write (mii_info, 0x1e, 0x0100);
+		phy_write (mii_info, 0x09, 0x0e00);
+		phy_write (mii_info, 0x04, 0x01e1);
+		phy_write (mii_info, 0x00, 0x9140);
+		phy_write (mii_info, 0x00, 0x1000);
+		udelay (100000);
+		phy_write (mii_info, 0x00, 0x2900);
+		phy_write (mii_info, 0x14, 0x0cd2);
+		phy_write (mii_info, 0x00, 0xa100);
+		phy_write (mii_info, 0x09, 0x0000);
+		phy_write (mii_info, 0x1b, 0x800b);
+		phy_write (mii_info, 0x04, 0x05e1);
+		phy_write (mii_info, 0x00, 0xa100);
+		phy_write (mii_info, 0x00, 0x2100);
+		udelay (1000000);
+	} else if (mode == ENET_10_RGMII) {
+		phy_write (mii_info, 0x14, 0x8e40);
+		phy_write (mii_info, 0x1b, 0x800b);
+		phy_write (mii_info, 0x14, 0x0c82);
+		phy_write (mii_info, 0x00, 0x8100);
+		udelay (1000000);
+	}
+}
+
+void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode)
+{
+#ifdef CONFIG_PHY_MODE_NEED_CHANGE
+	marvell_phy_interface_mode (dev, mode);
+#endif
+}
+#endif /* CONFIG_QE */
diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
new file mode 100644
index 0000000..9bd926d
--- /dev/null
+++ b/drivers/qe/uec_phy.h
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2005 Freescale Semiconductor, Inc.
+ *
+ * Author: Shlomi Gridish <gridish@freescale.com>
+ *
+ * Description: UCC ethernet driver -- PHY handling
+ *		Driver for UEC on QE
+ *		Based on 8260_io/fcc_enet.c
+ *
+ * This program is free software; you can redistribute	it and/or modify it
+ * under  the terms of	the GNU General	 Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#ifndef __UEC_PHY_H__
+#define __UEC_PHY_H__
+
+#define MII_end ((u32)-2)
+#define MII_read ((u32)-1)
+
+#define MIIMIND_BUSY		0x00000001
+#define MIIMIND_NOTVALID	0x00000004
+
+#define UGETH_AN_TIMEOUT	2000
+
+/* 1000BT control (Marvell & BCM54xx at least) */
+#define MII_1000BASETCONTROL		      0x09
+#define MII_1000BASETCONTROL_FULLDUPLEXCAP    0x0200
+#define MII_1000BASETCONTROL_HALFDUPLEXCAP    0x0100
+
+/* Cicada Extended Control Register 1 */
+#define MII_CIS8201_EXT_CON1	    0x17
+#define MII_CIS8201_EXTCON1_INIT    0x0000
+
+/* Cicada Interrupt Mask Register */
+#define MII_CIS8201_IMASK	    0x19
+#define MII_CIS8201_IMASK_IEN	    0x8000
+#define MII_CIS8201_IMASK_SPEED	    0x4000
+#define MII_CIS8201_IMASK_LINK	    0x2000
+#define MII_CIS8201_IMASK_DUPLEX    0x1000
+#define MII_CIS8201_IMASK_MASK	    0xf000
+
+/* Cicada Interrupt Status Register */
+#define MII_CIS8201_ISTAT	    0x1a
+#define MII_CIS8201_ISTAT_STATUS    0x8000
+#define MII_CIS8201_ISTAT_SPEED	    0x4000
+#define MII_CIS8201_ISTAT_LINK	    0x2000
+#define MII_CIS8201_ISTAT_DUPLEX    0x1000
+
+/* Cicada Auxiliary Control/Status Register */
+#define MII_CIS8201_AUX_CONSTAT	       0x1c
+#define MII_CIS8201_AUXCONSTAT_INIT    0x0004
+#define MII_CIS8201_AUXCONSTAT_DUPLEX  0x0020
+#define MII_CIS8201_AUXCONSTAT_SPEED   0x0018
+#define MII_CIS8201_AUXCONSTAT_GBIT    0x0010
+#define MII_CIS8201_AUXCONSTAT_100     0x0008
+
+/* 88E1011 PHY Status Register */
+#define MII_M1011_PHY_SPEC_STATUS		0x11
+#define MII_M1011_PHY_SPEC_STATUS_1000		0x8000
+#define MII_M1011_PHY_SPEC_STATUS_100		0x4000
+#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK	0xc000
+#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX	0x2000
+#define MII_M1011_PHY_SPEC_STATUS_RESOLVED	0x0800
+#define MII_M1011_PHY_SPEC_STATUS_LINK		0x0400
+
+#define MII_M1011_IEVENT		0x13
+#define MII_M1011_IEVENT_CLEAR		0x0000
+
+#define MII_M1011_IMASK			0x12
+#define MII_M1011_IMASK_INIT		0x6400
+#define MII_M1011_IMASK_CLEAR		0x0000
+
+#define MII_DM9161_SCR			0x10
+#define MII_DM9161_SCR_INIT		0x0610
+#define MII_DM9161_SCR_RMII_INIT	0x0710
+
+/* DM9161 Specified Configuration and Status Register */
+#define MII_DM9161_SCSR			0x11
+#define MII_DM9161_SCSR_100F		0x8000
+#define MII_DM9161_SCSR_100H		0x4000
+#define MII_DM9161_SCSR_10F		0x2000
+#define MII_DM9161_SCSR_10H		0x1000
+
+/* DM9161 Interrupt Register */
+#define MII_DM9161_INTR			0x15
+#define MII_DM9161_INTR_PEND		0x8000
+#define MII_DM9161_INTR_DPLX_MASK	0x0800
+#define MII_DM9161_INTR_SPD_MASK	0x0400
+#define MII_DM9161_INTR_LINK_MASK	0x0200
+#define MII_DM9161_INTR_MASK		0x0100
+#define MII_DM9161_INTR_DPLX_CHANGE	0x0010
+#define MII_DM9161_INTR_SPD_CHANGE	0x0008
+#define MII_DM9161_INTR_LINK_CHANGE	0x0004
+#define MII_DM9161_INTR_INIT		0x0000
+#define MII_DM9161_INTR_STOP	\
+(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
+ | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
+
+/* DM9161 10BT Configuration/Status */
+#define MII_DM9161_10BTCSR		0x12
+#define MII_DM9161_10BTCSR_INIT		0x7800
+
+#define MII_BASIC_FEATURES    (SUPPORTED_10baseT_Half | \
+		 SUPPORTED_10baseT_Full | \
+		 SUPPORTED_100baseT_Half | \
+		 SUPPORTED_100baseT_Full | \
+		 SUPPORTED_Autoneg | \
+		 SUPPORTED_TP | \
+		 SUPPORTED_MII)
+
+#define MII_GBIT_FEATURES    (MII_BASIC_FEATURES | \
+		 SUPPORTED_1000baseT_Half | \
+		 SUPPORTED_1000baseT_Full)
+
+#define MII_READ_COMMAND		0x00000001
+
+#define MII_INTERRUPT_DISABLED		0x0
+#define MII_INTERRUPT_ENABLED		0x1
+
+#define SPEED_10    10
+#define SPEED_100   100
+#define SPEED_1000  1000
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF		0x00
+#define DUPLEX_FULL		0x01
+
+/* Indicates what features are supported by the interface. */
+#define SUPPORTED_10baseT_Half		(1 << 0)
+#define SUPPORTED_10baseT_Full		(1 << 1)
+#define SUPPORTED_100baseT_Half		(1 << 2)
+#define SUPPORTED_100baseT_Full		(1 << 3)
+#define SUPPORTED_1000baseT_Half	(1 << 4)
+#define SUPPORTED_1000baseT_Full	(1 << 5)
+#define SUPPORTED_Autoneg		(1 << 6)
+#define SUPPORTED_TP			(1 << 7)
+#define SUPPORTED_AUI			(1 << 8)
+#define SUPPORTED_MII			(1 << 9)
+#define SUPPORTED_FIBRE			(1 << 10)
+#define SUPPORTED_BNC			(1 << 11)
+#define SUPPORTED_10000baseT_Full	(1 << 12)
+
+#define ADVERTISED_10baseT_Half		(1 << 0)
+#define ADVERTISED_10baseT_Full		(1 << 1)
+#define ADVERTISED_100baseT_Half	(1 << 2)
+#define ADVERTISED_100baseT_Full	(1 << 3)
+#define ADVERTISED_1000baseT_Half	(1 << 4)
+#define ADVERTISED_1000baseT_Full	(1 << 5)
+#define ADVERTISED_Autoneg		(1 << 6)
+#define ADVERTISED_TP			(1 << 7)
+#define ADVERTISED_AUI			(1 << 8)
+#define ADVERTISED_MII			(1 << 9)
+#define ADVERTISED_FIBRE		(1 << 10)
+#define ADVERTISED_BNC			(1 << 11)
+#define ADVERTISED_10000baseT_Full	(1 << 12)
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT		0x001f	/* Selector bits	       */
+#define ADVERTISE_CSMA		0x0001	/* Only selector supported     */
+#define ADVERTISE_10HALF	0x0020	/* Try for 10mbps half-duplex  */
+#define ADVERTISE_10FULL	0x0040	/* Try for 10mbps full-duplex  */
+#define ADVERTISE_100HALF	0x0080	/* Try for 100mbps half-duplex */
+#define ADVERTISE_100FULL	0x0100	/* Try for 100mbps full-duplex */
+#define ADVERTISE_100BASE4	0x0200	/* Try for 100mbps 4k packets  */
+#define ADVERTISE_RESV		0x1c00	/* Unused...		       */
+#define ADVERTISE_RFAULT	0x2000	/* Say we can detect faults    */
+#define ADVERTISE_LPACK		0x4000	/* Ack link partners response  */
+#define ADVERTISE_NPAGE		0x8000	/* Next page bit	       */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+		       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Taken from mii_if_info and sungem_phy.h */
+struct uec_mii_info {
+	/* Information about the PHY type */
+	/* And management functions */
+	struct phy_info *phyinfo;
+
+	struct eth_device *dev;
+
+	/* forced speed & duplex (no autoneg)
+	 * partner speed & duplex & pause (autoneg)
+	 */
+	int speed;
+	int duplex;
+	int pause;
+
+	/* The most recently read link state */
+	int link;
+
+	/* Enabled Interrupts */
+	u32 interrupts;
+
+	u32 advertising;
+	int autoneg;
+	int mii_id;
+
+	/* private data pointer */
+	/* For use by PHYs to maintain extra state */
+	void *priv;
+
+	/* Provided by ethernet driver */
+	int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
+	void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
+			    int val);
+};
+
+/* struct phy_info: a structure which defines attributes for a PHY
+ *
+ * id will contain a number which represents the PHY.  During
+ * startup, the driver will poll the PHY to find out what its
+ * UID--as defined by registers 2 and 3--is.  The 32-bit result
+ * gotten from the PHY will be ANDed with phy_id_mask to
+ * discard any bits which may change based on revision numbers
+ * unimportant to functionality
+ *
+ * There are 6 commands which take a ugeth_mii_info structure.
+ * Each PHY must declare config_aneg, and read_status.
+ */
+struct phy_info {
+	u32 phy_id;
+	char *name;
+	unsigned int phy_id_mask;
+	u32 features;
+
+	/* Called to initialize the PHY */
+	int (*init) (struct uec_mii_info * mii_info);
+
+	/* Called to suspend the PHY for power */
+	int (*suspend) (struct uec_mii_info * mii_info);
+
+	/* Reconfigures autonegotiation (or disables it) */
+	int (*config_aneg) (struct uec_mii_info * mii_info);
+
+	/* Determines the negotiated speed and duplex */
+	int (*read_status) (struct uec_mii_info * mii_info);
+
+	/* Clears any pending interrupts */
+	int (*ack_interrupt) (struct uec_mii_info * mii_info);
+
+	/* Enables or disables interrupts */
+	int (*config_intr) (struct uec_mii_info * mii_info);
+
+	/* Clears up any memory if needed */
+	void (*close) (struct uec_mii_info * mii_info);
+};
+
+struct phy_info *get_phy_info (struct uec_mii_info *mii_info);
+void write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
+		    int value);
+int read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
+void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
+void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
+				  u32 interrupts);
+#endif /* __UEC_PHY_H__ */
diff --git a/drivers/systemace.c b/drivers/systemace.c
new file mode 100644
index 0000000..3848d9c
--- /dev/null
+++ b/drivers/systemace.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (XXXXXXXXXXXXXXXX)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+/*
+ * The Xilinx SystemACE chip support is activated by defining
+ * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE
+ * to set the base address of the device. This code currently
+ * assumes that the chip is connected via a byte-wide bus.
+ *
+ * The CONFIG_SYSTEMACE also adds to fat support the device class
+ * "ace" that allows the user to execute "fatls ace 0" and the
+ * like. This works by making the systemace_get_dev function
+ * available to cmd_fat.c:get_dev and filling in a block device
+ * description that has all the bits needed for FAT support to
+ * read sectors.
+ *
+ * According to Xilinx technical support, before accessing the
+ * SystemACE CF you need to set the following control bits:
+ *      FORCECFGMODE : 1
+ *      CFGMODE : 0
+ *      CFGSTART : 0
+ */
+
+#include <common.h>
+#include <command.h>
+#include <systemace.h>
+#include <part.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYSTEMACE
+
+/*
+ * The ace_readw and writew functions read/write 16bit words, but the
+ * offset value is the BYTE offset as most used in the Xilinx
+ * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined
+ * to be the base address for the chip, usually in the local
+ * peripheral bus.
+ */
+#if (CFG_SYSTEMACE_WIDTH == 8)
+#if !defined(__BIG_ENDIAN)
+#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \
+			(readb(CFG_SYSTEMACE_BASE+off+1)))
+#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \
+			      writeb(val, CFG_SYSTEMACE_BASE+off+1);}
+#else
+#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \
+			(readb(CFG_SYSTEMACE_BASE+off+1)<<8))
+#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \
+			      writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);}
+#endif
+#else
+#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off))
+#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val))
+#endif
+
+/* */
+
+static unsigned long systemace_read(int dev, unsigned long start,
+				    unsigned long blkcnt, void *buffer);
+
+static block_dev_desc_t systemace_dev = { 0 };
+
+static int get_cf_lock(void)
+{
+	int retry = 10;
+
+	/* CONTROLREG = LOCKREG */
+	unsigned val = ace_readw(0x18);
+	val |= 0x0002;
+	ace_writew((val & 0xffff), 0x18);
+
+	/* Wait for MPULOCK in STATUSREG[15:0] */
+	while (!(ace_readw(0x04) & 0x0002)) {
+
+		if (retry < 0)
+			return -1;
+
+		udelay(100000);
+		retry -= 1;
+	}
+
+	return 0;
+}
+
+static void release_cf_lock(void)
+{
+	unsigned val = ace_readw(0x18);
+	val &= ~(0x0002);
+	ace_writew((val & 0xffff), 0x18);
+}
+
+block_dev_desc_t *systemace_get_dev(int dev)
+{
+	/* The first time through this, the systemace_dev object is
+	   not yet initialized. In that case, fill it in. */
+	if (systemace_dev.blksz == 0) {
+		systemace_dev.if_type = IF_TYPE_UNKNOWN;
+		systemace_dev.dev = 0;
+		systemace_dev.part_type = PART_TYPE_UNKNOWN;
+		systemace_dev.type = DEV_TYPE_HARDDISK;
+		systemace_dev.blksz = 512;
+		systemace_dev.removable = 1;
+		systemace_dev.block_read = systemace_read;
+
+		/*
+		 * Ensure the correct bus mode (8/16 bits) gets enabled
+		 */
+		ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0);
+
+		init_part(&systemace_dev);
+
+	}
+
+	return &systemace_dev;
+}
+
+/*
+ * This function is called (by dereferencing the block_read pointer in
+ * the dev_desc) to read blocks of data. The return value is the
+ * number of blocks read. A zero return indicates an error.
+ */
+static unsigned long systemace_read(int dev, unsigned long start,
+				    unsigned long blkcnt, void *buffer)
+{
+	int retry;
+	unsigned blk_countdown;
+	unsigned char *dp = buffer;
+	unsigned val;
+
+	if (get_cf_lock() < 0) {
+		unsigned status = ace_readw(0x04);
+
+		/* If CFDETECT is false, card is missing. */
+		if (!(status & 0x0010)) {
+			printf("** CompactFlash card not present. **\n");
+			return 0;
+		}
+
+		printf("**** ACE locked away from me (STATUSREG=%04x)\n",
+		       status);
+		return 0;
+	}
+#ifdef DEBUG_SYSTEMACE
+	printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
+#endif
+
+	retry = 2000;
+	for (;;) {
+		val = ace_readw(0x04);
+
+		/* If CFDETECT is false, card is missing. */
+		if (!(val & 0x0010)) {
+			printf("**** ACE CompactFlash not found.\n");
+			release_cf_lock();
+			return 0;
+		}
+
+		/* If RDYFORCMD, then we are ready to go. */
+		if (val & 0x0100)
+			break;
+
+		if (retry < 0) {
+			printf("**** SystemACE not ready.\n");
+			release_cf_lock();
+			return 0;
+		}
+
+		udelay(1000);
+		retry -= 1;
+	}
+
+	/* The SystemACE can only transfer 256 sectors at a time, so
+	   limit the current chunk of sectors. The blk_countdown
+	   variable is the number of sectors left to transfer. */
+
+	blk_countdown = blkcnt;
+	while (blk_countdown > 0) {
+		unsigned trans = blk_countdown;
+
+		if (trans > 256)
+			trans = 256;
+
+#ifdef DEBUG_SYSTEMACE
+		printf("... transfer %lu sector in a chunk\n", trans);
+#endif
+		/* Write LBA block address */
+		ace_writew((start >> 0) & 0xffff, 0x10);
+		ace_writew((start >> 16) & 0x0fff, 0x12);
+
+		/* NOTE: in the Write Sector count below, a count of 0
+		   causes a transfer of 256, so &0xff gives the right
+		   value for whatever transfer count we want. */
+
+		/* Write sector count | ReadMemCardData. */
+		ace_writew((trans & 0xff) | 0x0300, 0x14);
+
+		/* Reset the configruation controller */
+		val = ace_readw(0x18);
+		val |= 0x0080;
+		ace_writew(val, 0x18);
+
+		retry = trans * 16;
+		while (retry > 0) {
+			int idx;
+
+			/* Wait for buffer to become ready. */
+			while (!(ace_readw(0x04) & 0x0020)) {
+				udelay(100);
+			}
+
+			/* Read 16 words of 2bytes from the sector buffer. */
+			for (idx = 0; idx < 16; idx += 1) {
+				unsigned short val = ace_readw(0x40);
+				*dp++ = val & 0xff;
+				*dp++ = (val >> 8) & 0xff;
+			}
+
+			retry -= 1;
+		}
+
+		/* Clear the configruation controller reset */
+		val = ace_readw(0x18);
+		val &= ~0x0080;
+		ace_writew(val, 0x18);
+
+		/* Count the blocks we transfer this time. */
+		start += trans;
+		blk_countdown -= trans;
+	}
+
+	release_cf_lock();
+
+	return blkcnt;
+}
+#endif /* CONFIG_SYSTEMACE */
diff --git a/drivers/tsec.c b/drivers/tsec.c
index 400e593..3f11eb0 100644
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -381,6 +381,61 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 	return 0;
 }
 
+/*
+ * Parse the BCM54xx status register for speed and duplex information.
+ * The linux sungem_phy has this information, but in a table format.
+ */
+uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
+{
+
+	switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
+
+		case 1:
+			printf("Enet starting in 10BT/HD\n");
+			priv->duplexity = 0;
+			priv->speed = 10;
+			break;
+
+		case 2:
+			printf("Enet starting in 10BT/FD\n");
+			priv->duplexity = 1;
+			priv->speed = 10;
+			break;
+
+		case 3:
+			printf("Enet starting in 100BT/HD\n");
+			priv->duplexity = 0;
+			priv->speed = 100;
+			break;
+
+		case 5:
+			printf("Enet starting in 100BT/FD\n");
+			priv->duplexity = 1;
+			priv->speed = 100;
+			break;
+
+		case 6:
+			printf("Enet starting in 1000BT/HD\n");
+			priv->duplexity = 0;
+			priv->speed = 1000;
+			break;
+
+		case 7:
+			printf("Enet starting in 1000BT/FD\n");
+			priv->duplexity = 1;
+			priv->speed = 1000;
+			break;
+
+		default:
+			printf("Auto-neg error, defaulting to 10BT/HD\n");
+			priv->duplexity = 0;
+			priv->speed = 10;
+			break;
+	}
+
+	return 0;
+
+}
 /* Parse the 88E1011's status register for speed and duplex
  * information
  */
@@ -610,11 +665,10 @@ static void adjust_link(struct eth_device *dev)
 			regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 					 | MACCFG2_MII);
 
-			/* If We're in reduced mode, we need
-			 * to say whether we're 10 or 100 MB.
+			/* Set R100 bit in all modes although
+			 * it is only used in RGMII mode
 			 */
-			if ((priv->speed == 100)
-			    && (priv->flags & TSEC_REDUCED))
+			if (priv->speed == 100)
 				regs->ecntrl |= ECNTRL_R100;
 			else
 				regs->ecntrl &= ~(ECNTRL_R100);
@@ -771,6 +825,34 @@ static void tsec_halt(struct eth_device *dev)
 		phy_run_commands(priv, priv->phyinfo->shutdown);
 }
 
+/* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
+struct phy_info phy_info_BCM5461S = {
+	0x02060c1,	/* 5461 ID */
+	"Broadcom BCM5461S",
+	0, /* not clear to me what minor revisions we can shift away */
+	(struct phy_cmd[]) { /* config */
+		/* Reset and configure the PHY */
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+		{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
+		{miim_end,}
+	},
+	(struct phy_cmd[]) { /* startup */
+		/* Status is read once to clear old link state */
+		{MIIM_STATUS, miim_read, NULL},
+		/* Auto-negotiate */
+		{MIIM_STATUS, miim_read, &mii_parse_sr},
+		/* Read the status */
+		{MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
+		{miim_end,}
+	},
+	(struct phy_cmd[]) { /* shutdown */
+		{miim_end,}
+	},
+};
+
 struct phy_info phy_info_M88E1011S = {
 	0x01410c6,
 	"Marvell 88E1011S",
@@ -816,6 +898,7 @@ struct phy_info phy_info_M88E1111S = {
 			   {0x1d, 0x5, NULL},
 			   {0x1e, 0x0, NULL},
 			   {0x1e, 0x100, NULL},
+			   {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
 			   {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 			   {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 			   {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
@@ -1110,10 +1193,9 @@ struct phy_info phy_info_dp83865 = {
 };
 
 struct phy_info *phy_info[] = {
-#if 0
-	&phy_info_cis8201,
-#endif
 	&phy_info_cis8204,
+	&phy_info_cis8201,
+	&phy_info_BCM5461S,
 	&phy_info_M88E1011S,
 	&phy_info_M88E1111S,
 	&phy_info_M88E1145,
diff --git a/drivers/tsec.h b/drivers/tsec.h
index 4aa331c..422bc66 100644
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -30,7 +30,7 @@
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
     #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
 #elif defined(CONFIG_MPC83XX)
-    #define TSEC_BASE_ADDR	(CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+    #define TSEC_BASE_ADDR	(CFG_IMMR + CFG_TSEC1_OFFSET)
 #endif
 
 
@@ -109,6 +109,11 @@
 #define MIIM_GBIT_CONTROL	0x9
 #define MIIM_GBIT_CONTROL_INIT	0xe00
 
+/* Broadcom BCM54xx -- taken from linux sungem_phy */
+#define MIIM_BCM54xx_AUXSTATUS			0x19
+#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK	0x0700
+#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT	8
+
 /* Cicada Auxiliary Control/Status Register */
 #define MIIM_CIS8201_AUX_CONSTAT        0x1c
 #define MIIM_CIS8201_AUXCONSTAT_INIT    0x0004
diff --git a/dtt/Makefile b/dtt/Makefile
index 79d4e9f..e6cb128 100644
--- a/dtt/Makefile
+++ b/dtt/Makefile
@@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)libdtt.a
 
-COBJS	= lm75.o ds1621.o adm1021.o
+COBJS	= lm75.o ds1621.o adm1021.o lm81.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/dtt/adm1021.c b/dtt/adm1021.c
index 14c38f0..9f65cfb 100644
--- a/dtt/adm1021.c
+++ b/dtt/adm1021.c
@@ -144,12 +144,15 @@ dtt_init (void)
 	unsigned char sensors[] = CONFIG_DTT_SENSORS;
 	const char *const header = "DTT:   ";
 
+	/* switch to correct I2C bus */
+	I2C_SET_BUS(CFG_DTT_BUS_NUM);
+
 	for (i = 0; i < sizeof(sensors); i++) {
-	    if (_dtt_init(sensors[i]) != 0)
-		printf ("%s%d FAILED INIT\n", header, i+1);
-	    else
-		printf ("%s%d is %i C\n", header, i+1,
-		       dtt_get_temp(sensors[i]));
+		if (_dtt_init(sensors[i]) != 0)
+			printf ("%s%d FAILED INIT\n", header, i+1);
+		else
+			printf ("%s%d is %i C\n", header, i+1,
+				dtt_get_temp(sensors[i]));
 	}
 
 	return (0);
diff --git a/dtt/lm81.c b/dtt/lm81.c
new file mode 100644
index 0000000..03bc53d
--- /dev/null
+++ b/dtt/lm81.c
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Enginnering <hs@denx.de>
+ *
+ * based on dtt/lm75.c which is ...
+ *
+ * (C) Copyright 2001
+ * Bill Hunter,  Wave 7 Optics, williamhunter@mediaone.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * On Semiconductor's LM81 Temperature Sensor
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DTT_LM81
+#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
+	(CFG_EEPROM_PAGE_WRITE_BITS < 1)
+# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than  1 to use CONFIG_DTT_LM81"
+#endif
+
+#include <i2c.h>
+#include <dtt.h>
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x2c			/* ON Semi's LM81 device */
+
+int dtt_read(int sensor, int reg)
+{
+    int dlen = 1;
+    uchar data[2];
+
+    /*
+     * Calculate sensor address and register.
+     */
+    sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */
+
+    /*
+     * Now try to read the register.
+     */
+    if (i2c_read(sensor, reg, 1, data, dlen) != 0)
+	return -1;
+
+    return (int)data[0];
+} /* dtt_read() */
+
+
+int dtt_write(int sensor, int reg, int val)
+{
+    uchar data;
+
+    /*
+     * Calculate sensor address and register.
+     */
+    sensor = DTT_I2C_DEV_CODE + (sensor & 0x03); /* calculate address of lm81 */
+
+    data = (char)(val & 0xff);
+
+    /*
+     * Write value to register.
+     */
+    if (i2c_write(sensor, reg, 1, &data, 1) != 0)
+	return 1;
+
+    return 0;
+} /* dtt_write() */
+
+#define DTT_MANU	0x3e
+#define DTT_REV		0x3f
+#define DTT_CONFIG	0x40
+#define DTT_ADR		0x48
+
+static int _dtt_init(int sensor)
+{
+	int	man;
+	int	adr;
+	int	rev;
+
+	if (dtt_write (sensor, DTT_CONFIG, 0x01) < 0)
+		return 1;
+	/* The LM81 needs 400ms to get the correct values ... */
+	udelay (400000);
+	man = dtt_read (sensor, DTT_MANU);
+	if (man != 0x01)
+		return 1;
+	adr = dtt_read (sensor, DTT_ADR);
+	if (adr < 0)
+		return 1;
+	rev = dtt_read (sensor, DTT_REV);
+	if (adr < 0)
+		return 1;
+
+	printf ("DTT:   Found LM81@%x Rev: %d\n", adr, rev);
+	return 0;
+} /* _dtt_init() */
+
+
+int dtt_init (void)
+{
+    int i;
+    unsigned char sensors[] = CONFIG_DTT_SENSORS;
+    const char *const header = "DTT:   ";
+
+    for (i = 0; i < sizeof(sensors); i++) {
+	if (_dtt_init(sensors[i]) != 0)
+	    printf("%s%d FAILED INIT\n", header, i+1);
+	else
+	    printf("%s%d is %i C\n", header, i+1,
+		   dtt_get_temp(sensors[i]));
+    }
+
+    return (0);
+} /* dtt_init() */
+
+#define TEMP_FROM_REG(temp) \
+   ((temp)<256?((((temp)&0x1fe) >> 1) * 10)	 + ((temp) & 1) * 5:  \
+	       ((((temp)&0x1fe) >> 1) -255) * 10 - ((temp) & 1) * 5)  \
+
+int dtt_get_temp(int sensor)
+{
+	int val = dtt_read (sensor, DTT_READ_TEMP);
+	int tmpcnf = dtt_read (sensor, DTT_CONFIG_TEMP);
+
+	return (TEMP_FROM_REG((val << 1) + ((tmpcnf & 0x80) >> 7))) / 10;
+} /* dtt_get_temp() */
+
+#endif /* CONFIG_DTT_LM81 */
diff --git a/examples/Makefile b/examples/Makefile
index 423a79b..e9b4974 100644
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -86,10 +86,14 @@ BIN	+= sched.bin
 endif
 
 ifeq ($(ARCH),blackfin)
+ifneq ($(BOARD),bf537-stamp)
+ifneq ($(BOARD),bf537-pnav)
 ELF	+= smc91111_eeprom
 SREC	+= smc91111_eeprom.srec
 BIN 	+= smc91111_eeprom.bin
 endif
+endif
+endif
 
 # The following example is pretty 8xx specific...
 ifeq ($(CPU),mpc8xx)
diff --git a/examples/stubs.c b/examples/stubs.c
index ffd314e..26df6e0 100644
--- a/examples/stubs.c
+++ b/examples/stubs.c
@@ -132,7 +132,7 @@ gd_t *global_data;
  */
 #define EXPORT_FUNC(x)			\
 	asm volatile (			\
-"       .globl " #x "\n"		\
+"       .globl _" #x "\n_"		\
 #x ":\n"				\
 "	P0 = [P5 + %0]\n"		\
 "	P0 = [P0 + %1]\n"		\
diff --git a/include/405gp_i2c.h b/include/405gp_i2c.h
deleted file mode 100644
index 5a9a497..0000000
--- a/include/405gp_i2c.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef _405gp_i2c_h_
-#define _405gp_i2c_h_
-
-#define	   I2C_REGISTERS_BASE_ADDRESS 0xEF600500
-#define    IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
-#define    IIC_SDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
-#define    IIC_LMADR	(I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
-#define    IIC_HMADR	(I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
-#define    IIC_CNTL	(I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
-#define    IIC_MDCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
-#define    IIC_STS	(I2C_REGISTERS_BASE_ADDRESS+IICSTS)
-#define    IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
-#define    IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
-#define    IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
-#define    IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
-#define    IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
-#define    IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
-#define    IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
-
-/* MDCNTL Register Bit definition */
-#define    IIC_MDCNTL_HSCL 0x01
-#define    IIC_MDCNTL_EUBS 0x02
-#define    IIC_MDCNTL_EINT 0x04
-#define    IIC_MDCNTL_ESM  0x08
-#define    IIC_MDCNTL_FSM  0x10
-#define    IIC_MDCNTL_EGC  0x20
-#define    IIC_MDCNTL_FMDB 0x40
-#define    IIC_MDCNTL_FSDB 0x80
-
-/* CNTL Register Bit definition */
-#define    IIC_CNTL_PT     0x01
-#define    IIC_CNTL_READ   0x02
-#define    IIC_CNTL_CHT    0x04
-#define    IIC_CNTL_RPST   0x08
-/* bit 2/3 for Transfer count*/
-#define    IIC_CNTL_AMD    0x40
-#define    IIC_CNTL_HMT    0x80
-
-/* STS Register Bit definition */
-#define    IIC_STS_PT	   0X01
-#define    IIC_STS_IRQA    0x02
-#define    IIC_STS_ERR	   0X04
-#define    IIC_STS_SCMP    0x08
-#define    IIC_STS_MDBF    0x10
-#define    IIC_STS_MDBS    0X20
-#define    IIC_STS_SLPR    0x40
-#define    IIC_STS_SSS     0x80
-
-/* EXTSTS Register Bit definition */
-#define    IIC_EXTSTS_XFRA 0X01
-#define    IIC_EXTSTS_ICT  0X02
-#define    IIC_EXTSTS_LA   0X04
-
-/* XTCNTLSS Register Bit definition */
-#define    IIC_XTCNTLSS_SRST  0x01
-#define    IIC_XTCNTLSS_EPI   0x02
-#define    IIC_XTCNTLSS_SDBF  0x04
-#define    IIC_XTCNTLSS_SBDD  0x08
-#define    IIC_XTCNTLSS_SWS   0x10
-#define    IIC_XTCNTLSS_SWC   0x20
-#define    IIC_XTCNTLSS_SRS   0x40
-#define    IIC_XTCNTLSS_SRC   0x80
-#endif
diff --git a/include/440_i2c.h b/include/440_i2c.h
deleted file mode 100644
index 0c2bf36..0000000
--- a/include/440_i2c.h
+++ /dev/null
@@ -1,71 +0,0 @@
-#ifndef _440_i2c_h_
-#define _440_i2c_h_
-
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
-#else
-#define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
-#endif /*CONFIG_440EP CONFIG_440GR*/
-
-#define	   I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
-#define    IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
-#define    IIC_SDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
-#define    IIC_LMADR	(I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
-#define    IIC_HMADR	(I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
-#define    IIC_CNTL	(I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
-#define    IIC_MDCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
-#define    IIC_STS	(I2C_REGISTERS_BASE_ADDRESS+IICSTS)
-#define    IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
-#define    IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
-#define    IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
-#define    IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
-#define    IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
-#define    IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
-#define    IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
-
-/* MDCNTL Register Bit definition */
-#define    IIC_MDCNTL_HSCL 0x01
-#define    IIC_MDCNTL_EUBS 0x02
-#define    IIC_MDCNTL_EINT 0x04
-#define    IIC_MDCNTL_ESM  0x08
-#define    IIC_MDCNTL_FSM  0x10
-#define    IIC_MDCNTL_EGC  0x20
-#define    IIC_MDCNTL_FMDB 0x40
-#define    IIC_MDCNTL_FSDB 0x80
-
-/* CNTL Register Bit definition */
-#define    IIC_CNTL_PT     0x01
-#define    IIC_CNTL_READ   0x02
-#define    IIC_CNTL_CHT    0x04
-#define    IIC_CNTL_RPST   0x08
-/* bit 2/3 for Transfer count*/
-#define    IIC_CNTL_AMD    0x40
-#define    IIC_CNTL_HMT    0x80
-
-/* STS Register Bit definition */
-#define    IIC_STS_PT	   0X01
-#define    IIC_STS_IRQA    0x02
-#define    IIC_STS_ERR	   0X04
-#define    IIC_STS_SCMP    0x08
-#define    IIC_STS_MDBF    0x10
-#define    IIC_STS_MDBS    0X20
-#define    IIC_STS_SLPR    0x40
-#define    IIC_STS_SSS     0x80
-
-/* EXTSTS Register Bit definition */
-#define    IIC_EXTSTS_XFRA 0X01
-#define    IIC_EXTSTS_ICT  0X02
-#define    IIC_EXTSTS_LA   0X04
-
-/* XTCNTLSS Register Bit definition */
-#define    IIC_XTCNTLSS_SRST  0x01
-#define    IIC_XTCNTLSS_EPI   0x02
-#define    IIC_XTCNTLSS_SDBF  0x04
-#define    IIC_XTCNTLSS_SBDD  0x08
-#define    IIC_XTCNTLSS_SWS   0x10
-#define    IIC_XTCNTLSS_SWC   0x20
-#define    IIC_XTCNTLSS_SRS   0x40
-#define    IIC_XTCNTLSS_SRC   0x80
-#endif
diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h
new file mode 100644
index 0000000..66b7997
--- /dev/null
+++ b/include/4xx_i2c.h
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _4xx_i2c_h_
+#define _4xx_i2c_h_
+
+#define IIC_OK		0
+#define IIC_NOK		1
+#define IIC_NOK_LA	2		/* Lost arbitration */
+#define IIC_NOK_ICT	3		/* Incomplete transfer */
+#define IIC_NOK_XFRA	4		/* Transfer aborted */
+#define IIC_NOK_DATA	5		/* No data in buffer */
+#define IIC_NOK_TOUT	6		/* Transfer timeout */
+
+#define IIC_TIMEOUT	1		/* 1 second */
+
+#if defined(CONFIG_I2C_MULTI_BUS)
+#define I2C_BUS_OFFS	(i2c_bus_num * 0x100)
+#else
+#define I2C_BUS_OFFS	(0x000)
+#endif /* CONFIG_I2C_MULTI_BUS */
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define I2C_BASE_ADDR	(CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
+#elif defined(CONFIG_440)
+/* all remaining 440 variants */
+#define I2C_BASE_ADDR	(CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
+#else
+/* all 405 variants */
+#define I2C_BASE_ADDR	(0xEF600500 + I2C_BUS_OFFS)
+#endif
+
+#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
+#define IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
+#define IIC_SDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
+#define IIC_LMADR	(I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
+#define IIC_HMADR	(I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
+#define IIC_CNTL	(I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
+#define IIC_MDCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
+#define IIC_STS		(I2C_REGISTERS_BASE_ADDRESS+IICSTS)
+#define IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
+#define IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
+#define IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
+#define IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
+#define IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
+#define IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
+#define IIC_DIRECTCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
+
+/* MDCNTL Register Bit definition */
+#define IIC_MDCNTL_HSCL		0x01
+#define IIC_MDCNTL_EUBS		0x02
+#define IIC_MDCNTL_EINT		0x04
+#define IIC_MDCNTL_ESM		0x08
+#define IIC_MDCNTL_FSM		0x10
+#define IIC_MDCNTL_EGC		0x20
+#define IIC_MDCNTL_FMDB		0x40
+#define IIC_MDCNTL_FSDB		0x80
+
+/* CNTL Register Bit definition */
+#define IIC_CNTL_PT		0x01
+#define IIC_CNTL_READ		0x02
+#define IIC_CNTL_CHT		0x04
+#define IIC_CNTL_RPST		0x08
+/* bit 2/3 for Transfer count*/
+#define IIC_CNTL_AMD		0x40
+#define IIC_CNTL_HMT		0x80
+
+/* STS Register Bit definition */
+#define IIC_STS_PT		0x01
+#define IIC_STS_IRQA		0x02
+#define IIC_STS_ERR		0x04
+#define IIC_STS_SCMP		0x08
+#define IIC_STS_MDBF		0x10
+#define IIC_STS_MDBS		0x20
+#define IIC_STS_SLPR		0x40
+#define IIC_STS_SSS		0x80
+
+/* EXTSTS Register Bit definition */
+#define IIC_EXTSTS_XFRA		0x01
+#define IIC_EXTSTS_ICT		0x02
+#define IIC_EXTSTS_LA		0x04
+
+/* XTCNTLSS Register Bit definition */
+#define IIC_XTCNTLSS_SRST	0x01
+#define IIC_XTCNTLSS_EPI	0x02
+#define IIC_XTCNTLSS_SDBF	0x04
+#define IIC_XTCNTLSS_SBDD	0x08
+#define IIC_XTCNTLSS_SWS	0x10
+#define IIC_XTCNTLSS_SWC	0x20
+#define IIC_XTCNTLSS_SRS	0x40
+#define IIC_XTCNTLSS_SRC	0x80
+
+/* IICx_DIRECTCNTL register */
+#define IIC_DIRCNTL_SDAC	0x08
+#define IIC_DIRCNTL_SCC		0x04
+#define IIC_DIRCNTL_MSDA	0x02
+#define IIC_DIRCNTL_MSC		0x01
+
+#define DIRCTNL_FREE(v)		(((v) & 0x0f) == 0x0f)
+#endif
diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h
index a628798..33e396a 100644
--- a/include/74xx_7xx.h
+++ b/include/74xx_7xx.h
@@ -111,6 +111,7 @@ typedef enum __cpu_t {
 	CPU_750CX, CPU_750FX, CPU_750GX,
 	CPU_7400,
 	CPU_7410,
+	CPU_7448,
 	CPU_7450, CPU_7455, CPU_7457,
 	CPU_UNKNOWN} cpu_t;
 
diff --git a/include/ACEX1K.h b/include/ACEX1K.h
index f75c463..f249d64 100644
--- a/include/ACEX1K.h
+++ b/include/ACEX1K.h
@@ -35,6 +35,11 @@ extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize );
 extern int ACEX1K_info( Altera_desc *desc );
 extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off );
 
+extern int CYC2_load( Altera_desc *desc, void *image, size_t size );
+extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize );
+extern int CYC2_info( Altera_desc *desc );
+extern int CYC2_reloc( Altera_desc *desc, ulong reloc_off );
+
 /* Slave Serial Implementation function table */
 typedef struct {
 	Altera_pre_fn		pre;
@@ -48,6 +53,18 @@ typedef struct {
 	int			relocated;
 } Altera_ACEX1K_Passive_Serial_fns;
 
+/* Slave Serial Implementation function table */
+typedef struct {
+	Altera_pre_fn		pre;
+	Altera_config_fn	config;
+	Altera_status_fn	status;
+	Altera_done_fn		done;
+	Altera_write_fn		write;
+	Altera_abort_fn		abort;
+	Altera_post_fn		post;
+	int			relocated;
+} Altera_CYC2_Passive_Serial_fns;
+
 /* Device Image Sizes
  *********************************************************************/
 /* ACEX1K */
@@ -60,6 +77,8 @@ typedef struct {
 #endif
 #define Altera_EP1K100_SIZE  	(166965*8)
 
+#define Altera_EP2C35_SIZE	883905
+
 /* Descriptor Macros
  *********************************************************************/
 /* ACEX1K devices */
diff --git a/include/altera.h b/include/altera.h
index 74b6729..7b8cb4a 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -34,8 +34,10 @@
 /* Altera Model definitions
  *********************************************************************/
 #define CFG_ACEX1K		CFG_FPGA_DEV( 0x1 )
+#define CFG_CYCLON2		CFG_FPGA_DEV( 0x2 )
 
 #define CFG_ALTERA_ACEX1K	(CFG_FPGA_ALTERA | CFG_ACEX1K)
+#define CFG_ALTERA_CYCLON2	(CFG_FPGA_ALTERA | CFG_CYCLON2)
 /* Add new models here */
 
 /* Altera Interface definitions
@@ -56,6 +58,7 @@ typedef enum {				/* typedef Altera_iface */
 typedef enum {			/* typedef Altera_Family */
     min_altera_type,		/* insert all new types after this */
     Altera_ACEX1K,		/* ACEX1K Family */
+    Altera_CYC2,		/* CYCLONII Family */
 /* Add new models here */
     max_altera_type		/* insert all new types before this */
 } Altera_Family;		/* end, typedef Altera_Family */
@@ -84,6 +87,7 @@ typedef int (*Altera_status_fn)( int cookie );
 typedef int (*Altera_done_fn)( int cookie );
 typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
 typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
+typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie);
 typedef int (*Altera_abort_fn)( int cookie );
 typedef int (*Altera_post_fn)( int cookie );
 
diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h
index 3056ca7..1e9cd41 100644
--- a/include/asm-arm/arch-arm720t/hardware.h
+++ b/include/asm-arm/arch-arm720t/hardware.h
@@ -36,6 +36,8 @@
 /* include armadillo specific hardware file if there was one */
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 /* include IntegratorCP/CM720T specific hardware file if there was one */
+#elif defined(CONFIG_LPC2292)
+#include <asm-arm/arch-arm720t/lpc2292_registers.h>
 #else
 #error No hardware file defined for this configuration
 #endif
diff --git a/include/asm-arm/arch-arm720t/lpc2292_registers.h b/include/asm-arm/arch-arm720t/lpc2292_registers.h
new file mode 100644
index 0000000..5715f3e
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/lpc2292_registers.h
@@ -0,0 +1,225 @@
+#ifndef __LPC2292_REGISTERS_H
+#define __LPC2292_REGISTERS_H
+
+#include <config.h>
+
+/* Macros for reading/writing registers */
+#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
+#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
+#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
+#define GET8(reg) (*(volatile unsigned char*)(reg))
+#define GET16(reg) (*(volatile unsigned short*)(reg))
+#define GET32(reg) (*(volatile unsigned int*)(reg))
+
+/* External Memory Controller */
+
+#define BCFG0 0xFFE00000	/* 32-bits */
+#define BCFG1 0xFFE00004	/* 32-bits */
+#define BCFG2 0xFFE00008	/* 32-bits */
+#define BCFG3 0xFFE0000c	/* 32-bits */
+
+/* System Control Block */
+
+#define EXTINT   0xE01FC140
+#define EXTWAKE  0xE01FC144
+#define EXTMODE  0xE01FC148
+#define EXTPOLAR 0xE01FC14C
+#define MEMMAP   0xE01FC040
+#define PLLCON   0xE01FC080
+#define PLLCFG   0xE01FC084
+#define PLLSTAT  0xE01FC088
+#define PLLFEED  0xE01FC08C
+#define PCON     0xE01FC0C0
+#define PCONP    0xE01FC0C4
+#define VPBDIV   0xE01FC100
+
+/* Memory Acceleration Module */
+
+#define MAMCR  0xE01FC000
+#define MAMTIM 0xE01FC004
+
+/* Vectored Interrupt Controller */
+
+#define VICIRQStatus    0xFFFFF000
+#define VICFIQStatus    0xFFFFF004
+#define VICRawIntr      0xFFFFF008
+#define VICIntSelect    0xFFFFF00C
+#define VICIntEnable    0xFFFFF010
+#define VICIntEnClr     0xFFFFF014
+#define VICSoftInt      0xFFFFF018
+#define VICSoftIntClear 0xFFFFF01C
+#define VICProtection   0xFFFFF020
+#define VICVectAddr     0xFFFFF030
+#define VICDefVectAddr  0xFFFFF034
+#define VICVectAddr0    0xFFFFF100
+#define VICVectAddr1    0xFFFFF104
+#define VICVectAddr2    0xFFFFF108
+#define VICVectAddr3    0xFFFFF10C
+#define VICVectAddr4    0xFFFFF110
+#define VICVectAddr5    0xFFFFF114
+#define VICVectAddr6    0xFFFFF118
+#define VICVectAddr7    0xFFFFF11C
+#define VICVectAddr8    0xFFFFF120
+#define VICVectAddr9    0xFFFFF124
+#define VICVectAddr10   0xFFFFF128
+#define VICVectAddr11   0xFFFFF12C
+#define VICVectAddr12   0xFFFFF130
+#define VICVectAddr13   0xFFFFF134
+#define VICVectAddr14   0xFFFFF138
+#define VICVectAddr15   0xFFFFF13C
+#define VICVectCntl0    0xFFFFF200
+#define VICVectCntl1	0xFFFFF204
+#define VICVectCntl2	0xFFFFF208
+#define VICVectCntl3	0xFFFFF20C
+#define VICVectCntl4	0xFFFFF210
+#define VICVectCntl5	0xFFFFF214
+#define VICVectCntl6	0xFFFFF218
+#define VICVectCntl7	0xFFFFF21C
+#define VICVectCntl8	0xFFFFF220
+#define VICVectCntl9	0xFFFFF224
+#define VICVectCntl10	0xFFFFF228
+#define VICVectCntl11	0xFFFFF22C
+#define VICVectCntl12	0xFFFFF230
+#define VICVectCntl13	0xFFFFF234
+#define VICVectCntl14	0xFFFFF238
+#define VICVectCntl15	0xFFFFF23C
+
+/* Pin connect block */
+
+#define PINSEL0 0xE002C000	/* 32 bits */
+#define PINSEL1 0xE002C004	/* 32 bits */
+#define PINSEL2 0xE002C014	/* 32 bits */
+
+/* GPIO */
+
+#define IO0PIN 0xE0028000
+#define IO0SET 0xE0028004
+#define IO0DIR 0xE0028008
+#define IO0CLR 0xE002800C
+#define IO1PIN 0xE0028010
+#define IO1SET 0xE0028014
+#define IO1DIR 0xE0028018
+#define IO1CLR 0xE002801C
+#define IO2PIN 0xE0028020
+#define IO2SET 0xE0028024
+#define IO2DIR 0xE0028028
+#define IO2CLR 0xE002802C
+#define IO3PIN 0xE0028030
+#define IO3SET 0xE0028034
+#define IO3DIR 0xE0028038
+#define IO3CLR 0xE002803C
+
+/* Uarts */
+
+#define U0RBR 0xE000C000
+#define U0THR 0xE000C000
+#define U0IER 0xE000C004
+#define U0IIR 0xE000C008
+#define U0FCR 0xE000C008
+#define U0LCR 0xE000C00C
+#define U0LSR 0xE000C014
+#define U0SCR 0xE000C01C
+#define U0DLL 0xE000C000
+#define U0DLM 0xE000C004
+
+#define U1RBR 0xE0010000
+#define U1THR 0xE0010000
+#define U1IER 0xE0010004
+#define U1IIR 0xE0010008
+#define U1FCR 0xE0010008
+#define U1LCR 0xE001000C
+#define U1MCR 0xE0010010
+#define U1LSR 0xE0010014
+#define U1MSR 0xE0010018
+#define U1SCR 0xE001001C
+#define U1DLL 0xE0010000
+#define U1DLM 0xE0010004
+
+/* I2C */
+
+#define I2CONSET 0xE001C000
+#define I2STAT   0xE001C004
+#define I2DAT    0xE001C008
+#define I2ADR    0xE001C00C
+#define I2SCLH   0xE001C010
+#define I2SCLL   0xE001C014
+#define I2CONCLR 0xE001C018
+
+/* SPI */
+
+#define S0SPCR  0xE0020000
+#define S0SPSR  0xE0020004
+#define S0SPDR  0xE0020008
+#define S0SPCCR 0xE002000C
+#define S0SPINT 0xE002001C
+
+#define S1SPCR  0xE0030000
+#define S1SPSR  0xE0030004
+#define S1SPDR  0xE0030008
+#define S1SPCCR 0xE003000C
+#define S1SPINT 0xE003001C
+
+/* CAN controller */
+
+/* skip for now */
+
+/* Timers */
+
+#define T0IR  0xE0004000
+#define T0TCR 0xE0004004
+#define T0TC  0xE0004008
+#define T0PR  0xE000400C
+#define T0PC  0xE0004010
+#define T0MCR 0xE0004014
+#define T0MR0 0xE0004018
+#define T0MR1 0xE000401C
+#define T0MR2 0xE0004020
+#define T0MR3 0xE0004024
+#define T0CCR 0xE0004028
+#define T0CR0 0xE000402C
+#define T0CR1 0xE0004030
+#define T0CR2 0xE0004034
+#define T0CR3 0xE0004038
+#define T0EMR 0xE000403C
+
+#define T1IR  0xE0008000
+#define T1TCR 0xE0008004
+#define T1TC  0xE0008008
+#define T1PR  0xE000800C
+#define T1PC  0xE0008010
+#define T1MCR 0xE0008014
+#define T1MR0 0xE0008018
+#define T1MR1 0xE000801C
+#define T1MR2 0xE0008020
+#define T1MR3 0xE0008024
+#define T1CCR 0xE0008028
+#define T1CR0 0xE000802C
+#define T1CR1 0xE0008030
+#define T1CR2 0xE0008034
+#define T1CR3 0xE0008038
+#define T1EMR 0xE000803C
+
+/* PWM */
+
+/* skip for now */
+
+/* A/D converter */
+
+/* skip for now */
+
+/* Real Time Clock */
+
+/* skip for now */
+
+/* Watchdog */
+
+#define WDMOD  0xE0000000
+#define WDTC   0xE0000004
+#define WDFEED 0xE0000008
+#define WDTV   0xE000000C
+
+/* EmbeddedICE LOGIC */
+
+/* skip for now */
+
+#endif
diff --git a/include/asm-arm/arch-arm720t/mmc.h b/include/asm-arm/arch-arm720t/mmc.h
new file mode 100644
index 0000000..e664a5f
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/mmc.h
@@ -0,0 +1,22 @@
+/*
+ * A dummy header file for use with the LPC2292 port to keep the
+ * compiler happy.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MMC_ARM_TDM_H_
+#define _MMC_ARM_TDM_H_
+#endif /* _MMC_ARM_TDM_H_ */
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 648a10d..47c18e7 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -29,6 +29,10 @@
 #include <asm/arch/hardware.h>
 #endif	/* XXX###XXX */
 
+static inline void sync(void)
+{
+}
+
 /*
  * Generic virtual read/write.  Note that we don't support half-word
  * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h
index e86c456..3c0d569 100644
--- a/include/asm-avr32/io.h
+++ b/include/asm-avr32/io.h
@@ -89,4 +89,8 @@ static __inline__ void * phys_to_virt(unsigned long address)
 
 #endif /* __KERNEL__ */
 
+static inline void sync(void)
+{
+}
+
 #endif /* __ASM_AVR32_IO_H */
diff --git a/include/asm-blackfin/arch-bf533/anomaly.h b/include/asm-blackfin/arch-bf533/anomaly.h
new file mode 100644
index 0000000..4fe425c
--- /dev/null
+++ b/include/asm-blackfin/arch-bf533/anomaly.h
@@ -0,0 +1,172 @@
+/*
+ * File:         include/asm-blackfin/arch-bf533/anomaly.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* This file shoule be up to date with:
+ *  - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
+ *  - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
+ *  - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1 or 0.2 silicon - sorry */
+#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
+#error Kernel will not work on BF533 Version 0.1 or 0.2
+#endif
+
+/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
+#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
+			    slot1 and store of a P register in slot 2 is not
+			    supported */
+#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
+			    every corresponding match */
+#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
+			    Channel DMA stops */
+#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
+			    registers. */
+#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
+			    upper bits*/
+#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
+#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
+			    syncs */
+#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
+			    functional */
+#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
+			    state */
+#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
+#define ANOMALY_05000272 /* Certain data cache write through modes fail for
+			    VDDint <=0.9V */
+#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
+#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
+			    an edge is detected may clear interrupt */
+#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
+			    DMA system instability */
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
+			    not restored */
+#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
+			    control */
+#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
+			    killed in a particular stage*/
+#endif
+
+/* These issues only occur on 0.3 or 0.4 BF533 */
+#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
+			    updated at the same time. */
+#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
+			    Cache Fill can be corrupted after or during
+			    Instruction DMA if certain core stalls exist */
+#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
+			    Purpose TX or RX modes */
+#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
+			    preceding memory read */
+#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
+			    inactive channels in certain conditions */
+#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
+			    situation */
+#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
+#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
+#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
+			    data*/
+#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
+			    Differences in certain Conditions */
+#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
+#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
+			    hardware reset */
+#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
+			    IDLE around a Change of Control causes
+			    unpredictable results */
+#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
+			    shadow of a conditional branch */
+#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
+			    errors */
+#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
+#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
+			    interrupt not functional */
+#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
+			    loops may cause the instruction fetch unit to
+			    malfunction */
+#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
+			    the ICPLB Data registers differ */
+#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
+#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
+#define ANOMALY_05000262 /* Stores to data cache may be lost */
+#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
+#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
+			    instruction will cause an infinite stall in the
+			    second to last instruction in a hardware loop */
+#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
+			    SPORT external receive and transmit clocks. */
+#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
+			    internal voltage regulator (VDDint) to increase. */
+#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
+			    internal voltage regulator (VDDint) to decrease */
+#endif
+
+/* These issues are only on 0.4 silicon */
+#if (defined(CONFIG_BF_REV_0_4))
+#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
+#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
+			    (TDM) */
+#endif
+
+/* These issues are only on 0.3 silicon */
+#if defined(CONFIG_BF_REV_0_3)
+#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
+			    External Frame Syncs */
+#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
+			    Instruction or Data Fetches, or by Fetches at the
+			    boundary of reserved memory space */
+#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
+			    when polarity setting is changed */
+#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
+			    corruption */
+#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
+			    fix */
+#define ANOMALY_05000201 /* Receive frame sync not ignored during active
+			    frames in sport MCM */
+#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
+			    stopping */
+#if defined(CONFIG_BF533)
+#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
+			    allocate cache lines on reads only mode */
+#endif /* CONFIG_BF533 */
+#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
+#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
+			    instructions */
+#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
+			    Sync Transmit Mode */
+#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
+#endif
+
+#endif /*  _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/cpu/bf533_serial.h b/include/asm-blackfin/arch-bf533/bf533_serial.h
index d5e162a..ce58863 100644
--- a/include/asm-blackfin/cpu/bf533_serial.h
+++ b/include/asm-blackfin/arch-bf533/bf533_serial.h
@@ -22,7 +22,6 @@
  * MA 02111-1307 USA
  */
 
-
 #ifndef _BF533_SERIAL_H_
 #define _BF533_SERIAL_H_
 
diff --git a/include/asm-blackfin/cpu/bf533_rtc.h b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h
index bc09922..bc09922 100644
--- a/include/asm-blackfin/cpu/bf533_rtc.h
+++ b/include/asm-blackfin/arch-bf533/bf5xx_rtc.h
diff --git a/include/asm-blackfin/cpu/cdefBF531.h b/include/asm-blackfin/arch-bf533/cdefBF531.h
index 68d841d..3877db8 100644
--- a/include/asm-blackfin/cpu/cdefBF531.h
+++ b/include/asm-blackfin/arch-bf533/cdefBF531.h
@@ -19,6 +19,6 @@
 #ifndef _CDEFBF531_H
 #define _CDEFBF531_H
 
-#include <cdefBF532.h>
+#include <asm/arch-bf533/cdefBF532.h>
 
 #endif	/* _CDEFBF531_H */
diff --git a/include/asm-blackfin/cpu/cdefBF532.h b/include/asm-blackfin/arch-bf533/cdefBF532.h
index a4d422f..bca1ed1 100644
--- a/include/asm-blackfin/cpu/cdefBF532.h
+++ b/include/asm-blackfin/arch-bf533/cdefBF532.h
@@ -26,10 +26,10 @@
  */
 
 /* include all Core registers and bit definitions */
-#include <asm/cpu/defBF532.h>
+#include <asm/arch-bf533/defBF532.h>
 
 /* include core specific register pointer definitions */
-#include <asm/cpu/cdef_LPBlackfin.h>
+#include <asm/arch-common/cdef_LPBlackfin.h>
 
 /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
 #define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
diff --git a/include/asm-blackfin/cpu/cdefBF533.h b/include/asm-blackfin/arch-bf533/cdefBF533.h
index 8c751e6..c72bac9 100644
--- a/include/asm-blackfin/cpu/cdefBF533.h
+++ b/include/asm-blackfin/arch-bf533/cdefBF533.h
@@ -19,6 +19,6 @@
 #ifndef _CDEFBF533_H
 #define _CDEFBF533_H
 
-#include <asm/cpu/cdefBF532.h>
+#include <asm/arch-bf533/cdefBF532.h>
 
 #endif	/* _CDEFBF533_H */
diff --git a/include/asm-blackfin/arch-bf533/cplbtab.h b/include/asm-blackfin/arch-bf533/cplbtab.h
new file mode 100644
index 0000000..89f0325
--- /dev/null
+++ b/include/asm-blackfin/arch-bf533/cplbtab.h
@@ -0,0 +1,482 @@
+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
+ * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
+ *	        shouldn't be victimized. cplbmgr.S search logic is corrected
+ *	        to findout the appropriate victim.
+ *	     2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
+ *	     : LG Soft India
+ */
+#include <config.h>
+
+#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
+#define __ARCH_BFINNOMMU_CPLBTAB_H
+
+/*************************************************************************
+ *  			ICPLB TABLE
+ *************************************************************************/
+
+.data
+/* This table is configurable */
+    .align 4;
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY            	(PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL		(PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158		0x200
+#ifdef CONFIG_BLKFIN_WB		/*Write Back Policy */
+#define SDRAM_DGENERIC  	(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU		(PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+#else				/*Write Through */
+#define SDRAM_DGENERIC 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU		(PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+#endif
+
+.align 4;
+.global _ipdt_table _ipdt_table:.byte4 0x00000000;
+.byte4(SDRAM_IKERNEL);		/*SDRAM_Page0 */
+.byte4 0x00400000;
+.byte4(SDRAM_IKERNEL);		/*SDRAM_Page1 */
+.byte4 0x00800000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page2 */
+.byte4 0x00C00000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page3 */
+.byte4 0x01000000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page4 */
+.byte4 0x01400000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page5 */
+.byte4 0x01800000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page6 */
+.byte4 0x01C00000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page7 */
+#ifndef CONFIG_EZKIT		/*STAMP Memory regions */
+.byte4 0x02000000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page8 */
+.byte4 0x02400000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page9 */
+.byte4 0x02800000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page10 */
+.byte4 0x02C00000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page11 */
+.byte4 0x03000000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page12 */
+.byte4 0x03400000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page13 */
+.byte4 0x03800000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page14 */
+.byte4 0x03C00000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page15 */
+#endif
+.byte4 0x20000000;
+.byte4(SDRAM_EBIU);		/* Async Memory Bank 2 (Secnd) */
+
+#ifdef CONFIG_STAMP
+.byte4 0x04000000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x04400000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x04800000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x04C00000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x05000000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x05400000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x05800000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x05C00000;
+.byte4(SDRAM_IGENERIC);
+.byte4 0x06000000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page25 */
+.byte4 0x06400000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page26 */
+.byte4 0x06800000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page27 */
+.byte4 0x06C00000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page28 */
+.byte4 0x07000000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page29 */
+.byte4 0x07400000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page30 */
+.byte4 0x07800000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page31 */
+.byte4 0x07C00000;
+.byte4(SDRAM_IKERNEL);		/*SDRAM_Page32 */
+#endif
+.byte4 0xffffffff;		/* end of section - termination */
+
+/**********************************************************************
+ *		PAGE DESCRIPTOR TABLE
+ *
+ **********************************************************************/
+
+/* Till here we are discussing about the static memory management model.
+ * However, the operating envoronments commonly define more CPLB
+ * descriptors to cover the entire addressable memory than will fit into
+ * the available on-chip 16 CPLB MMRs. When this happens, the below table
+ * will be used which will hold all the potentially required CPLB descriptors
+ *
+ * This is how Page descriptor Table is implemented in uClinux/Blackfin.
+ */
+.global _dpdt_table _dpdt_table:.byte4 0x00000000;
+.byte4(SDRAM_DKERNEL);		/*SDRAM_Page0 */
+.byte4 0x00400000;
+.byte4(SDRAM_DKERNEL);		/*SDRAM_Page1 */
+.byte4 0x00800000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page2 */
+.byte4 0x00C00000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page3 */
+.byte4 0x01000000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page4 */
+.byte4 0x01400000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page5 */
+.byte4 0x01800000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page6 */
+.byte4 0x01C00000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page7 */
+
+#ifndef CONFIG_EZKIT
+.byte4 0x02000000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page8 */
+.byte4 0x02400000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page9 */
+.byte4 0x02800000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page10 */
+.byte4 0x02C00000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page11 */
+.byte4 0x03000000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page12 */
+.byte4 0x03400000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page13 */
+.byte4 0x03800000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page14 */
+.byte4 0x03C00000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page15 */
+#endif
+
+#ifdef CONFIG_STAMP
+.byte4 0x04000000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x04400000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x04800000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x04C00000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x05000000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x05400000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x05800000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x05C00000;
+.byte4(SDRAM_DGENERIC);
+.byte4 0x06000000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page25 */
+.byte4 0x06400000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page26 */
+.byte4 0x06800000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page27 */
+.byte4 0x06C00000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page28 */
+.byte4 0x07000000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page29 */
+.byte4 0x07400000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page30 */
+.byte4 0x07800000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page31 */
+.byte4 0x07C00000;
+.byte4(SDRAM_DKERNEL);		/*SDRAM_Page32 */
+#endif
+
+.byte4 0x20000000;
+.byte4(SDRAM_EBIU);		/* Async Memory Bank 0 (Prim A) */
+
+#if (BFIN_CPU == ADSP_BF533)
+.byte4 0xFF800000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF801000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF802000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF803000;
+.byte4(L1_DMEMORY);
+#endif
+.byte4 0xFF804000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF805000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF806000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF807000;
+.byte4(L1_DMEMORY);
+#if (BFIN_CPU == ADSP_BF533)
+.byte4 0xFF900000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF901000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF902000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF903000;
+.byte4(L1_DMEMORY);
+#endif
+#if ((BFIN_CPU == ADSP_BF532) || (BFIN_CPU == ADSP_BF533))
+.byte4 0xFF904000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF905000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF906000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF907000;
+.byte4(L1_DMEMORY);
+#endif
+.byte4 0xFFB00000;
+.byte4(L1_DMEMORY);
+
+.byte4 0xffffffff;		/*end of section - termination */
+
+#ifdef CONFIG_CPLB_INFO
+.global _ipdt_swapcount_table;	/* swapin count first, then swapout count */
+_ipdt_swapcount_table:
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 10 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 20 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 30 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 40 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 50 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 60 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 70 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 90 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 100 */
+
+.global _dpdt_swapcount_table;	/* swapin count first, then swapout count */
+_dpdt_swapcount_table:
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 10 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 20 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 30 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 40 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 50 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 60 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 70 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 100 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 110 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 120 */
+#endif
+
+#endif	/*__ARCH_BFINNOMMU_CPLBTAB_H*/
diff --git a/include/asm-blackfin/cpu/defBF531.h b/include/asm-blackfin/arch-bf533/defBF531.h
index 6c7cd5a..6c7cd5a 100644
--- a/include/asm-blackfin/cpu/defBF531.h
+++ b/include/asm-blackfin/arch-bf533/defBF531.h
diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/arch-bf533/defBF532.h
index 26a5fe6..25a74e6 100644
--- a/include/asm-blackfin/cpu/defBF532.h
+++ b/include/asm-blackfin/arch-bf533/defBF532.h
@@ -28,7 +28,7 @@
  */
 
 /* include all Core registers and bit definitions */
-#include <asm/cpu/def_LPBlackfin.h>
+#include <asm/arch-common/def_LPBlackfin.h>
 
 /* Helper macros
  * usage:
@@ -51,7 +51,7 @@
 #define VR_CTL			0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
 #define PLL_STAT		0xFFC0000C	/* PLL Status register (16-bit) */
 #define PLL_LOCKCNT		0xFFC00010	/* PLL Lock Count register (16-bit) */
-#define	CHIPID			0xFFC00014	/* Chip ID register (32-bit)	*/
+#define	CHIPID			0xFFC00014	/* Chip ID register (32-bit)    */
 #define SWRST			0xFFC00100	/* Software Reset Register (16-bit) */
 #define SYSCR			0xFFC00104	/* System Configuration register */
 
@@ -88,7 +88,7 @@
 #define UART_LCR		0xFFC0040C	/* Line Control Register */
 #define UART_MCR		0xFFC00410	/* Modem Control Register */
 #define UART_LSR		0xFFC00414	/* Line Status Register */
-/* #define UART_MSR 0xFFC00418 */	/* Modem Status Register (UNUSED in ADSP-BF532) */
+/* #define UART_MSR 0xFFC00418 */		/* Modem Status Register (UNUSED in ADSP-BF532) */
 #define UART_SCR		0xFFC0041C	/* SCR Scratch Register */
 #define UART_GCTL		0xFFC00424	/* Global Control Register */
 
@@ -405,7 +405,7 @@
 #define BYPASS			0x00000100	/* Bypass the PLL */
 
 /* PLL_DIV Masks */
-#define SCLK_DIV(x)		(x)		/* SCLK = VCO / x */
+#define SCLK_DIV(x)		(x)	/* SCLK = VCO / x */
 
 #define CCLK_DIV1		0x00000000	/* CCLK = VCO / 1 */
 #define CCLK_DIV2		0x00000010	/* CCLK = VCO / 2 */
@@ -420,7 +420,7 @@
  */
 
 /* SIC_IAR0 Masks */
-#define P0_IVG(x)		((x)-7)		/* Peripheral #0 assigned IVG #x */
+#define P0_IVG(x)		((x)-7)	/* Peripheral #0 assigned IVG #x */
 #define P1_IVG(x)		((x)-7) << 0x4	/* Peripheral #1 assigned IVG #x */
 #define P2_IVG(x)		((x)-7) << 0x8	/* Peripheral #2 assigned IVG #x */
 #define P3_IVG(x)		((x)-7) << 0xC	/* Peripheral #3 assigned IVG #x */
@@ -430,7 +430,7 @@
 #define P7_IVG(x)		((x)-7) << 0x1C	/* Peripheral #7 assigned IVG #x */
 
 /* SIC_IAR1 Masks */
-#define P8_IVG(x)		((x)-7)		/* Peripheral #8 assigned IVG #x */
+#define P8_IVG(x)		((x)-7)	/* Peripheral #8 assigned IVG #x */
 #define P9_IVG(x)		((x)-7) << 0x4	/* Peripheral #9 assigned IVG #x */
 #define P10_IVG(x)		((x)-7) << 0x8	/* Peripheral #10 assigned IVG #x */
 #define P11_IVG(x)		((x)-7) << 0xC	/* Peripheral #11 assigned IVG #x */
@@ -440,7 +440,7 @@
 #define P15_IVG(x)		((x)-7) << 0x1C	/* Peripheral #15 assigned IVG #x */
 
 /* SIC_IAR2 Masks */
-#define P16_IVG(x)		((x)-7)		/* Peripheral #16 assigned IVG #x */
+#define P16_IVG(x)		((x)-7)	/* Peripheral #16 assigned IVG #x */
 #define P17_IVG(x)		((x)-7) << 0x4	/* Peripheral #17 assigned IVG #x */
 #define P18_IVG(x)		((x)-7) << 0x8	/* Peripheral #18 assigned IVG #x */
 #define P19_IVG(x)		((x)-7) << 0xC	/* Peripheral #19 assigned IVG #x */
@@ -486,25 +486,25 @@
 #define	RTDAY			0xFFFE0000	/* Real-Time Clock Days */
 
 /* RTC_ICTL register */
-#define	SWIE			0x0001		/* Stopwatch Interrupt Enable */
-#define	AIE			0x0002		/* Alarm Interrupt Enable */
-#define	SIE			0x0004		/* Seconds (1 Hz) Interrupt Enable */
-#define	MIE			0x0008		/* Minutes Interrupt Enable */
-#define	HIE			0x0010		/* Hours Interrupt Enable */
-#define	DIE			0x0020		/* 24 Hours (Days) Interrupt Enable */
-#define	DAIE			0x0040		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
-#define	WCIE			0x8000		/* Write Complete Interrupt Enable */
+#define	SWIE			0x0001	/* Stopwatch Interrupt Enable */
+#define	AIE			0x0002	/* Alarm Interrupt Enable */
+#define	SIE			0x0004	/* Seconds (1 Hz) Interrupt Enable */
+#define	MIE			0x0008	/* Minutes Interrupt Enable */
+#define	HIE			0x0010	/* Hours Interrupt Enable */
+#define	DIE			0x0020	/* 24 Hours (Days) Interrupt Enable */
+#define	DAIE			0x0040	/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define	WCIE			0x8000	/* Write Complete Interrupt Enable */
 
 /* RTC_ISTAT register */
-#define	SWEF			0x0001		/* Stopwatch Event Flag */
-#define	AEF			0x0002		/* Alarm Event Flag */
-#define	SEF			0x0004		/* Seconds (1 Hz) Event Flag */
-#define	MEF			0x0008		/* Minutes Event Flag */
-#define	HEF			0x0010		/* Hours Event Flag */
-#define	DEF			0x0020		/* 24 Hours (Days) Event Flag */
-#define	DAEF			0x0040		/* Day Alarm (Day, Hour, Minute, Second) Event Flag */
-#define	WPS			0x4000		/* Write Pending Status (RO) */
-#define	WCOM			0x8000		/* Write Complete */
+#define	SWEF			0x0001	/* Stopwatch Event Flag */
+#define	AEF			0x0002	/* Alarm Event Flag */
+#define	SEF			0x0004	/* Seconds (1 Hz) Event Flag */
+#define	MEF			0x0008	/* Minutes Event Flag */
+#define	HEF			0x0010	/* Hours Event Flag */
+#define	DEF			0x0020	/* 24 Hours (Days) Event Flag */
+#define	DAEF			0x0040	/* Day Alarm (Day, Hour, Minute, Second) Event Flag */
+#define	WPS			0x4000	/* Write Pending Status (RO) */
+#define	WCOM			0x8000	/* Write Complete */
 
 /* RTC_FAST Mask (RTC_PREN Mask) */
 #define ENABLE_PRESCALE		0x00000001	/* Enable prescaler so RTC runs at 1 Hz */
@@ -588,50 +588,50 @@
  * SERIAL PORT MASKS
  */
 /* SPORTx_TCR1 Masks */
-#define TSPEN    		0x0001		/* TX enable */
-#define ITCLK    		0x0002		/* Internal TX Clock Select */
-#define TDTYPE			0x000C		/* TX Data Formatting Select */
-#define TLSBIT			0x0010		/* TX Bit Order */
-#define ITFS			0x0200		/* Internal TX Frame Sync Select */
-#define TFSR			0x0400		/* TX Frame Sync Required Select */
-#define DITFS			0x0800		/* Data Independent TX Frame Sync Select */
-#define LTFS			0x1000		/* Low TX Frame Sync Select */
-#define LATFS			0x2000		/* Late TX Frame Sync Select */
-#define TCKFE			0x4000		/* TX Clock Falling Edge Select */
+#define TSPEN    		0x0001	/* TX enable */
+#define ITCLK    		0x0002	/* Internal TX Clock Select */
+#define TDTYPE			0x000C	/* TX Data Formatting Select */
+#define TLSBIT			0x0010	/* TX Bit Order */
+#define ITFS			0x0200	/* Internal TX Frame Sync Select */
+#define TFSR			0x0400	/* TX Frame Sync Required Select */
+#define DITFS			0x0800	/* Data Independent TX Frame Sync Select */
+#define LTFS			0x1000	/* Low TX Frame Sync Select */
+#define LATFS			0x2000	/* Late TX Frame Sync Select */
+#define TCKFE			0x4000	/* TX Clock Falling Edge Select */
 
 /* SPORTx_TCR2 Masks */
-#define SLEN			0x001F		/*TX Word Length */
-#define TXSE			0x0100		/*TX Secondary Enable */
-#define TSFSE			0x0200		/*TX Stereo Frame Sync Enable */
-#define TRFST			0x0400		/*TX Right-First Data Order */
+#define SLEN			0x001F	/*TX Word Length */
+#define TXSE			0x0100	/*TX Secondary Enable */
+#define TSFSE			0x0200	/*TX Stereo Frame Sync Enable */
+#define TRFST			0x0400	/*TX Right-First Data Order */
 
 /* SPORTx_RCR1 Masks */
-#define RSPEN			0x0001		/* RX enable */
-#define IRCLK			0x0002		/* Internal RX Clock Select */
-#define RDTYPE			0x000C		/* RX Data Formatting Select */
-#define RULAW			0x0008		/* u-Law enable */
-#define RALAW			0x000C		/* A-Law enable */
-#define RLSBIT			0x0010		/* RX Bit Order */
-#define IRFS			0x0200		/* Internal RX Frame Sync Select */
-#define RFSR			0x0400		/* RX Frame Sync Required Select */
-#define LRFS			0x1000		/* Low RX Frame Sync Select */
-#define LARFS			0x2000		/* Late RX Frame Sync Select */
-#define RCKFE			0x4000		/* RX Clock Falling Edge Select */
+#define RSPEN			0x0001	/* RX enable */
+#define IRCLK			0x0002	/* Internal RX Clock Select */
+#define RDTYPE			0x000C	/* RX Data Formatting Select */
+#define RULAW			0x0008	/* u-Law enable */
+#define RALAW			0x000C	/* A-Law enable */
+#define RLSBIT			0x0010	/* RX Bit Order */
+#define IRFS			0x0200	/* Internal RX Frame Sync Select */
+#define RFSR			0x0400	/* RX Frame Sync Required Select */
+#define LRFS			0x1000	/* Low RX Frame Sync Select */
+#define LARFS			0x2000	/* Late RX Frame Sync Select */
+#define RCKFE			0x4000	/* RX Clock Falling Edge Select */
 
 /* SPORTx_RCR2 Masks */
-#define SLEN			0x001F		/* RX Word Length */
-#define RXSE			0x0100		/* RX Secondary Enable */
-#define RSFSE			0x0200		/* RX Stereo Frame Sync Enable */
-#define RRFST			0x0400		/* Right-First Data Order */
+#define SLEN			0x001F	/* RX Word Length */
+#define RXSE			0x0100	/* RX Secondary Enable */
+#define RSFSE			0x0200	/* RX Stereo Frame Sync Enable */
+#define RRFST			0x0400	/* Right-First Data Order */
 
 /* SPORTx_STAT Masks */
-#define RXNE			0x0001		/* RX FIFO Not Empty Status */
-#define RUVF			0x0002		/* RX Underflow Status */
-#define ROVF			0x0004		/* RX Overflow Status */
-#define TXF			0x0008		/* TX FIFO Full Status */
-#define TUVF			0x0010		/* TX Underflow Status */
-#define TOVF			0x0020		/* TX Overflow Status */
-#define TXHRE			0x0040		/* TX Hold Register Empty */
+#define RXNE			0x0001	/* RX FIFO Not Empty Status */
+#define RUVF			0x0002	/* RX Underflow Status */
+#define ROVF			0x0004	/* RX Overflow Status */
+#define TXF			0x0008	/* TX FIFO Full Status */
+#define TUVF			0x0010	/* TX Underflow Status */
+#define TOVF			0x0020	/* TX Overflow Status */
+#define TXHRE			0x0040	/* TX Hold Register Empty */
 
 /* SPORTx_MCMC1 Masks */
 #define WSIZE			0x0000F000	/* Multichannel Window Size Field */
@@ -660,7 +660,7 @@
 #define SKIP_EN			0x00000200	/* PPI Skip Element Enable */
 #define SKIP_EO			0x00000400	/* PPI Skip Even/Odd Elements */
 #define DLENGTH			0x00003800	/* PPI Data Length */
-#define DLEN_8			0x0		/* PPI Data Length mask for DLEN=8 */
+#define DLEN_8			0x0	/* PPI Data Length mask for DLEN=8 */
 #define DLEN(x)			(((x-9) & 0x07) << 11)	/* PPI Data Length (only works for x=10-->x=16) */
 #define POL			0x0000C000	/* PPI Signal Polarities */
 
@@ -689,12 +689,12 @@
 #define NDSIZE			0x00000900	/* Next Descriptor Size */
 #define FLOW			0x00007000	/* Flow Control */
 
-#define DMAEN_P			0		/* Channel Enable */
-#define WNR_P			1		/* Channel Direction (W/R*) */
-#define DMA2D_P			4		/* 2D/1D* Mode */
-#define RESTART_P		5		/* Restart */
-#define DI_SEL_P		6		/* Data Interrupt Select */
-#define DI_EN_P			7		/* Data Interrupt Enable */
+#define DMAEN_P			0	/* Channel Enable */
+#define WNR_P			1	/* Channel Direction (W/R*) */
+#define DMA2D_P			4	/* 2D/1D* Mode */
+#define RESTART_P		5	/* Restart */
+#define DI_SEL_P		6	/* Data Interrupt Select */
+#define DI_EN_P			7	/* Data Interrupt Enable */
 
 /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
 #define DMA_DONE		0x00000001	/* DMA Done Indicator */
@@ -702,14 +702,14 @@
 #define DFETCH			0x00000004	/* Descriptor Fetch Indicator */
 #define DMA_RUN			0x00000008	/* DMA Running Indicator */
 
-#define DMA_DONE_P		0		/* DMA Done Indicator */
-#define DMA_ERR_P		1		/* DMA Error Indicator */
-#define DFETCH_P		2		/* Descriptor Fetch Indicator */
-#define DMA_RUN_P		3		/* DMA Running Indicator */
+#define DMA_DONE_P		0	/* DMA Done Indicator */
+#define DMA_ERR_P		1	/* DMA Error Indicator */
+#define DFETCH_P		2	/* Descriptor Fetch Indicator */
+#define DMA_RUN_P		3	/* DMA Running Indicator */
 
 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
 #define CTYPE			0x00000040	/* DMA Channel Type Indicator */
-#define CTYPE_P			6		/* DMA Channel Type Indicator BIT POSITION */
+#define CTYPE_P			6	/* DMA Channel Type Indicator BIT POSITION */
 #define PCAP8			0x00000080	/* DMA 8-bit Operation Indicator */
 #define PCAP16			0x00000100	/* DMA 16-bit Operation Indicator */
 #define PCAP32			0x00000200	/* DMA 32-bit Operation Indicator */
@@ -1156,4 +1156,4 @@
 #define SDEASE			0x00000010	/* SDRAM EAB sticky error status - W1C */
 #define BGSTAT			0x00000020	/* Bus granted */
 
-#endif /* _DEF_BF532_H */
+#endif	/* _DEF_BF532_H */
diff --git a/include/asm-blackfin/cpu/defBF533.h b/include/asm-blackfin/arch-bf533/defBF533.h
index 90e50af..90e50af 100644
--- a/include/asm-blackfin/cpu/defBF533.h
+++ b/include/asm-blackfin/arch-bf533/defBF533.h
diff --git a/include/asm-blackfin/cpu/defBF533_extn.h b/include/asm-blackfin/arch-bf533/defBF533_extn.h
index a9a1c7c..045e8e4 100644
--- a/include/asm-blackfin/cpu/defBF533_extn.h
+++ b/include/asm-blackfin/arch-bf533/defBF533_extn.h
@@ -19,9 +19,10 @@
 #ifndef _DEF_BF533_EXTN_H
 #define _DEF_BF533_EXTN_H
 
-#define OFFSET_( x )		((x) & 0x0000FFFF) /* define macro for offset */
+/* define macro for offset */
+#define OFFSET_( x )		((x) & 0x0000FFFF)
 /* Delay inserted for PLL transition */
-#define DELAY			0x1000
+#define PLL_DELAY			0x1000
 
 #define L1_ISRAM		0xFFA00000
 #define L1_ISRAM_END		0xFFA10000
diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/arch-bf533/irq.h
index 9c5230d..9c5230d 100644
--- a/include/asm-blackfin/cpu/bf533_irq.h
+++ b/include/asm-blackfin/arch-bf533/irq.h
diff --git a/include/asm-blackfin/arch-bf537/anomaly.h b/include/asm-blackfin/arch-bf537/anomaly.h
new file mode 100644
index 0000000..50b44da
--- /dev/null
+++ b/include/asm-blackfin/arch-bf537/anomaly.h
@@ -0,0 +1,116 @@
+/*
+ * File: include/asm-blackfin/arch-bf537/anomaly.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* This file shoule be up to date with:
+ *  - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
+ *  - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1 silicon - sorry */
+#if (defined(CONFIG_BF_REV_0_1))
+#error Kernel will not work on BF537/6/4 Version 0.1
+#endif
+
+#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
+#define ANOMALY_05000074	/* A multi issue instruction with dsp32shiftimm in
+				   slot1 and store of a P register in slot 2 is not
+				   supported */
+#define ANOMALY_05000119	/* DMA_RUN bit is not valid after a Peripheral Receive
+				   Channel DMA stops */
+#define ANOMALY_05000122	/* Rx.H can not be used to access 16-bit System MMR
+				   registers. */
+#define ANOMALY_05000166	/* PPI Data Lengths Between 8 and 16 do not zero out
+				   upper bits */
+#define ANOMALY_05000180	/* PPI_DELAY not functional in PPI modes with 0 frame
+				   syncs */
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+#define ANOMALY_05000247	/* CLKIN Buffer Output Enable Reset Behavior Is
+				   Changed */
+#endif
+#define ANOMALY_05000265	/* Sensitivity to noise with slow input edge rates on
+				   SPORT external receive and transmit clocks. */
+#define ANOMALY_05000272	/* Certain data cache write through modes fail for
+				   VDDint <=0.9V */
+#define ANOMALY_05000273	/* Writes to Synchronous SDRAM memory may be lost */
+#define ANOMALY_05000277	/* Writes to a flag data register one SCLK cycle after
+				   an edge is detected may clear interrupt */
+#define ANOMALY_05000281	/* False Hardware Error Exception when ISR context is
+				   not restored */
+#define ANOMALY_05000282	/* Memory DMA corruption with 32-bit data and traffic
+				   control */
+#define ANOMALY_05000283	/* A system MMR write is stalled indefinitely when
+				   killed in a particular stage */
+#endif
+
+#if defined(CONFIG_BF_REV_0_2)
+#define ANOMALY_05000244	/* With instruction cache enabled, a CSYNC or SSYNC or
+				   IDLE around a Change of Control causes
+				   unpredictable results */
+#define ANOMALY_05000250	/* Incorrect Bit-Shift of Data Word in Multichannel
+				   (TDM) */
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+#define ANOMALY_05000252	/* EMAC Tx DMA error after an early frame abort */
+#endif
+#define ANOMALY_05000253	/* Maximum external clock speed for Timers */
+#define ANOMALY_05000255	/* Entering Hibernate Mode with RTC Seconds event
+				   interrupt not functional */
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+#define ANOMALY_05000256	/* EMAC MDIO input latched on wrong MDC edge */
+#endif
+#define ANOMALY_05000257	/* An interrupt or exception during short Hardware
+				   loops may cause the instruction fetch unit to
+				   malfunction */
+#define ANOMALY_05000258	/* Instruction Cache is corrupted when bit 9 and 12 of
+				   the ICPLB Data registers differ */
+#define ANOMALY_05000260	/* ICPLB_STATUS MMR register may be corrupted */
+#define ANOMALY_05000261	/* DCPLB_FAULT_ADDR MMR register may be corrupted */
+#define ANOMALY_05000262	/* Stores to data cache may be lost */
+#define ANOMALY_05000263	/* Hardware loop corrupted when taking an ICPLB exception */
+#define ANOMALY_05000264	/* A Sync instruction (CSYNC, SSYNC) or an IDLE
+				   instruction will cause an infinite stall in the
+				   second to last instruction in a hardware loop */
+#define ANOMALY_05000268	/* Memory DMA error when peripheral DMA is running
+				   and non-zero DEB_TRAFFIC_PERIOD value */
+#define ANOMALY_05000270	/* High I/O activity causes the output voltage of the
+				   internal voltage regulator (VDDint) to decrease */
+#define ANOMALY_05000277	/* Writes to a flag data register one SCLK cycle after
+				   an edge is detected may clear interrupt */
+#define ANOMALY_05000278	/* Disabling Peripherals with DMA running may cause
+				   DMA system instability */
+#define ANOMALY_05000280	/* SPI Master boot mode does not work well with
+				   Atmel Dataflash devices */
+
+#endif				/* CONFIG_BF_REV_0_2 */
+
+#endif				/* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/arch-bf537/bf537_serial.h b/include/asm-blackfin/arch-bf537/bf537_serial.h
new file mode 100644
index 0000000..1610411
--- /dev/null
+++ b/include/asm-blackfin/arch-bf537/bf537_serial.h
@@ -0,0 +1,78 @@
+/*
+ * U-boot bf537_serial.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF537_SERIAL_H_
+#define _BF537_SERIAL_H_
+
+#define BYTE_REF(addr)		(*((volatile char*)addr))
+#define HALFWORD_REF(addr)	(*((volatile short*)addr))
+#define WORD_REF(addr)		(*((volatile long*)addr))
+
+#define UART_THR_LO		HALFWORD_REF(UART_THR)
+#define UART_RBR_LO		HALFWORD_REF(UART_RBR)
+#define UART_DLL_LO		HALFWORD_REF(UART_DLL)
+#define UART_IER_LO		HALFWORD_REF(UART_IER)
+#define UART_IER_ERBFI		0x01
+#define UART_IER_ETBEI		0x02
+#define UART_IER_ELSI		0x04
+#define UART_IER_EDDSI		0x08
+
+#define UART_DLH_LO		HALFWORD_REF(UART_DLH)
+#define UART_IIR_LO		HALFWORD_REF(UART_IIR)
+#define UART_IIR_NOINT		0x01
+#define UART_IIR_STATUS		0x06
+#define UART_IIR_LSR		0x06
+#define UART_IIR_RBR		0x04
+#define UART_IIR_THR		0x02
+#define UART_IIR_MSR		0x00
+
+#define UART_LCR_LO		HALFWORD_REF(UART_LCR)
+#define UART_LCR_WLS5		0
+#define UART_LCR_WLS6		0x01
+#define UART_LCR_WLS7		0x02
+#define UART_LCR_WLS8		0x03
+#define UART_LCR_STB		0x04
+#define UART_LCR_PEN		0x08
+#define UART_LCR_EPS		0x10
+#define UART_LCR_SP		0x20
+#define UART_LCR_SB		0x40
+#define UART_LCR_DLAB		0x80
+
+#define UART_MCR_LO		HALFWORD_REF(UART_MCR)
+
+#define UART_LSR_LO		HALFWORD_REF(UART_LSR)
+#define UART_LSR_DR		0x01
+#define UART_LSR_OE		0x02
+#define UART_LSR_PE		0x04
+#define UART_LSR_FE		0x08
+#define UART_LSR_BI		0x10
+#define UART_LSR_THRE		0x20
+#define UART_LSR_TEMT		0x40
+
+#define UART_MSR_LO		HALFWORD_REF(UART_MSR)
+#define UART_SCR_LO		HALFWORD_REF(UART_SCR)
+#define UART_GCTL_LO		HALFWORD_REF(UART_GCTL)
+#define UART_GCTL_UCEN		0x01
+
+#endif
diff --git a/include/asm-blackfin/arch-bf537/bf5xx_rtc.h b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h
new file mode 100644
index 0000000..0043e42
--- /dev/null
+++ b/include/asm-blackfin/arch-bf537/bf5xx_rtc.h
@@ -0,0 +1,46 @@
+/*
+ * U-boot - bf537_rtc.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF537_RTC_H_
+#define _BF537_RTC_H_
+
+void rtc_init(void);
+void wait_for_complete(void);
+void rtc_reset(void);
+
+#define MIN_TO_SECS(_x_)	(60 * _x_)
+#define HRS_TO_SECS(_x_)	(60 * 60 * _x_)
+#define DAYS_TO_SECS(_x_)	(24 * 60 * 60 * _x_)
+
+#define NUM_SECS_IN_DAY		(24 * 3600)
+#define NUM_SECS_IN_HOUR	(3600)
+#define NUM_SECS_IN_MIN		(60)
+
+/* Shift values for RTC_STAT register */
+#define DAY_BITS_OFF		17
+#define HOUR_BITS_OFF		12
+#define MIN_BITS_OFF		6
+#define SEC_BITS_OFF		0
+
+#endif
diff --git a/include/asm-blackfin/arch-bf537/cdefBF534.h b/include/asm-blackfin/arch-bf537/cdefBF534.h
new file mode 100644
index 0000000..5a89e92
--- /dev/null
+++ b/include/asm-blackfin/arch-bf537/cdefBF534.h
@@ -0,0 +1,1009 @@
+/*
+ * Copyright (C) 2005 Analog Devices Inc., All Rights Reserved.
+ *
+ ***********************************************************************************
+ *
+ * This include file contains a list of macro "defines" to enable the programmer
+ * to use symbolic names for register-access.
+ *
+ *   ----------------------------
+ *   revision 0.1
+ *   date: 2005/01/27 14:31:01;  author: joeb
+ *   Initial revision
+ */
+
+/*
+ * System MMR Register Map
+ */
+
+#ifndef _CDEF_BF534_H
+#define _CDEF_BF534_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/arch-bf537/defBF534.h>
+
+/* Include core specific register pointer definitions */
+#include <asm/arch-common/cdef_LPBlackfin.h>
+
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+
+/* Clock and System Control	(0xFFC00000 - 0xFFC000FF) */
+#define pPLL_CTL 		((volatile unsigned short *)PLL_CTL)
+#define pPLL_DIV 		((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL 		((volatile unsigned short *)VR_CTL)
+#define pPLL_STAT 		((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT 		((volatile unsigned short *)PLL_LOCKCNT)
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define pSWRST 			((volatile unsigned short *)SWRST)
+#define pSYSCR 			((volatile unsigned short *)SYSCR)
+#define	pSIC_RVECT		((void * volatile *)SIC_RVECT)
+#define pSIC_IMASK 		((volatile unsigned long  *)SIC_IMASK)
+#define pSIC_IAR0 		((volatile unsigned long  *)SIC_IAR0)
+#define pSIC_IAR1 		((volatile unsigned long  *)SIC_IAR1)
+#define pSIC_IAR2 		((volatile unsigned long  *)SIC_IAR2)
+#define pSIC_IAR3 		((volatile unsigned long  *)SIC_IAR3)
+#define pSIC_ISR 		((volatile unsigned long  *)SIC_ISR)
+#define pSIC_IWR 		((volatile unsigned long  *)SIC_IWR)
+
+/* Watchdog Timer		(0xFFC00200 - 0xFFC002FF) */
+#define pWDOG_CTL 		((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT 		((volatile unsigned long  *)WDOG_CNT)
+#define pWDOG_STAT 		((volatile unsigned long  *)WDOG_STAT)
+
+/* Real Time Clock		(0xFFC00300 - 0xFFC003FF) */
+#define pRTC_STAT 		((volatile unsigned long  *)RTC_STAT)
+#define pRTC_ICTL 		((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT 		((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT 		((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM 		((volatile unsigned long  *)RTC_ALARM)
+#define pRTC_FAST 		((volatile unsigned short *)RTC_FAST)
+#define pRTC_PREN 		((volatile unsigned short *)RTC_PREN)
+
+/* UART0 Controller		(0xFFC00400 - 0xFFC004FF) */
+#define pUART0_THR 		((volatile unsigned short *)UART0_THR)
+#define pUART0_RBR 		((volatile unsigned short *)UART0_RBR)
+#define pUART0_DLL 		((volatile unsigned short *)UART0_DLL)
+#define pUART0_IER 		((volatile unsigned short *)UART0_IER)
+#define pUART0_DLH 		((volatile unsigned short *)UART0_DLH)
+#define pUART0_IIR 		((volatile unsigned short *)UART0_IIR)
+#define pUART0_LCR 		((volatile unsigned short *)UART0_LCR)
+#define pUART0_MCR 		((volatile unsigned short *)UART0_MCR)
+#define pUART0_LSR 		((volatile unsigned short *)UART0_LSR)
+#define pUART0_MSR		((volatile unsigned short *)UART0_LSR)
+#define pUART0_SCR 		((volatile unsigned short *)UART0_SCR)
+#define pUART0_GCTL 		((volatile unsigned short *)UART0_GCTL)
+
+/* SPI Controller		(0xFFC00500 - 0xFFC005FF) */
+#define pSPI_CTL 		((volatile unsigned short *)SPI_CTL)
+#define pSPI_FLG 		((volatile unsigned short *)SPI_FLG)
+#define pSPI_STAT 		((volatile unsigned short *)SPI_STAT)
+#define pSPI_TDBR 		((volatile unsigned short *)SPI_TDBR)
+#define pSPI_RDBR 		((volatile unsigned short *)SPI_RDBR)
+#define pSPI_BAUD 		((volatile unsigned short *)SPI_BAUD)
+#define pSPI_SHADOW 		((volatile unsigned short *)SPI_SHADOW)
+
+/* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF) */
+#define pTIMER0_CONFIG 		((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER 	((volatile unsigned long  *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD 		((volatile unsigned long  *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH 		((volatile unsigned long  *)TIMER0_WIDTH)
+
+#define pTIMER1_CONFIG 		((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER 	((volatile unsigned long  *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD 		((volatile unsigned long  *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH 		((volatile unsigned long  *)TIMER1_WIDTH)
+
+#define pTIMER2_CONFIG 		((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER 	((volatile unsigned long  *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD 		((volatile unsigned long  *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH 		((volatile unsigned long  *)TIMER2_WIDTH)
+
+#define pTIMER3_CONFIG 		((volatile unsigned short *)TIMER3_CONFIG)
+#define pTIMER3_COUNTER 	((volatile unsigned long  *)TIMER3_COUNTER)
+#define pTIMER3_PERIOD 		((volatile unsigned long  *)TIMER3_PERIOD)
+#define pTIMER3_WIDTH 		((volatile unsigned long  *)TIMER3_WIDTH)
+
+#define pTIMER4_CONFIG 		((volatile unsigned short *)TIMER4_CONFIG)
+#define pTIMER4_COUNTER 	((volatile unsigned long  *)TIMER4_COUNTER)
+#define pTIMER4_PERIOD 		((volatile unsigned long  *)TIMER4_PERIOD)
+#define pTIMER4_WIDTH 		((volatile unsigned long  *)TIMER4_WIDTH)
+
+#define pTIMER5_CONFIG 		((volatile unsigned short *)TIMER5_CONFIG)
+#define pTIMER5_COUNTER 	((volatile unsigned long  *)TIMER5_COUNTER)
+#define pTIMER5_PERIOD 		((volatile unsigned long  *)TIMER5_PERIOD)
+#define pTIMER5_WIDTH 		((volatile unsigned long  *)TIMER5_WIDTH)
+
+#define pTIMER6_CONFIG 		((volatile unsigned short *)TIMER6_CONFIG)
+#define pTIMER6_COUNTER 	((volatile unsigned long  *)TIMER6_COUNTER)
+#define pTIMER6_PERIOD 		((volatile unsigned long  *)TIMER6_PERIOD)
+#define pTIMER6_WIDTH 		((volatile unsigned long  *)TIMER6_WIDTH)
+
+#define pTIMER7_CONFIG 		((volatile unsigned short *)TIMER7_CONFIG)
+#define pTIMER7_COUNTER 	((volatile unsigned long  *)TIMER7_COUNTER)
+#define pTIMER7_PERIOD 		((volatile unsigned long  *)TIMER7_PERIOD)
+#define pTIMER7_WIDTH 		((volatile unsigned long  *)TIMER7_WIDTH)
+
+#define pTIMER_ENABLE 		((volatile unsigned short *)TIMER_ENABLE)
+#define pTIMER_DISABLE 		((volatile unsigned short *)TIMER_DISABLE)
+#define pTIMER_STATUS		((volatile unsigned long  *)TIMER_STATUS)
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
+#define pPORTFIO	 	((volatile unsigned short *)PORTFIO)
+#define pPORTFIO_CLEAR	 	((volatile unsigned short *)PORTFIO_CLEAR)
+#define pPORTFIO_SET	 	((volatile unsigned short *)PORTFIO_SET)
+#define pPORTFIO_TOGGLE 	((volatile unsigned short *)PORTFIO_TOGGLE)
+#define pPORTFIO_MASKA		((volatile unsigned short *)PORTFIO_MASKA)
+#define pPORTFIO_MASKA_CLEAR	((volatile unsigned short *)PORTFIO_MASKA_CLEAR)
+#define pPORTFIO_MASKA_SET	((volatile unsigned short *)PORTFIO_MASKA_SET)
+#define pPORTFIO_MASKA_TOGGLE	((volatile unsigned short *)PORTFIO_MASKA_TOGGLE)
+#define pPORTFIO_MASKB		((volatile unsigned short *)PORTFIO_MASKB)
+#define pPORTFIO_MASKB_CLEAR	((volatile unsigned short *)PORTFIO_MASKB_CLEAR)
+#define pPORTFIO_MASKB_SET	((volatile unsigned short *)PORTFIO_MASKB_SET)
+#define pPORTFIO_MASKB_TOGGLE	((volatile unsigned short *)PORTFIO_MASKB_TOGGLE)
+#define pPORTFIO_DIR		((volatile unsigned short *)PORTFIO_DIR)
+#define pPORTFIO_POLAR		((volatile unsigned short *)PORTFIO_POLAR)
+#define pPORTFIO_EDGE		((volatile unsigned short *)PORTFIO_EDGE)
+#define pPORTFIO_BOTH		((volatile unsigned short *)PORTFIO_BOTH)
+#define pPORTFIO_INEN		((volatile unsigned short *)PORTFIO_INEN)
+
+#define pFIO_DIR		pPORTFIO_DIR
+#define pFIO_FLAG_C		pPORTFIO_CLEAR
+#define pFIO_FLAG_S		pPORTFIO_SET
+#define pFIO_INEN		pPORTFIO_INEN
+#define pFIO_FLAG_D		pPORTFIO
+
+/* SPORT0 Controller		(0xFFC00800 - 0xFFC008FF) */
+#define pSPORT0_TCR1		((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2		((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV		((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV		((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX		((volatile unsigned long  *)SPORT0_TX)
+#define pSPORT0_RX		((volatile unsigned long  *)SPORT0_RX)
+#define pSPORT0_TX32		((volatile unsigned long  *)SPORT0_TX)
+#define pSPORT0_RX32		((volatile unsigned long  *)SPORT0_RX)
+#define pSPORT0_TX16		((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16		((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1		((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2		((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV		((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV		((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT		((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL		((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1		((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2		((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0		((volatile unsigned long  *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1		((volatile unsigned long  *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2		((volatile unsigned long  *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3		((volatile unsigned long  *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0		((volatile unsigned long  *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1		((volatile unsigned long  *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2		((volatile unsigned long  *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3		((volatile unsigned long  *)SPORT0_MRCS3)
+
+/* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF) */
+#define pSPORT1_TCR1		((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2		((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV		((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV		((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX		((volatile unsigned long  *)SPORT1_TX)
+#define pSPORT1_RX		((volatile unsigned long  *)SPORT1_RX)
+#define pSPORT1_TX32		((volatile unsigned long  *)SPORT1_TX)
+#define pSPORT1_RX32		((volatile unsigned long  *)SPORT1_RX)
+#define pSPORT1_TX16		((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16		((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1		((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2		((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV		((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV		((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT		((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL		((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1		((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2		((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0		((volatile unsigned long  *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1		((volatile unsigned long  *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2		((volatile unsigned long  *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3		((volatile unsigned long  *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0		((volatile unsigned long  *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1		((volatile unsigned long  *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2		((volatile unsigned long  *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3		((volatile unsigned long  *)SPORT1_MRCS3)
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define pEBIU_AMGCTL		((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0		((volatile unsigned long  *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1		((volatile unsigned long  *)EBIU_AMBCTL1)
+#define pEBIU_SDGCTL		((volatile unsigned long  *)EBIU_SDGCTL)
+#define pEBIU_SDBCTL		((volatile unsigned short *)EBIU_SDBCTL)
+#define pEBIU_SDRRC		((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT		((volatile unsigned short *)EBIU_SDSTAT)
+
+/* DMA Traffic Control Registers */
+#define	pDMA_TCPER		((volatile unsigned short *)DMA_TCPER)
+#define	pDMA_TCCNT		((volatile unsigned short *)DMA_TCCNT)
+
+/* DMA Controller */
+#define pDMA0_CONFIG		((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_NEXT_DESC_PTR	((void * volatile *)DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR	((void * volatile *)DMA0_START_ADDR)
+#define pDMA0_X_COUNT		((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_Y_COUNT		((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_X_MODIFY		((volatile signed   short *)DMA0_X_MODIFY)
+#define pDMA0_Y_MODIFY		((volatile signed   short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR	((void * volatile *)DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR		((void * volatile *)DMA0_CURR_ADDR)
+#define pDMA0_CURR_X_COUNT	((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT	((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+#define pDMA0_IRQ_STATUS	((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP	((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+
+#define pDMA1_CONFIG		((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_NEXT_DESC_PTR	((void * volatile *)DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR	((void * volatile *)DMA1_START_ADDR)
+#define pDMA1_X_COUNT		((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_Y_COUNT		((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_X_MODIFY		((volatile signed   short *)DMA1_X_MODIFY)
+#define pDMA1_Y_MODIFY		((volatile signed   short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR	((void * volatile *)DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR		((void * volatile *)DMA1_CURR_ADDR)
+#define pDMA1_CURR_X_COUNT	((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT	((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+#define pDMA1_IRQ_STATUS	((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP	((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+
+#define pDMA2_CONFIG		((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_NEXT_DESC_PTR	((void * volatile *)DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR	((void * volatile *)DMA2_START_ADDR)
+#define pDMA2_X_COUNT		((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_Y_COUNT		((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_X_MODIFY		((volatile signed   short *)DMA2_X_MODIFY)
+#define pDMA2_Y_MODIFY		((volatile signed   short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR	((void * volatile *)DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR		((void * volatile *)DMA2_CURR_ADDR)
+#define pDMA2_CURR_X_COUNT	((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT	((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+#define pDMA2_IRQ_STATUS	((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP	((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+
+#define pDMA3_CONFIG		((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_NEXT_DESC_PTR	((void * volatile *)DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR	((void * volatile *)DMA3_START_ADDR)
+#define pDMA3_X_COUNT		((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_Y_COUNT		((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_X_MODIFY		((volatile signed   short *)DMA3_X_MODIFY)
+#define pDMA3_Y_MODIFY		((volatile signed   short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR	((void * volatile *)DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR		((void * volatile *)DMA3_CURR_ADDR)
+#define pDMA3_CURR_X_COUNT	((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT	((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+#define pDMA3_IRQ_STATUS	((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP	((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+
+#define pDMA4_CONFIG		((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_NEXT_DESC_PTR	((void * volatile *)DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR	((void * volatile *)DMA4_START_ADDR)
+#define pDMA4_X_COUNT		((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_Y_COUNT		((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_X_MODIFY		((volatile signed   short *)DMA4_X_MODIFY)
+#define pDMA4_Y_MODIFY		((volatile signed   short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR	((void * volatile *)DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR	((void * volatile *)DMA4_CURR_ADDR)
+#define pDMA4_CURR_X_COUNT	((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT	((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+#define pDMA4_IRQ_STATUS	((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP	((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+
+#define pDMA5_CONFIG		((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_NEXT_DESC_PTR	((void * volatile *)DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR	((void * volatile *)DMA5_START_ADDR)
+#define pDMA5_X_COUNT		((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_Y_COUNT		((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_X_MODIFY		((volatile signed   short *)DMA5_X_MODIFY)
+#define pDMA5_Y_MODIFY		((volatile signed   short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR	((void * volatile *)DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR		((void * volatile *)DMA5_CURR_ADDR)
+#define pDMA5_CURR_X_COUNT	((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT	((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+#define pDMA5_IRQ_STATUS	((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP	((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+
+#define pDMA6_CONFIG		((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_NEXT_DESC_PTR	((void * volatile *)DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR	((void * volatile *)DMA6_START_ADDR)
+#define pDMA6_X_COUNT		((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_Y_COUNT		((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_X_MODIFY		((volatile signed   short *)DMA6_X_MODIFY)
+#define pDMA6_Y_MODIFY		((volatile signed   short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR	((void * volatile *)DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR		((void * volatile *)DMA6_CURR_ADDR)
+#define pDMA6_CURR_X_COUNT	((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT	((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+#define pDMA6_IRQ_STATUS	((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP	((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+
+#define pDMA7_CONFIG		((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_NEXT_DESC_PTR	((void * volatile *)DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR	((void * volatile *)DMA7_START_ADDR)
+#define pDMA7_X_COUNT		((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_Y_COUNT		((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_X_MODIFY		((volatile signed   short *)DMA7_X_MODIFY)
+#define pDMA7_Y_MODIFY		((volatile signed   short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR	((void * volatile *)DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR		((void * volatile *)DMA7_CURR_ADDR)
+#define pDMA7_CURR_X_COUNT	((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT	((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+#define pDMA7_IRQ_STATUS	((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP	((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+
+#define pDMA8_CONFIG		((volatile unsigned short *)DMA8_CONFIG)
+#define pDMA8_NEXT_DESC_PTR	((void * volatile *)DMA8_NEXT_DESC_PTR)
+#define pDMA8_START_ADDR	((void * volatile *)DMA8_START_ADDR)
+#define pDMA8_X_COUNT		((volatile unsigned short *)DMA8_X_COUNT)
+#define pDMA8_Y_COUNT		((volatile unsigned short *)DMA8_Y_COUNT)
+#define pDMA8_X_MODIFY		((volatile signed   short *)DMA8_X_MODIFY)
+#define pDMA8_Y_MODIFY		((volatile signed   short *)DMA8_Y_MODIFY)
+#define pDMA8_CURR_DESC_PTR	((void * volatile *)DMA8_CURR_DESC_PTR)
+#define pDMA8_CURR_ADDR		((void * volatile *)DMA8_CURR_ADDR)
+#define pDMA8_CURR_X_COUNT	((volatile unsigned short *)DMA8_CURR_X_COUNT)
+#define pDMA8_CURR_Y_COUNT	((volatile unsigned short *)DMA8_CURR_Y_COUNT)
+#define pDMA8_IRQ_STATUS	((volatile unsigned short *)DMA8_IRQ_STATUS)
+#define pDMA8_PERIPHERAL_MAP	((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
+
+#define pDMA9_CONFIG		((volatile unsigned short *)DMA9_CONFIG)
+#define pDMA9_NEXT_DESC_PTR	((void * volatile *)DMA9_NEXT_DESC_PTR)
+#define pDMA9_START_ADDR	((void * volatile *)DMA9_START_ADDR)
+#define pDMA9_X_COUNT		((volatile unsigned short *)DMA9_X_COUNT)
+#define pDMA9_Y_COUNT		((volatile unsigned short *)DMA9_Y_COUNT)
+#define pDMA9_X_MODIFY		((volatile signed   short *)DMA9_X_MODIFY)
+#define pDMA9_Y_MODIFY		((volatile signed   short *)DMA9_Y_MODIFY)
+#define pDMA9_CURR_DESC_PTR	((void * volatile *)DMA9_CURR_DESC_PTR)
+#define pDMA9_CURR_ADDR		((void * volatile *)DMA9_CURR_ADDR)
+#define pDMA9_CURR_X_COUNT	((volatile unsigned short *)DMA9_CURR_X_COUNT)
+#define pDMA9_CURR_Y_COUNT	((volatile unsigned short *)DMA9_CURR_Y_COUNT)
+#define pDMA9_IRQ_STATUS	((volatile unsigned short *)DMA9_IRQ_STATUS)
+#define pDMA9_PERIPHERAL_MAP	((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
+
+#define pDMA10_CONFIG		((volatile unsigned short *)DMA10_CONFIG)
+#define pDMA10_NEXT_DESC_PTR	((void * volatile *)DMA10_NEXT_DESC_PTR)
+#define pDMA10_START_ADDR	((void * volatile *)DMA10_START_ADDR)
+#define pDMA10_X_COUNT		((volatile unsigned short *)DMA10_X_COUNT)
+#define pDMA10_Y_COUNT		((volatile unsigned short *)DMA10_Y_COUNT)
+#define pDMA10_X_MODIFY		((volatile signed   short *)DMA10_X_MODIFY)
+#define pDMA10_Y_MODIFY		((volatile signed   short *)DMA10_Y_MODIFY)
+#define pDMA10_CURR_DESC_PTR	((void * volatile *)DMA10_CURR_DESC_PTR)
+#define pDMA10_CURR_ADDR	((void * volatile *)DMA10_CURR_ADDR)
+#define pDMA10_CURR_X_COUNT	((volatile unsigned short *)DMA10_CURR_X_COUNT)
+#define pDMA10_CURR_Y_COUNT	((volatile unsigned short *)DMA10_CURR_Y_COUNT)
+#define pDMA10_IRQ_STATUS	((volatile unsigned short *)DMA10_IRQ_STATUS)
+#define pDMA10_PERIPHERAL_MAP	((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
+
+#define pDMA11_CONFIG		((volatile unsigned short *)DMA11_CONFIG)
+#define pDMA11_NEXT_DESC_PTR	((void * volatile *)DMA11_NEXT_DESC_PTR)
+#define pDMA11_START_ADDR	((void * volatile *)DMA11_START_ADDR)
+#define pDMA11_X_COUNT		((volatile unsigned short *)DMA11_X_COUNT)
+#define pDMA11_Y_COUNT		((volatile unsigned short *)DMA11_Y_COUNT)
+#define pDMA11_X_MODIFY		((volatile signed   short *)DMA11_X_MODIFY)
+#define pDMA11_Y_MODIFY		((volatile signed   short *)DMA11_Y_MODIFY)
+#define pDMA11_CURR_DESC_PTR	((void * volatile *)DMA11_CURR_DESC_PTR)
+#define pDMA11_CURR_ADDR	((void * volatile *)DMA11_CURR_ADDR)
+#define pDMA11_CURR_X_COUNT	((volatile unsigned short *)DMA11_CURR_X_COUNT)
+#define pDMA11_CURR_Y_COUNT	((volatile unsigned short *)DMA11_CURR_Y_COUNT)
+#define pDMA11_IRQ_STATUS	((volatile unsigned short *)DMA11_IRQ_STATUS)
+#define pDMA11_PERIPHERAL_MAP	((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
+
+#define pMDMA_D0_CONFIG		((volatile unsigned short *)MDMA_D0_CONFIG)
+#define pMDMA_D0_NEXT_DESC_PTR	((void * volatile *)MDMA_D0_NEXT_DESC_PTR)
+#define pMDMA_D0_START_ADDR	((void * volatile *)MDMA_D0_START_ADDR)
+#define pMDMA_D0_X_COUNT	((volatile unsigned short *)MDMA_D0_X_COUNT)
+#define pMDMA_D0_Y_COUNT	((volatile unsigned short *)MDMA_D0_Y_COUNT)
+#define pMDMA_D0_X_MODIFY	((volatile signed   short *)MDMA_D0_X_MODIFY)
+#define pMDMA_D0_Y_MODIFY	((volatile signed   short *)MDMA_D0_Y_MODIFY)
+#define pMDMA_D0_CURR_DESC_PTR	((void * volatile *)MDMA_D0_CURR_DESC_PTR)
+#define pMDMA_D0_CURR_ADDR	((void * volatile *)MDMA_D0_CURR_ADDR)
+#define pMDMA_D0_CURR_X_COUNT	((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
+#define pMDMA_D0_CURR_Y_COUNT	((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
+#define pMDMA_D0_IRQ_STATUS	((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
+#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
+
+#define pMDMA_S0_CONFIG		((volatile unsigned short *)MDMA_S0_CONFIG)
+#define pMDMA_S0_NEXT_DESC_PTR	((void * volatile *)MDMA_S0_NEXT_DESC_PTR)
+#define pMDMA_S0_START_ADDR	((void * volatile *)MDMA_S0_START_ADDR)
+#define pMDMA_S0_X_COUNT	((volatile unsigned short *)MDMA_S0_X_COUNT)
+#define pMDMA_S0_Y_COUNT	((volatile unsigned short *)MDMA_S0_Y_COUNT)
+#define pMDMA_S0_X_MODIFY	((volatile signed   short *)MDMA_S0_X_MODIFY)
+#define pMDMA_S0_Y_MODIFY	((volatile signed   short *)MDMA_S0_Y_MODIFY)
+#define pMDMA_S0_CURR_DESC_PTR	((void * volatile *)MDMA_S0_CURR_DESC_PTR)
+#define pMDMA_S0_CURR_ADDR	((void * volatile *)MDMA_S0_CURR_ADDR)
+#define pMDMA_S0_CURR_X_COUNT	((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
+#define pMDMA_S0_CURR_Y_COUNT	((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
+#define pMDMA_S0_IRQ_STATUS	((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
+#define pMDMA_S0_PERIPHERAL_MAP	((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
+
+#define pMDMA_D1_CONFIG		((volatile unsigned short *)MDMA_D1_CONFIG)
+#define pMDMA_D1_NEXT_DESC_PTR	((void * volatile *)MDMA_D1_NEXT_DESC_PTR)
+#define pMDMA_D1_START_ADDR	((void * volatile *)MDMA_D1_START_ADDR)
+#define pMDMA_D1_X_COUNT	((volatile unsigned short *)MDMA_D1_X_COUNT)
+#define pMDMA_D1_Y_COUNT	((volatile unsigned short *)MDMA_D1_Y_COUNT)
+#define pMDMA_D1_X_MODIFY	((volatile signed   short *)MDMA_D1_X_MODIFY)
+#define pMDMA_D1_Y_MODIFY	((volatile signed   short *)MDMA_D1_Y_MODIFY)
+#define pMDMA_D1_CURR_DESC_PTR	((void * volatile *)MDMA_D1_CURR_DESC_PTR)
+#define pMDMA_D1_CURR_ADDR	((void * volatile *)MDMA_D1_CURR_ADDR)
+#define pMDMA_D1_CURR_X_COUNT	((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
+#define pMDMA_D1_CURR_Y_COUNT	((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
+#define pMDMA_D1_IRQ_STATUS	((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
+#define pMDMA_D1_PERIPHERAL_MAP	((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
+
+#define pMDMA_S1_CONFIG		((volatile unsigned short *)MDMA_S1_CONFIG)
+#define pMDMA_S1_NEXT_DESC_PTR	((void * volatile *)MDMA_S1_NEXT_DESC_PTR)
+#define pMDMA_S1_START_ADDR	((void * volatile *)MDMA_S1_START_ADDR)
+#define pMDMA_S1_X_COUNT	((volatile unsigned short *)MDMA_S1_X_COUNT)
+#define pMDMA_S1_Y_COUNT	((volatile unsigned short *)MDMA_S1_Y_COUNT)
+#define pMDMA_S1_X_MODIFY	((volatile signed   short *)MDMA_S1_X_MODIFY)
+#define pMDMA_S1_Y_MODIFY	((volatile signed   short *)MDMA_S1_Y_MODIFY)
+#define pMDMA_S1_CURR_DESC_PTR	((void * volatile *)MDMA_S1_CURR_DESC_PTR)
+#define pMDMA_S1_CURR_ADDR	((void * volatile *)MDMA_S1_CURR_ADDR)
+#define pMDMA_S1_CURR_X_COUNT	((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
+#define pMDMA_S1_CURR_Y_COUNT	((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
+#define pMDMA_S1_IRQ_STATUS	((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
+#define pMDMA_S1_PERIPHERAL_MAP	((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
+#define pPPI_CONTROL		((volatile unsigned short *)PPI_CONTROL)
+#define pPPI_STATUS		((volatile unsigned short *)PPI_STATUS)
+#define pPPI_DELAY		((volatile unsigned short *)PPI_DELAY)
+#define pPPI_COUNT		((volatile unsigned short *)PPI_COUNT)
+#define pPPI_FRAME		((volatile unsigned short *)PPI_FRAME)
+
+/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF) */
+#define pTWI_CLKDIV		((volatile unsigned short *)TWI_CLKDIV)
+#define pTWI_CONTROL		((volatile unsigned short *)TWI_CONTROL)
+#define pTWI_SLAVE_CTL		((volatile unsigned short *)TWI_SLAVE_CTL)
+#define pTWI_SLAVE_STAT		((volatile unsigned short *)TWI_SLAVE_STAT)
+#define pTWI_SLAVE_ADDR		((volatile unsigned short *)TWI_SLAVE_ADDR)
+#define pTWI_MASTER_CTL		((volatile unsigned short *)TWI_MASTER_CTL)
+#define pTWI_MASTER_STAT	((volatile unsigned short *)TWI_MASTER_STAT)
+#define pTWI_MASTER_ADDR	((volatile unsigned short *)TWI_MASTER_ADDR)
+#define pTWI_INT_STAT		((volatile unsigned short *)TWI_INT_STAT)
+#define pTWI_INT_MASK		((volatile unsigned short *)TWI_INT_MASK)
+#define pTWI_FIFO_CTL		((volatile unsigned short *)TWI_FIFO_CTL)
+#define pTWI_FIFO_STAT		((volatile unsigned short *)TWI_FIFO_STAT)
+#define pTWI_XMT_DATA8		((volatile unsigned short *)TWI_XMT_DATA8)
+#define pTWI_XMT_DATA16		((volatile unsigned short *)TWI_XMT_DATA16)
+#define pTWI_RCV_DATA8		((volatile unsigned short *)TWI_RCV_DATA8)
+#define pTWI_RCV_DATA16		((volatile unsigned short *)TWI_RCV_DATA16)
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
+#define pPORTGIO		((volatile unsigned short *)PORTGIO)
+#define pPORTGIO_CLEAR		((volatile unsigned short *)PORTGIO_CLEAR)
+#define pPORTGIO_SET		((volatile unsigned short *)PORTGIO_SET)
+#define pPORTGIO_TOGGLE	((volatile unsigned short *)PORTGIO_TOGGLE)
+#define pPORTGIO_MASKA		((volatile unsigned short *)PORTGIO_MASKA)
+#define pPORTGIO_MASKA_CLEAR	((volatile unsigned short *)PORTGIO_MASKA_CLEAR)
+#define pPORTGIO_MASKA_SET	((volatile unsigned short *)PORTGIO_MASKA_SET)
+#define pPORTGIO_MASKA_TOGGLE	((volatile unsigned short *)PORTGIO_MASKA_TOGGLE)
+#define pPORTGIO_MASKB		((volatile unsigned short *)PORTGIO_MASKB)
+#define pPORTGIO_MASKB_CLEAR	((volatile unsigned short *)PORTGIO_MASKB_CLEAR)
+#define pPORTGIO_MASKB_SET	((volatile unsigned short *)PORTGIO_MASKB_SET)
+#define pPORTGIO_MASKB_TOGGLE	((volatile unsigned short *)PORTGIO_MASKB_TOGGLE)
+#define pPORTGIO_DIR		((volatile unsigned short *)PORTGIO_DIR)
+#define pPORTGIO_POLAR		((volatile unsigned short *)PORTGIO_POLAR)
+#define pPORTGIO_EDGE		((volatile unsigned short *)PORTGIO_EDGE)
+#define pPORTGIO_BOTH		((volatile unsigned short *)PORTGIO_BOTH)
+#define pPORTGIO_INEN		((volatile unsigned short *)PORTGIO_INEN)
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
+#define pPORTHIO		((volatile unsigned short *)PORTHIO)
+#define pPORTHIO_CLEAR		((volatile unsigned short *)PORTHIO_CLEAR)
+#define pPORTHIO_SET		((volatile unsigned short *)PORTHIO_SET)
+#define pPORTHIO_TOGGLE		((volatile unsigned short *)PORTHIO_TOGGLE)
+#define pPORTHIO_MASKA		((volatile unsigned short *)PORTHIO_MASKA)
+#define pPORTHIO_MASKA_CLEAR	((volatile unsigned short *)PORTHIO_MASKA_CLEAR)
+#define pPORTHIO_MASKA_SET	((volatile unsigned short *)PORTHIO_MASKA_SET)
+#define pPORTHIO_MASKA_TOGGLE	((volatile unsigned short *)PORTHIO_MASKA_TOGGLE)
+#define pPORTHIO_MASKB		((volatile unsigned short *)PORTHIO_MASKB)
+#define pPORTHIO_MASKB_CLEAR	((volatile unsigned short *)PORTHIO_MASKB_CLEAR)
+#define pPORTHIO_MASKB_SET	((volatile unsigned short *)PORTHIO_MASKB_SET)
+#define pPORTHIO_MASKB_TOGGLE	((volatile unsigned short *)PORTHIO_MASKB_TOGGLE)
+#define pPORTHIO_DIR		((volatile unsigned short *)PORTHIO_DIR)
+#define pPORTHIO_POLAR		((volatile unsigned short *)PORTHIO_POLAR)
+#define pPORTHIO_EDGE		((volatile unsigned short *)PORTHIO_EDGE)
+#define pPORTHIO_BOTH		((volatile unsigned short *)PORTHIO_BOTH)
+#define pPORTHIO_INEN		((volatile unsigned short *)PORTHIO_INEN)
+
+/* UART1 Controller		(0xFFC02000 - 0xFFC020FF) */
+#define pUART1_THR		((volatile unsigned short *)UART1_THR)
+#define pUART1_RBR		((volatile unsigned short *)UART1_RBR)
+#define pUART1_DLL		((volatile unsigned short *)UART1_DLL)
+#define pUART1_IER		((volatile unsigned short *)UART1_IER)
+#define pUART1_DLH		((volatile unsigned short *)UART1_DLH)
+#define pUART1_IIR		((volatile unsigned short *)UART1_IIR)
+#define pUART1_LCR		((volatile unsigned short *)UART1_LCR)
+#define pUART1_MCR		((volatile unsigned short *)UART1_MCR)
+#define pUART1_LSR		((volatile unsigned short *)UART1_LSR)
+#define pUART1_MSR		((volatile unsigned short *)UART1_LSR)
+#define pUART1_SCR		((volatile unsigned short *)UART1_SCR)
+#define pUART1_GCTL		((volatile unsigned short *)UART1_GCTL)
+
+/* default UART controller */
+#if (CONFIG_UART_CONSOLE==1)
+
+#define pUART_THR		pUART1_THR
+#define pUART_RBR		pUART1_RBR
+#define pUART_DLL		pUART1_DLL
+#define pUART_IER		pUART1_IER
+#define pUART_DLH		pUART1_DLH
+#define pUART_IIR		pUART1_IIR
+#define pUART_LCR		pUART1_LCR
+#define pUART_MCR		pUART1_MCR
+#define pUART_LSR		pUART1_LSR
+#define pUART_MSR		pUART1_MSR
+#define pUART_SCR		pUART1_SCR
+#define pUART_GCTL		pUART1_GCTL
+
+#else
+
+#define pUART_THR		pUART0_THR
+#define pUART_RBR		pUART0_RBR
+#define pUART_DLL		pUART0_DLL
+#define pUART_IER		pUART0_IER
+#define pUART_DLH		pUART0_DLH
+#define pUART_IIR		pUART0_IIR
+#define pUART_LCR		pUART0_LCR
+#define pUART_MCR		pUART0_MCR
+#define pUART_LSR		pUART0_LSR
+#define pUART_MSR		pUART0_MSR
+#define pUART_SCR		pUART0_SCR
+#define pUART_GCTL		pUART0_GCTL
+
+#endif
+
+/* CAN Controller		(0xFFC02A00 - 0xFFC02FFF) */
+/* For Mailboxes 0-15 */
+#define pCAN_MC1		((volatile unsigned short *)CAN_MC1)
+#define pCAN_MD1		((volatile unsigned short *)CAN_MD1)
+#define pCAN_TRS1		((volatile unsigned short *)CAN_TRS1)
+#define pCAN_TRR1		((volatile unsigned short *)CAN_TRR1)
+#define pCAN_TA1		((volatile unsigned short *)CAN_TA1)
+#define pCAN_AA1		((volatile unsigned short *)CAN_AA1)
+#define pCAN_RMP1		((volatile unsigned short *)CAN_RMP1)
+#define pCAN_RML1		((volatile unsigned short *)CAN_RML1)
+#define pCAN_MBTIF1		((volatile unsigned short *)CAN_MBTIF1)
+#define pCAN_MBRIF1		((volatile unsigned short *)CAN_MBRIF1)
+#define pCAN_MBIM1		((volatile unsigned short *)CAN_MBIM1)
+#define pCAN_RFH1		((volatile unsigned short *)CAN_RFH1)
+#define pCAN_OPSS1		((volatile unsigned short *)CAN_OPSS1)
+
+/* For Mailboxes 16-31 */
+#define pCAN_MC2		((volatile unsigned short *)CAN_MC2)
+#define pCAN_MD2		((volatile unsigned short *)CAN_MD2)
+#define pCAN_TRS2		((volatile unsigned short *)CAN_TRS2)
+#define pCAN_TRR2		((volatile unsigned short *)CAN_TRR2)
+#define pCAN_TA2		((volatile unsigned short *)CAN_TA2)
+#define pCAN_AA2		((volatile unsigned short *)CAN_AA2)
+#define pCAN_RMP2		((volatile unsigned short *)CAN_RMP2)
+#define pCAN_RML2		((volatile unsigned short *)CAN_RML2)
+#define pCAN_MBTIF2		((volatile unsigned short *)CAN_MBTIF2)
+#define pCAN_MBRIF2		((volatile unsigned short *)CAN_MBRIF2)
+#define pCAN_MBIM2		((volatile unsigned short *)CAN_MBIM2)
+#define pCAN_RFH2		((volatile unsigned short *)CAN_RFH2)
+#define pCAN_OPSS2		((volatile unsigned short *)CAN_OPSS2)
+
+#define pCAN_CLOCK		((volatile unsigned short *)CAN_CLOCK)
+#define pCAN_TIMING		((volatile unsigned short *)CAN_TIMING)
+#define pCAN_DEBUG		((volatile unsigned short *)CAN_DEBUG)
+#define pCAN_STATUS		((volatile unsigned short *)CAN_STATUS)
+#define pCAN_CEC		((volatile unsigned short *)CAN_CEC)
+#define pCAN_GIS		((volatile unsigned short *)CAN_GIS)
+#define pCAN_GIM		((volatile unsigned short *)CAN_GIM)
+#define pCAN_GIF		((volatile unsigned short *)CAN_GIF)
+#define pCAN_CONTROL		((volatile unsigned short *)CAN_CONTROL)
+#define pCAN_INTR		((volatile unsigned short *)CAN_INTR)
+#define pCAN_SFCMVER		((volatile unsigned short *)CAN_SFCMVER)
+#define pCAN_MBTD		((volatile unsigned short *)CAN_MBTD)
+#define pCAN_EWR		((volatile unsigned short *)CAN_EWR)
+#define pCAN_ESR		((volatile unsigned short *)CAN_ESR)
+#define pCAN_UCREG		((volatile unsigned short *)CAN_UCREG)
+#define pCAN_UCCNT		((volatile unsigned short *)CAN_UCCNT)
+#define pCAN_UCRC		((volatile unsigned short *)CAN_UCRC)
+#define pCAN_UCCNF		((volatile unsigned short *)CAN_UCCNF)
+#define pCAN_SFCMVER2		((volatile unsigned short *)CAN_SFCMVER2)
+
+/* Mailbox Acceptance Masks */
+#define pCAN_AM00L		((volatile unsigned short *)CAN_AM00L)
+#define pCAN_AM00H		((volatile unsigned short *)CAN_AM00H)
+#define pCAN_AM01L		((volatile unsigned short *)CAN_AM01L)
+#define pCAN_AM01H		((volatile unsigned short *)CAN_AM01H)
+#define pCAN_AM02L		((volatile unsigned short *)CAN_AM02L)
+#define pCAN_AM02H		((volatile unsigned short *)CAN_AM02H)
+#define pCAN_AM03L		((volatile unsigned short *)CAN_AM03L)
+#define pCAN_AM03H		((volatile unsigned short *)CAN_AM03H)
+#define pCAN_AM04L		((volatile unsigned short *)CAN_AM04L)
+#define pCAN_AM04H		((volatile unsigned short *)CAN_AM04H)
+#define pCAN_AM05L		((volatile unsigned short *)CAN_AM05L)
+#define pCAN_AM05H		((volatile unsigned short *)CAN_AM05H)
+#define pCAN_AM06L		((volatile unsigned short *)CAN_AM06L)
+#define pCAN_AM06H		((volatile unsigned short *)CAN_AM06H)
+#define pCAN_AM07L		((volatile unsigned short *)CAN_AM07L)
+#define pCAN_AM07H		((volatile unsigned short *)CAN_AM07H)
+#define pCAN_AM08L		((volatile unsigned short *)CAN_AM08L)
+#define pCAN_AM08H		((volatile unsigned short *)CAN_AM08H)
+#define pCAN_AM09L		((volatile unsigned short *)CAN_AM09L)
+#define pCAN_AM09H		((volatile unsigned short *)CAN_AM09H)
+#define pCAN_AM10L		((volatile unsigned short *)CAN_AM10L)
+#define pCAN_AM10H		((volatile unsigned short *)CAN_AM10H)
+#define pCAN_AM11L		((volatile unsigned short *)CAN_AM11L)
+#define pCAN_AM11H		((volatile unsigned short *)CAN_AM11H)
+#define pCAN_AM12L		((volatile unsigned short *)CAN_AM12L)
+#define pCAN_AM12H		((volatile unsigned short *)CAN_AM12H)
+#define pCAN_AM13L		((volatile unsigned short *)CAN_AM13L)
+#define pCAN_AM13H		((volatile unsigned short *)CAN_AM13H)
+#define pCAN_AM14L		((volatile unsigned short *)CAN_AM14L)
+#define pCAN_AM14H		((volatile unsigned short *)CAN_AM14H)
+#define pCAN_AM15L		((volatile unsigned short *)CAN_AM15L)
+#define pCAN_AM15H		((volatile unsigned short *)CAN_AM15H)
+
+#define pCAN_AM16L		((volatile unsigned short *)CAN_AM16L)
+#define pCAN_AM16H		((volatile unsigned short *)CAN_AM16H)
+#define pCAN_AM17L		((volatile unsigned short *)CAN_AM17L)
+#define pCAN_AM17H		((volatile unsigned short *)CAN_AM17H)
+#define pCAN_AM18L		((volatile unsigned short *)CAN_AM18L)
+#define pCAN_AM18H		((volatile unsigned short *)CAN_AM18H)
+#define pCAN_AM19L		((volatile unsigned short *)CAN_AM19L)
+#define pCAN_AM19H		((volatile unsigned short *)CAN_AM19H)
+#define pCAN_AM20L		((volatile unsigned short *)CAN_AM20L)
+#define pCAN_AM20H		((volatile unsigned short *)CAN_AM20H)
+#define pCAN_AM21L		((volatile unsigned short *)CAN_AM21L)
+#define pCAN_AM21H		((volatile unsigned short *)CAN_AM21H)
+#define pCAN_AM22L		((volatile unsigned short *)CAN_AM22L)
+#define pCAN_AM22H		((volatile unsigned short *)CAN_AM22H)
+#define pCAN_AM23L		((volatile unsigned short *)CAN_AM23L)
+#define pCAN_AM23H		((volatile unsigned short *)CAN_AM23H)
+#define pCAN_AM24L		((volatile unsigned short *)CAN_AM24L)
+#define pCAN_AM24H		((volatile unsigned short *)CAN_AM24H)
+#define pCAN_AM25L		((volatile unsigned short *)CAN_AM25L)
+#define pCAN_AM25H		((volatile unsigned short *)CAN_AM25H)
+#define pCAN_AM26L		((volatile unsigned short *)CAN_AM26L)
+#define pCAN_AM26H		((volatile unsigned short *)CAN_AM26H)
+#define pCAN_AM27L		((volatile unsigned short *)CAN_AM27L)
+#define pCAN_AM27H		((volatile unsigned short *)CAN_AM27H)
+#define pCAN_AM28L		((volatile unsigned short *)CAN_AM28L)
+#define pCAN_AM28H		((volatile unsigned short *)CAN_AM28H)
+#define pCAN_AM29L		((volatile unsigned short *)CAN_AM29L)
+#define pCAN_AM29H		((volatile unsigned short *)CAN_AM29H)
+#define pCAN_AM30L		((volatile unsigned short *)CAN_AM30L)
+#define pCAN_AM30H		((volatile unsigned short *)CAN_AM30H)
+#define pCAN_AM31L		((volatile unsigned short *)CAN_AM31L)
+#define pCAN_AM31H		((volatile unsigned short *)CAN_AM31H)
+
+/* CAN Acceptance Mask Area Macros */
+#define pCAN_AM_L(x)		((volatile unsigned short *)CAN_AM_L(x))
+#define pCAN_AM_H(x)		((volatile unsigned short *)CAN_AM_H(x))
+
+/* Mailbox Registers */
+#define pCAN_MB00_ID1		((volatile unsigned short *)CAN_MB00_ID1)
+#define pCAN_MB00_ID0		((volatile unsigned short *)CAN_MB00_ID0)
+#define pCAN_MB00_TIMESTAMP	((volatile unsigned short *)CAN_MB00_TIMESTAMP)
+#define pCAN_MB00_LENGTH	((volatile unsigned short *)CAN_MB00_LENGTH)
+#define pCAN_MB00_DATA3		((volatile unsigned short *)CAN_MB00_DATA3)
+#define pCAN_MB00_DATA2		((volatile unsigned short *)CAN_MB00_DATA2)
+#define pCAN_MB00_DATA1		((volatile unsigned short *)CAN_MB00_DATA1)
+#define pCAN_MB00_DATA0		((volatile unsigned short *)CAN_MB00_DATA0)
+
+#define pCAN_MB01_ID1		((volatile unsigned short *)CAN_MB01_ID1)
+#define pCAN_MB01_ID0		((volatile unsigned short *)CAN_MB01_ID0)
+#define pCAN_MB01_TIMESTAMP	((volatile unsigned short *)CAN_MB01_TIMESTAMP)
+#define pCAN_MB01_LENGTH	((volatile unsigned short *)CAN_MB01_LENGTH)
+#define pCAN_MB01_DATA3		((volatile unsigned short *)CAN_MB01_DATA3)
+#define pCAN_MB01_DATA2		((volatile unsigned short *)CAN_MB01_DATA2)
+#define pCAN_MB01_DATA1		((volatile unsigned short *)CAN_MB01_DATA1)
+#define pCAN_MB01_DATA0		((volatile unsigned short *)CAN_MB01_DATA0)
+
+#define pCAN_MB02_ID1		((volatile unsigned short *)CAN_MB02_ID1)
+#define pCAN_MB02_ID0		((volatile unsigned short *)CAN_MB02_ID0)
+#define pCAN_MB02_TIMESTAMP	((volatile unsigned short *)CAN_MB02_TIMESTAMP)
+#define pCAN_MB02_LENGTH	((volatile unsigned short *)CAN_MB02_LENGTH)
+#define pCAN_MB02_DATA3		((volatile unsigned short *)CAN_MB02_DATA3)
+#define pCAN_MB02_DATA2		((volatile unsigned short *)CAN_MB02_DATA2)
+#define pCAN_MB02_DATA1		((volatile unsigned short *)CAN_MB02_DATA1)
+#define pCAN_MB02_DATA0		((volatile unsigned short *)CAN_MB02_DATA0)
+
+#define pCAN_MB03_ID1		((volatile unsigned short *)CAN_MB03_ID1)
+#define pCAN_MB03_ID0		((volatile unsigned short *)CAN_MB03_ID0)
+#define pCAN_MB03_TIMESTAMP	((volatile unsigned short *)CAN_MB03_TIMESTAMP)
+#define pCAN_MB03_LENGTH	((volatile unsigned short *)CAN_MB03_LENGTH)
+#define pCAN_MB03_DATA3		((volatile unsigned short *)CAN_MB03_DATA3)
+#define pCAN_MB03_DATA2		((volatile unsigned short *)CAN_MB03_DATA2)
+#define pCAN_MB03_DATA1		((volatile unsigned short *)CAN_MB03_DATA1)
+#define pCAN_MB03_DATA0		((volatile unsigned short *)CAN_MB03_DATA0)
+
+#define pCAN_MB04_ID1		((volatile unsigned short *)CAN_MB04_ID1)
+#define pCAN_MB04_ID0		((volatile unsigned short *)CAN_MB04_ID0)
+#define pCAN_MB04_TIMESTAMP	((volatile unsigned short *)CAN_MB04_TIMESTAMP)
+#define pCAN_MB04_LENGTH	((volatile unsigned short *)CAN_MB04_LENGTH)
+#define pCAN_MB04_DATA3		((volatile unsigned short *)CAN_MB04_DATA3)
+#define pCAN_MB04_DATA2		((volatile unsigned short *)CAN_MB04_DATA2)
+#define pCAN_MB04_DATA1		((volatile unsigned short *)CAN_MB04_DATA1)
+#define pCAN_MB04_DATA0		((volatile unsigned short *)CAN_MB04_DATA0)
+
+#define pCAN_MB05_ID1		((volatile unsigned short *)CAN_MB05_ID1)
+#define pCAN_MB05_ID0		((volatile unsigned short *)CAN_MB05_ID0)
+#define pCAN_MB05_TIMESTAMP	((volatile unsigned short *)CAN_MB05_TIMESTAMP)
+#define pCAN_MB05_LENGTH	((volatile unsigned short *)CAN_MB05_LENGTH)
+#define pCAN_MB05_DATA3		((volatile unsigned short *)CAN_MB05_DATA3)
+#define pCAN_MB05_DATA2		((volatile unsigned short *)CAN_MB05_DATA2)
+#define pCAN_MB05_DATA1		((volatile unsigned short *)CAN_MB05_DATA1)
+#define pCAN_MB05_DATA0		((volatile unsigned short *)CAN_MB05_DATA0)
+
+#define pCAN_MB06_ID1		((volatile unsigned short *)CAN_MB06_ID1)
+#define pCAN_MB06_ID0		((volatile unsigned short *)CAN_MB06_ID0)
+#define pCAN_MB06_TIMESTAMP	((volatile unsigned short *)CAN_MB06_TIMESTAMP)
+#define pCAN_MB06_LENGTH	((volatile unsigned short *)CAN_MB06_LENGTH)
+#define pCAN_MB06_DATA3		((volatile unsigned short *)CAN_MB06_DATA3)
+#define pCAN_MB06_DATA2		((volatile unsigned short *)CAN_MB06_DATA2)
+#define pCAN_MB06_DATA1		((volatile unsigned short *)CAN_MB06_DATA1)
+#define pCAN_MB06_DATA0		((volatile unsigned short *)CAN_MB06_DATA0)
+
+#define pCAN_MB07_ID1		((volatile unsigned short *)CAN_MB07_ID1)
+#define pCAN_MB07_ID0		((volatile unsigned short *)CAN_MB07_ID0)
+#define pCAN_MB07_TIMESTAMP	((volatile unsigned short *)CAN_MB07_TIMESTAMP)
+#define pCAN_MB07_LENGTH	((volatile unsigned short *)CAN_MB07_LENGTH)
+#define pCAN_MB07_DATA3		((volatile unsigned short *)CAN_MB07_DATA3)
+#define pCAN_MB07_DATA2		((volatile unsigned short *)CAN_MB07_DATA2)
+#define pCAN_MB07_DATA1		((volatile unsigned short *)CAN_MB07_DATA1)
+#define pCAN_MB07_DATA0		((volatile unsigned short *)CAN_MB07_DATA0)
+
+#define pCAN_MB08_ID1		((volatile unsigned short *)CAN_MB08_ID1)
+#define pCAN_MB08_ID0		((volatile unsigned short *)CAN_MB08_ID0)
+#define pCAN_MB08_TIMESTAMP	((volatile unsigned short *)CAN_MB08_TIMESTAMP)
+#define pCAN_MB08_LENGTH	((volatile unsigned short *)CAN_MB08_LENGTH)
+#define pCAN_MB08_DATA3		((volatile unsigned short *)CAN_MB08_DATA3)
+#define pCAN_MB08_DATA2		((volatile unsigned short *)CAN_MB08_DATA2)
+#define pCAN_MB08_DATA1		((volatile unsigned short *)CAN_MB08_DATA1)
+#define pCAN_MB08_DATA0		((volatile unsigned short *)CAN_MB08_DATA0)
+
+#define pCAN_MB09_ID1		((volatile unsigned short *)CAN_MB09_ID1)
+#define pCAN_MB09_ID0		((volatile unsigned short *)CAN_MB09_ID0)
+#define pCAN_MB09_TIMESTAMP	((volatile unsigned short *)CAN_MB09_TIMESTAMP)
+#define pCAN_MB09_LENGTH	((volatile unsigned short *)CAN_MB09_LENGTH)
+#define pCAN_MB09_DATA3		((volatile unsigned short *)CAN_MB09_DATA3)
+#define pCAN_MB09_DATA2		((volatile unsigned short *)CAN_MB09_DATA2)
+#define pCAN_MB09_DATA1		((volatile unsigned short *)CAN_MB09_DATA1)
+#define pCAN_MB09_DATA0		((volatile unsigned short *)CAN_MB09_DATA0)
+
+#define pCAN_MB10_ID1		((volatile unsigned short *)CAN_MB10_ID1)
+#define pCAN_MB10_ID0		((volatile unsigned short *)CAN_MB10_ID0)
+#define pCAN_MB10_TIMESTAMP	((volatile unsigned short *)CAN_MB10_TIMESTAMP)
+#define pCAN_MB10_LENGTH	((volatile unsigned short *)CAN_MB10_LENGTH)
+#define pCAN_MB10_DATA3		((volatile unsigned short *)CAN_MB10_DATA3)
+#define pCAN_MB10_DATA2		((volatile unsigned short *)CAN_MB10_DATA2)
+#define pCAN_MB10_DATA1		((volatile unsigned short *)CAN_MB10_DATA1)
+#define pCAN_MB10_DATA0		((volatile unsigned short *)CAN_MB10_DATA0)
+
+#define pCAN_MB11_ID1		((volatile unsigned short *)CAN_MB11_ID1)
+#define pCAN_MB11_ID0		((volatile unsigned short *)CAN_MB11_ID0)
+#define pCAN_MB11_TIMESTAMP	((volatile unsigned short *)CAN_MB11_TIMESTAMP)
+#define pCAN_MB11_LENGTH	((volatile unsigned short *)CAN_MB11_LENGTH)
+#define pCAN_MB11_DATA3		((volatile unsigned short *)CAN_MB11_DATA3)
+#define pCAN_MB11_DATA2		((volatile unsigned short *)CAN_MB11_DATA2)
+#define pCAN_MB11_DATA1		((volatile unsigned short *)CAN_MB11_DATA1)
+#define pCAN_MB11_DATA0		((volatile unsigned short *)CAN_MB11_DATA0)
+
+#define pCAN_MB12_ID1		((volatile unsigned short *)CAN_MB12_ID1)
+#define pCAN_MB12_ID0		((volatile unsigned short *)CAN_MB12_ID0)
+#define pCAN_MB12_TIMESTAMP	((volatile unsigned short *)CAN_MB12_TIMESTAMP)
+#define pCAN_MB12_LENGTH	((volatile unsigned short *)CAN_MB12_LENGTH)
+#define pCAN_MB12_DATA3		((volatile unsigned short *)CAN_MB12_DATA3)
+#define pCAN_MB12_DATA2		((volatile unsigned short *)CAN_MB12_DATA2)
+#define pCAN_MB12_DATA1		((volatile unsigned short *)CAN_MB12_DATA1)
+#define pCAN_MB12_DATA0		((volatile unsigned short *)CAN_MB12_DATA0)
+
+#define pCAN_MB13_ID1		((volatile unsigned short *)CAN_MB13_ID1)
+#define pCAN_MB13_ID0		((volatile unsigned short *)CAN_MB13_ID0)
+#define pCAN_MB13_TIMESTAMP	((volatile unsigned short *)CAN_MB13_TIMESTAMP)
+#define pCAN_MB13_LENGTH	((volatile unsigned short *)CAN_MB13_LENGTH)
+#define pCAN_MB13_DATA3		((volatile unsigned short *)CAN_MB13_DATA3)
+#define pCAN_MB13_DATA2		((volatile unsigned short *)CAN_MB13_DATA2)
+#define pCAN_MB13_DATA1		((volatile unsigned short *)CAN_MB13_DATA1)
+#define pCAN_MB13_DATA0		((volatile unsigned short *)CAN_MB13_DATA0)
+
+#define pCAN_MB14_ID1		((volatile unsigned short *)CAN_MB14_ID1)
+#define pCAN_MB14_ID0		((volatile unsigned short *)CAN_MB14_ID0)
+#define pCAN_MB14_TIMESTAMP	((volatile unsigned short *)CAN_MB14_TIMESTAMP)
+#define pCAN_MB14_LENGTH	((volatile unsigned short *)CAN_MB14_LENGTH)
+#define pCAN_MB14_DATA3		((volatile unsigned short *)CAN_MB14_DATA3)
+#define pCAN_MB14_DATA2		((volatile unsigned short *)CAN_MB14_DATA2)
+#define pCAN_MB14_DATA1		((volatile unsigned short *)CAN_MB14_DATA1)
+#define pCAN_MB14_DATA0		((volatile unsigned short *)CAN_MB14_DATA0)
+
+#define pCAN_MB15_ID1		((volatile unsigned short *)CAN_MB15_ID1)
+#define pCAN_MB15_ID0		((volatile unsigned short *)CAN_MB15_ID0)
+#define pCAN_MB15_TIMESTAMP	((volatile unsigned short *)CAN_MB15_TIMESTAMP)
+#define pCAN_MB15_LENGTH	((volatile unsigned short *)CAN_MB15_LENGTH)
+#define pCAN_MB15_DATA3		((volatile unsigned short *)CAN_MB15_DATA3)
+#define pCAN_MB15_DATA2		((volatile unsigned short *)CAN_MB15_DATA2)
+#define pCAN_MB15_DATA1		((volatile unsigned short *)CAN_MB15_DATA1)
+#define pCAN_MB15_DATA0		((volatile unsigned short *)CAN_MB15_DATA0)
+
+#define pCAN_MB16_ID1		((volatile unsigned short *)CAN_MB16_ID1)
+#define pCAN_MB16_ID0		((volatile unsigned short *)CAN_MB16_ID0)
+#define pCAN_MB16_TIMESTAMP	((volatile unsigned short *)CAN_MB16_TIMESTAMP)
+#define pCAN_MB16_LENGTH	((volatile unsigned short *)CAN_MB16_LENGTH)
+#define pCAN_MB16_DATA3		((volatile unsigned short *)CAN_MB16_DATA3)
+#define pCAN_MB16_DATA2		((volatile unsigned short *)CAN_MB16_DATA2)
+#define pCAN_MB16_DATA1		((volatile unsigned short *)CAN_MB16_DATA1)
+#define pCAN_MB16_DATA0		((volatile unsigned short *)CAN_MB16_DATA0)
+
+#define pCAN_MB17_ID1		((volatile unsigned short *)CAN_MB17_ID1)
+#define pCAN_MB17_ID0		((volatile unsigned short *)CAN_MB17_ID0)
+#define pCAN_MB17_TIMESTAMP	((volatile unsigned short *)CAN_MB17_TIMESTAMP)
+#define pCAN_MB17_LENGTH	((volatile unsigned short *)CAN_MB17_LENGTH)
+#define pCAN_MB17_DATA3		((volatile unsigned short *)CAN_MB17_DATA3)
+#define pCAN_MB17_DATA2		((volatile unsigned short *)CAN_MB17_DATA2)
+#define pCAN_MB17_DATA1		((volatile unsigned short *)CAN_MB17_DATA1)
+#define pCAN_MB17_DATA0		((volatile unsigned short *)CAN_MB17_DATA0)
+
+#define pCAN_MB18_ID1		((volatile unsigned short *)CAN_MB18_ID1)
+#define pCAN_MB18_ID0		((volatile unsigned short *)CAN_MB18_ID0)
+#define pCAN_MB18_TIMESTAMP	((volatile unsigned short *)CAN_MB18_TIMESTAMP)
+#define pCAN_MB18_LENGTH	((volatile unsigned short *)CAN_MB18_LENGTH)
+#define pCAN_MB18_DATA3		((volatile unsigned short *)CAN_MB18_DATA3)
+#define pCAN_MB18_DATA2		((volatile unsigned short *)CAN_MB18_DATA2)
+#define pCAN_MB18_DATA1		((volatile unsigned short *)CAN_MB18_DATA1)
+#define pCAN_MB18_DATA0		((volatile unsigned short *)CAN_MB18_DATA0)
+
+#define pCAN_MB19_ID1		((volatile unsigned short *)CAN_MB19_ID1)
+#define pCAN_MB19_ID0		((volatile unsigned short *)CAN_MB19_ID0)
+#define pCAN_MB19_TIMESTAMP	((volatile unsigned short *)CAN_MB19_TIMESTAMP)
+#define pCAN_MB19_LENGTH	((volatile unsigned short *)CAN_MB19_LENGTH)
+#define pCAN_MB19_DATA3		((volatile unsigned short *)CAN_MB19_DATA3)
+#define pCAN_MB19_DATA2		((volatile unsigned short *)CAN_MB19_DATA2)
+#define pCAN_MB19_DATA1		((volatile unsigned short *)CAN_MB19_DATA1)
+#define pCAN_MB19_DATA0		((volatile unsigned short *)CAN_MB19_DATA0)
+
+#define pCAN_MB20_ID1		((volatile unsigned short *)CAN_MB20_ID1)
+#define pCAN_MB20_ID0		((volatile unsigned short *)CAN_MB20_ID0)
+#define pCAN_MB20_TIMESTAMP	((volatile unsigned short *)CAN_MB20_TIMESTAMP)
+#define pCAN_MB20_LENGTH	((volatile unsigned short *)CAN_MB20_LENGTH)
+#define pCAN_MB20_DATA3		((volatile unsigned short *)CAN_MB20_DATA3)
+#define pCAN_MB20_DATA2		((volatile unsigned short *)CAN_MB20_DATA2)
+#define pCAN_MB20_DATA1		((volatile unsigned short *)CAN_MB20_DATA1)
+#define pCAN_MB20_DATA0		((volatile unsigned short *)CAN_MB20_DATA0)
+
+#define pCAN_MB21_ID1		((volatile unsigned short *)CAN_MB21_ID1)
+#define pCAN_MB21_ID0		((volatile unsigned short *)CAN_MB21_ID0)
+#define pCAN_MB21_TIMESTAMP	((volatile unsigned short *)CAN_MB21_TIMESTAMP)
+#define pCAN_MB21_LENGTH	((volatile unsigned short *)CAN_MB21_LENGTH)
+#define pCAN_MB21_DATA3		((volatile unsigned short *)CAN_MB21_DATA3)
+#define pCAN_MB21_DATA2		((volatile unsigned short *)CAN_MB21_DATA2)
+#define pCAN_MB21_DATA1		((volatile unsigned short *)CAN_MB21_DATA1)
+#define pCAN_MB21_DATA0		((volatile unsigned short *)CAN_MB21_DATA0)
+
+#define pCAN_MB22_ID1		((volatile unsigned short *)CAN_MB22_ID1)
+#define pCAN_MB22_ID0		((volatile unsigned short *)CAN_MB22_ID0)
+#define pCAN_MB22_TIMESTAMP	((volatile unsigned short *)CAN_MB22_TIMESTAMP)
+#define pCAN_MB22_LENGTH	((volatile unsigned short *)CAN_MB22_LENGTH)
+#define pCAN_MB22_DATA3		((volatile unsigned short *)CAN_MB22_DATA3)
+#define pCAN_MB22_DATA2		((volatile unsigned short *)CAN_MB22_DATA2)
+#define pCAN_MB22_DATA1		((volatile unsigned short *)CAN_MB22_DATA1)
+#define pCAN_MB22_DATA0		((volatile unsigned short *)CAN_MB22_DATA0)
+
+#define pCAN_MB23_ID1		((volatile unsigned short *)CAN_MB23_ID1)
+#define pCAN_MB23_ID0		((volatile unsigned short *)CAN_MB23_ID0)
+#define pCAN_MB23_TIMESTAMP	((volatile unsigned short *)CAN_MB23_TIMESTAMP)
+#define pCAN_MB23_LENGTH	((volatile unsigned short *)CAN_MB23_LENGTH)
+#define pCAN_MB23_DATA3		((volatile unsigned short *)CAN_MB23_DATA3)
+#define pCAN_MB23_DATA2		((volatile unsigned short *)CAN_MB23_DATA2)
+#define pCAN_MB23_DATA1		((volatile unsigned short *)CAN_MB23_DATA1)
+#define pCAN_MB23_DATA0		((volatile unsigned short *)CAN_MB23_DATA0)
+
+#define pCAN_MB24_ID1		((volatile unsigned short *)CAN_MB24_ID1)
+#define pCAN_MB24_ID0		((volatile unsigned short *)CAN_MB24_ID0)
+#define pCAN_MB24_TIMESTAMP	((volatile unsigned short *)CAN_MB24_TIMESTAMP)
+#define pCAN_MB24_LENGTH	((volatile unsigned short *)CAN_MB24_LENGTH)
+#define pCAN_MB24_DATA3		((volatile unsigned short *)CAN_MB24_DATA3)
+#define pCAN_MB24_DATA2		((volatile unsigned short *)CAN_MB24_DATA2)
+#define pCAN_MB24_DATA1		((volatile unsigned short *)CAN_MB24_DATA1)
+#define pCAN_MB24_DATA0		((volatile unsigned short *)CAN_MB24_DATA0)
+
+#define pCAN_MB25_ID1		((volatile unsigned short *)CAN_MB25_ID1)
+#define pCAN_MB25_ID0		((volatile unsigned short *)CAN_MB25_ID0)
+#define pCAN_MB25_TIMESTAMP	((volatile unsigned short *)CAN_MB25_TIMESTAMP)
+#define pCAN_MB25_LENGTH	((volatile unsigned short *)CAN_MB25_LENGTH)
+#define pCAN_MB25_DATA3		((volatile unsigned short *)CAN_MB25_DATA3)
+#define pCAN_MB25_DATA2		((volatile unsigned short *)CAN_MB25_DATA2)
+#define pCAN_MB25_DATA1		((volatile unsigned short *)CAN_MB25_DATA1)
+#define pCAN_MB25_DATA0		((volatile unsigned short *)CAN_MB25_DATA0)
+
+#define pCAN_MB26_ID1		((volatile unsigned short *)CAN_MB26_ID1)
+#define pCAN_MB26_ID0		((volatile unsigned short *)CAN_MB26_ID0)
+#define pCAN_MB26_TIMESTAMP	((volatile unsigned short *)CAN_MB26_TIMESTAMP)
+#define pCAN_MB26_LENGTH	((volatile unsigned short *)CAN_MB26_LENGTH)
+#define pCAN_MB26_DATA3		((volatile unsigned short *)CAN_MB26_DATA3)
+#define pCAN_MB26_DATA2		((volatile unsigned short *)CAN_MB26_DATA2)
+#define pCAN_MB26_DATA1		((volatile unsigned short *)CAN_MB26_DATA1)
+#define pCAN_MB26_DATA0		((volatile unsigned short *)CAN_MB26_DATA0)
+
+#define pCAN_MB27_ID1		((volatile unsigned short *)CAN_MB27_ID1)
+#define pCAN_MB27_ID0		((volatile unsigned short *)CAN_MB27_ID0)
+#define pCAN_MB27_TIMESTAMP	((volatile unsigned short *)CAN_MB27_TIMESTAMP)
+#define pCAN_MB27_LENGTH	((volatile unsigned short *)CAN_MB27_LENGTH)
+#define pCAN_MB27_DATA3		((volatile unsigned short *)CAN_MB27_DATA3)
+#define pCAN_MB27_DATA2		((volatile unsigned short *)CAN_MB27_DATA2)
+#define pCAN_MB27_DATA1		((volatile unsigned short *)CAN_MB27_DATA1)
+#define pCAN_MB27_DATA0		((volatile unsigned short *)CAN_MB27_DATA0)
+
+#define pCAN_MB28_ID1		((volatile unsigned short *)CAN_MB28_ID1)
+#define pCAN_MB28_ID0		((volatile unsigned short *)CAN_MB28_ID0)
+#define pCAN_MB28_TIMESTAMP	((volatile unsigned short *)CAN_MB28_TIMESTAMP)
+#define pCAN_MB28_LENGTH	((volatile unsigned short *)CAN_MB28_LENGTH)
+#define pCAN_MB28_DATA3		((volatile unsigned short *)CAN_MB28_DATA3)
+#define pCAN_MB28_DATA2		((volatile unsigned short *)CAN_MB28_DATA2)
+#define pCAN_MB28_DATA1		((volatile unsigned short *)CAN_MB28_DATA1)
+#define pCAN_MB28_DATA0		((volatile unsigned short *)CAN_MB28_DATA0)
+
+#define pCAN_MB29_ID1		((volatile unsigned short *)CAN_MB29_ID1)
+#define pCAN_MB29_ID0		((volatile unsigned short *)CAN_MB29_ID0)
+#define pCAN_MB29_TIMESTAMP	((volatile unsigned short *)CAN_MB29_TIMESTAMP)
+#define pCAN_MB29_LENGTH	((volatile unsigned short *)CAN_MB29_LENGTH)
+#define pCAN_MB29_DATA3		((volatile unsigned short *)CAN_MB29_DATA3)
+#define pCAN_MB29_DATA2		((volatile unsigned short *)CAN_MB29_DATA2)
+#define pCAN_MB29_DATA1		((volatile unsigned short *)CAN_MB29_DATA1)
+#define pCAN_MB29_DATA0		((volatile unsigned short *)CAN_MB29_DATA0)
+
+#define pCAN_MB30_ID1		((volatile unsigned short *)CAN_MB30_ID1)
+#define pCAN_MB30_ID0		((volatile unsigned short *)CAN_MB30_ID0)
+#define pCAN_MB30_TIMESTAMP	((volatile unsigned short *)CAN_MB30_TIMESTAMP)
+#define pCAN_MB30_LENGTH	((volatile unsigned short *)CAN_MB30_LENGTH)
+#define pCAN_MB30_DATA3		((volatile unsigned short *)CAN_MB30_DATA3)
+#define pCAN_MB30_DATA2		((volatile unsigned short *)CAN_MB30_DATA2)
+#define pCAN_MB30_DATA1		((volatile unsigned short *)CAN_MB30_DATA1)
+#define pCAN_MB30_DATA0		((volatile unsigned short *)CAN_MB30_DATA0)
+
+#define pCAN_MB31_ID1		((volatile unsigned short *)CAN_MB31_ID1)
+#define pCAN_MB31_ID0		((volatile unsigned short *)CAN_MB31_ID0)
+#define pCAN_MB31_TIMESTAMP	((volatile unsigned short *)CAN_MB31_TIMESTAMP)
+#define pCAN_MB31_LENGTH	((volatile unsigned short *)CAN_MB31_LENGTH)
+#define pCAN_MB31_DATA3		((volatile unsigned short *)CAN_MB31_DATA3)
+#define pCAN_MB31_DATA2		((volatile unsigned short *)CAN_MB31_DATA2)
+#define pCAN_MB31_DATA1		((volatile unsigned short *)CAN_MB31_DATA1)
+#define pCAN_MB31_DATA0		((volatile unsigned short *)CAN_MB31_DATA0)
+
+/* CAN Mailbox Area Macros */
+#define pCAN_MB_ID1(x)		((volatile unsigned short *)CAN_MB_ID1(x))
+#define pCAN_MB_ID0(x)		((volatile unsigned short *)CAN_MB_ID0(x))
+#define pCAN_MB_TIMESTAMP(x)	((volatile unsigned short *)CAN_MB_TIMESTAMP(x))
+#define pCAN_MB_LENGTH(x)	((volatile unsigned short *)CAN_MB_LENGTH(x))
+#define pCAN_MB_DATA3(x)	((volatile unsigned short *)CAN_MB_DATA3(x))
+#define pCAN_MB_DATA2(x)	((volatile unsigned short *)CAN_MB_DATA2(x))
+#define pCAN_MB_DATA1(x)	((volatile unsigned short *)CAN_MB_DATA1(x))
+#define pCAN_MB_DATA0(x)	((volatile unsigned short *)CAN_MB_DATA0(x))
+
+/* Pin Control Registers	(0xFFC03200 - 0xFFC032FF) */
+#define pPORTF_FER		((volatile unsigned short *)PORTF_FER)
+#define pPORTG_FER		((volatile unsigned short *)PORTG_FER)
+#define pPORTH_FER		((volatile unsigned short *)PORTH_FER)
+#define pPORT_MUX		((volatile unsigned short *)PORT_MUX)
+
+#define PORTF_UART0_TX		0x0001
+#define PORTF_UART0_RX		0x0002
+
+#define PORT_MUX_PFDE		0x0040	/* 0: Enable UART0 RX, UART0 TX; 1: Enable DMAR0, DMAr1 */
+
+/* Handshake MDMA Registers	(0xFFC03300 - 0xFFC033FF) */
+#define pHMDMA0_CONTROL		((volatile unsigned short *)HMDMA0_CONTROL)
+#define pHMDMA0_ECINIT		((volatile unsigned short *)HMDMA0_ECINIT)
+#define pHMDMA0_BCINIT		((volatile unsigned short *)HMDMA0_BCINIT)
+#define pHMDMA0_ECURGENT	((volatile unsigned short *)HMDMA0_ECURGENT)
+#define pHMDMA0_ECOVERFLOW	((volatile unsigned short *)HMDMA0_ECOVERFLOW)
+#define pHMDMA0_ECOUNT		((volatile unsigned short *)HMDMA0_ECOUNT)
+#define pHMDMA0_BCOUNT		((volatile unsigned short *)HMDMA0_BCOUNT)
+
+#define pHMDMA1_CONTROL		((volatile unsigned short *)HMDMA1_CONTROL)
+#define pHMDMA1_ECINIT		((volatile unsigned short *)HMDMA1_ECINIT)
+#define pHMDMA1_BCINIT		((volatile unsigned short *)HMDMA1_BCINIT)
+#define pHMDMA1_ECURGENT	((volatile unsigned short *)HMDMA1_ECURGENT)
+#define pHMDMA1_ECOVERFLOW	((volatile unsigned short *)HMDMA1_ECOVERFLOW)
+#define pHMDMA1_ECOUNT		((volatile unsigned short *)HMDMA1_ECOUNT)
+#define pHMDMA1_BCOUNT		((volatile unsigned short *)HMDMA1_BCOUNT)
+
+#endif				/* _CDEF_BF534_H */
diff --git a/include/asm-blackfin/arch-bf537/cdefBF537.h b/include/asm-blackfin/arch-bf537/cdefBF537.h
new file mode 100644
index 0000000..3de1d93
--- /dev/null
+++ b/include/asm-blackfin/arch-bf537/cdefBF537.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (C) 2004 Analog Devices Inc., All Rights Reserved.
+ *
+ ***********************************************************************************
+ *
+ * This include file contains a list of macro "defines" to enable the programmer
+ * to use symbolic names for register-access.
+ *
+ *   ----------------------------
+ *   revision 0.1
+ *   date: 2004/03/01 21:23:01;  author: joeb
+ *   Initial revision
+ *
+ *   ----------------------------
+ *   revision 0.2
+ *   date: 2004/05/15 16:30:00;  author: joeb
+ *   comments: removed I2C/IIC references to TWI, changed GPIO sections
+ *
+ *   ----------------------------
+ *   revision 0.3
+ *   date: 2004/06/08 12:25:00;  author: joeb
+ *   comments: renamed some TWI and GPIO registers
+ *
+ *   ----------------------------
+ *   revision 0.4
+ *   date: 2004/06/09 14:25:00;  author: joeb
+ *   comments: changed Timer status register to 32-bit, renamed EMAC count registers
+ *
+ *   ----------------------------
+ *   revision 0.5
+ *   date: 2004/08/10 10:25:00;  author: joeb
+ *   comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
+ *
+ *   ----------------------------
+ *   revision 0.6
+ *   date: 2004/08/17 16:25:00;  author: joeb
+ *   comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
+ *
+ *   ----------------------------
+ *   revision 0.7
+ *   date: 2004/08/18 13:21:00;  author: joeb
+ *   comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
+ *
+ *   ----------------------------
+ *   revision 0.8
+ *   date: 2004/08/20 10:27:00;  author: joeb
+ *   comments: Renamed External DMA to Handshake DMA
+ *
+ *   ----------------------------
+ *   revision 0.9
+ *   date: 2004/08/23 13:42:00;  author: joeb
+ *   comments: Renamed Handshake DMA Register Set
+ *
+ *   ----------------------------
+ *   revision 0.10
+ *   date: 2004/10/28 15:40:00;  author: joeb
+ *   comments: Shortened EMAC Count Register Names
+ *
+ *   ----------------------------
+ *   revision 0.11
+ *   date: 2004/12/13 11:05:00;  author: joeb
+ *   comments: Fixed address pointers - (volatile void **) to (void * volatile *)
+ *
+ *   ----------------------------
+ *   revision 0.12
+ *   date: 2004/12/17 14:25:00;  author: joeb
+ *   comments: Replaced C++ Single-Line Comments w/C-standard Comments
+ *				Changed EMAC EQ1024 TX/RX References to GE1024
+ *
+ *   ----------------------------
+ *   revision 0.13
+ *   date: 2005/01/05 10:50:00;  author: joeb
+ *   comments: Removed excess white space in CAN_AM section
+ *				Added support for CAN Macros to Index AM and Mailbox Areas
+ *
+ *   ----------------------------
+ *   revision 0.14
+ *   date: 2005/01/26 14:10:00;  author: joeb
+ *   comments: Fixed Typo In EMAC_RXC_PAUSE register
+ *
+ *   ----------------------------
+ *   revision 0.15
+ *   date: 2005/01/27 14:41:00;  author: joeb
+ *   comments: Moved Common MMRs to cdefBF534.h
+ */
+
+/*
+ * System MMR Register Map
+ */
+
+#ifndef _CDEF_BF537_H
+#define _CDEF_BF537_H
+
+/* Include MMRs Common to BF534 */
+#include <asm/arch-bf537/cdefBF534.h>
+
+/* Include all Core registers and bit definitions */
+#include <asm/arch-bf537/defBF537.h>
+
+/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
+/* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
+#define	pEMAC_OPMODE		((volatile unsigned long  *)EMAC_OPMODE)
+#define pEMAC_ADDRLO		((volatile unsigned long  *)EMAC_ADDRLO)
+#define pEMAC_ADDRHI		((volatile unsigned long  *)EMAC_ADDRHI)
+#define pEMAC_HASHLO		((volatile unsigned long  *)EMAC_HASHLO)
+#define pEMAC_HASHHI		((volatile unsigned long  *)EMAC_HASHHI)
+#define pEMAC_STAADD		((volatile unsigned long  *)EMAC_STAADD)
+#define pEMAC_STADAT		((volatile unsigned long  *)EMAC_STADAT)
+#define pEMAC_FLC		((volatile unsigned long  *)EMAC_FLC)
+#define pEMAC_VLAN1		((volatile unsigned long  *)EMAC_VLAN1)
+#define pEMAC_VLAN2		((volatile unsigned long  *)EMAC_VLAN2)
+#define pEMAC_WKUP_CTL		((volatile unsigned long  *)EMAC_WKUP_CTL)
+#define pEMAC_WKUP_FFMSK0	((volatile unsigned long  *)EMAC_WKUP_FFMSK0)
+#define pEMAC_WKUP_FFMSK1	((volatile unsigned long  *)EMAC_WKUP_FFMSK1)
+#define pEMAC_WKUP_FFMSK2	((volatile unsigned long  *)EMAC_WKUP_FFMSK2)
+#define pEMAC_WKUP_FFMSK3	((volatile unsigned long  *)EMAC_WKUP_FFMSK3)
+#define pEMAC_WKUP_FFCMD	((volatile unsigned long  *)EMAC_WKUP_FFCMD)
+#define pEMAC_WKUP_FFOFF	((volatile unsigned long  *)EMAC_WKUP_FFOFF)
+#define pEMAC_WKUP_FFCRC0	((volatile unsigned long  *)EMAC_WKUP_FFCRC0)
+#define pEMAC_WKUP_FFCRC1	((volatile unsigned long  *)EMAC_WKUP_FFCRC1)
+
+#define	pEMAC_SYSCTL		((volatile unsigned long  *)EMAC_SYSCTL)
+#define pEMAC_SYSTAT		((volatile unsigned long  *)EMAC_SYSTAT)
+#define pEMAC_RX_STAT		((volatile unsigned long  *)EMAC_RX_STAT)
+#define pEMAC_RX_STKY		((volatile unsigned long  *)EMAC_RX_STKY)
+#define pEMAC_RX_IRQE		((volatile unsigned long  *)EMAC_RX_IRQE)
+#define pEMAC_TX_STAT		((volatile unsigned long  *)EMAC_TX_STAT)
+#define pEMAC_TX_STKY		((volatile unsigned long  *)EMAC_TX_STKY)
+#define pEMAC_TX_IRQE		((volatile unsigned long  *)EMAC_TX_IRQE)
+
+#define pEMAC_MMC_CTL		((volatile unsigned long  *)EMAC_MMC_CTL)
+#define pEMAC_MMC_RIRQS		((volatile unsigned long  *)EMAC_MMC_RIRQS)
+#define pEMAC_MMC_RIRQE		((volatile unsigned long  *)EMAC_MMC_RIRQE)
+#define pEMAC_MMC_TIRQS		((volatile unsigned long  *)EMAC_MMC_TIRQS)
+#define pEMAC_MMC_TIRQE		((volatile unsigned long  *)EMAC_MMC_TIRQE)
+
+#define pEMAC_RXC_OK		((volatile unsigned long  *)EMAC_RXC_OK)
+#define pEMAC_RXC_FCS		((volatile unsigned long  *)EMAC_RXC_FCS)
+#define pEMAC_RXC_ALIGN		((volatile unsigned long  *)EMAC_RXC_ALIGN)
+#define pEMAC_RXC_OCTET		((volatile unsigned long  *)EMAC_RXC_OCTET)
+#define pEMAC_RXC_DMAOVF	((volatile unsigned long  *)EMAC_RXC_DMAOVF)
+#define pEMAC_RXC_UNICST	((volatile unsigned long  *)EMAC_RXC_UNICST)
+#define pEMAC_RXC_MULTI		((volatile unsigned long  *)EMAC_RXC_MULTI)
+#define pEMAC_RXC_BROAD		((volatile unsigned long  *)EMAC_RXC_BROAD)
+#define pEMAC_RXC_LNERRI	((volatile unsigned long  *)EMAC_RXC_LNERRI)
+#define pEMAC_RXC_LNERRO	((volatile unsigned long  *)EMAC_RXC_LNERRO)
+#define pEMAC_RXC_LONG		((volatile unsigned long  *)EMAC_RXC_LONG)
+#define pEMAC_RXC_MACCTL	((volatile unsigned long  *)EMAC_RXC_MACCTL)
+#define pEMAC_RXC_OPCODE	((volatile unsigned long  *)EMAC_RXC_OPCODE)
+#define pEMAC_RXC_PAUSE		((volatile unsigned long  *)EMAC_RXC_PAUSE)
+#define pEMAC_RXC_ALLFRM	((volatile unsigned long  *)EMAC_RXC_ALLFRM)
+#define pEMAC_RXC_ALLOCT	((volatile unsigned long  *)EMAC_RXC_ALLOCT)
+#define pEMAC_RXC_TYPED		((volatile unsigned long  *)EMAC_RXC_TYPED)
+#define pEMAC_RXC_SHORT		((volatile unsigned long  *)EMAC_RXC_SHORT)
+#define pEMAC_RXC_EQ64		((volatile unsigned long  *)EMAC_RXC_EQ64)
+#define	pEMAC_RXC_LT128		((volatile unsigned long  *)EMAC_RXC_LT128)
+#define pEMAC_RXC_LT256		((volatile unsigned long  *)EMAC_RXC_LT256)
+#define pEMAC_RXC_LT512		((volatile unsigned long  *)EMAC_RXC_LT512)
+#define pEMAC_RXC_LT1024	((volatile unsigned long  *)EMAC_RXC_LT1024)
+#define pEMAC_RXC_GE1024	((volatile unsigned long  *)EMAC_RXC_GE1024)
+
+#define pEMAC_TXC_OK		((volatile unsigned long  *)EMAC_TXC_OK)
+#define pEMAC_TXC_1COL		((volatile unsigned long  *)EMAC_TXC_1COL)
+#define pEMAC_TXC_GT1COL	((volatile unsigned long  *)EMAC_TXC_GT1COL)
+#define pEMAC_TXC_OCTET		((volatile unsigned long  *)EMAC_TXC_OCTET)
+#define pEMAC_TXC_DEFER		((volatile unsigned long  *)EMAC_TXC_DEFER)
+#define pEMAC_TXC_LATECL	((volatile unsigned long  *)EMAC_TXC_LATECL)
+#define pEMAC_TXC_XS_COL	((volatile unsigned long  *)EMAC_TXC_XS_COL)
+#define pEMAC_TXC_DMAUND	((volatile unsigned long  *)EMAC_TXC_DMAUND)
+#define pEMAC_TXC_CRSERR	((volatile unsigned long  *)EMAC_TXC_CRSERR)
+#define pEMAC_TXC_UNICST	((volatile unsigned long  *)EMAC_TXC_UNICST)
+#define pEMAC_TXC_MULTI		((volatile unsigned long  *)EMAC_TXC_MULTI)
+#define pEMAC_TXC_BROAD		((volatile unsigned long  *)EMAC_TXC_BROAD)
+#define pEMAC_TXC_XS_DFR	((volatile unsigned long  *)EMAC_TXC_XS_DFR)
+#define pEMAC_TXC_MACCTL	((volatile unsigned long  *)EMAC_TXC_MACCTL)
+#define pEMAC_TXC_ALLFRM	((volatile unsigned long  *)EMAC_TXC_ALLFRM)
+#define pEMAC_TXC_ALLOCT	((volatile unsigned long  *)EMAC_TXC_ALLOCT)
+#define pEMAC_TXC_EQ64		((volatile unsigned long  *)EMAC_TXC_EQ64)
+#define pEMAC_TXC_LT128		((volatile unsigned long  *)EMAC_TXC_LT128)
+#define pEMAC_TXC_LT256		((volatile unsigned long  *)EMAC_TXC_LT256)
+#define pEMAC_TXC_LT512		((volatile unsigned long  *)EMAC_TXC_LT512)
+#define pEMAC_TXC_LT1024	((volatile unsigned long  *)EMAC_TXC_LT1024)
+#define pEMAC_TXC_GE1024	((volatile unsigned long  *)EMAC_TXC_GE1024)
+#define pEMAC_TXC_ABORT		((volatile unsigned long  *)EMAC_TXC_ABORT)
+
+#endif				/* _CDEF_BF537_H */
diff --git a/include/asm-blackfin/arch-bf537/cplbtab.h b/include/asm-blackfin/arch-bf537/cplbtab.h
new file mode 100644
index 0000000..c5151bb
--- /dev/null
+++ b/include/asm-blackfin/arch-bf537/cplbtab.h
@@ -0,0 +1,408 @@
+/*This file is subject to the terms and conditions of the GNU General Public
+ * License.
+ *
+ * Blackfin BF533/2.6 support : LG Soft India
+ * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
+ * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
+ *	        shouldn't be victimized. cplbmgr.S search logic is corrected
+ *	        to findout the appropriate victim.
+ *	     2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
+ *	     : LG Soft India
+ */
+#include <config.h>
+
+#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
+#define __ARCH_BFINNOMMU_CPLBTAB_H
+
+/*
+ * ICPLB TABLE
+ */
+
+.data
+/* This table is configurable */
+    .align 4;
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY		(PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL		(PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158	0x200
+#ifdef CONFIG_BLKFIN_WB		/*Write Back Policy */
+#define SDRAM_DGENERIC		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL		(PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU		(PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+#else				/*Write Through */
+#define SDRAM_DGENERIC		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL		(PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU		(PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+#endif
+
+.align 4;
+.global _ipdt_table _ipdt_table:.byte4 0x00000000;
+.byte4(SDRAM_IKERNEL);		/*SDRAM_Page0 */
+.byte4 0x00400000;
+.byte4(SDRAM_IKERNEL);		/*SDRAM_Page1 */
+.byte4 0x00800000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page2 */
+.byte4 0x00C00000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page3 */
+.byte4 0x01000000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page4 */
+.byte4 0x01400000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page5 */
+.byte4 0x01800000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page6 */
+.byte4 0x01C00000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page7 */
+.byte4 0x02000000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page8 */
+.byte4 0x02400000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page9 */
+.byte4 0x02800000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page10 */
+.byte4 0x02C00000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page11 */
+.byte4 0x03000000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page12 */
+.byte4 0x03400000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page13 */
+.byte4 0x03800000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page14 */
+.byte4 0x03C00000;
+.byte4(SDRAM_IGENERIC);		/*SDRAM_Page15 */
+.byte4 0x20000000;
+.byte4(SDRAM_EBIU);		/* Async Memory Bank 2 (Secnd) */
+
+.byte4 0xffffffff;		/* end of section - termination */
+
+/*
+ * PAGE DESCRIPTOR TABLE
+ *
+ */
+
+/*
+ * Till here we are discussing about the static memory management model.
+ * However, the operating envoronments commonly define more CPLB
+ * descriptors to cover the entire addressable memory than will fit into
+ * the available on-chip 16 CPLB MMRs. When this happens, the below table
+ * will be used which will hold all the potentially required CPLB descriptors
+ *
+ * This is how Page descriptor Table is implemented in uClinux/Blackfin.
+ */
+.global _dpdt_table _dpdt_table:.byte4 0x00000000;
+.byte4(SDRAM_DKERNEL);		/*SDRAM_Page0 */
+.byte4 0x00400000;
+.byte4(SDRAM_DKERNEL);		/*SDRAM_Page1 */
+.byte4 0x00800000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page2 */
+.byte4 0x00C00000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page3 */
+.byte4 0x01000000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page4 */
+.byte4 0x01400000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page5 */
+.byte4 0x01800000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page6 */
+.byte4 0x01C00000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page7 */
+.byte4 0x02000000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page8 */
+.byte4 0x02400000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page9 */
+.byte4 0x02800000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page10 */
+.byte4 0x02C00000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page11 */
+.byte4 0x03000000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page12 */
+.byte4 0x03400000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page13 */
+.byte4 0x03800000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page14 */
+.byte4 0x03C00000;
+.byte4(SDRAM_DGENERIC);		/*SDRAM_Page15 */
+.byte4 0x20000000;
+.byte4(SDRAM_EBIU);		/* Async Memory Bank 0 (Prim A) */
+
+#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
+.byte4 0xFF800000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF801000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF802000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF803000;
+.byte4(L1_DMEMORY);
+#endif
+.byte4 0xFF804000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF805000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF806000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF807000;
+.byte4(L1_DMEMORY);
+#if ((BFIN_CPU == ADSP_BF534) || (BFIN_CPU == ADSP_BF537))
+.byte4 0xFF900000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF901000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF902000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF903000;
+.byte4(L1_DMEMORY);
+#endif
+.byte4 0xFF904000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF905000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF906000;
+.byte4(L1_DMEMORY);
+.byte4 0xFF907000;
+.byte4(L1_DMEMORY);
+
+.byte4 0xFFB00000;
+.byte4(L1_DMEMORY);
+
+.byte4 0xffffffff;		/*end of section - termination */
+
+#ifdef CONFIG_CPLB_INFO
+.global _ipdt_swapcount_table;	/* swapin count first, then swapout count */
+_ipdt_swapcount_table:
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 10 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 20 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 30 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 40 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 50 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 60 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 70 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 90 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 100 */
+
+.global _dpdt_swapcount_table;	/* swapin count first, then swapout count */
+_dpdt_swapcount_table:
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 10 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 20 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 30 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 40 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 50 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 60 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 70 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 80 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 100 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 110 */
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;
+.byte4 0x00000000;		/* 120 */
+
+#endif
+
+#endif	/*__ARCH_BFINNOMMU_CPLBTAB_H*/
diff --git a/include/asm-blackfin/arch-bf537/defBF534.h b/include/asm-blackfin/arch-bf537/defBF534.h
new file mode 100644
index 0000000..c603d44
--- /dev/null
+++ b/include/asm-blackfin/arch-bf537/defBF534.h
@@ -0,0 +1,2627 @@
+/*
+ * Copyright (C) 2004 Analog Devices Inc., All Rights Reserved.
+ *
+ ***********************************************************************************
+ *
+ * This include file contains a list of macro "defines" to enable the programmer
+ * to use symbolic names for register-access and bit-manipulation.
+ *
+ *   ----------------------------
+ *   revision 0.1
+ *   date: 2004/03/01 21:23:01;  author: joeb
+ *   Initial revision
+ *
+ */
+#ifndef _DEF_BF534_H
+#define _DEF_BF534_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/arch-common/def_LPBlackfin.h>
+
+#define LO(con32)		((con32) & 0xFFFF)
+#define lo(con32)		((con32) & 0xFFFF)
+#define HI(con32)		(((con32) >> 16) & 0xFFFF)
+#define hi(con32)		(((con32) >> 16) & 0xFFFF)
+
+/*
+ * System MMR Register Map
+ */
+/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)*/
+#define PLL_CTL			0xFFC00000	/* PLL Control Register */
+#define PLL_DIV			0xFFC00004	/* PLL Divide Register */
+#define VR_CTL			0xFFC00008	/* Voltage Regulator Control Register */
+#define CHIPID			0xFFC00014	/* Chip ID register (32-bit) */
+#define PLL_STAT		0xFFC0000C	/* PLL Status Register */
+#define PLL_LOCKCNT		0xFFC00010	/* PLL Lock Count Register */
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST			0xFFC00100	/* Software Reset Register */
+#define SYSCR			0xFFC00104	/* System Configuration Register */
+#define SIC_RVECT		0xFFC00108	/* Interrupt Reset Vector Address Register */
+#define SIC_IMASK		0xFFC0010C	/* Interrupt Mask Register */
+#define SIC_IAR0		0xFFC00110	/* Interrupt Assignment Register 0 */
+#define SIC_IAR1		0xFFC00114	/* Interrupt Assignment Register 1 */
+#define SIC_IAR2		0xFFC00118	/* Interrupt Assignment Register 2 */
+#define SIC_IAR3		0xFFC0011C	/* Interrupt Assignment Register 3 */
+#define SIC_ISR			0xFFC00120	/* Interrupt Status Register */
+#define SIC_IWR			0xFFC00124	/* Interrupt Wakeup Register */
+
+/* Watchdog Timer		(0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL		0xFFC00200	/* Watchdog Control Register */
+#define WDOG_CNT		0xFFC00204	/* Watchdog Count Register */
+#define WDOG_STAT		0xFFC00208	/* Watchdog Status Register */
+
+/* Real Time Clock		(0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT		0xFFC00300	/* RTC Status Register */
+#define RTC_ICTL		0xFFC00304	/* RTC Interrupt Control Register */
+#define RTC_ISTAT		0xFFC00308	/* RTC Interrupt Status Register */
+#define RTC_SWCNT		0xFFC0030C	/* RTC Stopwatch Count Register */
+#define RTC_ALARM		0xFFC00310	/* RTC Alarm Time Register */
+#define RTC_FAST		0xFFC00314	/* RTC Prescaler Enable Register */
+#define RTC_PREN		0xFFC00314	/* RTC Prescaler Enable Alternate Macro */
+
+/* UART0 Controller		(0xFFC00400 - 0xFFC004FF) */
+#define UART0_THR		0xFFC00400	/* Transmit Holding register */
+#define UART0_RBR		0xFFC00400	/* Receive Buffer register */
+#define UART0_DLL		0xFFC00400	/* Divisor Latch (Low-Byte) */
+#define UART0_IER		0xFFC00404	/* Interrupt Enable Register */
+#define UART0_DLH		0xFFC00404	/* Divisor Latch (High-Byte) */
+#define UART0_IIR		0xFFC00408	/* Interrupt Identification Register */
+#define UART0_LCR		0xFFC0040C	/* Line Control Register */
+#define UART0_MCR		0xFFC00410	/* Modem Control Register */
+#define UART0_LSR		0xFFC00414	/* Line Status Register */
+#define UART0_MSR		0xFFC00418	/* Modem Status Register */
+#define UART0_SCR		0xFFC0041C	/* SCR Scratch Register */
+#define UART0_GCTL		0xFFC00424	/* Global Control Register */
+
+/* SPI Controller		(0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL			0xFFC00500	/* SPI Control Register */
+#define SPI_FLG			0xFFC00504	/* SPI Flag register */
+#define SPI_STAT		0xFFC00508	/* SPI Status register */
+#define SPI_TDBR		0xFFC0050C	/* SPI Transmit Data Buffer Register */
+#define SPI_RDBR		0xFFC00510	/* SPI Receive Data Buffer Register */
+#define SPI_BAUD		0xFFC00514	/* SPI Baud rate Register */
+#define SPI_SHADOW		0xFFC00518	/* SPI_RDBR Shadow Register */
+
+/* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG		0xFFC00600	/* Timer 0 Configuration Register */
+#define TIMER0_COUNTER		0xFFC00604	/* Timer 0 Counter Register */
+#define TIMER0_PERIOD		0xFFC00608	/* Timer 0 Period Register */
+#define TIMER0_WIDTH		0xFFC0060C	/* Timer 0 Width Register */
+
+#define TIMER1_CONFIG		0xFFC00610	/* Timer 1 Configuration Register */
+#define TIMER1_COUNTER		0xFFC00614	/* Timer 1 Counter Register */
+#define TIMER1_PERIOD		0xFFC00618	/* Timer 1 Period Register */
+#define TIMER1_WIDTH		0xFFC0061C	/* Timer 1 Width Register */
+
+#define TIMER2_CONFIG		0xFFC00620	/* Timer 2 Configuration Register */
+#define TIMER2_COUNTER		0xFFC00624	/* Timer 2 Counter Register */
+#define TIMER2_PERIOD		0xFFC00628	/* Timer 2 Period Register */
+#define TIMER2_WIDTH		0xFFC0062C	/* Timer 2 Width Register */
+
+#define TIMER3_CONFIG		0xFFC00630	/* Timer 3 Configuration Register */
+#define TIMER3_COUNTER		0xFFC00634	/* Timer 3 Counter Register */
+#define TIMER3_PERIOD		0xFFC00638	/* Timer 3 Period Register */
+#define TIMER3_WIDTH		0xFFC0063C	/* Timer 3 Width Register */
+
+#define TIMER4_CONFIG		0xFFC00640	/* Timer 4 Configuration Register */
+#define TIMER4_COUNTER		0xFFC00644	/* Timer 4 Counter Register */
+#define TIMER4_PERIOD		0xFFC00648	/* Timer 4 Period Register */
+#define TIMER4_WIDTH		0xFFC0064C	/* Timer 4 Width Register */
+
+#define TIMER5_CONFIG		0xFFC00650	/* Timer 5 Configuration Register */
+#define TIMER5_COUNTER		0xFFC00654	/* Timer 5 Counter Register */
+#define TIMER5_PERIOD		0xFFC00658	/* Timer 5 Period Register */
+#define TIMER5_WIDTH		0xFFC0065C	/* Timer 5 Width Register */
+
+#define TIMER6_CONFIG		0xFFC00660	/* Timer 6 Configuration Register */
+#define TIMER6_COUNTER		0xFFC00664	/* Timer 6 Counter Register */
+#define TIMER6_PERIOD		0xFFC00668	/* Timer 6 Period Register */
+#define TIMER6_WIDTH		0xFFC0066C	/* Timer 6 Width Register */
+
+#define TIMER7_CONFIG		0xFFC00670	/* Timer 7 Configuration Register */
+#define TIMER7_COUNTER		0xFFC00674	/* Timer 7 Counter Register */
+#define TIMER7_PERIOD		0xFFC00678	/* Timer 7 Period Register */
+#define TIMER7_WIDTH		0xFFC0067C	/* Timer 7 Width Register */
+
+#define TIMER_ENABLE		0xFFC00680	/* Timer Enable Register */
+#define TIMER_DISABLE		0xFFC00684	/* Timer Disable Register */
+#define TIMER_STATUS		0xFFC00688	/* Timer Status Register */
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
+#define PORTFIO			0xFFC00700	/* Port F I/O Pin State Specify Register */
+#define PORTFIO_CLEAR		0xFFC00704	/* Port F I/O Peripheral Interrupt Clear Register */
+#define PORTFIO_SET		0xFFC00708	/* Port F I/O Peripheral Interrupt Set Register */
+#define PORTFIO_TOGGLE		0xFFC0070C	/* Port F I/O Pin State Toggle Register */
+#define PORTFIO_MASKA		0xFFC00710	/* Port F I/O Mask State Specify Interrupt A Register */
+#define PORTFIO_MASKA_CLEAR	0xFFC00714	/* Port F I/O Mask Disable Interrupt A Register */
+#define PORTFIO_MASKA_SET	0xFFC00718	/* Port F I/O Mask Enable Interrupt A Register */
+#define PORTFIO_MASKA_TOGGLE	0xFFC0071C	/* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define PORTFIO_MASKB		0xFFC00720	/* Port F I/O Mask State Specify Interrupt B Register */
+#define PORTFIO_MASKB_CLEAR	0xFFC00724	/* Port F I/O Mask Disable Interrupt B Register */
+#define PORTFIO_MASKB_SET	0xFFC00728	/* Port F I/O Mask Enable Interrupt B Register */
+#define PORTFIO_MASKB_TOGGLE	0xFFC0072C	/* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define PORTFIO_DIR		0xFFC00730	/* Port F I/O Direction Register */
+#define PORTFIO_POLAR		0xFFC00734	/* Port F I/O Source Polarity Register */
+#define PORTFIO_EDGE		0xFFC00738	/* Port F I/O Source Sensitivity Register */
+#define PORTFIO_BOTH		0xFFC0073C	/* Port F I/O Set on BOTH Edges Register */
+#define PORTFIO_INEN		0xFFC00740	/* Port F I/O Input Enable Register */
+
+/* SPORT0 Controller		(0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1		0xFFC00800	/* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2		0xFFC00804	/* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX		0xFFC00810	/* SPORT0 TX Data Register */
+#define SPORT0_RX		0xFFC00818	/* SPORT0 RX Data Register */
+#define SPORT0_RCR1		0xFFC00820	/* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2		0xFFC00824	/* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT		0xFFC00830	/* SPORT0 Status Register */
+#define SPORT0_CHNL		0xFFC00834	/* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3 */
+
+/* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1		0xFFC00900	/* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2		0xFFC00904	/* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX		0xFFC00910	/* SPORT1 TX Data Register */
+#define SPORT1_RX		0xFFC00918	/* SPORT1 RX Data Register */
+#define SPORT1_RCR1		0xFFC00920	/* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2		0xFFC00924	/* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT		0xFFC00930	/* SPORT1 Status Register */
+#define SPORT1_CHNL		0xFFC00934	/* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3 */
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_AMGCTL		0xFFC00A00	/* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1 */
+#define EBIU_SDGCTL		0xFFC00A10	/* SDRAM Global Control Register */
+#define EBIU_SDBCTL		0xFFC00A14	/* SDRAM Bank Control Register */
+#define EBIU_SDRRC		0xFFC00A18	/* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT		0xFFC00A1C	/* SDRAM Status Register */
+
+/* DMA Traffic Control Registers */
+#define DMA_TCPER		0xFFC00B0C	/* Traffic Control Periods Register */
+#define DMA_TCCNT		0xFFC00B10	/* Traffic Control Current Counts Register */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
+#define DMA0_NEXT_DESC_PTR	0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR		0xFFC00C04	/* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG		0xFFC00C08	/* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT		0xFFC00C10	/* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY		0xFFC00C14	/* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT		0xFFC00C18	/* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY		0xFFC00C1C	/* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR	0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR		0xFFC00C24	/* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS		0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP	0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT	0xFFC00C30	/* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT	0xFFC00C38	/* DMA Channel 0 Current Y Count Register */
+
+#define DMA1_NEXT_DESC_PTR	0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR		0xFFC00C44	/* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG		0xFFC00C48	/* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT		0xFFC00C50	/* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY		0xFFC00C54	/* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT		0xFFC00C58	/* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY		0xFFC00C5C	/* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR	0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR		0xFFC00C64	/* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS		0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP	0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT	0xFFC00C70	/* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT	0xFFC00C78	/* DMA Channel 1 Current Y Count Register */
+
+#define DMA2_NEXT_DESC_PTR	0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR		0xFFC00C84	/* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG		0xFFC00C88	/* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT		0xFFC00C90	/* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY		0xFFC00C94	/* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT		0xFFC00C98	/* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY		0xFFC00C9C	/* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR	0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR		0xFFC00CA4	/* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS		0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP	0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT	0xFFC00CB0	/* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT	0xFFC00CB8	/* DMA Channel 2 Current Y Count Register */
+
+#define DMA3_NEXT_DESC_PTR	0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR		0xFFC00CC4	/* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG		0xFFC00CC8	/* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT		0xFFC00CD0	/* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY		0xFFC00CD4	/* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT		0xFFC00CD8	/* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY		0xFFC00CDC	/* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR	0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR		0xFFC00CE4	/* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS		0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP	0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT	0xFFC00CF0	/* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT	0xFFC00CF8	/* DMA Channel 3 Current Y Count Register */
+
+#define DMA4_NEXT_DESC_PTR	0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR		0xFFC00D04	/* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG		0xFFC00D08	/* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT		0xFFC00D10	/* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY		0xFFC00D14	/* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT		0xFFC00D18	/* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY		0xFFC00D1C	/* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR	0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR		0xFFC00D24	/* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS		0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP	0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT	0xFFC00D30	/* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT	0xFFC00D38	/* DMA Channel 4 Current Y Count Register */
+
+#define DMA5_NEXT_DESC_PTR	0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR		0xFFC00D44	/* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG		0xFFC00D48	/* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT		0xFFC00D50	/* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY		0xFFC00D54	/* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT		0xFFC00D58	/* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY		0xFFC00D5C	/* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR	0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR		0xFFC00D64	/* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS		0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP	0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT	0xFFC00D70	/* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT	0xFFC00D78	/* DMA Channel 5 Current Y Count Register */
+
+#define DMA6_NEXT_DESC_PTR	0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR		0xFFC00D84	/* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG		0xFFC00D88	/* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT		0xFFC00D90	/* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY		0xFFC00D94	/* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT		0xFFC00D98	/* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY		0xFFC00D9C	/* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR	0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR		0xFFC00DA4	/* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS		0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP	0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT	0xFFC00DB0	/* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT	0xFFC00DB8	/* DMA Channel 6 Current Y Count Register */
+
+#define DMA7_NEXT_DESC_PTR	0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR		0xFFC00DC4	/* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG		0xFFC00DC8	/* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT		0xFFC00DD0	/* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY		0xFFC00DD4	/* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT		0xFFC00DD8	/* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY		0xFFC00DDC	/* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR	0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR		0xFFC00DE4	/* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS		0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP	0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT	0xFFC00DF0	/* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT	0xFFC00DF8	/* DMA Channel 7 Current Y Count Register */
+
+#define DMA8_NEXT_DESC_PTR	0xFFC00E00	/* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR		0xFFC00E04	/* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG		0xFFC00E08	/* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT		0xFFC00E10	/* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY		0xFFC00E14	/* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT		0xFFC00E18	/* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY		0xFFC00E1C	/* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR	0xFFC00E20	/* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR		0xFFC00E24	/* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS		0xFFC00E28	/* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP	0xFFC00E2C	/* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT	0xFFC00E30	/* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT	0xFFC00E38	/* DMA Channel 8 Current Y Count Register */
+
+#define DMA9_NEXT_DESC_PTR	0xFFC00E40	/* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR		0xFFC00E44	/* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG		0xFFC00E48	/* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT		0xFFC00E50	/* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY		0xFFC00E54	/* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT		0xFFC00E58	/* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY		0xFFC00E5C	/* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR	0xFFC00E60	/* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR		0xFFC00E64	/* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS		0xFFC00E68	/* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP	0xFFC00E6C	/* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT	0xFFC00E70	/* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT	0xFFC00E78	/* DMA Channel 9 Current Y Count Register */
+
+#define DMA10_NEXT_DESC_PTR	0xFFC00E80	/* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR	0xFFC00E84	/* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG		0xFFC00E88	/* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT		0xFFC00E90	/* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY		0xFFC00E94	/* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT		0xFFC00E98	/* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY		0xFFC00E9C	/* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR	0xFFC00EA0	/* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR		0xFFC00EA4	/* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS	0xFFC00EA8	/* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP	0xFFC00EAC	/* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT	0xFFC00EB0	/* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT	0xFFC00EB8	/* DMA Channel 10 Current Y Count Register */
+
+#define DMA11_NEXT_DESC_PTR	0xFFC00EC0	/* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR	0xFFC00EC4	/* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG		0xFFC00EC8	/* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT		0xFFC00ED0	/* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY		0xFFC00ED4	/* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT		0xFFC00ED8	/* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY		0xFFC00EDC	/* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR	0xFFC00EE0	/* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR		0xFFC00EE4	/* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS	0xFFC00EE8	/* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP	0xFFC00EEC	/* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT	0xFFC00EF0	/* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT	0xFFC00EF8	/* DMA Channel 11 Current Y Count Register */
+
+#define MDMA_D0_NEXT_DESC_PTR	0xFFC00F00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR	0xFFC00F04	/* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG		0xFFC00F08	/* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT		0xFFC00F10	/* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY	0xFFC00F14	/* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT		0xFFC00F18	/* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY	0xFFC00F1C	/* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR	0xFFC00F20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR	0xFFC00F24	/* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS	0xFFC00F28	/* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP	0xFFC00F2C	/* MemDMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT	0xFFC00F30	/* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT	0xFFC00F38	/* MemDMA Stream 0 Destination Current Y Count Register */
+
+#define MDMA_S0_NEXT_DESC_PTR	0xFFC00F40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR	0xFFC00F44	/* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG		0xFFC00F48	/* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT		0xFFC00F50	/* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY	0xFFC00F54	/* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT		0xFFC00F58	/* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY	0xFFC00F5C	/* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR	0xFFC00F60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR	0xFFC00F64	/* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS	0xFFC00F68	/* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP	0xFFC00F6C	/* MemDMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT	0xFFC00F70	/* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT	0xFFC00F78	/* MemDMA Stream 0 Source Current Y Count Register */
+
+#define MDMA_D1_NEXT_DESC_PTR	0xFFC00F80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR	0xFFC00F84	/* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG		0xFFC00F88	/* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT		0xFFC00F90	/* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY	0xFFC00F94	/* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT		0xFFC00F98	/* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY	0xFFC00F9C	/* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR	0xFFC00FA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR	0xFFC00FA4	/* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS	0xFFC00FA8	/* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP	0xFFC00FAC	/* MemDMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT	0xFFC00FB0	/* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT	0xFFC00FB8	/* MemDMA Stream 1 Destination Current Y Count Register */
+
+#define MDMA_S1_NEXT_DESC_PTR	0xFFC00FC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR	0xFFC00FC4	/* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG		0xFFC00FC8	/* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT		0xFFC00FD0	/* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY	0xFFC00FD4	/* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT		0xFFC00FD8	/* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY	0xFFC00FDC	/* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR	0xFFC00FE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR	0xFFC00FE4	/* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS	0xFFC00FE8	/* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP	0xFFC00FEC	/* MemDMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT	0xFFC00FF0	/* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT	0xFFC00FF8	/* MemDMA Stream 1 Source Current Y Count Register */
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL		0xFFC01000	/* PPI Control Register */
+#define PPI_STATUS		0xFFC01004	/* PPI Status Register */
+#define PPI_COUNT		0xFFC01008	/* PPI Transfer Count Register */
+#define PPI_DELAY		0xFFC0100C	/* PPI Delay Count Register */
+#define PPI_FRAME		0xFFC01010	/* PPI Frame Length Register */
+
+/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF) */
+#define TWI_CLKDIV		0xFFC01400	/* Serial Clock Divider Register */
+#define TWI_CONTROL		0xFFC01404	/* TWI Control Register */
+#define TWI_SLAVE_CTL		0xFFC01408	/* Slave Mode Control Register */
+#define TWI_SLAVE_STAT		0xFFC0140C	/* Slave Mode Status Register */
+#define TWI_SLAVE_ADDR		0xFFC01410	/* Slave Mode Address Register */
+#define TWI_MASTER_CTL		0xFFC01414	/* Master Mode Control Register */
+#define TWI_MASTER_STAT		0xFFC01418	/* Master Mode Status Register */
+#define TWI_MASTER_ADDR		0xFFC0141C	/* Master Mode Address Register */
+#define TWI_INT_STAT		0xFFC01420	/* TWI Interrupt Status Register */
+#define TWI_INT_MASK		0xFFC01424	/* TWI Master Interrupt Mask Register */
+#define TWI_FIFO_CTL		0xFFC01428	/* FIFO Control Register */
+#define TWI_FIFO_STAT		0xFFC0142C	/* FIFO Status Register */
+#define TWI_XMT_DATA8		0xFFC01480	/* FIFO Transmit Data Single Byte Register */
+#define TWI_XMT_DATA16		0xFFC01484	/* FIFO Transmit Data Double Byte Register */
+#define TWI_RCV_DATA8		0xFFC01488	/* FIFO Receive Data Single Byte Register */
+#define TWI_RCV_DATA16		0xFFC0148C	/* FIFO Receive Data Double Byte Register */
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
+#define PORTGIO			0xFFC01500	/* Port G I/O Pin State Specify Register */
+#define PORTGIO_CLEAR		0xFFC01504	/* Port G I/O Peripheral Interrupt Clear Register */
+#define PORTGIO_SET		0xFFC01508	/* Port G I/O Peripheral Interrupt Set Register */
+#define PORTGIO_TOGGLE		0xFFC0150C	/* Port G I/O Pin State Toggle Register */
+#define PORTGIO_MASKA		0xFFC01510	/* Port G I/O Mask State Specify Interrupt A Register */
+#define PORTGIO_MASKA_CLEAR	0xFFC01514	/* Port G I/O Mask Disable Interrupt A Register */
+#define PORTGIO_MASKA_SET	0xFFC01518	/* Port G I/O Mask Enable Interrupt A Register */
+#define PORTGIO_MASKA_TOGGLE	0xFFC0151C	/* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define PORTGIO_MASKB		0xFFC01520	/* Port G I/O Mask State Specify Interrupt B Register */
+#define PORTGIO_MASKB_CLEAR	0xFFC01524	/* Port G I/O Mask Disable Interrupt B Register */
+#define PORTGIO_MASKB_SET	0xFFC01528	/* Port G I/O Mask Enable Interrupt B Register */
+#define PORTGIO_MASKB_TOGGLE	0xFFC0152C	/* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define PORTGIO_DIR		0xFFC01530	/* Port G I/O Direction Register */
+#define PORTGIO_POLAR		0xFFC01534	/* Port G I/O Source Polarity Register */
+#define PORTGIO_EDGE		0xFFC01538	/* Port G I/O Source Sensitivity Register */
+#define PORTGIO_BOTH		0xFFC0153C	/* Port G I/O Set on BOTH Edges Register */
+#define PORTGIO_INEN		0xFFC01540	/* Port G I/O Input Enable Register */
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
+#define PORTHIO			0xFFC01700	/* Port H I/O Pin State Specify Register */
+#define PORTHIO_CLEAR		0xFFC01704	/* Port H I/O Peripheral Interrupt Clear Register */
+#define PORTHIO_SET		0xFFC01708	/* Port H I/O Peripheral Interrupt Set Register */
+#define PORTHIO_TOGGLE		0xFFC0170C	/* Port H I/O Pin State Toggle Register */
+#define PORTHIO_MASKA		0xFFC01710	/* Port H I/O Mask State Specify Interrupt A Register */
+#define PORTHIO_MASKA_CLEAR	0xFFC01714	/* Port H I/O Mask Disable Interrupt A Register */
+#define PORTHIO_MASKA_SET	0xFFC01718	/* Port H I/O Mask Enable Interrupt A Register */
+#define PORTHIO_MASKA_TOGGLE	0xFFC0171C	/* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define PORTHIO_MASKB		0xFFC01720	/* Port H I/O Mask State Specify Interrupt B Register */
+#define PORTHIO_MASKB_CLEAR	0xFFC01724	/* Port H I/O Mask Disable Interrupt B Register */
+#define PORTHIO_MASKB_SET	0xFFC01728	/* Port H I/O Mask Enable Interrupt B Register */
+#define PORTHIO_MASKB_TOGGLE	0xFFC0172C	/* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define PORTHIO_DIR		0xFFC01730	/* Port H I/O Direction Register */
+#define PORTHIO_POLAR		0xFFC01734	/* Port H I/O Source Polarity Register */
+#define PORTHIO_EDGE		0xFFC01738	/* Port H I/O Source Sensitivity Register */
+#define PORTHIO_BOTH		0xFFC0173C	/* Port H I/O Set on BOTH Edges Register */
+#define PORTHIO_INEN		0xFFC01740	/* Port H I/O Input Enable Register */
+
+/* UART1 Controller		(0xFFC02000 - 0xFFC020FF) */
+#define UART1_THR		0xFFC02000	/* Transmit Holding register */
+#define UART1_RBR		0xFFC02000	/* Receive Buffer register */
+#define UART1_DLL		0xFFC02000	/* Divisor Latch (Low-Byte) */
+#define UART1_IER		0xFFC02004	/* Interrupt Enable Register */
+#define UART1_DLH		0xFFC02004	/* Divisor Latch (High-Byte) */
+#define UART1_IIR		0xFFC02008	/* Interrupt Identification Register */
+#define UART1_LCR		0xFFC0200C	/* Line Control Register */
+#define UART1_MCR		0xFFC02010	/* Modem Control Register */
+#define UART1_LSR		0xFFC02014	/* Line Status Register */
+#define UART1_MSR		0xFFC02018	/* Modem Status Register */
+#define UART1_SCR		0xFFC0201C	/* SCR Scratch Register */
+#define UART1_GCTL		0xFFC02024	/* Global Control Register */
+
+/* CAN Controller		(0xFFC02A00 - 0xFFC02FFF) */
+/* For Mailboxes 0-15 */
+#define CAN_MC1			0xFFC02A00	/* Mailbox config reg 1 */
+#define CAN_MD1			0xFFC02A04	/* Mailbox direction reg 1 */
+#define CAN_TRS1		0xFFC02A08	/* Transmit Request Set reg 1 */
+#define CAN_TRR1		0xFFC02A0C	/* Transmit Request Reset reg 1 */
+#define CAN_TA1			0xFFC02A10	/* Transmit Acknowledge reg 1 */
+#define CAN_AA1			0xFFC02A14	/* Transmit Abort Acknowledge reg 1 */
+#define CAN_RMP1		0xFFC02A18	/* Receive Message Pending reg 1 */
+#define CAN_RML1		0xFFC02A1C	/* Receive Message Lost reg 1 */
+#define CAN_MBTIF1		0xFFC02A20	/* Mailbox Transmit Interrupt Flag reg 1 */
+#define CAN_MBRIF1		0xFFC02A24	/* Mailbox Receive  Interrupt Flag reg 1 */
+#define CAN_MBIM1		0xFFC02A28	/* Mailbox Interrupt Mask reg 1 */
+#define CAN_RFH1		0xFFC02A2C	/* Remote Frame Handling reg 1 */
+#define CAN_OPSS1		0xFFC02A30	/* Overwrite Protection Single Shot Xmit reg 1 */
+
+/* For Mailboxes 16-31 */
+#define CAN_MC2			0xFFC02A40	/* Mailbox config reg 2 */
+#define CAN_MD2			0xFFC02A44	/* Mailbox direction reg 2 */
+#define CAN_TRS2		0xFFC02A48	/* Transmit Request Set reg 2 */
+#define CAN_TRR2		0xFFC02A4C	/* Transmit Request Reset reg 2 */
+#define CAN_TA2			0xFFC02A50	/* Transmit Acknowledge reg 2 */
+#define CAN_AA2			0xFFC02A54	/* Transmit Abort Acknowledge reg 2 */
+#define CAN_RMP2		0xFFC02A58	/* Receive Message Pending reg 2 */
+#define CAN_RML2		0xFFC02A5C	/* Receive Message Lost reg 2 */
+#define CAN_MBTIF2		0xFFC02A60	/* Mailbox Transmit Interrupt Flag reg 2 */
+#define CAN_MBRIF2		0xFFC02A64	/* Mailbox Receive  Interrupt Flag reg 2 */
+#define CAN_MBIM2		0xFFC02A68	/* Mailbox Interrupt Mask reg 2 */
+#define CAN_RFH2		0xFFC02A6C	/* Remote Frame Handling reg 2 */
+#define CAN_OPSS2		0xFFC02A70	/* Overwrite Protection Single Shot Xmit reg 2 */
+
+/* CAN Configuration, Control, and Status Registers */
+#define CAN_CLOCK		0xFFC02A80	/* Bit Timing Configuration register 0 */
+#define CAN_TIMING		0xFFC02A84	/* Bit Timing Configuration register 1 */
+#define CAN_DEBUG		0xFFC02A88	/* Debug Register */
+#define CAN_STATUS		0xFFC02A8C	/* Global Status Register */
+#define CAN_CEC			0xFFC02A90	/* Error Counter Register */
+#define CAN_GIS			0xFFC02A94	/* Global Interrupt Status Register */
+#define CAN_GIM			0xFFC02A98	/* Global Interrupt Mask Register */
+#define CAN_GIF			0xFFC02A9C	/* Global Interrupt Flag Register */
+#define CAN_CONTROL		0xFFC02AA0	/* Master Control Register */
+#define CAN_INTR		0xFFC02AA4	/* Interrupt Pending Register */
+#define CAN_SFCMVER		0xFFC02AA8	/* Version Code Register */
+#define CAN_MBTD		0xFFC02AAC	/* Mailbox Temporary Disable Feature */
+#define CAN_EWR			0xFFC02AB0	/* Programmable Warning Level */
+#define CAN_ESR			0xFFC02AB4	/* Error Status Register */
+#define CAN_UCREG		0xFFC02AC0	/* Universal Counter Register/Capture Register */
+#define CAN_UCCNT		0xFFC02AC4	/* Universal Counter */
+#define CAN_UCRC		0xFFC02AC8	/* Universal Counter Force Reload Register */
+#define CAN_UCCNF		0xFFC02ACC	/* Universal Counter Configuration Register */
+
+/* Mailbox Acceptance Masks */
+#define CAN_AM00L		0xFFC02B00	/* Mailbox 0 Low Acceptance Mask */
+#define CAN_AM00H		0xFFC02B04	/* Mailbox 0 High Acceptance Mask */
+#define CAN_AM01L		0xFFC02B08	/* Mailbox 1 Low Acceptance Mask */
+#define CAN_AM01H		0xFFC02B0C	/* Mailbox 1 High Acceptance Mask */
+#define CAN_AM02L		0xFFC02B10	/* Mailbox 2 Low Acceptance Mask */
+#define CAN_AM02H		0xFFC02B14	/* Mailbox 2 High Acceptance Mask */
+#define CAN_AM03L		0xFFC02B18	/* Mailbox 3 Low Acceptance Mask */
+#define CAN_AM03H		0xFFC02B1C	/* Mailbox 3 High Acceptance Mask */
+#define CAN_AM04L		0xFFC02B20	/* Mailbox 4 Low Acceptance Mask */
+#define CAN_AM04H		0xFFC02B24	/* Mailbox 4 High Acceptance Mask */
+#define CAN_AM05L		0xFFC02B28	/* Mailbox 5 Low Acceptance Mask */
+#define CAN_AM05H		0xFFC02B2C	/* Mailbox 5 High Acceptance Mask */
+#define CAN_AM06L		0xFFC02B30	/* Mailbox 6 Low Acceptance Mask */
+#define CAN_AM06H		0xFFC02B34	/* Mailbox 6 High Acceptance Mask */
+#define CAN_AM07L		0xFFC02B38	/* Mailbox 7 Low Acceptance Mask */
+#define CAN_AM07H		0xFFC02B3C	/* Mailbox 7 High Acceptance Mask */
+#define CAN_AM08L		0xFFC02B40	/* Mailbox 8 Low Acceptance Mask */
+#define CAN_AM08H		0xFFC02B44	/* Mailbox 8 High Acceptance Mask */
+#define CAN_AM09L		0xFFC02B48	/* Mailbox 9 Low Acceptance Mask */
+#define CAN_AM09H		0xFFC02B4C	/* Mailbox 9 High Acceptance Mask */
+#define CAN_AM10L		0xFFC02B50	/* Mailbox 10 Low Acceptance Mask */
+#define CAN_AM10H		0xFFC02B54	/* Mailbox 10 High Acceptance Mask */
+#define CAN_AM11L		0xFFC02B58	/* Mailbox 11 Low Acceptance Mask */
+#define CAN_AM11H		0xFFC02B5C	/* Mailbox 11 High Acceptance Mask */
+#define CAN_AM12L		0xFFC02B60	/* Mailbox 12 Low Acceptance Mask */
+#define CAN_AM12H		0xFFC02B64	/* Mailbox 12 High Acceptance Mask */
+#define CAN_AM13L		0xFFC02B68	/* Mailbox 13 Low Acceptance Mask */
+#define CAN_AM13H		0xFFC02B6C	/* Mailbox 13 High Acceptance Mask */
+#define CAN_AM14L		0xFFC02B70	/* Mailbox 14 Low Acceptance Mask */
+#define CAN_AM14H		0xFFC02B74	/* Mailbox 14 High Acceptance Mask */
+#define CAN_AM15L		0xFFC02B78	/* Mailbox 15 Low Acceptance Mask */
+#define CAN_AM15H		0xFFC02B7C	/* Mailbox 15 High Acceptance Mask */
+
+#define CAN_AM16L		0xFFC02B80	/* Mailbox 16 Low Acceptance Mask */
+#define CAN_AM16H		0xFFC02B84	/* Mailbox 16 High Acceptance Mask */
+#define CAN_AM17L		0xFFC02B88	/* Mailbox 17 Low Acceptance Mask */
+#define CAN_AM17H		0xFFC02B8C	/* Mailbox 17 High Acceptance Mask */
+#define CAN_AM18L		0xFFC02B90	/* Mailbox 18 Low Acceptance Mask */
+#define CAN_AM18H		0xFFC02B94	/* Mailbox 18 High Acceptance Mask */
+#define CAN_AM19L		0xFFC02B98	/* Mailbox 19 Low Acceptance Mask */
+#define CAN_AM19H		0xFFC02B9C	/* Mailbox 19 High Acceptance Mask */
+#define CAN_AM20L		0xFFC02BA0	/* Mailbox 20 Low Acceptance Mask */
+#define CAN_AM20H		0xFFC02BA4	/* Mailbox 20 High Acceptance Mask */
+#define CAN_AM21L		0xFFC02BA8	/* Mailbox 21 Low Acceptance Mask */
+#define CAN_AM21H		0xFFC02BAC	/* Mailbox 21 High Acceptance Mask */
+#define CAN_AM22L		0xFFC02BB0	/* Mailbox 22 Low Acceptance Mask */
+#define CAN_AM22H		0xFFC02BB4	/* Mailbox 22 High Acceptance Mask */
+#define CAN_AM23L		0xFFC02BB8	/* Mailbox 23 Low Acceptance Mask */
+#define CAN_AM23H		0xFFC02BBC	/* Mailbox 23 High Acceptance Mask */
+#define CAN_AM24L		0xFFC02BC0	/* Mailbox 24 Low Acceptance Mask */
+#define CAN_AM24H		0xFFC02BC4	/* Mailbox 24 High Acceptance Mask */
+#define CAN_AM25L		0xFFC02BC8	/* Mailbox 25 Low Acceptance Mask */
+#define CAN_AM25H		0xFFC02BCC	/* Mailbox 25 High Acceptance Mask */
+#define CAN_AM26L		0xFFC02BD0	/* Mailbox 26 Low Acceptance Mask */
+#define CAN_AM26H		0xFFC02BD4	/* Mailbox 26 High Acceptance Mask */
+#define CAN_AM27L		0xFFC02BD8	/* Mailbox 27 Low Acceptance Mask */
+#define CAN_AM27H		0xFFC02BDC	/* Mailbox 27 High Acceptance Mask */
+#define CAN_AM28L		0xFFC02BE0	/* Mailbox 28 Low Acceptance Mask */
+#define CAN_AM28H		0xFFC02BE4	/* Mailbox 28 High Acceptance Mask */
+#define CAN_AM29L		0xFFC02BE8	/* Mailbox 29 Low Acceptance Mask */
+#define CAN_AM29H		0xFFC02BEC	/* Mailbox 29 High Acceptance Mask */
+#define CAN_AM30L		0xFFC02BF0	/* Mailbox 30 Low Acceptance Mask */
+#define CAN_AM30H		0xFFC02BF4	/* Mailbox 30 High Acceptance Mask */
+#define CAN_AM31L		0xFFC02BF8	/* Mailbox 31 Low Acceptance Mask */
+#define CAN_AM31H		0xFFC02BFC	/* Mailbox 31 High Acceptance Mask */
+
+/* CAN Acceptance Mask Macros */
+#define CAN_AM_L(x)		(CAN_AM00L+((x)*0x8))
+#define CAN_AM_H(x)		(CAN_AM00H+((x)*0x8))
+
+/* Mailbox Registers */
+#define CAN_MB00_DATA0		0xFFC02C00	/* Mailbox 0 Data Word 0 [15:0] Register */
+#define CAN_MB00_DATA1		0xFFC02C04	/* Mailbox 0 Data Word 1 [31:16] Register */
+#define CAN_MB00_DATA2		0xFFC02C08	/* Mailbox 0 Data Word 2 [47:32] Register */
+#define CAN_MB00_DATA3		0xFFC02C0C	/* Mailbox 0 Data Word 3 [63:48] Register */
+#define CAN_MB00_LENGTH		0xFFC02C10	/* Mailbox 0 Data Length Code Register */
+#define CAN_MB00_TIMESTAMP	0xFFC02C14	/* Mailbox 0 Time Stamp Value Register */
+#define CAN_MB00_ID0		0xFFC02C18	/* Mailbox 0 Identifier Low Register */
+#define CAN_MB00_ID1		0xFFC02C1C	/* Mailbox 0 Identifier High Register */
+
+#define CAN_MB01_DATA0		0xFFC02C20	/* Mailbox 1 Data Word 0 [15:0] Register */
+#define CAN_MB01_DATA1		0xFFC02C24	/* Mailbox 1 Data Word 1 [31:16] Register */
+#define CAN_MB01_DATA2		0xFFC02C28	/* Mailbox 1 Data Word 2 [47:32] Register */
+#define CAN_MB01_DATA3		0xFFC02C2C	/* Mailbox 1 Data Word 3 [63:48] Register */
+#define CAN_MB01_LENGTH		0xFFC02C30	/* Mailbox 1 Data Length Code Register */
+#define CAN_MB01_TIMESTAMP	0xFFC02C34	/* Mailbox 1 Time Stamp Value Register */
+#define CAN_MB01_ID0		0xFFC02C38	/* Mailbox 1 Identifier Low Register */
+#define CAN_MB01_ID1		0xFFC02C3C	/* Mailbox 1 Identifier High Register */
+
+#define CAN_MB02_DATA0		0xFFC02C40	/* Mailbox 2 Data Word 0 [15:0] Register */
+#define CAN_MB02_DATA1		0xFFC02C44	/* Mailbox 2 Data Word 1 [31:16] Register */
+#define CAN_MB02_DATA2		0xFFC02C48	/* Mailbox 2 Data Word 2 [47:32] Register */
+#define CAN_MB02_DATA3		0xFFC02C4C	/* Mailbox 2 Data Word 3 [63:48] Register */
+#define CAN_MB02_LENGTH		0xFFC02C50	/* Mailbox 2 Data Length Code Register */
+#define CAN_MB02_TIMESTAMP	0xFFC02C54	/* Mailbox 2 Time Stamp Value Register */
+#define CAN_MB02_ID0		0xFFC02C58	/* Mailbox 2 Identifier Low Register */
+#define CAN_MB02_ID1		0xFFC02C5C	/* Mailbox 2 Identifier High Register */
+
+#define CAN_MB03_DATA0		0xFFC02C60	/* Mailbox 3 Data Word 0 [15:0] Register */
+#define CAN_MB03_DATA1		0xFFC02C64	/* Mailbox 3 Data Word 1 [31:16] Register */
+#define CAN_MB03_DATA2		0xFFC02C68	/* Mailbox 3 Data Word 2 [47:32] Register */
+#define CAN_MB03_DATA3		0xFFC02C6C	/* Mailbox 3 Data Word 3 [63:48] Register */
+#define CAN_MB03_LENGTH		0xFFC02C70	/* Mailbox 3 Data Length Code Register */
+#define CAN_MB03_TIMESTAMP	0xFFC02C74	/* Mailbox 3 Time Stamp Value Register */
+#define CAN_MB03_ID0		0xFFC02C78	/* Mailbox 3 Identifier Low Register */
+#define CAN_MB03_ID1		0xFFC02C7C	/* Mailbox 3 Identifier High Register */
+
+#define CAN_MB04_DATA0		0xFFC02C80	/* Mailbox 4 Data Word 0 [15:0] Register */
+#define CAN_MB04_DATA1		0xFFC02C84	/* Mailbox 4 Data Word 1 [31:16] Register */
+#define CAN_MB04_DATA2		0xFFC02C88	/* Mailbox 4 Data Word 2 [47:32] Register */
+#define CAN_MB04_DATA3		0xFFC02C8C	/* Mailbox 4 Data Word 3 [63:48] Register */
+#define CAN_MB04_LENGTH		0xFFC02C90	/* Mailbox 4 Data Length Code Register */
+#define CAN_MB04_TIMESTAMP	0xFFC02C94	/* Mailbox 4 Time Stamp Value Register */
+#define CAN_MB04_ID0		0xFFC02C98	/* Mailbox 4 Identifier Low Register */
+#define CAN_MB04_ID1		0xFFC02C9C	/* Mailbox 4 Identifier High Register */
+
+#define CAN_MB05_DATA0		0xFFC02CA0	/* Mailbox 5 Data Word 0 [15:0] Register */
+#define CAN_MB05_DATA1		0xFFC02CA4	/* Mailbox 5 Data Word 1 [31:16] Register */
+#define CAN_MB05_DATA2		0xFFC02CA8	/* Mailbox 5 Data Word 2 [47:32] Register */
+#define CAN_MB05_DATA3		0xFFC02CAC	/* Mailbox 5 Data Word 3 [63:48] Register */
+#define CAN_MB05_LENGTH		0xFFC02CB0	/* Mailbox 5 Data Length Code Register */
+#define CAN_MB05_TIMESTAMP	0xFFC02CB4	/* Mailbox 5 Time Stamp Value Register */
+#define CAN_MB05_ID0		0xFFC02CB8	/* Mailbox 5 Identifier Low Register */
+#define CAN_MB05_ID1		0xFFC02CBC	/* Mailbox 5 Identifier High Register */
+
+#define CAN_MB06_DATA0		0xFFC02CC0	/* Mailbox 6 Data Word 0 [15:0] Register */
+#define CAN_MB06_DATA1		0xFFC02CC4	/* Mailbox 6 Data Word 1 [31:16] Register */
+#define CAN_MB06_DATA2		0xFFC02CC8	/* Mailbox 6 Data Word 2 [47:32] Register */
+#define CAN_MB06_DATA3		0xFFC02CCC	/* Mailbox 6 Data Word 3 [63:48] Register */
+#define CAN_MB06_LENGTH		0xFFC02CD0	/* Mailbox 6 Data Length Code Register */
+#define CAN_MB06_TIMESTAMP	0xFFC02CD4	/* Mailbox 6 Time Stamp Value Register */
+#define CAN_MB06_ID0		0xFFC02CD8	/* Mailbox 6 Identifier Low Register */
+#define CAN_MB06_ID1		0xFFC02CDC	/* Mailbox 6 Identifier High Register */
+
+#define CAN_MB07_DATA0		0xFFC02CE0	/* Mailbox 7 Data Word 0 [15:0] Register */
+#define CAN_MB07_DATA1		0xFFC02CE4	/* Mailbox 7 Data Word 1 [31:16] Register */
+#define CAN_MB07_DATA2		0xFFC02CE8	/* Mailbox 7 Data Word 2 [47:32] Register */
+#define CAN_MB07_DATA3		0xFFC02CEC	/* Mailbox 7 Data Word 3 [63:48] Register */
+#define CAN_MB07_LENGTH		0xFFC02CF0	/* Mailbox 7 Data Length Code Register */
+#define CAN_MB07_TIMESTAMP	0xFFC02CF4	/* Mailbox 7 Time Stamp Value Register */
+#define CAN_MB07_ID0		0xFFC02CF8	/* Mailbox 7 Identifier Low Register */
+#define CAN_MB07_ID1		0xFFC02CFC	/* Mailbox 7 Identifier High Register */
+
+#define CAN_MB08_DATA0		0xFFC02D00	/* Mailbox 8 Data Word 0 [15:0] Register */
+#define CAN_MB08_DATA1		0xFFC02D04	/* Mailbox 8 Data Word 1 [31:16] Register */
+#define CAN_MB08_DATA2		0xFFC02D08	/* Mailbox 8 Data Word 2 [47:32] Register */
+#define CAN_MB08_DATA3		0xFFC02D0C	/* Mailbox 8 Data Word 3 [63:48] Register */
+#define CAN_MB08_LENGTH		0xFFC02D10	/* Mailbox 8 Data Length Code Register */
+#define CAN_MB08_TIMESTAMP	0xFFC02D14	/* Mailbox 8 Time Stamp Value Register */
+#define CAN_MB08_ID0		0xFFC02D18	/* Mailbox 8 Identifier Low Register */
+#define CAN_MB08_ID1		0xFFC02D1C	/* Mailbox 8 Identifier High Register */
+
+#define CAN_MB09_DATA0		0xFFC02D20	/* Mailbox 9 Data Word 0 [15:0] Register */
+#define CAN_MB09_DATA1		0xFFC02D24	/* Mailbox 9 Data Word 1 [31:16] Register */
+#define CAN_MB09_DATA2		0xFFC02D28	/* Mailbox 9 Data Word 2 [47:32] Register */
+#define CAN_MB09_DATA3		0xFFC02D2C	/* Mailbox 9 Data Word 3 [63:48] Register */
+#define CAN_MB09_LENGTH		0xFFC02D30	/* Mailbox 9 Data Length Code Register */
+#define CAN_MB09_TIMESTAMP	0xFFC02D34	/* Mailbox 9 Time Stamp Value Register */
+#define CAN_MB09_ID0		0xFFC02D38	/* Mailbox 9 Identifier Low Register */
+#define CAN_MB09_ID1		0xFFC02D3C	/* Mailbox 9 Identifier High Register */
+
+#define CAN_MB10_DATA0		0xFFC02D40	/* Mailbox 10 Data Word 0 [15:0] Register */
+#define CAN_MB10_DATA1		0xFFC02D44	/* Mailbox 10 Data Word 1 [31:16] Register */
+#define CAN_MB10_DATA2		0xFFC02D48	/* Mailbox 10 Data Word 2 [47:32] Register */
+#define CAN_MB10_DATA3		0xFFC02D4C	/* Mailbox 10 Data Word 3 [63:48] Register */
+#define CAN_MB10_LENGTH		0xFFC02D50	/* Mailbox 10 Data Length Code Register */
+#define CAN_MB10_TIMESTAMP	0xFFC02D54	/* Mailbox 10 Time Stamp Value Register */
+#define CAN_MB10_ID0		0xFFC02D58	/* Mailbox 10 Identifier Low Register */
+#define CAN_MB10_ID1		0xFFC02D5C	/* Mailbox 10 Identifier High Register */
+
+#define CAN_MB11_DATA0		0xFFC02D60	/* Mailbox 11 Data Word 0 [15:0] Register */
+#define CAN_MB11_DATA1		0xFFC02D64	/* Mailbox 11 Data Word 1 [31:16] Register */
+#define CAN_MB11_DATA2		0xFFC02D68	/* Mailbox 11 Data Word 2 [47:32] Register */
+#define CAN_MB11_DATA3		0xFFC02D6C	/* Mailbox 11 Data Word 3 [63:48] Register */
+#define CAN_MB11_LENGTH		0xFFC02D70	/* Mailbox 11 Data Length Code Register */
+#define CAN_MB11_TIMESTAMP	0xFFC02D74	/* Mailbox 11 Time Stamp Value Register */
+#define CAN_MB11_ID0		0xFFC02D78	/* Mailbox 11 Identifier Low Register */
+#define CAN_MB11_ID1		0xFFC02D7C	/* Mailbox 11 Identifier High Register */
+
+#define CAN_MB12_DATA0		0xFFC02D80	/* Mailbox 12 Data Word 0 [15:0] Register */
+#define CAN_MB12_DATA1		0xFFC02D84	/* Mailbox 12 Data Word 1 [31:16] Register */
+#define CAN_MB12_DATA2		0xFFC02D88	/* Mailbox 12 Data Word 2 [47:32] Register */
+#define CAN_MB12_DATA3		0xFFC02D8C	/* Mailbox 12 Data Word 3 [63:48] Register */
+#define CAN_MB12_LENGTH		0xFFC02D90	/* Mailbox 12 Data Length Code Register */
+#define CAN_MB12_TIMESTAMP	0xFFC02D94	/* Mailbox 12 Time Stamp Value Register */
+#define CAN_MB12_ID0		0xFFC02D98	/* Mailbox 12 Identifier Low Register */
+#define CAN_MB12_ID1		0xFFC02D9C	/* Mailbox 12 Identifier High Register */
+
+#define CAN_MB13_DATA0		0xFFC02DA0	/* Mailbox 13 Data Word 0 [15:0] Register */
+#define CAN_MB13_DATA1		0xFFC02DA4	/* Mailbox 13 Data Word 1 [31:16] Register */
+#define CAN_MB13_DATA2		0xFFC02DA8	/* Mailbox 13 Data Word 2 [47:32] Register */
+#define CAN_MB13_DATA3		0xFFC02DAC	/* Mailbox 13 Data Word 3 [63:48] Register */
+#define CAN_MB13_LENGTH		0xFFC02DB0	/* Mailbox 13 Data Length Code Register */
+#define CAN_MB13_TIMESTAMP	0xFFC02DB4	/* Mailbox 13 Time Stamp Value Register */
+#define CAN_MB13_ID0		0xFFC02DB8	/* Mailbox 13 Identifier Low Register */
+#define CAN_MB13_ID1		0xFFC02DBC	/* Mailbox 13 Identifier High Register */
+
+#define CAN_MB14_DATA0		0xFFC02DC0	/* Mailbox 14 Data Word 0 [15:0] Register */
+#define CAN_MB14_DATA1		0xFFC02DC4	/* Mailbox 14 Data Word 1 [31:16] Register */
+#define CAN_MB14_DATA2		0xFFC02DC8	/* Mailbox 14 Data Word 2 [47:32] Register */
+#define CAN_MB14_DATA3		0xFFC02DCC	/* Mailbox 14 Data Word 3 [63:48] Register */
+#define CAN_MB14_LENGTH		0xFFC02DD0	/* Mailbox 14 Data Length Code Register */
+#define CAN_MB14_TIMESTAMP	0xFFC02DD4	/* Mailbox 14 Time Stamp Value Register */
+#define CAN_MB14_ID0		0xFFC02DD8	/* Mailbox 14 Identifier Low Register */
+#define CAN_MB14_ID1		0xFFC02DDC	/* Mailbox 14 Identifier High Register */
+
+#define CAN_MB15_DATA0		0xFFC02DE0	/* Mailbox 15 Data Word 0 [15:0] Register */
+#define CAN_MB15_DATA1		0xFFC02DE4	/* Mailbox 15 Data Word 1 [31:16] Register */
+#define CAN_MB15_DATA2		0xFFC02DE8	/* Mailbox 15 Data Word 2 [47:32] Register */
+#define CAN_MB15_DATA3		0xFFC02DEC	/* Mailbox 15 Data Word 3 [63:48] Register */
+#define CAN_MB15_LENGTH		0xFFC02DF0	/* Mailbox 15 Data Length Code Register */
+#define CAN_MB15_TIMESTAMP	0xFFC02DF4	/* Mailbox 15 Time Stamp Value Register */
+#define CAN_MB15_ID0		0xFFC02DF8	/* Mailbox 15 Identifier Low Register */
+#define CAN_MB15_ID1		0xFFC02DFC	/* Mailbox 15 Identifier High Register */
+
+#define CAN_MB16_DATA0		0xFFC02E00	/* Mailbox 16 Data Word 0 [15:0] Register */
+#define CAN_MB16_DATA1		0xFFC02E04	/* Mailbox 16 Data Word 1 [31:16] Register */
+#define CAN_MB16_DATA2		0xFFC02E08	/* Mailbox 16 Data Word 2 [47:32] Register */
+#define CAN_MB16_DATA3		0xFFC02E0C	/* Mailbox 16 Data Word 3 [63:48] Register */
+#define CAN_MB16_LENGTH		0xFFC02E10	/* Mailbox 16 Data Length Code Register */
+#define CAN_MB16_TIMESTAMP	0xFFC02E14	/* Mailbox 16 Time Stamp Value Register */
+#define CAN_MB16_ID0		0xFFC02E18	/* Mailbox 16 Identifier Low Register */
+#define CAN_MB16_ID1		0xFFC02E1C	/* Mailbox 16 Identifier High Register */
+
+#define CAN_MB17_DATA0		0xFFC02E20	/* Mailbox 17 Data Word 0 [15:0] Register */
+#define CAN_MB17_DATA1		0xFFC02E24	/* Mailbox 17 Data Word 1 [31:16] Register */
+#define CAN_MB17_DATA2		0xFFC02E28	/* Mailbox 17 Data Word 2 [47:32] Register */
+#define CAN_MB17_DATA3		0xFFC02E2C	/* Mailbox 17 Data Word 3 [63:48] Register */
+#define CAN_MB17_LENGTH		0xFFC02E30	/* Mailbox 17 Data Length Code Register */
+#define CAN_MB17_TIMESTAMP	0xFFC02E34	/* Mailbox 17 Time Stamp Value Register */
+#define CAN_MB17_ID0		0xFFC02E38	/* Mailbox 17 Identifier Low Register */
+#define CAN_MB17_ID1		0xFFC02E3C	/* Mailbox 17 Identifier High Register */
+
+#define CAN_MB18_DATA0		0xFFC02E40	/* Mailbox 18 Data Word 0 [15:0] Register */
+#define CAN_MB18_DATA1		0xFFC02E44	/* Mailbox 18 Data Word 1 [31:16] Register */
+#define CAN_MB18_DATA2		0xFFC02E48	/* Mailbox 18 Data Word 2 [47:32] Register */
+#define CAN_MB18_DATA3		0xFFC02E4C	/* Mailbox 18 Data Word 3 [63:48] Register */
+#define CAN_MB18_LENGTH		0xFFC02E50	/* Mailbox 18 Data Length Code Register */
+#define CAN_MB18_TIMESTAMP	0xFFC02E54	/* Mailbox 18 Time Stamp Value Register */
+#define CAN_MB18_ID0		0xFFC02E58	/* Mailbox 18 Identifier Low Register */
+#define CAN_MB18_ID1		0xFFC02E5C	/* Mailbox 18 Identifier High Register */
+
+#define CAN_MB19_DATA0		0xFFC02E60	/* Mailbox 19 Data Word 0 [15:0] Register */
+#define CAN_MB19_DATA1		0xFFC02E64	/* Mailbox 19 Data Word 1 [31:16] Register */
+#define CAN_MB19_DATA2		0xFFC02E68	/* Mailbox 19 Data Word 2 [47:32] Register */
+#define CAN_MB19_DATA3		0xFFC02E6C	/* Mailbox 19 Data Word 3 [63:48] Register */
+#define CAN_MB19_LENGTH		0xFFC02E70	/* Mailbox 19 Data Length Code Register */
+#define CAN_MB19_TIMESTAMP	0xFFC02E74	/* Mailbox 19 Time Stamp Value Register */
+#define CAN_MB19_ID0		0xFFC02E78	/* Mailbox 19 Identifier Low Register */
+#define CAN_MB19_ID1		0xFFC02E7C	/* Mailbox 19 Identifier High Register */
+
+#define CAN_MB20_DATA0		0xFFC02E80	/* Mailbox 20 Data Word 0 [15:0] Register */
+#define CAN_MB20_DATA1		0xFFC02E84	/* Mailbox 20 Data Word 1 [31:16] Register */
+#define CAN_MB20_DATA2		0xFFC02E88	/* Mailbox 20 Data Word 2 [47:32] Register */
+#define CAN_MB20_DATA3		0xFFC02E8C	/* Mailbox 20 Data Word 3 [63:48] Register */
+#define CAN_MB20_LENGTH		0xFFC02E90	/* Mailbox 20 Data Length Code Register */
+#define CAN_MB20_TIMESTAMP	0xFFC02E94	/* Mailbox 20 Time Stamp Value Register */
+#define CAN_MB20_ID0		0xFFC02E98	/* Mailbox 20 Identifier Low Register */
+#define CAN_MB20_ID1		0xFFC02E9C	/* Mailbox 20 Identifier High Register */
+
+#define CAN_MB21_DATA0		0xFFC02EA0	/* Mailbox 21 Data Word 0 [15:0] Register */
+#define CAN_MB21_DATA1		0xFFC02EA4	/* Mailbox 21 Data Word 1 [31:16] Register */
+#define CAN_MB21_DATA2		0xFFC02EA8	/* Mailbox 21 Data Word 2 [47:32] Register */
+#define CAN_MB21_DATA3		0xFFC02EAC	/* Mailbox 21 Data Word 3 [63:48] Register */
+#define CAN_MB21_LENGTH		0xFFC02EB0	/* Mailbox 21 Data Length Code Register */
+#define CAN_MB21_TIMESTAMP	0xFFC02EB4	/* Mailbox 21 Time Stamp Value Register */
+#define CAN_MB21_ID0		0xFFC02EB8	/* Mailbox 21 Identifier Low Register */
+#define CAN_MB21_ID1		0xFFC02EBC	/* Mailbox 21 Identifier High Register */
+
+#define CAN_MB22_DATA0		0xFFC02EC0	/* Mailbox 22 Data Word 0 [15:0] Register */
+#define CAN_MB22_DATA1		0xFFC02EC4	/* Mailbox 22 Data Word 1 [31:16] Register */
+#define CAN_MB22_DATA2		0xFFC02EC8	/* Mailbox 22 Data Word 2 [47:32] Register */
+#define CAN_MB22_DATA3		0xFFC02ECC	/* Mailbox 22 Data Word 3 [63:48] Register */
+#define CAN_MB22_LENGTH		0xFFC02ED0	/* Mailbox 22 Data Length Code Register */
+#define CAN_MB22_TIMESTAMP	0xFFC02ED4	/* Mailbox 22 Time Stamp Value Register */
+#define CAN_MB22_ID0		0xFFC02ED8	/* Mailbox 22 Identifier Low Register */
+#define CAN_MB22_ID1		0xFFC02EDC	/* Mailbox 22 Identifier High Register */
+
+#define CAN_MB23_DATA0		0xFFC02EE0	/* Mailbox 23 Data Word 0 [15:0] Register */
+#define CAN_MB23_DATA1		0xFFC02EE4	/* Mailbox 23 Data Word 1 [31:16] Register */
+#define CAN_MB23_DATA2		0xFFC02EE8	/* Mailbox 23 Data Word 2 [47:32] Register */
+#define CAN_MB23_DATA3		0xFFC02EEC	/* Mailbox 23 Data Word 3 [63:48] Register */
+#define CAN_MB23_LENGTH		0xFFC02EF0	/* Mailbox 23 Data Length Code Register */
+#define CAN_MB23_TIMESTAMP	0xFFC02EF4	/* Mailbox 23 Time Stamp Value Register */
+#define CAN_MB23_ID0		0xFFC02EF8	/* Mailbox 23 Identifier Low Register */
+#define CAN_MB23_ID1		0xFFC02EFC	/* Mailbox 23 Identifier High Register */
+
+#define CAN_MB24_DATA0		0xFFC02F00	/* Mailbox 24 Data Word 0 [15:0] Register */
+#define CAN_MB24_DATA1		0xFFC02F04	/* Mailbox 24 Data Word 1 [31:16] Register */
+#define CAN_MB24_DATA2		0xFFC02F08	/* Mailbox 24 Data Word 2 [47:32] Register */
+#define CAN_MB24_DATA3		0xFFC02F0C	/* Mailbox 24 Data Word 3 [63:48] Register */
+#define CAN_MB24_LENGTH		0xFFC02F10	/* Mailbox 24 Data Length Code Register */
+#define CAN_MB24_TIMESTAMP	0xFFC02F14	/* Mailbox 24 Time Stamp Value Register */
+#define CAN_MB24_ID0		0xFFC02F18	/* Mailbox 24 Identifier Low Register */
+#define CAN_MB24_ID1		0xFFC02F1C	/* Mailbox 24 Identifier High Register */
+
+#define CAN_MB25_DATA0		0xFFC02F20	/* Mailbox 25 Data Word 0 [15:0] Register */
+#define CAN_MB25_DATA1		0xFFC02F24	/* Mailbox 25 Data Word 1 [31:16] Register */
+#define CAN_MB25_DATA2		0xFFC02F28	/* Mailbox 25 Data Word 2 [47:32] Register */
+#define CAN_MB25_DATA3		0xFFC02F2C	/* Mailbox 25 Data Word 3 [63:48] Register */
+#define CAN_MB25_LENGTH		0xFFC02F30	/* Mailbox 25 Data Length Code Register */
+#define CAN_MB25_TIMESTAMP	0xFFC02F34	/* Mailbox 25 Time Stamp Value Register */
+#define CAN_MB25_ID0		0xFFC02F38	/* Mailbox 25 Identifier Low Register */
+#define CAN_MB25_ID1		0xFFC02F3C	/* Mailbox 25 Identifier High Register */
+
+#define CAN_MB26_DATA0		0xFFC02F40	/* Mailbox 26 Data Word 0 [15:0] Register */
+#define CAN_MB26_DATA1		0xFFC02F44	/* Mailbox 26 Data Word 1 [31:16] Register */
+#define CAN_MB26_DATA2		0xFFC02F48	/* Mailbox 26 Data Word 2 [47:32] Register */
+#define CAN_MB26_DATA3		0xFFC02F4C	/* Mailbox 26 Data Word 3 [63:48] Register */
+#define CAN_MB26_LENGTH		0xFFC02F50	/* Mailbox 26 Data Length Code Register */
+#define CAN_MB26_TIMESTAMP	0xFFC02F54	/* Mailbox 26 Time Stamp Value Register */
+#define CAN_MB26_ID0		0xFFC02F58	/* Mailbox 26 Identifier Low Register */
+#define CAN_MB26_ID1		0xFFC02F5C	/* Mailbox 26 Identifier High Register */
+
+#define CAN_MB27_DATA0		0xFFC02F60	/* Mailbox 27 Data Word 0 [15:0] Register */
+#define CAN_MB27_DATA1		0xFFC02F64	/* Mailbox 27 Data Word 1 [31:16] Register */
+#define CAN_MB27_DATA2		0xFFC02F68	/* Mailbox 27 Data Word 2 [47:32] Register */
+#define CAN_MB27_DATA3		0xFFC02F6C	/* Mailbox 27 Data Word 3 [63:48] Register */
+#define CAN_MB27_LENGTH		0xFFC02F70	/* Mailbox 27 Data Length Code Register */
+#define CAN_MB27_TIMESTAMP	0xFFC02F74	/* Mailbox 27 Time Stamp Value Register */
+#define CAN_MB27_ID0		0xFFC02F78	/* Mailbox 27 Identifier Low Register */
+#define CAN_MB27_ID1		0xFFC02F7C	/* Mailbox 27 Identifier High Register */
+
+#define CAN_MB28_DATA0		0xFFC02F80	/* Mailbox 28 Data Word 0 [15:0] Register */
+#define CAN_MB28_DATA1		0xFFC02F84	/* Mailbox 28 Data Word 1 [31:16] Register */
+#define CAN_MB28_DATA2		0xFFC02F88	/* Mailbox 28 Data Word 2 [47:32] Register */
+#define CAN_MB28_DATA3		0xFFC02F8C	/* Mailbox 28 Data Word 3 [63:48] Register */
+#define CAN_MB28_LENGTH		0xFFC02F90	/* Mailbox 28 Data Length Code Register */
+#define CAN_MB28_TIMESTAMP	0xFFC02F94	/* Mailbox 28 Time Stamp Value Register */
+#define CAN_MB28_ID0		0xFFC02F98	/* Mailbox 28 Identifier Low Register */
+#define CAN_MB28_ID1		0xFFC02F9C	/* Mailbox 28 Identifier High Register */
+
+#define CAN_MB29_DATA0		0xFFC02FA0	/* Mailbox 29 Data Word 0 [15:0] Register */
+#define CAN_MB29_DATA1		0xFFC02FA4	/* Mailbox 29 Data Word 1 [31:16] Register */
+#define CAN_MB29_DATA2		0xFFC02FA8	/* Mailbox 29 Data Word 2 [47:32] Register */
+#define CAN_MB29_DATA3		0xFFC02FAC	/* Mailbox 29 Data Word 3 [63:48] Register */
+#define CAN_MB29_LENGTH		0xFFC02FB0	/* Mailbox 29 Data Length Code Register */
+#define CAN_MB29_TIMESTAMP	0xFFC02FB4	/* Mailbox 29 Time Stamp Value Register */
+#define CAN_MB29_ID0		0xFFC02FB8	/* Mailbox 29 Identifier Low Register */
+#define CAN_MB29_ID1		0xFFC02FBC	/* Mailbox 29 Identifier High Register */
+
+#define CAN_MB30_DATA0		0xFFC02FC0	/* Mailbox 30 Data Word 0 [15:0] Register */
+#define CAN_MB30_DATA1		0xFFC02FC4	/* Mailbox 30 Data Word 1 [31:16] Register */
+#define CAN_MB30_DATA2		0xFFC02FC8	/* Mailbox 30 Data Word 2 [47:32] Register */
+#define CAN_MB30_DATA3		0xFFC02FCC	/* Mailbox 30 Data Word 3 [63:48] Register */
+#define CAN_MB30_LENGTH		0xFFC02FD0	/* Mailbox 30 Data Length Code Register */
+#define CAN_MB30_TIMESTAMP	0xFFC02FD4	/* Mailbox 30 Time Stamp Value Register */
+#define CAN_MB30_ID0		0xFFC02FD8	/* Mailbox 30 Identifier Low Register */
+#define CAN_MB30_ID1		0xFFC02FDC	/* Mailbox 30 Identifier High Register */
+
+#define CAN_MB31_DATA0		0xFFC02FE0	/* Mailbox 31 Data Word 0 [15:0] Register */
+#define CAN_MB31_DATA1		0xFFC02FE4	/* Mailbox 31 Data Word 1 [31:16] Register */
+#define CAN_MB31_DATA2		0xFFC02FE8	/* Mailbox 31 Data Word 2 [47:32] Register */
+#define CAN_MB31_DATA3		0xFFC02FEC	/* Mailbox 31 Data Word 3 [63:48] Register */
+#define CAN_MB31_LENGTH		0xFFC02FF0	/* Mailbox 31 Data Length Code Register */
+#define CAN_MB31_TIMESTAMP	0xFFC02FF4	/* Mailbox 31 Time Stamp Value Register */
+#define CAN_MB31_ID0		0xFFC02FF8	/* Mailbox 31 Identifier Low Register */
+#define CAN_MB31_ID1		0xFFC02FFC	/* Mailbox 31 Identifier High Register */
+
+/* CAN Mailbox Area Macros */
+#define CAN_MB_ID1(x)		(CAN_MB00_ID1+((x)*0x20))
+#define CAN_MB_ID0(x)		(CAN_MB00_ID0+((x)*0x20))
+#define CAN_MB_TIMESTAMP(x)	(CAN_MB00_TIMESTAMP+((x)*0x20))
+#define CAN_MB_LENGTH(x)	(CAN_MB00_LENGTH+((x)*0x20))
+#define CAN_MB_DATA3(x)		(CAN_MB00_DATA3+((x)*0x20))
+#define CAN_MB_DATA2(x)		(CAN_MB00_DATA2+((x)*0x20))
+#define CAN_MB_DATA1(x)		(CAN_MB00_DATA1+((x)*0x20))
+#define CAN_MB_DATA0(x)		(CAN_MB00_DATA0+((x)*0x20))
+
+/* Pin Control Registers	(0xFFC03200 - 0xFFC032FF) */
+#define PORTF_FER		0xFFC03200	/* Port F Function Enable Register (Alternate/Flag*) */
+#define PORTG_FER		0xFFC03204	/* Port G Function Enable Register (Alternate/Flag*) */
+#define PORTH_FER		0xFFC03208	/* Port H Function Enable Register (Alternate/Flag*) */
+#define PORT_MUX		0xFFC0320C	/* Port Multiplexer Control Register */
+
+/* Handshake MDMA Registers	(0xFFC03300 - 0xFFC033FF) */
+#define HMDMA0_CONTROL		0xFFC03300	/* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT		0xFFC03304	/* HMDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT		0xFFC03308	/* HMDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT		0xFFC0330C	/* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW	0xFFC03310	/* HMDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT		0xFFC03314	/* HMDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT		0xFFC03318	/* HMDMA0 Current Block Count Register */
+
+#define HMDMA1_CONTROL		0xFFC03340	/* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT		0xFFC03344	/* HMDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT		0xFFC03348	/* HMDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT		0xFFC0334C	/* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW	0xFFC03350	/* HMDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT		0xFFC03354	/* HMDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT		0xFFC03358	/* HMDMA1 Current Block Count Register */
+
+/*
+ * System MMR Register Bits And Macros
+ *
+ * Disclaimer:	All macros are intended to make C and Assembly code more readable.
+ *	Use these macros carefully, as any that do left shifts for field
+ *	depositing will result in the lower order bits being destroyed.  Any
+ *	macro that shifts left to properly position the bit-field should be
+ *	used as part of an OR to initialize a register and NOT as a dynamic
+ *	modifier UNLESS the lower order bits are saved and ORed back in when
+ *	the macro is used.
+ */
+/*
+ * PLL AND RESET MASKS
+ * PLL_CTL Masks
+ */
+#define DF			0x0001		/* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF			0x0002		/* PLL Not Powered */
+#define STOPCK			0x0008		/* Core Clock Off */
+#define PDWN			0x0020		/* Enter Deep Sleep Mode */
+#define	IN_DELAY		0x0040		/* Add 200ps Delay To EBIU Input Latches */
+#define	OUT_DELAY		0x0080		/* Add 200ps Delay To EBIU Output Signals */
+#define BYPASS			0x0100		/* Bypass the PLL */
+#define	MSEL			0x7E00		/* Multiplier Select For CCLK/VCO Factors */
+/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
+#define	SET_MSEL(x)		(((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+
+/* PLL_DIV Masks */
+#define SSEL			0x000F		/* System Select */
+#define	CSEL			0x0030		/* Core Select */
+#define CSEL_DIV1		0x0000		/* CCLK = VCO / 1 */
+#define CSEL_DIV2		0x0010		/* CCLK = VCO / 2 */
+#define	CSEL_DIV4		0x0020		/* CCLK = VCO / 4 */
+#define	CSEL_DIV8		0x0030		/* CCLK = VCO / 8 */
+
+#define CCLK_DIV1		CSEL_DIV1
+#define CCLK_DIV2		CSEL_DIV2
+#define CCLK_DIV4		CSEL_DIV4
+#define CCLK_DIV8		CSEL_DIV8
+/* PLL_DIV Macros */
+#define SET_SSEL(x)		((x)&0xF)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+
+/* VR_CTL Masks */
+#define	FREQ			0x0003		/* Switching Oscillator Frequency For Regulator */
+#define	HIBERNATE		0x0000		/* Powerdown/Bypass On-Board Regulation */
+#define	FREQ_333		0x0001		/* Switching Frequency Is 333 kHz */
+#define	FREQ_667		0x0002		/* Switching Frequency Is 667 kHz */
+#define	FREQ_1000		0x0003		/* Switching Frequency Is 1 MHz */
+
+#define GAIN			0x000C		/* Voltage Level Gain */
+#define	GAIN_5			0x0000		/* GAIN = 5 */
+#define	GAIN_10			0x0004		/* GAIN = 10 */
+#define	GAIN_20			0x0008		/* GAIN = 20 */
+#define	GAIN_50			0x000C		/* GAIN = 50 */
+
+#define	VLEV			0x00F0		/* Internal Voltage Level */
+#define	VLEV_085		0x0060		/* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define	VLEV_090		0x0070		/* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define	VLEV_095		0x0080		/* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define	VLEV_100		0x0090		/* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define	VLEV_105		0x00A0		/* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define	VLEV_110		0x00B0		/* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define	VLEV_115		0x00C0		/* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define	VLEV_120		0x00D0		/* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define	VLEV_125		0x00E0		/* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define	VLEV_130		0x00F0		/* VLEV = 1.30 V (-5% - +10% Accuracy) */
+
+#define	WAKE			0x0100		/* Enable RTC/Reset Wakeup From Hibernate */
+#define	CANWE			0x0200		/* Enable CAN Wakeup From Hibernate */
+#define	PHYWE			0x0400		/* Enable PHY Wakeup From Hibernate */
+#define	CLKBUFOE		0x4000		/* CLKIN Buffer Output Enable */
+#define	PHYCLKOE		CLKBUFOE	/* Alternative legacy name for the above */
+#define	CKELOW			0x8000		/* Enable Drive CKE Low During Reset */
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED	0x0001		/* Processor In Active Mode With PLL Enabled */
+#define	FULL_ON			0x0002		/* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED	0x0004		/* Processor In Active Mode With PLL Disabled */
+#define	PLL_LOCKED		0x0020		/* PLL_LOCKCNT Has Been Reached */
+
+/* SWRST Masks */
+#define SYSTEM_RESET		0x0007		/* Initiates A System Software Reset */
+#define	DOUBLE_FAULT		0x0008		/* Core Double Fault Causes Reset */
+#define RESET_DOUBLE		0x2000		/* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG		0x4000		/* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE		0x8000		/* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks */
+#define BMODE			0x0007		/* Boot Mode - Latched During HW Reset From Mode Pins */
+#define	NOBOOT			0x0010		/* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+
+/*
+ * SYSTEM INTERRUPT CONTROLLER MASKS
+ */
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
+#define IRQ_PLL_WAKEUP		0x00000001	/* PLL Wakeup Interrupt */
+#define IRQ_ERROR1		0x00000002	/* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
+#define IRQ_ERROR2		0x00000004	/* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
+#define IRQ_RTC			0x00000008	/* Real Time Clock Interrupt */
+#define IRQ_DMA0		0x00000010	/* DMA Channel 0 (PPI) Interrupt */
+#define IRQ_DMA3		0x00000020	/* DMA Channel 3 (SPORT0 RX) Interrupt */
+#define IRQ_DMA4		0x00000040	/* DMA Channel 4 (SPORT0 TX) Interrupt */
+#define IRQ_DMA5		0x00000080	/* DMA Channel 5 (SPORT1 RX) Interrupt */
+
+#define IRQ_DMA6		0x00000100	/* DMA Channel 6 (SPORT1 TX) Interrupt */
+#define IRQ_TWI			0x00000200	/* TWI Interrupt */
+#define IRQ_DMA7		0x00000400	/* DMA Channel 7 (SPI) Interrupt */
+#define IRQ_DMA8		0x00000800	/* DMA Channel 8 (UART0 RX) Interrupt */
+#define IRQ_DMA9		0x00001000	/* DMA Channel 9 (UART0 TX) Interrupt */
+#define IRQ_DMA10		0x00002000	/* DMA Channel 10 (UART1 RX) Interrupt */
+#define IRQ_DMA11		0x00004000	/* DMA Channel 11 (UART1 TX) Interrupt */
+#define IRQ_CAN_RX		0x00008000	/* CAN Receive Interrupt */
+
+#define IRQ_CAN_TX		0x00010000	/* CAN Transmit Interrupt */
+#define IRQ_DMA1		0x00020000	/* DMA Channel 1 (Ethernet RX) Interrupt */
+#define IRQ_PFA_PORTH		0x00020000	/* PF Port H (PF47:32) Interrupt A */
+#define IRQ_DMA2		0x00040000	/* DMA Channel 2 (Ethernet TX) Interrupt */
+#define IRQ_PFB_PORTH		0x00040000	/* PF Port H (PF47:32) Interrupt B */
+#define IRQ_TIMER0		0x00080000	/* Timer 0 Interrupt */
+#define IRQ_TIMER1		0x00100000	/* Timer 1 Interrupt */
+#define IRQ_TIMER2		0x00200000	/* Timer 2 Interrupt */
+#define IRQ_TIMER3		0x00400000	/* Timer 3 Interrupt */
+#define IRQ_TIMER4		0x00800000	/* Timer 4 Interrupt */
+
+#define IRQ_TIMER5		0x01000000	/* Timer 5 Interrupt */
+#define IRQ_TIMER6		0x02000000	/* Timer 6 Interrupt */
+#define IRQ_TIMER7		0x04000000	/* Timer 7 Interrupt */
+#define IRQ_PFA_PORTFG		0x08000000	/* PF Ports F&G (PF31:0) Interrupt A */
+#define IRQ_PFB_PORTF		0x80000000	/* PF Port F (PF15:0) Interrupt B */
+#define IRQ_DMA12		0x20000000	/* DMA Channels 12 (MDMA1 Source) RX Interrupt */
+#define IRQ_DMA13		0x20000000	/* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA14		0x40000000	/* DMA Channels 14 (MDMA0 Source) RX Interrupt */
+#define IRQ_DMA15		0x40000000	/* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
+#define IRQ_WDOG		0x80000000	/* Software Watchdog Timer Interrupt */
+#define IRQ_PFB_PORTG		0x10000000	/* PF Port G (PF31:16) Interrupt B */
+
+/* SIC_IAR0 Macros */
+#define P0_IVG(x)		(((x)&0xF)-7)		/* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x)		(((x)&0xF)-7) << 0x4	/* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x)		(((x)&0xF)-7) << 0x8	/* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x)		(((x)&0xF)-7) << 0xC	/* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x)		(((x)&0xF)-7) << 0x10	/* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x)		(((x)&0xF)-7) << 0x14	/* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x)		(((x)&0xF)-7) << 0x18	/* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x)		(((x)&0xF)-7) << 0x1C	/* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Macros */
+#define P8_IVG(x)		(((x)&0xF)-7)		/* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x)		(((x)&0xF)-7) << 0x4	/* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x)		(((x)&0xF)-7) << 0x8	/* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x)		(((x)&0xF)-7) << 0xC	/* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x)		(((x)&0xF)-7) << 0x10	/* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x)		(((x)&0xF)-7) << 0x14	/* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x)		(((x)&0xF)-7) << 0x18	/* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x)		(((x)&0xF)-7) << 0x1C	/* Peripheral #15 assigned IVG #x */
+
+/* SIC_IAR2 Macros */
+#define P16_IVG(x)		(((x)&0xF)-7)		/* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x)		(((x)&0xF)-7) << 0x4	/* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x)		(((x)&0xF)-7) << 0x8	/* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x)		(((x)&0xF)-7) << 0xC	/* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x)		(((x)&0xF)-7) << 0x10	/* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x)		(((x)&0xF)-7) << 0x14	/* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x)		(((x)&0xF)-7) << 0x18	/* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x)		(((x)&0xF)-7) << 0x1C	/* Peripheral #23 assigned IVG #x */
+
+/* SIC_IAR3 Macros */
+#define P24_IVG(x)		(((x)&0xF)-7)		/* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x)		(((x)&0xF)-7) << 0x4	/* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x)		(((x)&0xF)-7) << 0x8	/* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x)		(((x)&0xF)-7) << 0xC	/* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x)		(((x)&0xF)-7) << 0x10	/* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x)		(((x)&0xF)-7) << 0x14	/* Peripheral #29 assigned IVG #x */
+#define P30_IVG(x)		(((x)&0xF)-7) << 0x18	/* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x)		(((x)&0xF)-7) << 0x1C	/* Peripheral #31 assigned IVG #x */
+
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL		0x00000000		/* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL		0xFFFFFFFF		/* Mask all peripheral interrupts */
+#define SIC_MASK(x)		(1 << ((x)&0x1F))	/* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x)		(0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL		0x00000000		/* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL		0xFFFFFFFF		/* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x)		(1 << ((x)&0x1F))	/* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x)		(0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+
+#define WDEV(x)			((x<<1) & 0x0006)	/* event generated on roll over */
+#define WDEV_RESET		0x0000			/* generate reset event on roll over */
+#define WDEV_NMI		0x0002			/* generate NMI event on roll over */
+#define WDEV_GPI		0x0004			/* generate GP IRQ on roll over */
+#define WDEV_NONE		0x0006			/* no event on roll over */
+#define WDEN			0x0FF0			/* enable watchdog */
+#define WDDIS			0x0AD0			/* disable watchdog */
+#define WDRO			0x8000			/* watchdog rolled over latch */
+
+/* depreciated WDOG_CTL Register Masks for legacy code */
+
+#define ICTL WDEV
+#define ENABLE_RESET WDEV_RESET
+#define WDOG_RESET WDEV_RESET
+#define ENABLE_NMI WDEV_NMI
+#define WDOG_NMI WDEV_NMI
+#define ENABLE_GPI WDEV_GPI
+#define WDOG_GPI WDEV_GPI
+#define DISABLE_EVT WDEV_NONE
+#define WDOG_NONE WDEV_NONE
+
+#define TMR_EN WDEN
+#define TMR_DIS WDDIS
+#define TRO WDRO
+#define ICTL_P0 0x01
+#define ICTL_P1 0x02
+#define TRO_P 0x0F
+
+/*
+ * REAL TIME CLOCK MASKS
+ */
+/* RTC_STAT and RTC_ALARM Masks */
+#define	RTC_SEC			0x0000003F	/* Real-Time Clock Seconds */
+#define	RTC_MIN			0x00000FC0	/* Real-Time Clock Minutes */
+#define	RTC_HR			0x0001F000	/* Real-Time Clock Hours */
+#define	RTC_DAY			0xFFFE0000	/* Real-Time Clock Days */
+
+/*
+ * RTC_ALARM Macro
+ * z=day	y=hr	x=min	w=sec
+ */
+#define SET_ALARM(z,y,x,w)	((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+
+/* RTC_ICTL and RTC_ISTAT Masks */
+#define	STOPWATCH		0x0001	/* Stopwatch Interrupt Enable */
+#define	ALARM			0x0002	/* Alarm Interrupt Enable */
+#define	SECOND			0x0004	/* Seconds (1 Hz) Interrupt Enable */
+#define	MINUTE			0x0008	/* Minutes Interrupt Enable */
+#define	HOUR			0x0010	/* Hours Interrupt Enable */
+#define	DAY			0x0020	/* 24 Hours (Days) Interrupt Enable */
+#define	DAY_ALARM		0x0040	/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define	WRITE_PENDING		0x4000	/* Write Pending Status */
+#define	WRITE_COMPLETE		0x8000	/* Write Complete Interrupt Enable */
+
+/* RTC_FAST / RTC_PREN Mask */
+#define PREN			0x0001	/* Enable Prescaler, RTC Runs @1 Hz */
+
+/*
+ * UART CONTROLLER MASKS
+ */
+/* UARTx_LCR Masks */
+#define WLS(x)			((((x)&0x3)-5) & 0x03)	/* Word Length Select */
+#define STB			0x04	/* Stop Bits */
+#define PEN			0x08	/* Parity Enable */
+#define EPS			0x10	/* Even Parity Select */
+#define STP			0x20	/* Stick Parity */
+#define SB			0x40	/* Set Break */
+#define DLAB			0x80	/* Divisor Latch Access */
+
+/* UARTx_MCR Mask */
+#define LOOP			0x10	/* Loopback Mode Enable */
+
+/* UARTx_LSR Masks */
+#define DR			0x01	/* Data Ready */
+#define OE			0x02	/* Overrun Error */
+#define PE			0x04	/* Parity Error */
+#define FE			0x08	/* Framing Error */
+#define BI			0x10	/* Break Interrupt */
+#define THRE			0x20	/* THR Empty */
+#define TEMT			0x40	/* TSR and UART_THR Empty */
+
+/* UARTx_IER Masks */
+#define ERBFI			0x01	/* Enable Receive Buffer Full Interrupt */
+#define ETBEI			0x02	/* Enable Transmit Buffer Empty Interrupt */
+#define ELSI			0x04	/* Enable RX Status Interrupt */
+
+/* UARTx_IIR Masks */
+#define NINT			0x01	/* Pending Interrupt */
+#define STATUS			0x06	/* Highest Priority Pending Interrupt */
+
+/* UARTx_GCTL Masks */
+#define UCEN			0x01	/* Enable UARTx Clocks */
+#define IREN			0x02	/* Enable IrDA Mode */
+#define TPOLC			0x04	/* IrDA TX Polarity Change */
+#define RPOLC			0x08	/* IrDA RX Polarity Change */
+#define FPE			0x10	/* Force Parity Error On Transmit */
+#define FFE			0x20	/* Force Framing Error On Transmit */
+
+/*
+ * SERIAL PERIPHERAL INTERFACE (SPI) MASKS
+ */
+/* SPI_CTL Masks */
+#define	TIMOD			0x0003	/* Transfer Initiate Mode */
+#define RDBR_CORE		0x0000	/* RDBR Read Initiates, IRQ When RDBR Full */
+#define	TDBR_CORE		0x0001	/* TDBR Write Initiates, IRQ When TDBR Empty */
+#define RDBR_DMA		0x0002	/* DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA		0x0003	/* DMA Write, DMA Until FIFO Full */
+#define SZ			0x0004	/* Send Zero (When TDBR Empty, Send Zero/Last*) */
+#define GM			0x0008	/* Get More (When RDBR Full, Overwrite/Discard*) */
+#define PSSE			0x0010	/* Slave-Select Input Enable */
+#define EMISO			0x0020	/* Enable MISO As Output */
+#define SIZE			0x0100	/* Size of Words (16/8* Bits) */
+#define LSBF			0x0200	/* LSB First */
+#define CPHA			0x0400	/* Clock Phase */
+#define CPOL			0x0800	/* Clock Polarity */
+#define MSTR			0x1000	/* Master/Slave* */
+#define WOM			0x2000	/* Write Open Drain Master */
+#define SPE			0x4000	/* SPI Enable */
+
+/* SPI_FLG Masks */
+#define FLS1			0x0002	/* Enables SPI_FLOUT1 as SPI Slave-Select Output */
+#define FLS2			0x0004	/* Enables SPI_FLOUT2 as SPI Slave-Select Output */
+#define FLS3			0x0008	/* Enables SPI_FLOUT3 as SPI Slave-Select Output */
+#define FLS4			0x0010	/* Enables SPI_FLOUT4 as SPI Slave-Select Output */
+#define FLS5			0x0020	/* Enables SPI_FLOUT5 as SPI Slave-Select Output */
+#define FLS6			0x0040	/* Enables SPI_FLOUT6 as SPI Slave-Select Output */
+#define FLS7			0x0080	/* Enables SPI_FLOUT7 as SPI Slave-Select Output */
+#define FLG1			0xFDFF	/* Activates SPI_FLOUT1 */
+#define FLG2			0xFBFF	/* Activates SPI_FLOUT2 */
+#define FLG3			0xF7FF	/* Activates SPI_FLOUT3 */
+#define FLG4			0xEFFF	/* Activates SPI_FLOUT4 */
+#define FLG5			0xDFFF	/* Activates SPI_FLOUT5 */
+#define FLG6			0xBFFF	/* Activates SPI_FLOUT6 */
+#define FLG7			0x7FFF	/* Activates SPI_FLOUT7 */
+
+/* SPI_STAT Masks */
+#define SPIF			0x0001	/* SPI Finished (Single-Word Transfer Complete) */
+#define MODF			0x0002	/* Mode Fault Error (Another Device Tried To Become Master) */
+#define TXE			0x0004	/* Transmission Error (Data Sent With No New Data In TDBR) */
+#define TXS			0x0008	/* SPI_TDBR Data Buffer Status (Full/Empty*) */
+#define RBSY			0x0010	/* Receive Error (Data Received With RDBR Full) */
+#define RXS			0x0020	/* SPI_RDBR Data Buffer Status (Full/Empty*) */
+#define TXCOL			0x0040	/* Transmit Collision Error (Corrupt Data May Have Been Sent) */
+
+/*
+ * GENERAL PURPOSE TIMER MASKS
+ */
+/* TIMER_ENABLE Masks */
+#define TIMEN0			0x0001	/* Enable Timer 0 */
+#define TIMEN1			0x0002	/* Enable Timer 1 */
+#define TIMEN2			0x0004	/* Enable Timer 2 */
+#define TIMEN3			0x0008	/* Enable Timer 3 */
+#define TIMEN4			0x0010	/* Enable Timer 4 */
+#define TIMEN5			0x0020	/* Enable Timer 5 */
+#define TIMEN6			0x0040	/* Enable Timer 6 */
+#define TIMEN7			0x0080	/* Enable Timer 7 */
+
+/* TIMER_DISABLE Masks */
+#define TIMDIS0			TIMEN0	/* Disable Timer 0 */
+#define TIMDIS1			TIMEN1	/* Disable Timer 1 */
+#define TIMDIS2			TIMEN2	/* Disable Timer 2 */
+#define TIMDIS3			TIMEN3	/* Disable Timer 3 */
+#define TIMDIS4			TIMEN4	/* Disable Timer 4 */
+#define TIMDIS5			TIMEN5	/* Disable Timer 5 */
+#define TIMDIS6			TIMEN6	/* Disable Timer 6 */
+#define TIMDIS7			TIMEN7	/* Disable Timer 7 */
+
+/* TIMER_STATUS Masks */
+#define TIMIL0			0x00000001	/* Timer 0 Interrupt */
+#define TIMIL1			0x00000002	/* Timer 1 Interrupt */
+#define TIMIL2			0x00000004	/* Timer 2 Interrupt */
+#define TIMIL3			0x00000008	/* Timer 3 Interrupt */
+#define TOVF_ERR0		0x00000010	/* Timer 0 Counter Overflow */
+#define TOVF_ERR1		0x00000020	/* Timer 1 Counter Overflow */
+#define TOVF_ERR2		0x00000040	/* Timer 2 Counter Overflow */
+#define TOVF_ERR3		0x00000080	/* Timer 3 Counter Overflow */
+#define TRUN0			0x00001000	/* Timer 0 Slave Enable Status */
+#define TRUN1			0x00002000	/* Timer 1 Slave Enable Status */
+#define TRUN2			0x00004000	/* Timer 2 Slave Enable Status */
+#define TRUN3			0x00008000	/* Timer 3 Slave Enable Status */
+#define TIMIL4			0x00010000	/* Timer 4 Interrupt */
+#define TIMIL5			0x00020000	/* Timer 5 Interrupt */
+#define TIMIL6			0x00040000	/* Timer 6 Interrupt */
+#define TIMIL7			0x00080000	/* Timer 7 Interrupt */
+#define TOVF_ERR4		0x00100000	/* Timer 4 Counter Overflow */
+#define TOVF_ERR5		0x00200000	/* Timer 5 Counter Overflow */
+#define TOVF_ERR6		0x00400000	/* Timer 6 Counter Overflow */
+#define TOVF_ERR7		0x00800000	/* Timer 7 Counter Overflow */
+#define TRUN4			0x10000000	/* Timer 4 Slave Enable Status */
+#define TRUN5			0x20000000	/* Timer 5 Slave Enable Status */
+#define TRUN6			0x40000000	/* Timer 6 Slave Enable Status */
+#define TRUN7			0x80000000	/* Timer 7 Slave Enable Status */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks */
+#define PWM_OUT			0x0001	/* Pulse-Width Modulation Output Mode */
+#define WDTH_CAP		0x0002	/* Width Capture Input Mode */
+#define EXT_CLK			0x0003	/* External Clock Mode */
+#define PULSE_HI		0x0004	/* Action Pulse (Positive/Negative*) */
+#define PERIOD_CNT		0x0008	/* Period Count */
+#define IRQ_ENA			0x0010	/* Interrupt Request Enable */
+#define TIN_SEL			0x0020	/* Timer Input Select */
+#define OUT_DIS			0x0040	/* Output Pad Disable */
+#define CLK_SEL			0x0080	/* Timer Clock Select */
+#define TOGGLE_HI		0x0100	/* PWM_OUT PULSE_HI Toggle Mode */
+#define EMU_RUN			0x0200	/* Emulation Behavior Select */
+#define ERR_TYP			0xC000	/* Error Type */
+
+/*
+ * GPIO PORTS F, G, H MASKS
+ * General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks
+ */
+/* Port F Masks */
+#define PF0			0x0001
+#define PF1			0x0002
+#define PF2			0x0004
+#define PF3			0x0008
+#define PF4			0x0010
+#define PF5			0x0020
+#define PF6			0x0040
+#define PF7			0x0080
+#define PF8			0x0100
+#define PF9			0x0200
+#define PF10			0x0400
+#define PF11			0x0800
+#define PF12			0x1000
+#define PF13			0x2000
+#define PF14			0x4000
+#define PF15			0x8000
+
+/* Port G Masks */
+#define PG0			0x0001
+#define PG1			0x0002
+#define PG2			0x0004
+#define PG3			0x0008
+#define PG4			0x0010
+#define PG5			0x0020
+#define PG6			0x0040
+#define PG7			0x0080
+#define PG8			0x0100
+#define PG9			0x0200
+#define PG10			0x0400
+#define PG11			0x0800
+#define PG12			0x1000
+#define PG13			0x2000
+#define PG14			0x4000
+#define PG15			0x8000
+
+/* Port H Masks */
+#define PH0			0x0001
+#define PH1			0x0002
+#define PH2			0x0004
+#define PH3			0x0008
+#define PH4			0x0010
+#define PH5			0x0020
+#define PH6			0x0040
+#define PH7			0x0080
+#define PH8			0x0100
+#define PH9			0x0200
+#define PH10			0x0400
+#define PH11			0x0800
+#define PH12			0x1000
+#define PH13			0x2000
+#define PH14			0x4000
+#define PH15			0x8000
+
+/*
+ * SERIAL PORT MASKS
+ */
+/* SPORTx_TCR1 Masks */
+#define TSPEN			0x0001	/* Transmit Enable */
+#define ITCLK			0x0002	/* Internal Transmit Clock Select */
+#define DTYPE_NORM		0x0004	/* Data Format Normal */
+#define DTYPE_ULAW		0x0008	/* Compand Using u-Law */
+#define DTYPE_ALAW		0x000C	/* Compand Using A-Law */
+#define TLSBIT			0x0010	/* Transmit Bit Order */
+#define ITFS			0x0200	/* Internal Transmit Frame Sync Select */
+#define TFSR			0x0400	/* Transmit Frame Sync Required Select */
+#define DITFS			0x0800	/* Data-Independent Transmit Frame Sync Select */
+#define LTFS			0x1000	/* Low Transmit Frame Sync Select */
+#define LATFS			0x2000	/* Late Transmit Frame Sync Select */
+#define TCKFE			0x4000	/* Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks and Macro */
+#define SLEN(x)			((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#define TXSE			0x0100	/* TX Secondary Enable */
+#define TSFSE			0x0200	/* Transmit Stereo Frame Sync Enable */
+#define TRFST			0x0400	/* Left/Right Order (1 = Right Channel 1st) */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN			0x0001	/* Receive Enable */
+#define IRCLK			0x0002	/* Internal Receive Clock Select */
+#define DTYPE_NORM		0x0004	/* Data Format Normal */
+#define DTYPE_ULAW		0x0008	/* Compand Using u-Law */
+#define DTYPE_ALAW		0x000C	/* Compand Using A-Law */
+#define RLSBIT			0x0010	/* Receive Bit Order */
+#define IRFS			0x0200	/* Internal Receive Frame Sync Select */
+#define RFSR			0x0400	/* Receive Frame Sync Required Select */
+#define LRFS			0x1000	/* Low Receive Frame Sync Select */
+#define LARFS			0x2000	/* Late Receive Frame Sync Select */
+#define RCKFE			0x4000	/* Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN(x)			((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
+#define RXSE			0x0100	/* RX Secondary Enable */
+#define RSFSE			0x0200	/* RX Stereo Frame Sync Enable */
+#define RRFST			0x0400	/* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE			0x0001	/* Receive FIFO Not Empty Status */
+#define RUVF			0x0002	/* Sticky Receive Underflow Status */
+#define ROVF			0x0004	/* Sticky Receive Overflow Status */
+#define TXF			0x0008	/* Transmit FIFO Full Status */
+#define TUVF			0x0010	/* Sticky Transmit Underflow Status */
+#define TOVF			0x0020	/* Sticky Transmit Overflow Status */
+#define TXHRE			0x0040	/* Transmit Hold Register Empty */
+
+/* SPORTx_MCMC1 Macros */
+#define WOFF(x)			((x) & 0x3FF)	/* Multichannel Window Offset Field */
+
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define WSIZE(x)		(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1 */
+
+/* SPORTx_MCMC2 Masks */
+#define REC_BYPASS		0x0000	/* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4		0x0002	/* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16		0x0003	/* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE			0x0004	/* Multichannel DMA Transmit Packing */
+#define MCDRXPE			0x0008	/* Multichannel DMA Receive Packing */
+#define MCMEN			0x0010	/* Multichannel Frame Mode Enable */
+#define FSDR			0x0080	/* Multichannel Frame Sync to Data Relationship */
+#define MFD_0			0x0000	/* Multichannel Frame Delay = 0 */
+#define MFD_1			0x1000	/* Multichannel Frame Delay = 1 */
+#define MFD_2			0x2000	/* Multichannel Frame Delay = 2 */
+#define MFD_3			0x3000	/* Multichannel Frame Delay = 3 */
+#define MFD_4			0x4000	/* Multichannel Frame Delay = 4 */
+#define MFD_5			0x5000	/* Multichannel Frame Delay = 5 */
+#define MFD_6			0x6000	/* Multichannel Frame Delay = 6 */
+#define MFD_7			0x7000	/* Multichannel Frame Delay = 7 */
+#define MFD_8			0x8000	/* Multichannel Frame Delay = 8 */
+#define MFD_9			0x9000	/* Multichannel Frame Delay = 9 */
+#define MFD_10			0xA000	/* Multichannel Frame Delay = 10 */
+#define MFD_11			0xB000	/* Multichannel Frame Delay = 11 */
+#define MFD_12			0xC000	/* Multichannel Frame Delay = 12 */
+#define MFD_13			0xD000	/* Multichannel Frame Delay = 13 */
+#define MFD_14			0xE000	/* Multichannel Frame Delay = 14 */
+#define MFD_15			0xF000	/* Multichannel Frame Delay = 15 */
+
+/*
+ * ASYNCHRONOUS MEMORY CONTROLLER MASKS
+ */
+/* EBIU_AMGCTL Masks */
+#define AMCKEN			0x0001	/* Enable CLKOUT */
+#define	AMBEN_NONE		0x0000	/* All Banks Disabled */
+#define AMBEN_B0		0x0002	/* Enable Async Memory Bank 0 only */
+#define AMBEN_B0_B1		0x0004	/* Enable Async Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2		0x0006	/* Enable Async Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL		0x0008	/* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN			0x00000001	/* Bank 0 (B0) RDY Enable */
+#define B0RDYPOL		0x00000002	/* B0 RDY Active High */
+#define B0TT_1			0x00000004	/* B0 Transition Time (Read to Write) = 1 cycle */
+#define B0TT_2			0x00000008	/* B0 Transition Time (Read to Write) = 2 cycles */
+#define B0TT_3			0x0000000C	/* B0 Transition Time (Read to Write) = 3 cycles */
+#define B0TT_4			0x00000000	/* B0 Transition Time (Read to Write) = 4 cycles */
+#define B0ST_1			0x00000010	/* B0 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B0ST_2			0x00000020	/* B0 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B0ST_3			0x00000030	/* B0 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B0ST_4			0x00000000	/* B0 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B0HT_1			0x00000040	/* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B0HT_2			0x00000080	/* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B0HT_3			0x000000C0	/* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B0HT_0			0x00000000	/* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B0RAT_1			0x00000100	/* B0 Read Access Time = 1 cycle */
+#define B0RAT_2			0x00000200	/* B0 Read Access Time = 2 cycles */
+#define B0RAT_3			0x00000300	/* B0 Read Access Time = 3 cycles */
+#define B0RAT_4			0x00000400	/* B0 Read Access Time = 4 cycles */
+#define B0RAT_5			0x00000500	/* B0 Read Access Time = 5 cycles */
+#define B0RAT_6			0x00000600	/* B0 Read Access Time = 6 cycles */
+#define B0RAT_7			0x00000700	/* B0 Read Access Time = 7 cycles */
+#define B0RAT_8			0x00000800	/* B0 Read Access Time = 8 cycles */
+#define B0RAT_9			0x00000900	/* B0 Read Access Time = 9 cycles */
+#define B0RAT_10		0x00000A00	/* B0 Read Access Time = 10 cycles */
+#define B0RAT_11		0x00000B00	/* B0 Read Access Time = 11 cycles */
+#define B0RAT_12		0x00000C00	/* B0 Read Access Time = 12 cycles */
+#define B0RAT_13		0x00000D00	/* B0 Read Access Time = 13 cycles */
+#define B0RAT_14		0x00000E00	/* B0 Read Access Time = 14 cycles */
+#define B0RAT_15		0x00000F00	/* B0 Read Access Time = 15 cycles */
+#define B0WAT_1			0x00001000	/* B0 Write Access Time = 1 cycle */
+#define B0WAT_2			0x00002000	/* B0 Write Access Time = 2 cycles */
+#define B0WAT_3			0x00003000	/* B0 Write Access Time = 3 cycles */
+#define B0WAT_4			0x00004000	/* B0 Write Access Time = 4 cycles */
+#define B0WAT_5			0x00005000	/* B0 Write Access Time = 5 cycles */
+#define B0WAT_6			0x00006000	/* B0 Write Access Time = 6 cycles */
+#define B0WAT_7			0x00007000	/* B0 Write Access Time = 7 cycles */
+#define B0WAT_8			0x00008000	/* B0 Write Access Time = 8 cycles */
+#define B0WAT_9			0x00009000	/* B0 Write Access Time = 9 cycles */
+#define B0WAT_10		0x0000A000	/* B0 Write Access Time = 10 cycles */
+#define B0WAT_11		0x0000B000	/* B0 Write Access Time = 11 cycles */
+#define B0WAT_12		0x0000C000	/* B0 Write Access Time = 12 cycles */
+#define B0WAT_13		0x0000D000	/* B0 Write Access Time = 13 cycles */
+#define B0WAT_14		0x0000E000	/* B0 Write Access Time = 14 cycles */
+#define B0WAT_15		0x0000F000	/* B0 Write Access Time = 15 cycles */
+
+#define B1RDYEN			0x00010000	/* Bank 1 (B1) RDY Enable */
+#define B1RDYPOL		0x00020000	/* B1 RDY Active High */
+#define B1TT_1			0x00040000	/* B1 Transition Time (Read to Write) = 1 cycle */
+#define B1TT_2			0x00080000	/* B1 Transition Time (Read to Write) = 2 cycles */
+#define B1TT_3			0x000C0000	/* B1 Transition Time (Read to Write) = 3 cycles */
+#define B1TT_4			0x00000000	/* B1 Transition Time (Read to Write) = 4 cycles */
+#define B1ST_1			0x00100000	/* B1 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B1ST_2			0x00200000	/* B1 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B1ST_3			0x00300000	/* B1 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B1ST_4			0x00000000	/* B1 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B1HT_1			0x00400000	/* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B1HT_2			0x00800000	/* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B1HT_3			0x00C00000	/* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B1HT_0			0x00000000	/* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B1RAT_1			0x01000000	/* B1 Read Access Time = 1 cycle */
+#define B1RAT_2			0x02000000	/* B1 Read Access Time = 2 cycles */
+#define B1RAT_3			0x03000000	/* B1 Read Access Time = 3 cycles */
+#define B1RAT_4			0x04000000	/* B1 Read Access Time = 4 cycles */
+#define B1RAT_5			0x05000000	/* B1 Read Access Time = 5 cycles */
+#define B1RAT_6			0x06000000	/* B1 Read Access Time = 6 cycles */
+#define B1RAT_7			0x07000000	/* B1 Read Access Time = 7 cycles */
+#define B1RAT_8			0x08000000	/* B1 Read Access Time = 8 cycles */
+#define B1RAT_9			0x09000000	/* B1 Read Access Time = 9 cycles */
+#define B1RAT_10		0x0A000000	/* B1 Read Access Time = 10 cycles */
+#define B1RAT_11		0x0B000000	/* B1 Read Access Time = 11 cycles */
+#define B1RAT_12		0x0C000000	/* B1 Read Access Time = 12 cycles */
+#define B1RAT_13		0x0D000000	/* B1 Read Access Time = 13 cycles */
+#define B1RAT_14		0x0E000000	/* B1 Read Access Time = 14 cycles */
+#define B1RAT_15		0x0F000000	/* B1 Read Access Time = 15 cycles */
+#define B1WAT_1			0x10000000	/* B1 Write Access Time = 1 cycle */
+#define B1WAT_2			0x20000000	/* B1 Write Access Time = 2 cycles */
+#define B1WAT_3			0x30000000	/* B1 Write Access Time = 3 cycles */
+#define B1WAT_4			0x40000000	/* B1 Write Access Time = 4 cycles */
+#define B1WAT_5			0x50000000	/* B1 Write Access Time = 5 cycles */
+#define B1WAT_6			0x60000000	/* B1 Write Access Time = 6 cycles */
+#define B1WAT_7			0x70000000	/* B1 Write Access Time = 7 cycles */
+#define B1WAT_8			0x80000000	/* B1 Write Access Time = 8 cycles */
+#define B1WAT_9			0x90000000	/* B1 Write Access Time = 9 cycles */
+#define B1WAT_10		0xA0000000	/* B1 Write Access Time = 10 cycles */
+#define B1WAT_11		0xB0000000	/* B1 Write Access Time = 11 cycles */
+#define B1WAT_12		0xC0000000	/* B1 Write Access Time = 12 cycles */
+#define B1WAT_13		0xD0000000	/* B1 Write Access Time = 13 cycles */
+#define B1WAT_14		0xE0000000	/* B1 Write Access Time = 14 cycles */
+#define B1WAT_15		0xF0000000	/* B1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN			0x00000001	/* Bank 2 (B2) RDY Enable */
+#define B2RDYPOL		0x00000002	/* B2 RDY Active High */
+#define B2TT_1			0x00000004	/* B2 Transition Time (Read to Write) = 1 cycle */
+#define B2TT_2			0x00000008	/* B2 Transition Time (Read to Write) = 2 cycles */
+#define B2TT_3			0x0000000C	/* B2 Transition Time (Read to Write) = 3 cycles */
+#define B2TT_4			0x00000000	/* B2 Transition Time (Read to Write) = 4 cycles */
+#define B2ST_1			0x00000010	/* B2 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B2ST_2			0x00000020	/* B2 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B2ST_3			0x00000030	/* B2 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B2ST_4			0x00000000	/* B2 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B2HT_1			0x00000040	/* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B2HT_2			0x00000080	/* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B2HT_3			0x000000C0	/* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B2HT_0			0x00000000	/* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B2RAT_1			0x00000100	/* B2 Read Access Time = 1 cycle */
+#define B2RAT_2			0x00000200	/* B2 Read Access Time = 2 cycles */
+#define B2RAT_3			0x00000300	/* B2 Read Access Time = 3 cycles */
+#define B2RAT_4			0x00000400	/* B2 Read Access Time = 4 cycles */
+#define B2RAT_5			0x00000500	/* B2 Read Access Time = 5 cycles */
+#define B2RAT_6			0x00000600	/* B2 Read Access Time = 6 cycles */
+#define B2RAT_7			0x00000700	/* B2 Read Access Time = 7 cycles */
+#define B2RAT_8			0x00000800	/* B2 Read Access Time = 8 cycles */
+#define B2RAT_9			0x00000900	/* B2 Read Access Time = 9 cycles */
+#define B2RAT_10		0x00000A00	/* B2 Read Access Time = 10 cycles */
+#define B2RAT_11		0x00000B00	/* B2 Read Access Time = 11 cycles */
+#define B2RAT_12		0x00000C00	/* B2 Read Access Time = 12 cycles */
+#define B2RAT_13		0x00000D00	/* B2 Read Access Time = 13 cycles */
+#define B2RAT_14		0x00000E00	/* B2 Read Access Time = 14 cycles */
+#define B2RAT_15		0x00000F00	/* B2 Read Access Time = 15 cycles */
+#define B2WAT_1			0x00001000	/* B2 Write Access Time = 1 cycle */
+#define B2WAT_2			0x00002000	/* B2 Write Access Time = 2 cycles */
+#define B2WAT_3			0x00003000	/* B2 Write Access Time = 3 cycles */
+#define B2WAT_4			0x00004000	/* B2 Write Access Time = 4 cycles */
+#define B2WAT_5			0x00005000	/* B2 Write Access Time = 5 cycles */
+#define B2WAT_6			0x00006000	/* B2 Write Access Time = 6 cycles */
+#define B2WAT_7			0x00007000	/* B2 Write Access Time = 7 cycles */
+#define B2WAT_8			0x00008000	/* B2 Write Access Time = 8 cycles */
+#define B2WAT_9			0x00009000	/* B2 Write Access Time = 9 cycles */
+#define B2WAT_10		0x0000A000	/* B2 Write Access Time = 10 cycles */
+#define B2WAT_11		0x0000B000	/* B2 Write Access Time = 11 cycles */
+#define B2WAT_12		0x0000C000	/* B2 Write Access Time = 12 cycles */
+#define B2WAT_13		0x0000D000	/* B2 Write Access Time = 13 cycles */
+#define B2WAT_14		0x0000E000	/* B2 Write Access Time = 14 cycles */
+#define B2WAT_15		0x0000F000	/* B2 Write Access Time = 15 cycles */
+
+#define B3RDYEN			0x00010000	/* Bank 3 (B3) RDY Enable */
+#define B3RDYPOL		0x00020000	/* B3 RDY Active High */
+#define B3TT_1			0x00040000	/* B3 Transition Time (Read to Write) = 1 cycle */
+#define B3TT_2			0x00080000	/* B3 Transition Time (Read to Write) = 2 cycles */
+#define B3TT_3			0x000C0000	/* B3 Transition Time (Read to Write) = 3 cycles */
+#define B3TT_4			0x00000000	/* B3 Transition Time (Read to Write) = 4 cycles */
+#define B3ST_1			0x00100000	/* B3 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B3ST_2			0x00200000	/* B3 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B3ST_3			0x00300000	/* B3 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B3ST_4			0x00000000	/* B3 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B3HT_1			0x00400000	/* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B3HT_2			0x00800000	/* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B3HT_3			0x00C00000	/* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B3HT_0			0x00000000	/* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B3RAT_1			0x01000000	/* B3 Read Access Time = 1 cycle */
+#define B3RAT_2			0x02000000	/* B3 Read Access Time = 2 cycles */
+#define B3RAT_3			0x03000000	/* B3 Read Access Time = 3 cycles */
+#define B3RAT_4			0x04000000	/* B3 Read Access Time = 4 cycles */
+#define B3RAT_5			0x05000000	/* B3 Read Access Time = 5 cycles */
+#define B3RAT_6			0x06000000	/* B3 Read Access Time = 6 cycles */
+#define B3RAT_7			0x07000000	/* B3 Read Access Time = 7 cycles */
+#define B3RAT_8			0x08000000	/* B3 Read Access Time = 8 cycles */
+#define B3RAT_9			0x09000000	/* B3 Read Access Time = 9 cycles */
+#define B3RAT_10		0x0A000000	/* B3 Read Access Time = 10 cycles */
+#define B3RAT_11		0x0B000000	/* B3 Read Access Time = 11 cycles */
+#define B3RAT_12		0x0C000000	/* B3 Read Access Time = 12 cycles */
+#define B3RAT_13		0x0D000000	/* B3 Read Access Time = 13 cycles */
+#define B3RAT_14		0x0E000000	/* B3 Read Access Time = 14 cycles */
+#define B3RAT_15		0x0F000000	/* B3 Read Access Time = 15 cycles */
+#define B3WAT_1			0x10000000	/* B3 Write Access Time = 1 cycle */
+#define B3WAT_2			0x20000000	/* B3 Write Access Time = 2 cycles */
+#define B3WAT_3			0x30000000	/* B3 Write Access Time = 3 cycles */
+#define B3WAT_4			0x40000000	/* B3 Write Access Time = 4 cycles */
+#define B3WAT_5			0x50000000	/* B3 Write Access Time = 5 cycles */
+#define B3WAT_6			0x60000000	/* B3 Write Access Time = 6 cycles */
+#define B3WAT_7			0x70000000	/* B3 Write Access Time = 7 cycles */
+#define B3WAT_8			0x80000000	/* B3 Write Access Time = 8 cycles */
+#define B3WAT_9			0x90000000	/* B3 Write Access Time = 9 cycles */
+#define B3WAT_10		0xA0000000	/* B3 Write Access Time = 10 cycles */
+#define B3WAT_11		0xB0000000	/* B3 Write Access Time = 11 cycles */
+#define B3WAT_12		0xC0000000	/* B3 Write Access Time = 12 cycles */
+#define B3WAT_13		0xD0000000	/* B3 Write Access Time = 13 cycles */
+#define B3WAT_14		0xE0000000	/* B3 Write Access Time = 14 cycles */
+#define B3WAT_15		0xF0000000	/* B3 Write Access Time = 15 cycles */
+
+/*
+ * SDRAM CONTROLLER MASKS
+ */
+/* EBIU_SDGCTL Masks */
+#define SCTLE			0x00000001	/* Enable SDRAM Signals */
+#define CL_2			0x00000008	/* SDRAM CAS Latency = 2 cycles */
+#define CL_3			0x0000000C	/* SDRAM CAS Latency = 3 cycles */
+#define PASR_ALL		0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1		0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0			0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1			0x00000040	/* SDRAM tRAS = 1 cycle */
+#define TRAS_2			0x00000080	/* SDRAM tRAS = 2 cycles */
+#define TRAS_3			0x000000C0	/* SDRAM tRAS = 3 cycles */
+#define TRAS_4			0x00000100	/* SDRAM tRAS = 4 cycles */
+#define TRAS_5			0x00000140	/* SDRAM tRAS = 5 cycles */
+#define TRAS_6			0x00000180	/* SDRAM tRAS = 6 cycles */
+#define TRAS_7			0x000001C0	/* SDRAM tRAS = 7 cycles */
+#define TRAS_8			0x00000200	/* SDRAM tRAS = 8 cycles */
+#define TRAS_9			0x00000240	/* SDRAM tRAS = 9 cycles */
+#define TRAS_10			0x00000280	/* SDRAM tRAS = 10 cycles */
+#define TRAS_11			0x000002C0	/* SDRAM tRAS = 11 cycles */
+#define TRAS_12			0x00000300	/* SDRAM tRAS = 12 cycles */
+#define TRAS_13			0x00000340	/* SDRAM tRAS = 13 cycles */
+#define TRAS_14			0x00000380	/* SDRAM tRAS = 14 cycles */
+#define TRAS_15			0x000003C0	/* SDRAM tRAS = 15 cycles */
+#define TRP_1			0x00000800	/* SDRAM tRP = 1 cycle */
+#define TRP_2			0x00001000	/* SDRAM tRP = 2 cycles */
+#define TRP_3			0x00001800	/* SDRAM tRP = 3 cycles */
+#define TRP_4			0x00002000	/* SDRAM tRP = 4 cycles */
+#define TRP_5			0x00002800	/* SDRAM tRP = 5 cycles */
+#define TRP_6			0x00003000	/* SDRAM tRP = 6 cycles */
+#define TRP_7			0x00003800	/* SDRAM tRP = 7 cycles */
+#define TRCD_1			0x00008000	/* SDRAM tRCD = 1 cycle */
+#define TRCD_2			0x00010000	/* SDRAM tRCD = 2 cycles */
+#define TRCD_3			0x00018000	/* SDRAM tRCD = 3 cycles */
+#define TRCD_4			0x00020000	/* SDRAM tRCD = 4 cycles */
+#define TRCD_5			0x00028000	/* SDRAM tRCD = 5 cycles */
+#define TRCD_6			0x00030000	/* SDRAM tRCD = 6 cycles */
+#define TRCD_7			0x00038000	/* SDRAM tRCD = 7 cycles */
+#define TWR_1			0x00080000	/* SDRAM tWR = 1 cycle */
+#define TWR_2			0x00100000	/* SDRAM tWR = 2 cycles */
+#define TWR_3			0x00180000	/* SDRAM tWR = 3 cycles */
+#define PUPSD			0x00200000	/* Power-Up Start Delay (15 SCLK Cycles Delay) */
+#define PSM			0x00400000	/* Power-Up Sequence (Mode Register Before/After* Refresh) */
+#define PSS			0x00800000	/* Enable Power-Up Sequence on Next SDRAM Access */
+#define SRFS			0x01000000	/* Enable SDRAM Self-Refresh Mode */
+#define EBUFE			0x02000000	/* Enable External Buffering Timing */
+#define FBBRW			0x04000000	/* Enable Fast Back-To-Back Read To Write */
+#define EMREN			0x10000000	/* Extended Mode Register Enable */
+#define TCSR			0x20000000	/* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
+#define CDDBG			0x40000000	/* Tristate SDRAM Controls During Bus Grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE			0x0001	/* Enable SDRAM External Bank */
+#define EBSZ_16			0x0000	/* SDRAM External Bank Size = 16MB */
+#define EBSZ_32			0x0002	/* SDRAM External Bank Size = 32MB */
+#define EBSZ_64			0x0004	/* SDRAM External Bank Size = 64MB */
+#define EBSZ_128		0x0006	/* SDRAM External Bank Size = 128MB */
+#define EBCAW_8			0x0000	/* SDRAM External Bank Column Address Width = 8 Bits */
+#define EBCAW_9			0x0010	/* SDRAM External Bank Column Address Width = 9 Bits */
+#define EBCAW_10		0x0020	/* SDRAM External Bank Column Address Width = 10 Bits */
+#define EBCAW_11		0x0030	/* SDRAM External Bank Column Address Width = 11 Bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI			0x0001	/* SDRAM Controller Idle */
+#define SDSRA			0x0002	/* SDRAM Self-Refresh Active */
+#define SDPUA			0x0004	/* SDRAM Power-Up Active */
+#define SDRS			0x0008	/* SDRAM Will Power-Up On Next Access */
+#define SDEASE			0x0010	/* SDRAM EAB Sticky Error Status */
+#define BGSTAT			0x0020	/* Bus Grant Status */
+
+/*
+ * DMA CONTROLLER MASKS
+ */
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN			0x0001	/* DMA Channel Enable */
+#define WNR			0x0002	/* Channel Direction (W/R*) */
+#define WDSIZE_8		0x0000	/* Transfer Word Size = 8 */
+#define WDSIZE_16		0x0004	/* Transfer Word Size = 16 */
+#define WDSIZE_32		0x0008	/* Transfer Word Size = 32 */
+#define DMA2D			0x0010	/* DMA Mode (2D/1D*) */
+#define RESTART			0x0020	/* DMA Buffer Clear */
+#define DI_SEL			0x0040	/* Data Interrupt Timing Select */
+#define DI_EN			0x0080	/* Data Interrupt Enable */
+#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1 */
+#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2 */
+#define NDSIZE_3		0x0300	/* Next Descriptor Size = 3 */
+#define NDSIZE_4		0x0400	/* Next Descriptor Size = 4 */
+#define NDSIZE_5		0x0500	/* Next Descriptor Size = 5 */
+#define NDSIZE_6		0x0600	/* Next Descriptor Size = 6 */
+#define NDSIZE_7		0x0700	/* Next Descriptor Size = 7 */
+#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8 */
+#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9 */
+#define FLOW_STOP		0x0000	/* Stop Mode */
+#define FLOW_AUTO		0x1000	/* Autobuffer Mode */
+#define FLOW_ARRAY		0x4000	/* Descriptor Array Mode */
+#define FLOW_SMALL		0x6000	/* Small Model Descriptor List Mode */
+#define FLOW_LARGE		0x7000	/* Large Model Descriptor List Mode */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+#define CTYPE			0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*) */
+#define PMAP			0xF000	/* Peripheral Mapped To This Channel */
+#define PMAP_PPI		0x0000	/* PPI Port DMA */
+#define	PMAP_EMACRX		0x1000	/* Ethernet Receive DMA */
+#define PMAP_EMACTX		0x2000	/* Ethernet Transmit DMA */
+#define PMAP_SPORT0RX		0x3000	/* SPORT0 Receive DMA */
+#define PMAP_SPORT0TX		0x4000	/* SPORT0 Transmit DMA */
+#define PMAP_SPORT1RX		0x5000	/* SPORT1 Receive DMA */
+#define PMAP_SPORT1TX		0x6000	/* SPORT1 Transmit DMA */
+#define PMAP_SPI		0x7000	/* SPI Port DMA */
+#define PMAP_UART0RX		0x8000	/* UART0 Port Receive DMA */
+#define PMAP_UART0TX		0x9000	/* UART0 Port Transmit DMA */
+#define	PMAP_UART1RX		0xA000	/* UART1 Port Receive DMA */
+#define	PMAP_UART1TX		0xB000	/* UART1 Port Transmit DMA */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status */
+#define DMA_ERR			0x0002	/* DMA Error Interrupt Status */
+#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator */
+#define DMA_RUN			0x0008	/* DMA Channel Running Indicator */
+
+/*
+ * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS
+ */
+/* PPI_CONTROL Masks */
+#define PORT_EN			0x0001	/* PPI Port Enable */
+#define PORT_DIR		0x0002	/* PPI Port Direction */
+#define XFR_TYPE		0x000C	/* PPI Transfer Type */
+#define PORT_CFG		0x0030	/* PPI Port Configuration */
+#define FLD_SEL			0x0040	/* PPI Active Field Select */
+#define PACK_EN			0x0080	/* PPI Packing Mode */
+#define DMA32			0x0100	/* PPI 32-bit DMA Enable */
+#define SKIP_EN			0x0200	/* PPI Skip Element Enable */
+#define SKIP_EO			0x0400	/* PPI Skip Even/Odd Elements */
+#define DLEN_8			0x0000	/* Data Length = 8 Bits */
+#define DLEN_10			0x0800	/* Data Length = 10 Bits */
+#define DLEN_11			0x1000	/* Data Length = 11 Bits */
+#define DLEN_12			0x1800	/* Data Length = 12 Bits */
+#define DLEN_13			0x2000	/* Data Length = 13 Bits */
+#define DLEN_14			0x2800	/* Data Length = 14 Bits */
+#define DLEN_15			0x3000	/* Data Length = 15 Bits */
+#define DLEN_16			0x3800	/* Data Length = 16 Bits */
+#define POLC			0x4000	/* PPI Clock Polarity */
+#define POLS			0x8000	/* PPI Frame Sync Polarity */
+
+/* PPI_STATUS Masks */
+#define FLD			0x0400	/* Field Indicator */
+#define FT_ERR			0x0800	/* Frame Track Error */
+#define OVR			0x1000	/* FIFO Overflow Error */
+#define UNDR			0x2000	/* FIFO Underrun Error */
+#define ERR_DET			0x4000	/* Error Detected Indicator */
+#define ERR_NCOR		0x8000	/* Error Not Corrected Indicator */
+
+/*
+ * TWO-WIRE INTERFACE (TWI) MASKS
+ */
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#define	CLKLOW(x)		((x) & 0xFF)		/* Periods Clock Is Held Low */
+#define CLKHI(y)		(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low */
+
+/* TWI_PRESCALE Masks */
+#define	PRESCALE		0x007F	/* SCLKs Per Internal Time Reference (10MHz) */
+#define	TWI_ENA			0x0080	/* TWI Enable */
+#define	SCCB			0x0200	/* SCCB Compatibility Enable */
+
+/* TWI_SLAVE_CTRL Masks */
+#define	SEN			0x0001	/* Slave Enable */
+#define	SADD_LEN		0x0002	/* Slave Address Length */
+#define	STDVAL			0x0004	/* Slave Transmit Data Valid */
+#define	TSC_NAK			0x0008	/* NAK/ACK* Generated At Conclusion Of Transfer */
+#define	GEN			0x0010	/* General Call Adrress Matching Enabled */
+
+/* TWI_SLAVE_STAT Masks */
+#define	SDIR			0x0001	/* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL			0x0002	/* General Call Indicator */
+
+/* TWI_MASTER_CTRL Masks */
+#define	MEN			0x0001	/* Master Mode Enable */
+#define	MADD_LEN		0x0002	/* Master Address Length */
+#define	MDIR			0x0004	/* Master Transmit Direction (RX/TX*) */
+#define	FAST			0x0008	/* Use Fast Mode Timing Specs */
+#define	STOP			0x0010	/* Issue Stop Condition */
+#define	RSTART			0x0020	/* Repeat Start or Stop* At End Of Transfer */
+#define	DCNT			0x3FC0	/* Data Bytes To Transfer */
+#define	SDAOVR			0x4000	/* Serial Data Override */
+#define	SCLOVR			0x8000	/* Serial Clock Override */
+
+/* TWI_MASTER_STAT Masks */
+#define	MPROG			0x0001	/* Master Transfer In Progress */
+#define	LOSTARB			0x0002	/* Lost Arbitration Indicator (Xfer Aborted) */
+#define	ANAK			0x0004	/* Address Not Acknowledged */
+#define	DNAK			0x0008	/* Data Not Acknowledged */
+#define	BUFRDERR		0x0010	/* Buffer Read Error */
+#define	BUFWRERR		0x0020	/* Buffer Write Error */
+#define	SDASEN			0x0040	/* Serial Data Sense */
+#define	SCLSEN			0x0080	/* Serial Clock Sense */
+#define	BUSBUSY			0x0100	/* Bus Busy Indicator */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
+#define	SINIT			0x0001	/* Slave Transfer Initiated */
+#define	SCOMP			0x0002	/* Slave Transfer Complete */
+#define	SERR			0x0004	/* Slave Transfer Error */
+#define	SOVF			0x0008	/* Slave Overflow */
+#define	MCOMP			0x0010	/* Master Transfer Complete */
+#define	MERR			0x0020	/* Master Transfer Error */
+#define	XMTSERV			0x0040	/* Transmit FIFO Service */
+#define	RCVSERV			0x0080	/* Receive FIFO Service */
+
+/* TWI_FIFO_CTRL Masks */
+#define	XMTFLUSH		0x0001	/* Transmit Buffer Flush */
+#define	RCVFLUSH		0x0002	/* Receive Buffer Flush */
+#define	XMTINTLEN		0x0004	/* Transmit Buffer Interrupt Length */
+#define	RCVINTLEN		0x0008	/* Receive Buffer Interrupt Length */
+
+/* TWI_FIFO_STAT Masks */
+#define	XMTSTAT			0x0003	/* Transmit FIFO Status */
+#define	XMT_EMPTY		0x0000	/* Transmit FIFO Empty */
+#define	XMT_HALF		0x0001	/* Transmit FIFO Has 1 Byte To Write */
+#define	XMT_FULL		0x0003	/* Transmit FIFO Full (2 Bytes To Write) */
+
+#define	RCVSTAT			0x000C	/* Receive FIFO Status */
+#define	RCV_EMPTY		0x0000	/* Receive FIFO Empty */
+#define	RCV_HALF		0x0004	/* Receive FIFO Has 1 Byte To Read */
+#define	RCV_FULL		0x000C	/* Receive FIFO Full (2 Bytes To Read) */
+
+/*
+ * CONTROLLER AREA NETWORK (CAN) MASKS
+ */
+/* CAN_CONTROL Masks */
+#define	SRS			0x0001	/* Software Reset */
+#define	DNM			0x0002	/* Device Net Mode */
+#define	ABO			0x0004	/* Auto-Bus On Enable */
+#define	TXPRIO			0x0008	/* TX Priority (Priority/Mailbox*) */
+#define	WBA			0x0010	/* Wake-Up On CAN Bus Activity Enable */
+#define	SMR			0x0020	/* Sleep Mode Request */
+#define	CSR			0x0040	/* CAN Suspend Mode Request */
+#define	CCR			0x0080	/* CAN Configuration Mode Request */
+
+/* CAN_STATUS Masks */
+#define	WT			0x0001	/* TX Warning Flag */
+#define	WR			0x0002	/* RX Warning Flag */
+#define	EP			0x0004	/* Error Passive Mode */
+#define	EBO			0x0008	/* Error Bus Off Mode */
+#define	SMA			0x0020	/* Sleep Mode Acknowledge */
+#define	CSA			0x0040	/* Suspend Mode Acknowledge */
+#define	CCA			0x0080	/* Configuration Mode Acknowledge */
+#define	MBPTR			0x1F00	/* Mailbox Pointer */
+#define	TRM			0x4000	/* Transmit Mode */
+#define	REC			0x8000	/* Receive Mode */
+
+/* CAN_CLOCK Masks */
+#define	BRP			0x03FF	/* Bit-Rate Pre-Scaler */
+
+/* CAN_TIMING Masks */
+#define	TSEG1			0x000F	/* Time Segment 1 */
+#define	TSEG2			0x0070	/* Time Segment 2 */
+#define	SAM			0x0080	/* Sampling */
+#define	SJW			0x0300	/* Synchronization Jump Width */
+
+/* CAN_DEBUG Masks */
+#define	DEC			0x0001	/* Disable CAN Error Counters */
+#define	DRI			0x0002	/* Disable CAN RX Input */
+#define	DTO			0x0004	/* Disable CAN TX Output */
+#define	DIL			0x0008	/* Disable CAN Internal Loop */
+#define	MAA			0x0010	/* Mode Auto-Acknowledge Enable */
+#define	MRB			0x0020	/* Mode Read Back Enable */
+#define	CDE			0x8000	/* CAN Debug Enable */
+
+/* CAN_CEC Masks */
+#define	RXECNT			0x00FF	/* Receive Error Counter */
+#define	TXECNT			0xFF00	/* Transmit Error Counter */
+
+/* CAN_INTR Masks */
+#define	MBRIF			0x0001	/* Mailbox Receive Interrupt */
+#define	MBTIF			0x0002	/* Mailbox Transmit Interrupt */
+#define	GIRQ			0x0004	/* Global Interrupt */
+#define	SMACK			0x0008	/* Sleep Mode Acknowledge */
+#define	CANTX			0x0040	/* CAN TX Bus Value */
+#define	CANRX			0x0080	/* CAN RX Bus Value */
+
+/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
+#define DFC			0xFFFF	/* Data Filtering Code (If Enabled) (ID0) */
+#define	EXTID_LO		0xFFFF	/* Lower 16 Bits of Extended Identifier (ID0) */
+#define	EXTID_HI		0x0003	/* Upper 2 Bits of Extended Identifier (ID1) */
+#define	BASEID			0x1FFC	/* Base Identifier */
+#define	IDE			0x2000	/* Identifier Extension */
+#define	RTR			0x4000	/* Remote Frame Transmission Request */
+#define	AME			0x8000	/* Acceptance Mask Enable */
+
+/* CAN_MBxx_TIMESTAMP Masks */
+#define TSV			0xFFFF	/* Timestamp */
+
+/* CAN_MBxx_LENGTH Masks */
+#define DLC			0x000F	/* Data Length Code */
+
+/* CAN_AMxxH and CAN_AMxxL Masks */
+#define DFM			0xFFFF	/* Data Field Mask (If Enabled) (CAN_AMxxL) */
+#define	EXTID_LO		0xFFFF	/* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
+#define	EXTID_HI		0x0003	/* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
+#define	BASEID			0x1FFC	/* Base Identifier */
+#define	AMIDE			0x2000	/* Acceptance Mask ID Extension Enable */
+#define	FMD			0x4000	/* Full Mask Data Field Enable */
+#define	FDF			0x8000	/* Filter On Data Field Enable */
+
+/* CAN_MC1 Masks */
+#define	MC0			0x0001	/* Enable Mailbox 0 */
+#define	MC1			0x0002	/* Enable Mailbox 1 */
+#define	MC2			0x0004	/* Enable Mailbox 2 */
+#define	MC3			0x0008	/* Enable Mailbox 3 */
+#define	MC4			0x0010	/* Enable Mailbox 4 */
+#define	MC5			0x0020	/* Enable Mailbox 5 */
+#define	MC6			0x0040	/* Enable Mailbox 6 */
+#define	MC7			0x0080	/* Enable Mailbox 7 */
+#define	MC8			0x0100	/* Enable Mailbox 8 */
+#define	MC9			0x0200	/* Enable Mailbox 9 */
+#define	MC10			0x0400	/* Enable Mailbox 10 */
+#define	MC11			0x0800	/* Enable Mailbox 11 */
+#define	MC12			0x1000	/* Enable Mailbox 12 */
+#define	MC13			0x2000	/* Enable Mailbox 13 */
+#define	MC14			0x4000	/* Enable Mailbox 14 */
+#define	MC15			0x8000	/* Enable Mailbox 15 */
+
+/* CAN_MC2 Masks */
+#define	MC16			0x0001	/* Enable Mailbox 16 */
+#define	MC17			0x0002	/* Enable Mailbox 17 */
+#define	MC18			0x0004	/* Enable Mailbox 18 */
+#define	MC19			0x0008	/* Enable Mailbox 19 */
+#define	MC20			0x0010	/* Enable Mailbox 20 */
+#define	MC21			0x0020	/* Enable Mailbox 21 */
+#define	MC22			0x0040	/* Enable Mailbox 22 */
+#define	MC23			0x0080	/* Enable Mailbox 23 */
+#define	MC24			0x0100	/* Enable Mailbox 24 */
+#define	MC25			0x0200	/* Enable Mailbox 25 */
+#define	MC26			0x0400	/* Enable Mailbox 26 */
+#define	MC27			0x0800	/* Enable Mailbox 27 */
+#define	MC28			0x1000	/* Enable Mailbox 28 */
+#define	MC29			0x2000	/* Enable Mailbox 29 */
+#define	MC30			0x4000	/* Enable Mailbox 30 */
+#define	MC31			0x8000	/* Enable Mailbox 31 */
+
+/* CAN_MD1 Masks */
+#define	MD0			0x0001	/* Enable Mailbox 0 For Receive */
+#define	MD1			0x0002	/* Enable Mailbox 1 For Receive */
+#define	MD2			0x0004	/* Enable Mailbox 2 For Receive */
+#define	MD3			0x0008	/* Enable Mailbox 3 For Receive */
+#define	MD4			0x0010	/* Enable Mailbox 4 For Receive */
+#define	MD5			0x0020	/* Enable Mailbox 5 For Receive */
+#define	MD6			0x0040	/* Enable Mailbox 6 For Receive */
+#define	MD7			0x0080	/* Enable Mailbox 7 For Receive */
+#define	MD8			0x0100	/* Enable Mailbox 8 For Receive */
+#define	MD9			0x0200	/* Enable Mailbox 9 For Receive */
+#define	MD10			0x0400	/* Enable Mailbox 10 For Receive */
+#define	MD11			0x0800	/* Enable Mailbox 11 For Receive */
+#define	MD12			0x1000	/* Enable Mailbox 12 For Receive */
+#define	MD13			0x2000	/* Enable Mailbox 13 For Receive */
+#define	MD14			0x4000	/* Enable Mailbox 14 For Receive */
+#define	MD15			0x8000	/* Enable Mailbox 15 For Receive */
+
+/* CAN_MD2 Masks */
+#define	MD16			0x0001	/* Enable Mailbox 16 For Receive */
+#define	MD17			0x0002	/* Enable Mailbox 17 For Receive */
+#define	MD18			0x0004	/* Enable Mailbox 18 For Receive */
+#define	MD19			0x0008	/* Enable Mailbox 19 For Receive */
+#define	MD20			0x0010	/* Enable Mailbox 20 For Receive */
+#define	MD21			0x0020	/* Enable Mailbox 21 For Receive */
+#define	MD22			0x0040	/* Enable Mailbox 22 For Receive */
+#define	MD23			0x0080	/* Enable Mailbox 23 For Receive */
+#define	MD24			0x0100	/* Enable Mailbox 24 For Receive */
+#define	MD25			0x0200	/* Enable Mailbox 25 For Receive */
+#define	MD26			0x0400	/* Enable Mailbox 26 For Receive */
+#define	MD27			0x0800	/* Enable Mailbox 27 For Receive */
+#define	MD28			0x1000	/* Enable Mailbox 28 For Receive */
+#define	MD29			0x2000	/* Enable Mailbox 29 For Receive */
+#define	MD30			0x4000	/* Enable Mailbox 30 For Receive */
+#define	MD31			0x8000	/* Enable Mailbox 31 For Receive */
+
+/* CAN_RMP1 Masks */
+#define	RMP0			0x0001	/* RX Message Pending In Mailbox 0 */
+#define	RMP1			0x0002	/* RX Message Pending In Mailbox 1 */
+#define	RMP2			0x0004	/* RX Message Pending In Mailbox 2 */
+#define	RMP3			0x0008	/* RX Message Pending In Mailbox 3 */
+#define	RMP4			0x0010	/* RX Message Pending In Mailbox 4 */
+#define	RMP5			0x0020	/* RX Message Pending In Mailbox 5 */
+#define	RMP6			0x0040	/* RX Message Pending In Mailbox 6 */
+#define	RMP7			0x0080	/* RX Message Pending In Mailbox 7 */
+#define	RMP8			0x0100	/* RX Message Pending In Mailbox 8 */
+#define	RMP9			0x0200	/* RX Message Pending In Mailbox 9 */
+#define	RMP10			0x0400	/* RX Message Pending In Mailbox 10 */
+#define	RMP11			0x0800	/* RX Message Pending In Mailbox 11 */
+#define	RMP12			0x1000	/* RX Message Pending In Mailbox 12 */
+#define	RMP13			0x2000	/* RX Message Pending In Mailbox 13 */
+#define	RMP14			0x4000	/* RX Message Pending In Mailbox 14 */
+#define	RMP15			0x8000	/* RX Message Pending In Mailbox 15 */
+
+/* CAN_RMP2 Masks */
+#define	RMP16			0x0001	/* RX Message Pending In Mailbox 16 */
+#define	RMP17			0x0002	/* RX Message Pending In Mailbox 17 */
+#define	RMP18			0x0004	/* RX Message Pending In Mailbox 18 */
+#define	RMP19			0x0008	/* RX Message Pending In Mailbox 19 */
+#define	RMP20			0x0010	/* RX Message Pending In Mailbox 20 */
+#define	RMP21			0x0020	/* RX Message Pending In Mailbox 21 */
+#define	RMP22			0x0040	/* RX Message Pending In Mailbox 22 */
+#define	RMP23			0x0080	/* RX Message Pending In Mailbox 23 */
+#define	RMP24			0x0100	/* RX Message Pending In Mailbox 24 */
+#define	RMP25			0x0200	/* RX Message Pending In Mailbox 25 */
+#define	RMP26			0x0400	/* RX Message Pending In Mailbox 26 */
+#define	RMP27			0x0800	/* RX Message Pending In Mailbox 27 */
+#define	RMP28			0x1000	/* RX Message Pending In Mailbox 28 */
+#define	RMP29			0x2000	/* RX Message Pending In Mailbox 29 */
+#define	RMP30			0x4000	/* RX Message Pending In Mailbox 30 */
+#define	RMP31			0x8000	/* RX Message Pending In Mailbox 31 */
+
+/* CAN_RML1 Masks */
+#define	RML0			0x0001	/* RX Message Lost In Mailbox 0 */
+#define	RML1			0x0002	/* RX Message Lost In Mailbox 1 */
+#define	RML2			0x0004	/* RX Message Lost In Mailbox 2 */
+#define	RML3			0x0008	/* RX Message Lost In Mailbox 3 */
+#define	RML4			0x0010	/* RX Message Lost In Mailbox 4 */
+#define	RML5			0x0020	/* RX Message Lost In Mailbox 5 */
+#define	RML6			0x0040	/* RX Message Lost In Mailbox 6 */
+#define	RML7			0x0080	/* RX Message Lost In Mailbox 7 */
+#define	RML8			0x0100	/* RX Message Lost In Mailbox 8 */
+#define	RML9			0x0200	/* RX Message Lost In Mailbox 9 */
+#define	RML10			0x0400	/* RX Message Lost In Mailbox 10 */
+#define	RML11			0x0800	/* RX Message Lost In Mailbox 11 */
+#define	RML12			0x1000	/* RX Message Lost In Mailbox 12 */
+#define	RML13			0x2000	/* RX Message Lost In Mailbox 13 */
+#define	RML14			0x4000	/* RX Message Lost In Mailbox 14 */
+#define	RML15			0x8000	/* RX Message Lost In Mailbox 15 */
+
+/* CAN_RML2 Masks */
+#define	RML16			0x0001	/* RX Message Lost In Mailbox 16 */
+#define	RML17			0x0002	/* RX Message Lost In Mailbox 17 */
+#define	RML18			0x0004	/* RX Message Lost In Mailbox 18 */
+#define	RML19			0x0008	/* RX Message Lost In Mailbox 19 */
+#define	RML20			0x0010	/* RX Message Lost In Mailbox 20 */
+#define	RML21			0x0020	/* RX Message Lost In Mailbox 21 */
+#define	RML22			0x0040	/* RX Message Lost In Mailbox 22 */
+#define	RML23			0x0080	/* RX Message Lost In Mailbox 23 */
+#define	RML24			0x0100	/* RX Message Lost In Mailbox 24 */
+#define	RML25			0x0200	/* RX Message Lost In Mailbox 25 */
+#define	RML26			0x0400	/* RX Message Lost In Mailbox 26 */
+#define	RML27			0x0800	/* RX Message Lost In Mailbox 27 */
+#define	RML28			0x1000	/* RX Message Lost In Mailbox 28 */
+#define	RML29			0x2000	/* RX Message Lost In Mailbox 29 */
+#define	RML30			0x4000	/* RX Message Lost In Mailbox 30 */
+#define	RML31			0x8000	/* RX Message Lost In Mailbox 31 */
+
+/* CAN_OPSS1 Masks */
+#define	OPSS0			0x0001	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
+#define	OPSS1			0x0002	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
+#define	OPSS2			0x0004	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
+#define	OPSS3			0x0008	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
+#define	OPSS4			0x0010	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
+#define	OPSS5			0x0020	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
+#define	OPSS6			0x0040	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
+#define	OPSS7			0x0080	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
+#define	OPSS8			0x0100	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
+#define	OPSS9			0x0200	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
+#define	OPSS10			0x0400	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
+#define	OPSS11			0x0800	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
+#define	OPSS12			0x1000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
+#define	OPSS13			0x2000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
+#define	OPSS14			0x4000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
+#define	OPSS15			0x8000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
+
+/* CAN_OPSS2 Masks */
+#define	OPSS16			0x0001	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
+#define	OPSS17			0x0002	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
+#define	OPSS18			0x0004	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
+#define	OPSS19			0x0008	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
+#define	OPSS20			0x0010	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
+#define	OPSS21			0x0020	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
+#define	OPSS22			0x0040	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
+#define	OPSS23			0x0080	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
+#define	OPSS24			0x0100	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
+#define	OPSS25			0x0200	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
+#define	OPSS26			0x0400	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
+#define	OPSS27			0x0800	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
+#define	OPSS28			0x1000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
+#define	OPSS29			0x2000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
+#define	OPSS30			0x4000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
+#define	OPSS31			0x8000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
+
+/* CAN_TRR1 Masks */
+#define	TRR0			0x0001	/* Deny But Don't Lock Access To Mailbox 0 */
+#define	TRR1			0x0002	/* Deny But Don't Lock Access To Mailbox 1 */
+#define	TRR2			0x0004	/* Deny But Don't Lock Access To Mailbox 2 */
+#define	TRR3			0x0008	/* Deny But Don't Lock Access To Mailbox 3 */
+#define	TRR4			0x0010	/* Deny But Don't Lock Access To Mailbox 4 */
+#define	TRR5			0x0020	/* Deny But Don't Lock Access To Mailbox 5 */
+#define	TRR6			0x0040	/* Deny But Don't Lock Access To Mailbox 6 */
+#define	TRR7			0x0080	/* Deny But Don't Lock Access To Mailbox 7 */
+#define	TRR8			0x0100	/* Deny But Don't Lock Access To Mailbox 8 */
+#define	TRR9			0x0200	/* Deny But Don't Lock Access To Mailbox 9 */
+#define	TRR10			0x0400	/* Deny But Don't Lock Access To Mailbox 10 */
+#define	TRR11			0x0800	/* Deny But Don't Lock Access To Mailbox 11 */
+#define	TRR12			0x1000	/* Deny But Don't Lock Access To Mailbox 12 */
+#define	TRR13			0x2000	/* Deny But Don't Lock Access To Mailbox 13 */
+#define	TRR14			0x4000	/* Deny But Don't Lock Access To Mailbox 14 */
+#define	TRR15			0x8000	/* Deny But Don't Lock Access To Mailbox 15 */
+
+/* CAN_TRR2 Masks */
+#define	TRR16			0x0001	/* Deny But Don't Lock Access To Mailbox 16 */
+#define	TRR17			0x0002	/* Deny But Don't Lock Access To Mailbox 17 */
+#define	TRR18			0x0004	/* Deny But Don't Lock Access To Mailbox 18 */
+#define	TRR19			0x0008	/* Deny But Don't Lock Access To Mailbox 19 */
+#define	TRR20			0x0010	/* Deny But Don't Lock Access To Mailbox 20 */
+#define	TRR21			0x0020	/* Deny But Don't Lock Access To Mailbox 21 */
+#define	TRR22			0x0040	/* Deny But Don't Lock Access To Mailbox 22 */
+#define	TRR23			0x0080	/* Deny But Don't Lock Access To Mailbox 23 */
+#define	TRR24			0x0100	/* Deny But Don't Lock Access To Mailbox 24 */
+#define	TRR25			0x0200	/* Deny But Don't Lock Access To Mailbox 25 */
+#define	TRR26			0x0400	/* Deny But Don't Lock Access To Mailbox 26 */
+#define	TRR27			0x0800	/* Deny But Don't Lock Access To Mailbox 27 */
+#define	TRR28			0x1000	/* Deny But Don't Lock Access To Mailbox 28 */
+#define	TRR29			0x2000	/* Deny But Don't Lock Access To Mailbox 29 */
+#define	TRR30			0x4000	/* Deny But Don't Lock Access To Mailbox 30 */
+#define	TRR31			0x8000	/* Deny But Don't Lock Access To Mailbox 31 */
+
+/* CAN_TRS1 Masks */
+#define	TRS0			0x0001	/* Remote Frame Request For Mailbox 0 */
+#define	TRS1			0x0002	/* Remote Frame Request For Mailbox 1 */
+#define	TRS2			0x0004	/* Remote Frame Request For Mailbox 2 */
+#define	TRS3			0x0008	/* Remote Frame Request For Mailbox 3 */
+#define	TRS4			0x0010	/* Remote Frame Request For Mailbox 4 */
+#define	TRS5			0x0020	/* Remote Frame Request For Mailbox 5 */
+#define	TRS6			0x0040	/* Remote Frame Request For Mailbox 6 */
+#define	TRS7			0x0080	/* Remote Frame Request For Mailbox 7 */
+#define	TRS8			0x0100	/* Remote Frame Request For Mailbox 8 */
+#define	TRS9			0x0200	/* Remote Frame Request For Mailbox 9 */
+#define	TRS10			0x0400	/* Remote Frame Request For Mailbox 10 */
+#define	TRS11			0x0800	/* Remote Frame Request For Mailbox 11 */
+#define	TRS12			0x1000	/* Remote Frame Request For Mailbox 12 */
+#define	TRS13			0x2000	/* Remote Frame Request For Mailbox 13 */
+#define	TRS14			0x4000	/* Remote Frame Request For Mailbox 14 */
+#define	TRS15			0x8000	/* Remote Frame Request For Mailbox 15 */
+
+/* CAN_TRS2 Masks */
+#define	TRS16			0x0001	/* Remote Frame Request For Mailbox 16 */
+#define	TRS17			0x0002	/* Remote Frame Request For Mailbox 17 */
+#define	TRS18			0x0004	/* Remote Frame Request For Mailbox 18 */
+#define	TRS19			0x0008	/* Remote Frame Request For Mailbox 19 */
+#define	TRS20			0x0010	/* Remote Frame Request For Mailbox 20 */
+#define	TRS21			0x0020	/* Remote Frame Request For Mailbox 21 */
+#define	TRS22			0x0040	/* Remote Frame Request For Mailbox 22 */
+#define	TRS23			0x0080	/* Remote Frame Request For Mailbox 23 */
+#define	TRS24			0x0100	/* Remote Frame Request For Mailbox 24 */
+#define	TRS25			0x0200	/* Remote Frame Request For Mailbox 25 */
+#define	TRS26			0x0400	/* Remote Frame Request For Mailbox 26 */
+#define	TRS27			0x0800	/* Remote Frame Request For Mailbox 27 */
+#define	TRS28			0x1000	/* Remote Frame Request For Mailbox 28 */
+#define	TRS29			0x2000	/* Remote Frame Request For Mailbox 29 */
+#define	TRS30			0x4000	/* Remote Frame Request For Mailbox 30 */
+#define	TRS31			0x8000	/* Remote Frame Request For Mailbox 31 */
+
+/* CAN_AA1 Masks */
+#define	AA0			0x0001	/* Aborted Message In Mailbox 0 */
+#define	AA1			0x0002	/* Aborted Message In Mailbox 1 */
+#define	AA2			0x0004	/* Aborted Message In Mailbox 2 */
+#define	AA3			0x0008	/* Aborted Message In Mailbox 3 */
+#define	AA4			0x0010	/* Aborted Message In Mailbox 4 */
+#define	AA5			0x0020	/* Aborted Message In Mailbox 5 */
+#define	AA6			0x0040	/* Aborted Message In Mailbox 6 */
+#define	AA7			0x0080	/* Aborted Message In Mailbox 7 */
+#define	AA8			0x0100	/* Aborted Message In Mailbox 8 */
+#define	AA9			0x0200	/* Aborted Message In Mailbox 9 */
+#define	AA10			0x0400	/* Aborted Message In Mailbox 10 */
+#define	AA11			0x0800	/* Aborted Message In Mailbox 11 */
+#define	AA12			0x1000	/* Aborted Message In Mailbox 12 */
+#define	AA13			0x2000	/* Aborted Message In Mailbox 13 */
+#define	AA14			0x4000	/* Aborted Message In Mailbox 14 */
+#define	AA15			0x8000	/* Aborted Message In Mailbox 15 */
+
+/* CAN_AA2 Masks */
+#define	AA16			0x0001	/* Aborted Message In Mailbox 16 */
+#define	AA17			0x0002	/* Aborted Message In Mailbox 17 */
+#define	AA18			0x0004	/* Aborted Message In Mailbox 18 */
+#define	AA19			0x0008	/* Aborted Message In Mailbox 19 */
+#define	AA20			0x0010	/* Aborted Message In Mailbox 20 */
+#define	AA21			0x0020	/* Aborted Message In Mailbox 21 */
+#define	AA22			0x0040	/* Aborted Message In Mailbox 22 */
+#define	AA23			0x0080	/* Aborted Message In Mailbox 23 */
+#define	AA24			0x0100	/* Aborted Message In Mailbox 24 */
+#define	AA25			0x0200	/* Aborted Message In Mailbox 25 */
+#define	AA26			0x0400	/* Aborted Message In Mailbox 26 */
+#define	AA27			0x0800	/* Aborted Message In Mailbox 27 */
+#define	AA28			0x1000	/* Aborted Message In Mailbox 28 */
+#define	AA29			0x2000	/* Aborted Message In Mailbox 29 */
+#define	AA30			0x4000	/* Aborted Message In Mailbox 30 */
+#define	AA31			0x8000	/* Aborted Message In Mailbox 31 */
+
+/* CAN_TA1 Masks */
+#define	TA0			0x0001	/* Transmit Successful From Mailbox 0 */
+#define	TA1			0x0002	/* Transmit Successful From Mailbox 1 */
+#define	TA2			0x0004	/* Transmit Successful From Mailbox 2 */
+#define	TA3			0x0008	/* Transmit Successful From Mailbox 3 */
+#define	TA4			0x0010	/* Transmit Successful From Mailbox 4 */
+#define	TA5			0x0020	/* Transmit Successful From Mailbox 5 */
+#define	TA6			0x0040	/* Transmit Successful From Mailbox 6 */
+#define	TA7			0x0080	/* Transmit Successful From Mailbox 7 */
+#define	TA8			0x0100	/* Transmit Successful From Mailbox 8 */
+#define	TA9			0x0200	/* Transmit Successful From Mailbox 9 */
+#define	TA10			0x0400	/* Transmit Successful From Mailbox 10 */
+#define	TA11			0x0800	/* Transmit Successful From Mailbox 11 */
+#define	TA12			0x1000	/* Transmit Successful From Mailbox 12 */
+#define	TA13			0x2000	/* Transmit Successful From Mailbox 13 */
+#define	TA14			0x4000	/* Transmit Successful From Mailbox 14 */
+#define	TA15			0x8000	/* Transmit Successful From Mailbox 15 */
+
+/* CAN_TA2 Masks */
+#define	TA16			0x0001	/* Transmit Successful From Mailbox 16 */
+#define	TA17			0x0002	/* Transmit Successful From Mailbox 17 */
+#define	TA18			0x0004	/* Transmit Successful From Mailbox 18 */
+#define	TA19			0x0008	/* Transmit Successful From Mailbox 19 */
+#define	TA20			0x0010	/* Transmit Successful From Mailbox 20 */
+#define	TA21			0x0020	/* Transmit Successful From Mailbox 21 */
+#define	TA22			0x0040	/* Transmit Successful From Mailbox 22 */
+#define	TA23			0x0080	/* Transmit Successful From Mailbox 23 */
+#define	TA24			0x0100	/* Transmit Successful From Mailbox 24 */
+#define	TA25			0x0200	/* Transmit Successful From Mailbox 25 */
+#define	TA26			0x0400	/* Transmit Successful From Mailbox 26 */
+#define	TA27			0x0800	/* Transmit Successful From Mailbox 27 */
+#define	TA28			0x1000	/* Transmit Successful From Mailbox 28 */
+#define	TA29			0x2000	/* Transmit Successful From Mailbox 29 */
+#define	TA30			0x4000	/* Transmit Successful From Mailbox 30 */
+#define	TA31			0x8000	/* Transmit Successful From Mailbox 31 */
+
+/* CAN_MBTD Masks */
+#define TDPTR			0x001F	/* Mailbox To Temporarily Disable */
+#define	TDA			0x0040	/* Temporary Disable Acknowledge */
+#define	TDR			0x0080	/* Temporary Disable Request */
+
+/* CAN_RFH1 Masks */
+#define	RFH0			0x0001	/* Enable Automatic Remote Frame Handling For Mailbox 0 */
+#define	RFH1			0x0002	/* Enable Automatic Remote Frame Handling For Mailbox 1 */
+#define	RFH2			0x0004	/* Enable Automatic Remote Frame Handling For Mailbox 2 */
+#define	RFH3			0x0008	/* Enable Automatic Remote Frame Handling For Mailbox 3 */
+#define	RFH4			0x0010	/* Enable Automatic Remote Frame Handling For Mailbox 4 */
+#define	RFH5			0x0020	/* Enable Automatic Remote Frame Handling For Mailbox 5 */
+#define	RFH6			0x0040	/* Enable Automatic Remote Frame Handling For Mailbox 6 */
+#define	RFH7			0x0080	/* Enable Automatic Remote Frame Handling For Mailbox 7 */
+#define	RFH8			0x0100	/* Enable Automatic Remote Frame Handling For Mailbox 8 */
+#define	RFH9			0x0200	/* Enable Automatic Remote Frame Handling For Mailbox 9 */
+#define	RFH10			0x0400	/* Enable Automatic Remote Frame Handling For Mailbox 10 */
+#define	RFH11			0x0800	/* Enable Automatic Remote Frame Handling For Mailbox 11 */
+#define	RFH12			0x1000	/* Enable Automatic Remote Frame Handling For Mailbox 12 */
+#define	RFH13			0x2000	/* Enable Automatic Remote Frame Handling For Mailbox 13 */
+#define	RFH14			0x4000	/* Enable Automatic Remote Frame Handling For Mailbox 14 */
+#define	RFH15			0x8000	/* Enable Automatic Remote Frame Handling For Mailbox 15 */
+
+/* CAN_RFH2 Masks */
+#define	RFH16			0x0001	/* Enable Automatic Remote Frame Handling For Mailbox 16 */
+#define	RFH17			0x0002	/* Enable Automatic Remote Frame Handling For Mailbox 17 */
+#define	RFH18			0x0004	/* Enable Automatic Remote Frame Handling For Mailbox 18 */
+#define	RFH19			0x0008	/* Enable Automatic Remote Frame Handling For Mailbox 19 */
+#define	RFH20			0x0010	/* Enable Automatic Remote Frame Handling For Mailbox 20 */
+#define	RFH21			0x0020	/* Enable Automatic Remote Frame Handling For Mailbox 21 */
+#define	RFH22			0x0040	/* Enable Automatic Remote Frame Handling For Mailbox 22 */
+#define	RFH23			0x0080	/* Enable Automatic Remote Frame Handling For Mailbox 23 */
+#define	RFH24			0x0100	/* Enable Automatic Remote Frame Handling For Mailbox 24 */
+#define	RFH25			0x0200	/* Enable Automatic Remote Frame Handling For Mailbox 25 */
+#define	RFH26			0x0400	/* Enable Automatic Remote Frame Handling For Mailbox 26 */
+#define	RFH27			0x0800	/* Enable Automatic Remote Frame Handling For Mailbox 27 */
+#define	RFH28			0x1000	/* Enable Automatic Remote Frame Handling For Mailbox 28 */
+#define	RFH29			0x2000	/* Enable Automatic Remote Frame Handling For Mailbox 29 */
+#define	RFH30			0x4000	/* Enable Automatic Remote Frame Handling For Mailbox 30 */
+#define	RFH31			0x8000	/* Enable Automatic Remote Frame Handling For Mailbox 31 */
+
+/* CAN_MBTIF1 Masks */
+#define	MBTIF0			0x0001	/* TX Interrupt Active In Mailbox 0 */
+#define	MBTIF1			0x0002	/* TX Interrupt Active In Mailbox 1 */
+#define	MBTIF2			0x0004	/* TX Interrupt Active In Mailbox 2 */
+#define	MBTIF3			0x0008	/* TX Interrupt Active In Mailbox 3 */
+#define	MBTIF4			0x0010	/* TX Interrupt Active In Mailbox 4 */
+#define	MBTIF5			0x0020	/* TX Interrupt Active In Mailbox 5 */
+#define	MBTIF6			0x0040	/* TX Interrupt Active In Mailbox 6 */
+#define	MBTIF7			0x0080	/* TX Interrupt Active In Mailbox 7 */
+#define	MBTIF8			0x0100	/* TX Interrupt Active In Mailbox 8 */
+#define	MBTIF9			0x0200	/* TX Interrupt Active In Mailbox 9 */
+#define	MBTIF10			0x0400	/* TX Interrupt Active In Mailbox 10 */
+#define	MBTIF11			0x0800	/* TX Interrupt Active In Mailbox 11 */
+#define	MBTIF12			0x1000	/* TX Interrupt Active In Mailbox 12 */
+#define	MBTIF13			0x2000	/* TX Interrupt Active In Mailbox 13 */
+#define	MBTIF14			0x4000	/* TX Interrupt Active In Mailbox 14 */
+#define	MBTIF15			0x8000	/* TX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBTIF2 Masks */
+#define	MBTIF16			0x0001	/* TX Interrupt Active In Mailbox 16 */
+#define	MBTIF17			0x0002	/* TX Interrupt Active In Mailbox 17 */
+#define	MBTIF18			0x0004	/* TX Interrupt Active In Mailbox 18 */
+#define	MBTIF19			0x0008	/* TX Interrupt Active In Mailbox 19 */
+#define	MBTIF20			0x0010	/* TX Interrupt Active In Mailbox 20 */
+#define	MBTIF21			0x0020	/* TX Interrupt Active In Mailbox 21 */
+#define	MBTIF22			0x0040	/* TX Interrupt Active In Mailbox 22 */
+#define	MBTIF23			0x0080	/* TX Interrupt Active In Mailbox 23 */
+#define	MBTIF24			0x0100	/* TX Interrupt Active In Mailbox 24 */
+#define	MBTIF25			0x0200	/* TX Interrupt Active In Mailbox 25 */
+#define	MBTIF26			0x0400	/* TX Interrupt Active In Mailbox 26 */
+#define	MBTIF27			0x0800	/* TX Interrupt Active In Mailbox 27 */
+#define	MBTIF28			0x1000	/* TX Interrupt Active In Mailbox 28 */
+#define	MBTIF29			0x2000	/* TX Interrupt Active In Mailbox 29 */
+#define	MBTIF30			0x4000	/* TX Interrupt Active In Mailbox 30 */
+#define	MBTIF31			0x8000	/* TX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBRIF1 Masks */
+#define	MBRIF0			0x0001	/* RX Interrupt Active In Mailbox 0 */
+#define	MBRIF1			0x0002	/* RX Interrupt Active In Mailbox 1 */
+#define	MBRIF2			0x0004	/* RX Interrupt Active In Mailbox 2 */
+#define	MBRIF3			0x0008	/* RX Interrupt Active In Mailbox 3 */
+#define	MBRIF4			0x0010	/* RX Interrupt Active In Mailbox 4 */
+#define	MBRIF5			0x0020	/* RX Interrupt Active In Mailbox 5 */
+#define	MBRIF6			0x0040	/* RX Interrupt Active In Mailbox 6 */
+#define	MBRIF7			0x0080	/* RX Interrupt Active In Mailbox 7 */
+#define	MBRIF8			0x0100	/* RX Interrupt Active In Mailbox 8 */
+#define	MBRIF9			0x0200	/* RX Interrupt Active In Mailbox 9 */
+#define	MBRIF10			0x0400	/* RX Interrupt Active In Mailbox 10 */
+#define	MBRIF11			0x0800	/* RX Interrupt Active In Mailbox 11 */
+#define	MBRIF12			0x1000	/* RX Interrupt Active In Mailbox 12 */
+#define	MBRIF13			0x2000	/* RX Interrupt Active In Mailbox 13 */
+#define	MBRIF14			0x4000	/* RX Interrupt Active In Mailbox 14 */
+#define	MBRIF15			0x8000	/* RX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBRIF2 Masks */
+#define	MBRIF16			0x0001	/* RX Interrupt Active In Mailbox 16 */
+#define	MBRIF17			0x0002	/* RX Interrupt Active In Mailbox 17 */
+#define	MBRIF18			0x0004	/* RX Interrupt Active In Mailbox 18 */
+#define	MBRIF19			0x0008	/* RX Interrupt Active In Mailbox 19 */
+#define	MBRIF20			0x0010	/* RX Interrupt Active In Mailbox 20 */
+#define	MBRIF21			0x0020	/* RX Interrupt Active In Mailbox 21 */
+#define	MBRIF22			0x0040	/* RX Interrupt Active In Mailbox 22 */
+#define	MBRIF23			0x0080	/* RX Interrupt Active In Mailbox 23 */
+#define	MBRIF24			0x0100	/* RX Interrupt Active In Mailbox 24 */
+#define	MBRIF25			0x0200	/* RX Interrupt Active In Mailbox 25 */
+#define	MBRIF26			0x0400	/* RX Interrupt Active In Mailbox 26 */
+#define	MBRIF27			0x0800	/* RX Interrupt Active In Mailbox 27 */
+#define	MBRIF28			0x1000	/* RX Interrupt Active In Mailbox 28 */
+#define	MBRIF29			0x2000	/* RX Interrupt Active In Mailbox 29 */
+#define	MBRIF30			0x4000	/* RX Interrupt Active In Mailbox 30 */
+#define	MBRIF31			0x8000	/* RX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBIM1 Masks */
+#define	MBIM0			0x0001	/* Enable Interrupt For Mailbox 0 */
+#define	MBIM1			0x0002	/* Enable Interrupt For Mailbox 1 */
+#define	MBIM2			0x0004	/* Enable Interrupt For Mailbox 2 */
+#define	MBIM3			0x0008	/* Enable Interrupt For Mailbox 3 */
+#define	MBIM4			0x0010	/* Enable Interrupt For Mailbox 4 */
+#define	MBIM5			0x0020	/* Enable Interrupt For Mailbox 5 */
+#define	MBIM6			0x0040	/* Enable Interrupt For Mailbox 6 */
+#define	MBIM7			0x0080	/* Enable Interrupt For Mailbox 7 */
+#define	MBIM8			0x0100	/* Enable Interrupt For Mailbox 8 */
+#define	MBIM9			0x0200	/* Enable Interrupt For Mailbox 9 */
+#define	MBIM10			0x0400	/* Enable Interrupt For Mailbox 10 */
+#define	MBIM11			0x0800	/* Enable Interrupt For Mailbox 11 */
+#define	MBIM12			0x1000	/* Enable Interrupt For Mailbox 12 */
+#define	MBIM13			0x2000	/* Enable Interrupt For Mailbox 13 */
+#define	MBIM14			0x4000	/* Enable Interrupt For Mailbox 14 */
+#define	MBIM15			0x8000	/* Enable Interrupt For Mailbox 15 */
+
+/* CAN_MBIM2 Masks */
+#define	MBIM16			0x0001	/* Enable Interrupt For Mailbox 16 */
+#define	MBIM17			0x0002	/* Enable Interrupt For Mailbox 17 */
+#define	MBIM18			0x0004	/* Enable Interrupt For Mailbox 18 */
+#define	MBIM19			0x0008	/* Enable Interrupt For Mailbox 19 */
+#define	MBIM20			0x0010	/* Enable Interrupt For Mailbox 20 */
+#define	MBIM21			0x0020	/* Enable Interrupt For Mailbox 21 */
+#define	MBIM22			0x0040	/* Enable Interrupt For Mailbox 22 */
+#define	MBIM23			0x0080	/* Enable Interrupt For Mailbox 23 */
+#define	MBIM24			0x0100	/* Enable Interrupt For Mailbox 24 */
+#define	MBIM25			0x0200	/* Enable Interrupt For Mailbox 25 */
+#define	MBIM26			0x0400	/* Enable Interrupt For Mailbox 26 */
+#define	MBIM27			0x0800	/* Enable Interrupt For Mailbox 27 */
+#define	MBIM28			0x1000	/* Enable Interrupt For Mailbox 28 */
+#define	MBIM29			0x2000	/* Enable Interrupt For Mailbox 29 */
+#define	MBIM30			0x4000	/* Enable Interrupt For Mailbox 30 */
+#define	MBIM31			0x8000	/* Enable Interrupt For Mailbox 31 */
+
+/* CAN_GIM Masks */
+#define	EWTIM			0x0001	/* Enable TX Error Count Interrupt */
+#define	EWRIM			0x0002	/* Enable RX Error Count Interrupt */
+#define	EPIM			0x0004	/* Enable Error-Passive Mode Interrupt */
+#define	BOIM			0x0008	/* Enable Bus Off Interrupt */
+#define	WUIM			0x0010	/* Enable Wake-Up Interrupt */
+#define	UIAIM			0x0020	/* Enable Access To Unimplemented Address Interrupt */
+#define	AAIM			0x0040	/* Enable Abort Acknowledge Interrupt */
+#define	RMLIM			0x0080	/* Enable RX Message Lost Interrupt */
+#define	UCEIM			0x0100	/* Enable Universal Counter Overflow Interrupt */
+#define	EXTIM			0x0200	/* Enable External Trigger Output Interrupt */
+#define	ADIM			0x0400	/* Enable Access Denied Interrupt */
+
+/* CAN_GIS Masks */
+#define	EWTIS			0x0001	/* TX Error Count IRQ Status */
+#define	EWRIS			0x0002	/* RX Error Count IRQ Status */
+#define	EPIS			0x0004	/* Error-Passive Mode IRQ Status */
+#define	BOIS			0x0008	/* Bus Off IRQ Status */
+#define	WUIS			0x0010	/* Wake-Up IRQ Status */
+#define	UIAIS			0x0020	/* Access To Unimplemented Address IRQ Status */
+#define	AAIS			0x0040	/* Abort Acknowledge IRQ Status */
+#define	RMLIS			0x0080	/* RX Message Lost IRQ Status */
+#define	UCEIS			0x0100	/* Universal Counter Overflow IRQ Status */
+#define	EXTIS			0x0200	/* External Trigger Output IRQ Status */
+#define	ADIS			0x0400	/* Access Denied IRQ Status */
+
+/* CAN_GIF Masks */
+#define	EWTIF			0x0001	/* TX Error Count IRQ Flag */
+#define	EWRIF			0x0002	/* RX Error Count IRQ Flag */
+#define	EPIF			0x0004	/* Error-Passive Mode IRQ Flag */
+#define	BOIF			0x0008	/* Bus Off IRQ Flag */
+#define	WUIF			0x0010	/* Wake-Up IRQ Flag */
+#define	UIAIF			0x0020	/* Access To Unimplemented Address IRQ Flag */
+#define	AAIF			0x0040	/* Abort Acknowledge IRQ Flag */
+#define	RMLIF			0x0080	/* RX Message Lost IRQ Flag */
+#define	UCEIF			0x0100	/* Universal Counter Overflow IRQ Flag */
+#define	EXTIF			0x0200	/* External Trigger Output IRQ Flag */
+#define	ADIF			0x0400	/* Access Denied IRQ Flag */
+
+/* CAN_UCCNF Masks */
+#define	UCCNF			0x000F	/* Universal Counter Mode */
+#define UC_STAMP		0x0001	/* Timestamp Mode */
+#define UC_WDOG			0x0002	/* Watchdog Mode */
+#define UC_AUTOTX		0x0003	/* Auto-Transmit Mode */
+#define UC_ERROR		0x0006	/* CAN Error Frame Count */
+#define UC_OVER			0x0007	/* CAN Overload Frame Count */
+#define UC_LOST			0x0008	/* Arbitration Lost During TX Count */
+#define UC_AA			0x0009	/* TX Abort Count */
+#define UC_TA			0x000A	/* TX Successful Count */
+#define UC_REJECT		0x000B	/* RX Message Rejected Count */
+#define UC_RML			0x000C	/* RX Message Lost Count */
+#define UC_RX			0x000D	/* Total Successful RX Messages Count */
+#define UC_RMP			0x000E	/* Successful RX W/Matching ID Count */
+#define UC_ALL			0x000F	/* Correct Message On CAN Bus Line Count */
+#define	UCRC			0x0020	/* Universal Counter Reload/Clear */
+#define	UCCT			0x0040	/* Universal Counter CAN Trigger */
+#define	UCE			0x0080	/* Universal Counter Enable */
+
+/* CAN_ESR Masks */
+#define	ACKE			0x0004	/* Acknowledge Error */
+#define	SER			0x0008	/* Stuff Error */
+#define	CRCE			0x0010	/* CRC Error */
+#define	SA0			0x0020	/* Stuck At Dominant Error */
+#define	BEF			0x0040	/* Bit Error Flag */
+#define	FER			0x0080	/* Form Error Flag */
+
+/* CAN_EWR Masks */
+#define	EWLREC			0x00FF	/* RX Error Count Limit (For EWRIS) */
+#define	EWLTEC			0xFF00	/* TX Error Count Limit (For EWTIS) */
+
+/*
+ * PIN CONTROL REGISTER MASKS
+ */
+/* PORT_MUX Masks */
+#define	PJSE			0x0001	/* Port J SPI/SPORT Enable */
+#define	PJSE_SPORT		0x0000	/* Enable TFS0/DT0PRI */
+#define	PJSE_SPI		0x0001	/* Enable SPI_SSEL3:2 */
+
+#define	PJCE(x)			(((x)&0x3)<<1)	/* Port J CAN/SPI/SPORT Enable */
+#define	PJCE_SPORT		0x0000	/* Enable DR0SEC/DT0SEC */
+#define	PJCE_CAN		0x0002	/* Enable CAN RX/TX */
+#define	PJCE_SPI		0x0004	/* Enable SPI_SSEL7 */
+
+#define	PFDE			0x0008	/* Port F DMA Request Enable */
+#define	PGDE_UART		0x0000	/* Enable UART0 RX/TX */
+#define	PGDE_DMA		0x0008	/* Enable DMAR1:0 */
+
+#define	PFTE			0x0010	/* Port F Timer Enable */
+#define	PFTE_UART		0x0000	/* Enable UART1 RX/TX */
+#define	PFTE_TIMER		0x0010	/* Enable TMR7:6 */
+
+#define	PFS6E			0x0020	/* Port F SPI SSEL 6 Enable */
+#define	PFS6E_TIMER		0x0000	/* Enable TMR5 */
+#define	PFS6E_SPI		0x0020	/* Enable SPI_SSEL6 */
+
+#define	PFS5E			0x0040	/* Port F SPI SSEL 5 Enable */
+#define	PFS5E_TIMER		0x0000	/* Enable TMR4 */
+#define	PFS5E_SPI		0x0040	/* Enable SPI_SSEL5 */
+
+#define	PFS4E			0x0080	/* Port F SPI SSEL 4 Enable */
+#define	PFS4E_TIMER		0x0000	/* Enable TMR3 */
+#define	PFS4E_SPI		0x0080	/* Enable SPI_SSEL4 */
+
+#define	PFFE			0x0100	/* Port F PPI Frame Sync Enable */
+#define	PFFE_TIMER		0x0000	/* Enable TMR2 */
+#define	PFFE_PPI		0x0100	/* Enable PPI FS3 */
+
+#define	PGSE			0x0200	/* Port G SPORT1 Secondary Enable */
+#define	PGSE_PPI		0x0000	/* Enable PPI D9:8 */
+#define	PGSE_SPORT		0x0200	/* Enable DR1SEC/DT1SEC */
+
+#define	PGRE			0x0400	/* Port G SPORT1 Receive Enable */
+#define	PGRE_PPI		0x0000	/* Enable PPI D12:10 */
+#define	PGRE_SPORT		0x0400	/* Enable DR1PRI/RFS1/RSCLK1 */
+
+#define	PGTE			0x0800	/* Port G SPORT1 Transmit Enable */
+#define	PGTE_PPI		0x0000	/* Enable PPI D15:13 */
+#define	PGTE_SPORT		0x0800	/* Enable DT1PRI/TFS1/TSCLK1 */
+
+/*
+ * HANDSHAKE DMA (HDMA) MASKS
+ */
+/* HDMAx_CTL Masks */
+#define	HMDMAEN			0x0001	/* Enable Handshake DMA 0/1 */
+#define	REP			0x0002	/* HDMA Request Polarity */
+#define	UTE			0x0004	/* Urgency Threshold Enable */
+#define	OIE			0x0010	/* Overflow Interrupt Enable */
+#define	BDIE			0x0020	/* Block Done Interrupt Enable */
+#define	MBDI			0x0040	/* Mask Block Done IRQ If Pending ECNT */
+#define	DRQ			0x0300	/* HDMA Request Type */
+#define	DRQ_NONE		0x0000	/* No Request */
+#define	DRQ_SINGLE		0x0100	/* Channels Request Single */
+#define	DRQ_MULTI		0x0200	/* Channels Request Multi (Default) */
+#define	DRQ_URGENT		0x0300	/* Channels Request Multi Urgent */
+#define	RBC			0x1000	/* Reload BCNT With IBCNT */
+#define	PS			0x2000	/* HDMA Pin Status */
+#define	OI			0x4000	/* Overflow Interrupt Generated */
+#define	BDI			0x8000	/* Block Done Interrupt Generated */
+
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+#endif				/* _DEF_BF534_H */
diff --git a/include/asm-blackfin/arch-bf537/defBF537.h b/include/asm-blackfin/arch-bf537/defBF537.h
new file mode 100644
index 0000000..8d16c37
--- /dev/null
+++ b/include/asm-blackfin/arch-bf537/defBF537.h
@@ -0,0 +1,488 @@
+/*
+ * Copyright (C) 2004-2005 Analog Devices Inc., All Rights Reserved.
+ *
+ ***********************************************************************************
+ *
+ * This include file contains a list of macro "defines" to enable the programmer
+ * to use symbolic names for register-access and bit-manipulation.
+ *
+ *   ----------------------------
+ *   revision 0.1
+ *   date: 2004/03/01 21:23:01;  author: joeb
+ *   Initial revision
+ *
+ *   ----------------------------
+ *   revision 0.2
+ *   date: 2004/05/15 16:30:00;  author: joeb
+ *   comments: removed I2C/IIC references, changed GPIO sections
+ *
+ *   ----------------------------
+ *   revision 0.3
+ *   date: 2004/06/08 12:25:00;  author: joeb
+ *   comments: fixed mis-mapped TIMER registers, changed TWI register names, fixed
+ *             FLAG references in GPIO register names
+ *
+ *   ----------------------------
+ *   revision 0.4
+ *   date: 2004/06/09 2:25:00;  author: joeb
+ *   comments: fixed bit-defines for EMAC section, renamed EMAC count registers,
+ *             combined 2 Timer status registers into one
+ *
+ *   ----------------------------
+ *   revision 0.5
+ *   date: 2004/08/10 10:25:00;  author: joeb
+ *   comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
+ *
+ *   ----------------------------
+ *   revision 0.6
+ *   date: 2004/08/17 16:25:00;  author: joeb
+ *   comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
+ *
+ *   ----------------------------
+ *   revision 0.7
+ *   date: 2004/08/18 13:21:00;  author: joeb
+ *   comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
+ *
+ *   ----------------------------
+ *   revision 0.8
+ *   date: 2004/08/20 10:24:00;  author: joeb
+ *   comments: Renamed External DMA to Handshake MDMA
+ *
+ *   ----------------------------
+ *   revision 0.9
+ *   date: 2004/08/23 13:42:00;  author: joeb
+ *   comments: Renamed Handshake DMA Register Set
+ *
+ *   ----------------------------
+ *   revision 0.10
+ *   date: 2004/09/07 11:21:00;  author: joeb
+ *   comments: Fixed EMAC TX/RX DMA Priority (DMA and SIC Bit Names)
+ *
+ *   ----------------------------
+ *   revision 0.11
+ *   date: 2004/09/28 15:14:00;  author: joeb
+ *   comments: Fixed CAN Mailbox Area
+ *
+ *   ----------------------------
+ *   revision 0.12
+ *   date: 2004/10/27 13:18:00;  author: joeb
+ *   comments: Added IEEE EMAC Register Support
+ *
+ *   ----------------------------
+ *   revision 0.13
+ *   date: 2004/10/28 15:40:00;  author: joeb
+ *   comments: Shortened EMAC Count Register Names
+ *
+ *   ----------------------------
+ *   revision 0.14
+ *   date: 2004/11/09 10:45:00;  author: joeb
+ *   comments: Fixed WDSIZE macros
+ *
+ *   ----------------------------
+ *   revision 0.15
+ *   date: 2004/11/18 07:45:00;  author: joeb
+ *   comments: Fixed TIMER_STATUS register, added EMAC macros
+ *
+ *   ----------------------------
+ *   revision 0.16
+ *   date: 2004/12/13 11:05:00;  author: joeb
+ *   comments: Removed HI/LO macros (now Assembler mnemonics)
+ *				Renamed enable bit for HMDMA from EN to HMDMAEN
+ *
+ *   ----------------------------
+ *   revision 0.17
+ *   date: 2004/12/17 14:25:00;  author: joeb
+ *   comments: Replaced C++ Single-Line Comments w/C-standard Comments
+ *				Changed EMAC EQ1024 TX/RX References to GE1024
+ *
+ *   ----------------------------
+ *   revision 0.18
+ *   date: 2005/01/05 10:50:00;  author: joeb
+ *   comments: Added CAN Macros To Index Mailbox Area and Acceptance Masks
+ *				Added mask values for field deposit protection
+ *
+ *   ----------------------------
+ *   revision 0.19
+ *   date: 2005/01/10 10:30:00;  author: joeb
+ *   comments: Made all Macro argument syntax compliant to MISRA-C 2004 rule 19.10.
+ *
+ *   ----------------------------
+ *   revision 0.20
+ *   date: 2005/01/27 14:25:15;  author: joeb
+ *   comments: Moved MMRs common to BF534 to BF534 header.
+ */
+#ifndef _DEF_BF537_H
+#define _DEF_BF537_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/arch-common/def_LPBlackfin.h>
+
+/* Include all MMR and bit defines common to BF534 */
+#include <asm/arch-bf537/defBF534.h>
+
+/*
+ * Define EMAC Section Unique to BF536/BF537
+ */
+
+/* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
+#define	EMAC_OPMODE		0xFFC03000	/* Operating Mode Register */
+#define EMAC_ADDRLO		0xFFC03004	/* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI		0xFFC03008	/* Address High (16 MSBs) Register */
+#define EMAC_HASHLO		0xFFC0300C	/* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI		0xFFC03010	/* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD		0xFFC03014	/* Station Management Address Register */
+#define EMAC_STADAT		0xFFC03018	/* Station Management Data Register */
+#define EMAC_FLC		0xFFC0301C	/* Flow Control Register */
+#define EMAC_VLAN1		0xFFC03020	/* VLAN1 Tag Register */
+#define EMAC_VLAN2		0xFFC03024	/* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL		0xFFC0302C	/* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0	0xFFC03030	/* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1	0xFFC03034	/* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2	0xFFC03038	/* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3	0xFFC0303C	/* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD		0xFFC03040	/* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF		0xFFC03044	/* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0	0xFFC03048	/* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1	0xFFC0304C	/* Wake-Up Frame Filter 2,3 CRC-16 Register */
+
+#define	EMAC_SYSCTL		0xFFC03060	/* EMAC System Control Register */
+#define EMAC_SYSTAT		0xFFC03064	/* EMAC System Status Register */
+#define EMAC_RX_STAT		0xFFC03068	/* RX Current Frame Status Register */
+#define EMAC_RX_STKY		0xFFC0306C	/* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE		0xFFC03070	/* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT		0xFFC03074	/* TX Current Frame Status Register */
+#define EMAC_TX_STKY		0xFFC03078	/* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE		0xFFC0307C	/* TX Frame Status Interrupt Enables Register */
+
+#define EMAC_MMC_CTL		0xFFC03080	/* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS		0xFFC03084	/* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE		0xFFC03088	/* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS		0xFFC0308C	/* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE		0xFFC03090	/* MMC TX Interrupt Enables Register */
+
+#define EMAC_RXC_OK		0xFFC03100	/* RX Frame Successful Count */
+#define EMAC_RXC_FCS		0xFFC03104	/* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN		0xFFC03108	/* RX Alignment Error Count */
+#define EMAC_RXC_OCTET		0xFFC0310C	/* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF		0xFFC03110	/* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST		0xFFC03114	/* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI		0xFFC03118	/* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD		0xFFC0311C	/* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI		0xFFC03120	/* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO		0xFFC03124	/* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG		0xFFC03128	/* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL		0xFFC0312C	/* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE		0xFFC03130	/* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE		0xFFC03134	/* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM		0xFFC03138	/* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT		0xFFC0313C	/* Overall RX Octet Count */
+#define EMAC_RXC_TYPED		0xFFC03140	/* Type/Length Consistent RX Frame Count */
+#define EMAC_RXC_SHORT		0xFFC03144	/* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64		0xFFC03148	/* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128		0xFFC0314C	/* Good RX Frame Count - Byte Count  64 <= x < 128 */
+#define EMAC_RXC_LT256		0xFFC03150	/* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512		0xFFC03154	/* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024		0xFFC03158	/* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024		0xFFC0315C	/* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define EMAC_TXC_OK		0xFFC03180	/* TX Frame Successful Count */
+#define EMAC_TXC_1COL		0xFFC03184	/* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL		0xFFC03188	/* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET		0xFFC0318C	/* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER		0xFFC03190	/* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL		0xFFC03194	/* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL		0xFFC03198	/* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND		0xFFC0319C	/* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR		0xFFC031A0	/* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST		0xFFC031A4	/* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI		0xFFC031A8	/* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD		0xFFC031AC	/* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR		0xFFC031B0	/* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL		0xFFC031B4	/* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM		0xFFC031B8	/* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT		0xFFC031BC	/* Overall TX Octet Count */
+#define EMAC_TXC_EQ64		0xFFC031C0	/* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128		0xFFC031C4	/* Good TX Frame Count - Byte Count  64 <= x < 128 */
+#define EMAC_TXC_LT256		0xFFC031C8	/* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512		0xFFC031CC	/* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024		0xFFC031D0	/* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024		0xFFC031D4	/* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT		0xFFC031D8	/* Total TX Frames Aborted Count */
+
+/* Listing for IEEE-Supported Count Registers */
+#define FramesReceivedOK		EMAC_RXC_OK	/* RX Frame Successful Count */
+#define FrameCheckSequenceErrors	EMAC_RXC_FCS	/* RX Frame FCS Failure Count */
+#define AlignmentErrors			EMAC_RXC_ALIGN	/* RX Alignment Error Count */
+#define OctetsReceivedOK		EMAC_RXC_OCTET	/* RX Octets Successfully Received Count */
+#define FramesLostDueToIntMACRcvError	EMAC_RXC_DMAOVF	/* Internal MAC Sublayer Error RX Frame Count */
+#define UnicastFramesReceivedOK		EMAC_RXC_UNICST	/* Unicast RX Frame Count */
+#define MulticastFramesReceivedOK	EMAC_RXC_MULTI	/* Multicast RX Frame Count */
+#define BroadcastFramesReceivedOK	EMAC_RXC_BROAD	/* Broadcast RX Frame Count */
+#define InRangeLengthErrors		EMAC_RXC_LNERRI	/* RX Frame In Range Error Count */
+#define OutOfRangeLengthField		EMAC_RXC_LNERRO	/* RX Frame Out Of Range Error Count */
+#define FrameTooLongErrors		EMAC_RXC_LONG	/* RX Frame Too Long Count */
+#define MACControlFramesReceived	EMAC_RXC_MACCTL	/* MAC Control RX Frame Count */
+#define UnsupportedOpcodesReceived	EMAC_RXC_OPCODE	/* Unsupported Op-Code RX Frame Count */
+#define PAUSEMACCtrlFramesReceived	EMAC_RXC_PAUSE	/* MAC Control Pause RX Frame Count */
+#define FramesReceivedAll		EMAC_RXC_ALLFRM	/* Overall RX Frame Count */
+#define OctetsReceivedAll		EMAC_RXC_ALLOCT	/* Overall RX Octet Count */
+#define TypedFramesReceived		EMAC_RXC_TYPED	/* Type/Length Consistent RX Frame Count */
+#define FramesLenLt64Received		EMAC_RXC_SHORT	/* RX Frame Fragment Count - Byte Count x < 64 */
+#define FramesLenEq64Received		EMAC_RXC_EQ64	/* Good RX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Received		EMAC_RXC_LT128	/* Good RX Frame Count - Byte Count  64 <= x < 128 */
+#define FramesLen128_255Received	EMAC_RXC_LT256	/* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Received	EMAC_RXC_LT512	/* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Received	EMAC_RXC_LT1024	/* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxReceived	EMAC_RXC_GE1024	/* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define FramesTransmittedOK		EMAC_TXC_OK	/* TX Frame Successful Count */
+#define SingleCollisionFrames		EMAC_TXC_1COL	/* TX Frames Successful After Single Collision Count */
+#define MultipleCollisionFrames		EMAC_TXC_GT1COL	/* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK		EMAC_TXC_OCTET	/* TX Octets Successfully Received Count */
+#define FramesWithDeferredXmissions	EMAC_TXC_DEFER	/* TX Frame Delayed Due To Busy Count */
+#define LateCollisions			EMAC_TXC_LATECL	/* Late TX Collisions Count */
+#define FramesAbortedDueToXSColls	EMAC_TXC_XS_COL	/* TX Frame Failed Due To Excessive Collisions Count */
+#define FramesLostDueToIntMacXmitError	EMAC_TXC_DMAUND	/* Internal MAC Sublayer Error TX Frame Count */
+#define CarrierSenseErrors		EMAC_TXC_CRSERR	/* Carrier Sense Deasserted During TX Frame Count */
+#define UnicastFramesXmittedOK		EMAC_TXC_UNICST	/* Unicast TX Frame Count */
+#define MulticastFramesXmittedOK	EMAC_TXC_MULTI	/* Multicast TX Frame Count */
+#define BroadcastFramesXmittedOK	EMAC_TXC_BROAD	/* Broadcast TX Frame Count */
+#define FramesWithExcessiveDeferral	EMAC_TXC_XS_DFR	/* TX Frames With Excessive Deferral Count */
+#define MACControlFramesTransmitted	EMAC_TXC_MACCTL	/* MAC Control TX Frame Count */
+#define FramesTransmittedAll		EMAC_TXC_ALLFRM	/* Overall TX Frame Count */
+#define OctetsTransmittedAll		EMAC_TXC_ALLOCT	/* Overall TX Octet Count */
+#define FramesLenEq64Transmitted	EMAC_TXC_EQ64	/* Good TX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Transmitted	EMAC_TXC_LT128	/* Good TX Frame Count - Byte Count  64 <= x < 128 */
+#define FramesLen128_255Transmitted	EMAC_TXC_LT256	/* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Transmitted	EMAC_TXC_LT512	/* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Transmitted	EMAC_TXC_LT1024	/* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxTransmitted	EMAC_TXC_GE1024	/* Good TX Frame Count - Byte Count x >= 1024 */
+#define TxAbortedFrames			EMAC_TXC_ABORT	/* Total TX Frames Aborted Count */
+
+/*
+ * System MMR Register Bits And Macros
+ *
+ * Disclaimer:	All macros are intended to make C and Assembly code more readable.
+ *		Use these macros carefully, as any that do left shifts for field
+ *		depositing will result in the lower order bits being destroyed.  Any
+ *		macro that shifts left to properly position the bit-field should be
+ *		used as part of an OR to initialize a register and NOT as a dynamic
+ *		modifier UNLESS the lower order bits are saved and ORed back in when
+ *		the macro is used.
+ */
+/*
+ * ETHERNET 10/100 CONTROLLER MASKS
+ */
+/* EMAC_OPMODE Masks */
+#define	RE		0x00000001	/* Receiver Enable */
+#define	ASTP		0x00000002	/* Enable Automatic Pad Stripping On RX Frames */
+#define	HU		0x00000010	/* Hash Filter Unicast Address */
+#define	HM		0x00000020	/* Hash Filter Multicast Address */
+#define	PAM		0x00000040	/* Pass-All-Multicast Mode Enable */
+#define	PR		0x00000080	/* Promiscuous Mode Enable */
+#define	IFE		0x00000100	/* Inverse Filtering Enable */
+#define	DBF		0x00000200	/* Disable Broadcast Frame Reception */
+#define	PBF		0x00000400	/* Pass Bad Frames Enable */
+#define	PSF		0x00000800	/* Pass Short Frames Enable */
+#define	RAF		0x00001000	/* Receive-All Mode */
+#define	TE		0x00010000	/* Transmitter Enable */
+#define	DTXPAD		0x00020000	/* Disable Automatic TX Padding */
+#define	DTXCRC		0x00040000	/* Disable Automatic TX CRC Generation */
+#define	DC		0x00080000	/* Deferral Check */
+#define	BOLMT		0x00300000	/* Back-Off Limit */
+#define	BOLMT_10	0x00000000	/* 10-bit range */
+#define	BOLMT_8		0x00100000	/* 8-bit range */
+#define	BOLMT_4		0x00200000	/* 4-bit range */
+#define	BOLMT_1		0x00300000	/* 1-bit range */
+#define	DRTY		0x00400000	/* Disable TX Retry On Collision */
+#define	LCTRE		0x00800000	/* Enable TX Retry On Late Collision */
+#define	RMII		0x01000000	/* RMII/MII* Mode */
+#define	RMII_10		0x02000000	/* Speed Select for RMII Port (10MBit/100MBit*) */
+#define	FDMODE		0x04000000	/* Duplex Mode Enable (Full/Half*) */
+#define	LB		0x08000000	/* Internal Loopback Enable */
+#define	DRO		0x10000000	/* Disable Receive Own Frames (Half-Duplex Mode) */
+
+/* EMAC_STAADD Masks */
+#define	STABUSY		0x00000001	/* Initiate Station Mgt Reg Access / STA Busy Stat */
+#define	STAOP		0x00000002	/* Station Management Operation Code (Write/Read*) */
+#define	STADISPRE	0x00000004	/* Disable Preamble Generation */
+#define	STAIE		0x00000008	/* Station Mgt. Transfer Done Interrupt Enable */
+#define	REGAD		0x000007C0	/* STA Register Address */
+#define	PHYAD		0x0000F800	/* PHY Device Address */
+
+#define	SET_REGAD(x)	(((x)&0x1F)<<  6 )	/* Set STA Register Address */
+#define	SET_PHYAD(x)	(((x)&0x1F)<< 11 )	/* Set PHY Device Address */
+
+/* EMAC_STADAT Mask */
+#define	STADATA		0x0000FFFF	/* Station Management Data */
+
+/* EMAC_FLC Masks */
+#define	FLCBUSY		0x00000001	/* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
+#define	FLCE		0x00000002	/* Flow Control Enable */
+#define	PCF		0x00000004	/* Pass Control Frames */
+#define	BKPRSEN		0x00000008	/* Enable Backpressure */
+#define	FLCPAUSE	0xFFFF0000	/* Pause Time */
+
+#define	SET_FLCPAUSE(x)	(((x)&0xFFFF)<< 16)	/* Set Pause Time */
+
+/* EMAC_WKUP_CTL Masks */
+#define	CAPWKFRM	0x00000001	/* Capture Wake-Up Frames */
+#define	MPKE		0x00000002	/* Magic Packet Enable */
+#define	RWKE		0x00000004	/* Remote Wake-Up Frame Enable */
+#define	GUWKE		0x00000008	/* Global Unicast Wake Enable */
+#define	MPKS		0x00000020	/* Magic Packet Received Status */
+#define	RWKS		0x00000F00	/* Wake-Up Frame Received Status, Filters 3:0 */
+
+/* EMAC_WKUP_FFCMD Masks */
+#define	WF0_E		0x00000001	/* Enable Wake-Up Filter 0 */
+#define	WF0_T		0x00000008	/* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
+#define	WF1_E		0x00000100	/* Enable Wake-Up Filter 1 */
+#define	WF1_T		0x00000800	/* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
+#define	WF2_E		0x00010000	/* Enable Wake-Up Filter 2 */
+#define	WF2_T		0x00080000	/* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
+#define	WF3_E		0x01000000	/* Enable Wake-Up Filter 3 */
+#define	WF3_T		0x08000000	/* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
+
+/* EMAC_WKUP_FFOFF Masks */
+#define	WF0_OFF		0x000000FF	/* Wake-Up Filter 0 Pattern Offset */
+#define	WF1_OFF		0x0000FF00	/* Wake-Up Filter 1 Pattern Offset */
+#define	WF2_OFF		0x00FF0000	/* Wake-Up Filter 2 Pattern Offset */
+#define	WF3_OFF		0xFF000000	/* Wake-Up Filter 3 Pattern Offset */
+
+#define	SET_WF0_OFF(x)	(((x)&0xFF)<<  0 )	/* Set Wake-Up Filter 0 Byte Offset */
+#define	SET_WF1_OFF(x)	(((x)&0xFF)<<  8 )	/* Set Wake-Up Filter 1 Byte Offset */
+#define	SET_WF2_OFF(x)	(((x)&0xFF)<< 16 )	/* Set Wake-Up Filter 2 Byte Offset */
+#define	SET_WF3_OFF(x)	(((x)&0xFF)<< 24 )	/* Set Wake-Up Filter 3 Byte Offset */
+/* Set ALL Offsets */
+#define	SET_WF_OFFS(x0,x1,x2,x3)	(SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+#define	WF0_CRC		0x0000FFFF	/* Wake-Up Filter 0 Pattern CRC */
+#define	WF1_CRC		0xFFFF0000	/* Wake-Up Filter 1 Pattern CRC */
+
+#define	SET_WF0_CRC(x)	(((x)&0xFFFF)<< 0)	/* Set Wake-Up Filter 0 Target CRC */
+#define	SET_WF1_CRC(x)	(((x)&0xFFFF)<< 16)	/* Set Wake-Up Filter 1 Target CRC */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+#define	WF2_CRC		0x0000FFFF	/* Wake-Up Filter 2 Pattern CRC */
+#define	WF3_CRC		0xFFFF0000	/* Wake-Up Filter 3 Pattern CRC */
+
+#define	SET_WF2_CRC(x)	(((x)&0xFFFF)<< 0)	/* Set Wake-Up Filter 2 Target CRC */
+#define	SET_WF3_CRC(x)	(((x)&0xFFFF)<< 16)	/* Set Wake-Up Filter 3 Target CRC */
+
+/* EMAC_SYSCTL Masks */
+#define	PHYIE		0x00000001	/* PHY_INT Interrupt Enable */
+#define	RXDWA		0x00000002	/* Receive Frame DMA Word Alignment (Odd/Even*) */
+#define	RXCKS		0x00000004	/* Enable RX Frame TCP/UDP Checksum Computation */
+#define	MDCDIV		0x00003F00	/* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
+
+#define	SET_MDCDIV(x)	(((x)&0x3F)<< 8)	/* Set MDC Clock Divisor */
+
+/* EMAC_SYSTAT Masks */
+#define	PHYINT		0x00000001	/* PHY_INT Interrupt Status */
+#define	MMCINT		0x00000002	/* MMC Counter Interrupt Status */
+#define	RXFSINT		0x00000004	/* RX Frame-Status Interrupt Status */
+#define	TXFSINT		0x00000008	/* TX Frame-Status Interrupt Status */
+#define	WAKEDET		0x00000010	/* Wake-Up Detected Status */
+#define	RXDMAERR	0x00000020	/* RX DMA Direction Error Status */
+#define	TXDMAERR	0x00000040	/* TX DMA Direction Error Status */
+#define	STMDONE		0x00000080	/* Station Mgt. Transfer Done Interrupt Status */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+#define	RX_FRLEN	0x000007FF	/* Frame Length In Bytes */
+#define	RX_COMP		0x00001000	/* RX Frame Complete */
+#define	RX_OK		0x00002000	/* RX Frame Received With No Errors */
+#define	RX_LONG		0x00004000	/* RX Frame Too Long Error */
+#define	RX_ALIGN	0x00008000	/* RX Frame Alignment Error */
+#define	RX_CRC		0x00010000	/* RX Frame CRC Error */
+#define	RX_LEN		0x00020000	/* RX Frame Length Error */
+#define	RX_FRAG		0x00040000	/* RX Frame Fragment Error */
+#define	RX_ADDR		0x00080000	/* RX Frame Address Filter Failed Error */
+#define	RX_DMAO		0x00100000	/* RX Frame DMA Overrun Error */
+#define	RX_PHY		0x00200000	/* RX Frame PHY Error */
+#define	RX_LATE		0x00400000	/* RX Frame Late Collision Error */
+#define	RX_RANGE	0x00800000	/* RX Frame Length Field Out of Range Error */
+#define	RX_MULTI	0x01000000	/* RX Multicast Frame Indicator */
+#define	RX_BROAD	0x02000000	/* RX Broadcast Frame Indicator */
+#define	RX_CTL		0x04000000	/* RX Control Frame Indicator */
+#define	RX_UCTL		0x08000000	/* Unsupported RX Control Frame Indicator */
+#define	RX_TYPE		0x10000000	/* RX Typed Frame Indicator */
+#define	RX_VLAN1	0x20000000	/* RX VLAN1 Frame Indicator */
+#define	RX_VLAN2	0x40000000	/* RX VLAN2 Frame Indicator */
+#define	RX_ACCEPT	0x80000000	/* RX Frame Accepted Indicator */
+
+/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
+#define	TX_COMP		0x00000001	/* TX Frame Complete */
+#define	TX_OK		0x00000002	/* TX Frame Sent With No Errors */
+#define	TX_ECOLL	0x00000004	/* TX Frame Excessive Collision Error */
+#define	TX_LATE		0x00000008	/* TX Frame Late Collision Error */
+#define	TX_DMAU		0x00000010	/* TX Frame DMA Underrun Error (STAT) */
+#define	TX_MACE		0x00000010	/* Internal MAC Error Detected (STKY and IRQE) */
+#define	TX_EDEFER	0x00000020	/* TX Frame Excessive Deferral Error */
+#define	TX_BROAD	0x00000040	/* TX Broadcast Frame Indicator */
+#define	TX_MULTI	0x00000080	/* TX Multicast Frame Indicator */
+#define	TX_CCNT		0x00000F00	/* TX Frame Collision Count */
+#define	TX_DEFER	0x00001000	/* TX Frame Deferred Indicator */
+#define	TX_CRS		0x00002000	/* TX Frame Carrier Sense Not Asserted Error */
+#define	TX_LOSS		0x00004000	/* TX Frame Carrier Lost During TX Error */
+#define	TX_RETRY	0x00008000	/* TX Frame Successful After Retry */
+#define	TX_FRLEN	0x07FF0000	/* TX Frame Length (Bytes) */
+
+/* EMAC_MMC_CTL Masks */
+#define	RSTC		0x00000001	/* Reset All Counters */
+#define	CROLL		0x00000002	/* Counter Roll-Over Enable */
+#define	CCOR		0x00000004	/* Counter Clear-On-Read Mode Enable */
+#define	MMCE		0x00000008	/* Enable MMC Counter Operation */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define	RX_OK_CNT	0x00000001	/* RX Frames Received With No Errors */
+#define	RX_FCS_CNT	0x00000002	/* RX Frames W/Frame Check Sequence Errors */
+#define	RX_ALIGN_CNT	0x00000004	/* RX Frames With Alignment Errors */
+#define	RX_OCTET_CNT	0x00000008	/* RX Octets Received OK */
+#define	RX_LOST_CNT	0x00000010	/* RX Frames Lost Due To Internal MAC RX Error */
+#define	RX_UNI_CNT	0x00000020	/* Unicast RX Frames Received OK */
+#define	RX_MULTI_CNT	0x00000040	/* Multicast RX Frames Received OK */
+#define	RX_BROAD_CNT	0x00000080	/* Broadcast RX Frames Received OK */
+#define	RX_IRL_CNT	0x00000100	/* RX Frames With In-Range Length Errors */
+#define	RX_ORL_CNT	0x00000200	/* RX Frames With Out-Of-Range Length Errors */
+#define	RX_LONG_CNT	0x00000400	/* RX Frames With Frame Too Long Errors */
+#define	RX_MACCTL_CNT	0x00000800	/* MAC Control RX Frames Received */
+#define	RX_OPCODE_CTL	0x00001000	/* Unsupported Op-Code RX Frames Received */
+#define	RX_PAUSE_CNT	0x00002000	/* PAUSEMAC Control RX Frames Received */
+#define	RX_ALLF_CNT	0x00004000	/* All RX Frames Received */
+#define	RX_ALLO_CNT	0x00008000	/* All RX Octets Received */
+#define	RX_TYPED_CNT	0x00010000	/* Typed RX Frames Received */
+#define	RX_SHORT_CNT	0x00020000	/* RX Frame Fragments (< 64 Bytes) Received */
+#define	RX_EQ64_CNT	0x00040000	/* 64-Byte RX Frames Received */
+#define	RX_LT128_CNT	0x00080000	/* 65-127-Byte RX Frames Received */
+#define	RX_LT256_CNT	0x00100000	/* 128-255-Byte RX Frames Received */
+#define	RX_LT512_CNT	0x00200000	/* 256-511-Byte RX Frames Received */
+#define	RX_LT1024_CNT	0x00400000	/* 512-1023-Byte RX Frames Received */
+#define	RX_GE1024_CNT	0x00800000	/* 1024-Max-Byte RX Frames Received */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
+#define	TX_OK_CNT	0x00000001	/* TX Frames Sent OK */
+#define	TX_SCOLL_CNT	0x00000002	/* TX Frames With Single Collisions */
+#define	TX_MCOLL_CNT	0x00000004	/* TX Frames With Multiple Collisions */
+#define	TX_OCTET_CNT	0x00000008	/* TX Octets Sent OK */
+#define	TX_DEFER_CNT	0x00000010	/* TX Frames With Deferred Transmission */
+#define	TX_LATE_CNT	0x00000020	/* TX Frames With Late Collisions */
+#define	TX_ABORTC_CNT	0x00000040	/* TX Frames Aborted Due To Excess Collisions */
+#define	TX_LOST_CNT	0x00000080	/* TX Frames Lost Due To Internal MAC TX Error */
+#define	TX_CRS_CNT	0x00000100	/* TX Frames With Carrier Sense Errors */
+#define	TX_UNI_CNT	0x00000200	/* Unicast TX Frames Sent */
+#define	TX_MULTI_CNT	0x00000400	/* Multicast TX Frames Sent */
+#define	TX_BROAD_CNT	0x00000800	/* Broadcast TX Frames Sent */
+#define	TX_EXDEF_CTL	0x00001000	/* TX Frames With Excessive Deferral */
+#define	TX_MACCTL_CNT	0x00002000	/* MAC Control TX Frames Sent */
+#define	TX_ALLF_CNT	0x00004000	/* All TX Frames Sent */
+#define	TX_ALLO_CNT	0x00008000	/* All TX Octets Sent */
+#define	TX_EQ64_CNT	0x00010000	/* 64-Byte TX Frames Sent */
+#define	TX_LT128_CNT	0x00020000	/* 65-127-Byte TX Frames Sent */
+#define	TX_LT256_CNT	0x00040000	/* 128-255-Byte TX Frames Sent */
+#define	TX_LT512_CNT	0x00080000	/* 256-511-Byte TX Frames Sent */
+#define	TX_LT1024_CNT	0x00100000	/* 512-1023-Byte TX Frames Sent */
+#define	TX_GE1024_CNT	0x00200000	/* 1024-Max-Byte TX Frames Sent */
+#define	TX_ABORT_CNT	0x00400000	/* TX Frames Aborted */
+
+#endif				/* _DEF_BF537_H */
diff --git a/include/asm-blackfin/arch-bf537/defBF537_extn.h b/include/asm-blackfin/arch-bf537/defBF537_extn.h
new file mode 100644
index 0000000..8090da6
--- /dev/null
+++ b/include/asm-blackfin/arch-bf537/defBF537_extn.h
@@ -0,0 +1,76 @@
+/*
+ * defBF537_extn.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEF_BF537_EXTN_H
+#define _DEF_BF537_EXTN_H
+
+#define OFFSET_( x )		((x) & 0x0000FFFF)	/* define macro for offset */
+/* Delay inserted for PLL transition */
+#define PLL_DELAY		0x1000
+
+#define L1_ISRAM		0xFFA00000
+#define L1_ISRAM_END		0xFFA10000
+#define DATA_BANKA_SRAM		0xFF800000
+#define DATA_BANKA_SRAM_END	0xFF808000
+#define DATA_BANKB_SRAM		0xFF900000
+#define DATA_BANKB_SRAM_END	0xFF908000
+#define SYSMMR_BASE		0xFFC00000
+#define WDSIZE16		0x00000004
+
+/* Event Vector Table Address */
+#define EVT_EMULATION_ADDR	0xffe02000
+#define EVT_RESET_ADDR		0xffe02004
+#define EVT_NMI_ADDR		0xffe02008
+#define EVT_EXCEPTION_ADDR	0xffe0200c
+#define EVT_GLOBAL_INT_ENB_ADDR	0xffe02010
+#define EVT_HARDWARE_ERROR_ADDR	0xffe02014
+#define EVT_TIMER_ADDR		0xffe02018
+#define EVT_IVG7_ADDR		0xffe0201c
+#define EVT_IVG8_ADDR		0xffe02020
+#define EVT_IVG9_ADDR		0xffe02024
+#define EVT_IVG10_ADDR		0xffe02028
+#define EVT_IVG11_ADDR		0xffe0202c
+#define EVT_IVG12_ADDR		0xffe02030
+#define EVT_IVG13_ADDR		0xffe02034
+#define EVT_IVG14_ADDR		0xffe02038
+#define EVT_IVG15_ADDR		0xffe0203c
+#define EVT_OVERRIDE_ADDR	0xffe02100
+
+/* IMASK Bit values */
+#define IVG15_POS		0x00008000
+#define IVG14_POS		0x00004000
+#define IVG13_POS		0x00002000
+#define IVG12_POS		0x00001000
+#define IVG11_POS		0x00000800
+#define IVG10_POS		0x00000400
+#define IVG9_POS		0x00000200
+#define IVG8_POS		0x00000100
+#define IVG7_POS		0x00000080
+#define IVGTMR_POS		0x00000040
+#define IVGHW_POS		0x00000020
+
+#define WDOG_TMR_DISABLE	(0xAD << 4)
+#define ICTL_RST		0x00000000
+#define ICTL_NMI		0x00000002
+#define ICTL_GP			0x00000004
+#define ICTL_DISABLE		0x00000003
+
+/* Watch Dog timer values setup */
+#define WATCHDOG_DISABLE	WDOG_TMR_DISABLE | ICTL_DISABLE
+
+#endif				/* _DEF_BF537_EXTN_H */
diff --git a/include/asm-blackfin/arch-bf537/irq.h b/include/asm-blackfin/arch-bf537/irq.h
new file mode 100644
index 0000000..4cb4c15
--- /dev/null
+++ b/include/asm-blackfin/arch-bf537/irq.h
@@ -0,0 +1,94 @@
+/*
+ * U-boot bf537_irq.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * This file is based on
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
+ * Changed by HuTao Apr18, 2003
+ *
+ * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
+ *
+ * Adapted for BlackFin BF537 by Bas Vermeulen <bas@buyways.nl>
+ * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF537_IRQ_H_
+#define _BF537_IRQ_H_
+
+/*
+ * Interrupt source definitions
+ * Event Source			Core Event Name		Number
+ * 				EMU			0
+ * Reset			RST			1
+ * NMI				NMI			2
+ * Exception			EVX			3
+ * Reserved			--			4
+ * Hardware Error		IVHW			5
+ * Core Timer			IVTMR			6
+ * PLL Wakeup Interrupt		IVG7			7
+ * DMA Error (generic)		IVG7			8
+ * PPI Error Interrupt		IVG7			9
+ * SPORT0 Error Interrupt	IVG7			10
+ * SPORT1 Error Interrupt	IVG7			11
+ * SPI Error Interrupt		IVG7			12
+ * UART Error Interrupt		IVG7			13
+ * RTC Interrupt		IVG8			14
+ * DMA0 Interrupt (PPI)		IVG8			15
+ * DMA1 (SPORT0 RX)		IVG9			16
+ * DMA2 (SPORT0 TX)		IVG9			17
+ * DMA3 (SPORT1 RX)		IVG9			18
+ * DMA4 (SPORT1 TX)		IVG9			19
+ * DMA5 (PPI)			IVG10			20
+ * DMA6 (UART RX)		IVG10			21
+ * DMA7 (UART TX)		IVG10			22
+ * Timer0			IVG11			23
+ * Timer1			IVG11			24
+ * Timer2			IVG11			25
+ * PF Interrupt A		IVG12			26
+ * PF Interrupt B		IVG12			27
+ * DMA8/9 Interrupt		IVG13			28
+ * DMA10/11 Interrupt		IVG13			29
+ * Watchdog Timer		IVG13			30
+ * Software Interrupt 1		IVG14			31
+ * Software Interrupt 2		--
+ * (lowest priority)		IVG15			32
+ */
+
+#define IRQ_EMU			0	/* Emulation */
+#define IRQ_RST			1	/* reset */
+#define IRQ_NMI			2	/* Non Maskable */
+#define IRQ_EVX			3	/* Exception */
+#define IRQ_UNUSED		4	/*  - unused interrupt */
+#define IRQ_HWERR		5	/* Hardware Error */
+#define IRQ_CORETMR		6	/* Core timer */
+
+#define IRQ_UART_RX_BIT		0x0800
+#define IRQ_UART_TX_BIT		0x1000
+#define IRQ_UART_ERROR_BIT	0x40
+
+#endif
diff --git a/include/asm-blackfin/arch-bf561/anomaly.h b/include/asm-blackfin/arch-bf561/anomaly.h
new file mode 100644
index 0000000..467649b
--- /dev/null
+++ b/include/asm-blackfin/arch-bf561/anomaly.h
@@ -0,0 +1,181 @@
+/*
+ * File:	include/asm-blackfin/arch-bf561/anomaly.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:	Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/*
+ * This file shoule be up to date with:
+ *  - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1 or 0.4 silicon - sorry */
+#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4))
+#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4
+#endif
+
+/* Issues that are common to 0.5 and  0.3 silicon */
+#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000074	/* A multi issue instruction with dsp32shiftimm in
+				   slot1 and store of a P register in slot 2 is not
+				   supported */
+#define ANOMALY_05000099	/* UART Line Status Register (UART_LSR) bits are not
+				   updated at the same time. */
+#define ANOMALY_05000120	/* Testset instructions restricted to 32-bit aligned
+				   memory locations */
+#define ANOMALY_05000122	/* Rx.H cannot be used to access 16-bit System MMR
+				   registers */
+#define ANOMALY_05000127	/* Signbits instruction not functional under certain
+				   conditions */
+#define ANOMALY_05000149	/* IMDMA S1/D1 channel may stall */
+#define ANOMALY_05000166	/* PPI Data Lengths Between 8 and 16 do not zero out
+				   upper bits */
+#define ANOMALY_05000167	/* Turning Serial Ports on With External Frame Syncs */
+#define ANOMALY_05000180	/* PPI_DELAY not functional in PPI modes with 0 frame
+				   syncs */
+#define ANOMALY_05000182	/* IMDMA does not operate to full speed for 600MHz
+				   and higher devices */
+#define ANOMALY_05000187	/* IMDMA Corrupted Data after a Halt */
+#define ANOMALY_05000190	/* PPI not functional at core voltage < 1Volt */
+#define ANOMALY_05000208	/* VSTAT status bit in PLL_STAT register is not
+				   functional */
+#define ANOMALY_05000245	/* Spurious Hardware Error from an access in the
+				   shadow of a conditional branch */
+#define ANOMALY_05000257	/* Interrupt/Exception during short hardware loop
+				   may cause bad instruction fetches */
+#define ANOMALY_05000265	/* Sensitivity to noise with slow input edge rates on
+				   external SPORT TX and RX clocks */
+#define ANOMALY_05000267	/* IMDMA may corrupt data under certain conditions */
+#define ANOMALY_05000269	/* High I/O activity causes output voltage of internal
+				   voltage regulator (VDDint) to increase */
+#define ANOMALY_05000270	/* High I/O activity causes output voltage of internal
+				   voltage regulator (VDDint) to decrease */
+#define ANOMALY_05000272	/* Certain data cache write through modes fail for
+				   VDDint <=0.9V */
+#define ANOMALY_05000274	/* Data cache write back to external synchronous memory
+				   may be lost */
+#define ANOMALY_05000275	/* PPI Timing and sampling informaton updates */
+#endif				/*  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */
+
+#if  (defined(CONFIG_BF_REV_0_5))
+#define ANOMALY_05000254	/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
+				   mode with external clock */
+#define ANOMALY_05000266	/* IMDMA destination IRQ status must be read prior to
+				   using IMDMA */
+#endif
+
+#if  (defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000156	/* Timers in PWM-Out Mode with PPI GP Receive (Input)
+				   Mode with 0 Frame Syncs */
+#define ANOMALY_05000168	/* SDRAM auto-refresh and subsequent Power Ups */
+#define ANOMALY_05000169	/* DATA CPLB page miss can result in lost write-through
+				   cache data writes */
+#define ANOMALY_05000171	/* Boot-ROM code modifies SICA_IWRx wakeup registers */
+#define ANOMALY_05000174	/* Cache Fill Buffer Data lost */
+#define ANOMALY_05000175	/* Overlapping Sequencer and Memory Stalls */
+#define ANOMALY_05000176	/* Multiplication of (-1) by (-1) followed by an
+				   accumulator saturation */
+#define ANOMALY_05000179	/* PPI_COUNT cannot be programmed to 0 in General
+				   Purpose TX or RX modes */
+#define ANOMALY_05000181	/* Disabling the PPI resets the PPI configuration
+				   registers */
+#define ANOMALY_05000184	/* Timer Pin limitations for PPI TX Modes with
+				   External Frame Syncs */
+#define ANOMALY_05000185	/* PPI TX Mode with 2 External Frame Syncs */
+#define ANOMALY_05000186	/* PPI packing with Data Length greater than 8 bits
+				   (not a meaningful mode) */
+#define ANOMALY_05000188	/* IMDMA Restrictions on Descriptor and Buffer
+				   Placement in Memory */
+#define ANOMALY_05000189	/* False Protection Exception */
+#define ANOMALY_05000193	/* False Flag Pin Interrupts on Edge Sensitive Inputs
+				   when polarity setting is changed */
+#define ANOMALY_05000194	/* Restarting SPORT in specific modes may cause data
+				   corruption */
+#define ANOMALY_05000198	/* Failing MMR accesses when stalled by preceding
+				   memory read */
+#define ANOMALY_05000199	/* DMA current address shows wrong value during carry
+				   fix */
+#define ANOMALY_05000200	/* SPORT TFS and DT are incorrectly driven during
+				   inactive channels in certain conditions */
+#define ANOMALY_05000202	/* Possible infinite stall with specific dual-DAG
+				   situation */
+#define ANOMALY_05000204	/* Incorrect data read with write-through cache and
+				   allocate cache lines on reads only mode */
+#define ANOMALY_05000205	/* Specific sequence that can cause DMA error or DMA
+				   stopping */
+#define ANOMALY_05000207	/* Recovery from "brown-out" condition */
+#define ANOMALY_05000209	/* Speed-Path in computational unit affects certain
+				   instructions */
+#define ANOMALY_05000215	/* UART TX Interrupt masked erroneously */
+#define ANOMALY_05000219	/* NMI event at boot time results in unpredictable
+				   state */
+#define ANOMALY_05000220	/* Data Corruption with Cached External Memory and
+				   Non-Cached On-Chip L2 Memory */
+#define ANOMALY_05000225	/* Incorrect pulse-width of UART start-bit */
+#define ANOMALY_05000227	/* Scratchpad memory bank reads may return incorrect
+				   data */
+#define ANOMALY_05000230	/* UART Receiver is less robust against Baudrate
+				   Differences in certain Conditions */
+#define ANOMALY_05000231	/* UART STB bit incorrectly affects receiver setting */
+#define ANOMALY_05000232	/* SPORT data transmit lines are incorrectly driven in
+				   multichannel mode */
+#define ANOMALY_05000242	/* DF bit in PLL_CTL register does not respond to
+				   hardware reset */
+#define ANOMALY_05000244	/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
+				   Control causes failures */
+#define ANOMALY_05000248	/* TESTSET operation forces stall on the other core */
+#define ANOMALY_05000250	/* Incorrect Bit-Shift of Data Word in Multichannel
+				   (TDM) mode in certain conditions */
+#define ANOMALY_05000251	/* Exception not generated for MMR accesses in
+				   reserved region */
+#define ANOMALY_05000253	/* Maximum external clock speed for Timers */
+#define ANOMALY_05000258	/* Instruction Cache is corrupted when bits 9 and 12
+				   of the ICPLB Data registers differ */
+#define ANOMALY_05000260	/* ICPLB_STATUS MMR register may be corrupted */
+#define ANOMALY_05000261	/* DCPLB_FAULT_ADDR MMR register may be corrupted */
+#define ANOMALY_05000262	/* Stores to data cache may be lost */
+#define ANOMALY_05000263	/* Hardware loop corrupted when taking an ICPLB
+				   exception */
+#define ANOMALY_05000264	/* CSYNC/SSYNC/IDLE causes infinite stall in second
+				   to last instruction in hardware loop */
+#define ANOMALY_05000276	/* Timing requirements change for External Frame
+				   Sync PPI Modes with non-zero PPI_DELAY */
+#define ANOMALY_05000278	/* Disabling Peripherals with DMA running may cause
+				   DMA system instability */
+#define ANOMALY_05000281	/* False Hardware Error Exception when ISR context is
+				   not restored */
+#define ANOMALY_05000283	/* An MMR write is stalled indefinitely when killed
+				   in a particular stage */
+#define ANOMALY_05000287	/* A read will receive incorrect data under certain
+				   conditions */
+#define ANOMALY_05000288	/* SPORTs may receive bad data if FIFOs fill up */
+#endif
+
+#endif				/* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/arch-bf561/bf561_serial.h b/include/asm-blackfin/arch-bf561/bf561_serial.h
new file mode 100644
index 0000000..0810228
--- /dev/null
+++ b/include/asm-blackfin/arch-bf561/bf561_serial.h
@@ -0,0 +1,78 @@
+/*
+ * U-boot bf561_serial.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF561_SERIAL_H_
+#define _BF561_SERIAL_H_
+
+#define BYTE_REF(addr)		(*((volatile char*)addr))
+#define HALFWORD_REF(addr)	(*((volatile short*)addr))
+#define WORD_REF(addr)		(*((volatile long*)addr))
+
+#define UART_THR_LO		HALFWORD_REF(UART_THR)
+#define UART_RBR_LO		HALFWORD_REF(UART_RBR)
+#define UART_DLL_LO		HALFWORD_REF(UART_DLL)
+#define UART_IER_LO		HALFWORD_REF(UART_IER)
+#define UART_IER_ERBFI		0x01
+#define UART_IER_ETBEI		0x02
+#define UART_IER_ELSI		0x04
+#define UART_IER_EDDSI		0x08
+
+#define UART_DLH_LO		HALFWORD_REF(UART_DLH)
+#define UART_IIR_LO		HALFWORD_REF(UART_IIR)
+#define UART_IIR_NOINT		0x01
+#define UART_IIR_STATUS		0x06
+#define UART_IIR_LSR		0x06
+#define UART_IIR_RBR		0x04
+#define UART_IIR_THR		0x02
+#define UART_IIR_MSR		0x00
+
+#define UART_LCR_LO		HALFWORD_REF(UART_LCR)
+#define UART_LCR_WLS5		0
+#define UART_LCR_WLS6		0x01
+#define UART_LCR_WLS7		0x02
+#define UART_LCR_WLS8		0x03
+#define UART_LCR_STB		0x04
+#define UART_LCR_PEN		0x08
+#define UART_LCR_EPS		0x10
+#define UART_LCR_SP		0x20
+#define UART_LCR_SB		0x40
+#define UART_LCR_DLAB		0x80
+
+#define UART_MCR_LO		HALFWORD_REF(UART_MCR)
+
+#define UART_LSR_LO		HALFWORD_REF(UART_LSR)
+#define UART_LSR_DR		0x01
+#define UART_LSR_OE		0x02
+#define UART_LSR_PE		0x04
+#define UART_LSR_FE		0x08
+#define UART_LSR_BI		0x10
+#define UART_LSR_THRE		0x20
+#define UART_LSR_TEMT		0x40
+
+#define UART_MSR_LO		HALFWORD_REF(UART_MSR)
+#define UART_SCR_LO		HALFWORD_REF(UART_SCR)
+#define UART_GCTL_LO		HALFWORD_REF(UART_GCTL)
+#define UART_GCTL_UCEN		0x01
+
+#endif
diff --git a/include/asm-blackfin/arch-bf561/cdefBF561.h b/include/asm-blackfin/arch-bf561/cdefBF561.h
new file mode 100644
index 0000000..f217ba7
--- /dev/null
+++ b/include/asm-blackfin/arch-bf561/cdefBF561.h
@@ -0,0 +1,998 @@
+/*
+ * cdefBF561.h
+ *
+ * (c) Copyright 2001-2004 Analog Devices, Inc.  All rights reserved.
+ *
+ */
+
+/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
+
+#ifndef _CDEF_BF561_H
+#define _CDEF_BF561_H
+
+/*
+ * #if !defined(__ADSPBF561__)
+ * #warning cdefBF561.h should only be included for BF561 chip.
+ * #endif
+ */
+
+/* include all Core registers and bit definitions */
+#include <asm/arch-bf561/defBF561.h>
+#include <asm/arch-common/cdef_LPBlackfin.h>
+
+/*
+ * System MMR Register Map
+ */
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define pPLL_CTL		(volatile unsigned short *)PLL_CTL
+#define pPLL_DIV		(volatile unsigned short *)PLL_DIV
+#define pVR_CTL			(volatile unsigned short *)VR_CTL
+#define pPLL_STAT		(volatile unsigned short *)PLL_STAT
+#define pPLL_LOCKCNT		(volatile unsigned short *)PLL_LOCKCNT
+
+/*
+ * System Reset and Interrupt Controller registers for
+ * core A (0xFFC0 0100-0xFFC0 01FF)
+ */
+#define pSICA_SWRST		(volatile unsigned short *)SICA_SWRST
+#define pSICA_SYSCR		(volatile unsigned short *)SICA_SYSCR
+#define pSICA_RVECT		(volatile unsigned short *)SICA_RVECT
+#define pSICA_IMASK		(volatile unsigned long *)SICA_IMASK
+#define pSICA_IMASK0		(volatile unsigned long *)SICA_IMASK0
+#define pSICA_IMASK1		(volatile unsigned long *)SICA_IMASK1
+#define pSICA_IAR0		(volatile unsigned long *)SICA_IAR0
+#define pSICA_IAR1		(volatile unsigned long *)SICA_IAR1
+#define pSICA_IAR2		(volatile unsigned long *)SICA_IAR2
+#define pSICA_IAR3		(volatile unsigned long *)SICA_IAR3
+#define pSICA_IAR4		(volatile unsigned long *)SICA_IAR4
+#define pSICA_IAR5		(volatile unsigned long *)SICA_IAR5
+#define pSICA_IAR6		(volatile unsigned long *)SICA_IAR6
+#define pSICA_IAR7		(volatile unsigned long *)SICA_IAR7
+#define pSICA_ISR0		(volatile unsigned long *)SICA_ISR0
+#define pSICA_ISR1		(volatile unsigned long *)SICA_ISR1
+#define pSICA_IWR0		(volatile unsigned long *)SICA_IWR0
+#define pSICA_IWR1		(volatile unsigned long *)SICA_IWR1
+
+/*
+ * System Reset and Interrupt Controller registers for
+ * Core B (0xFFC0 1100-0xFFC0 11FF)
+ */
+#define pSICB_SWRST		(volatile unsigned short *)SICB_SWRST
+#define pSICB_SYSCR		(volatile unsigned short *)SICB_SYSCR
+#define pSICB_RVECT		(volatile unsigned short *)SICB_RVECT
+#define pSICB_IMASK0		(volatile unsigned long *)SICB_IMASK0
+#define pSICB_IMASK1		(volatile unsigned long *)SICB_IMASK1
+#define pSICB_IAR0		(volatile unsigned long *)SICB_IAR0
+#define pSICB_IAR1		(volatile unsigned long *)SICB_IAR1
+#define pSICB_IAR2		(volatile unsigned long *)SICB_IAR2
+#define pSICB_IAR3		(volatile unsigned long *)SICB_IAR3
+#define pSICB_IAR4		(volatile unsigned long *)SICB_IAR4
+#define pSICB_IAR5		(volatile unsigned long *)SICB_IAR5
+#define pSICB_IAR6		(volatile unsigned long *)SICB_IAR6
+#define pSICB_IAR7		(volatile unsigned long *)SICB_IAR7
+#define pSICB_ISR0		(volatile unsigned long *)SICB_ISR0
+#define pSICB_ISR1		(volatile unsigned long *)SICB_ISR1
+#define pSICB_IWR0		(volatile unsigned long *)SICB_IWR0
+#define pSICB_IWR1		(volatile unsigned long *)SICB_IWR1
+
+/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
+#define pWDOGA_CTL		(volatile unsigned short *)WDOGA_CTL
+#define pWDOGA_CNT		(volatile unsigned long *)WDOGA_CNT
+#define pWDOGA_STAT		(volatile unsigned long *)WDOGA_STAT
+
+/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
+#define pWDOGB_CTL		(volatile unsigned short *)WDOGB_CTL
+#define pWDOGB_CNT		(volatile unsigned long *)WDOGB_CNT
+#define pWDOGB_STAT		(volatile unsigned long *)WDOGB_STAT
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define pUART_THR		(volatile unsigned short *)UART_THR
+#define pUART_RBR		(volatile unsigned short *)UART_RBR
+#define pUART_DLL		(volatile unsigned short *)UART_DLL
+#define pUART_IER		(volatile unsigned short *)UART_IER
+#define pUART_DLH		(volatile unsigned short *)UART_DLH
+#define pUART_IIR		(volatile unsigned short *)UART_IIR
+#define pUART_LCR		(volatile unsigned short *)UART_LCR
+#define pUART_MCR		(volatile unsigned short *)UART_MCR
+#define pUART_LSR		(volatile unsigned short *)UART_LSR
+#define pUART_MSR		(volatile unsigned short *)UART_MSR
+#define pUART_SCR		(volatile unsigned short *)UART_SCR
+#define pUART_GCTL		(volatile unsigned short *)UART_GCTL
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define pSPI_CTL		(volatile unsigned short *)SPI_CTL
+#define pSPI_FLG		(volatile unsigned short *)SPI_FLG
+#define pSPI_STAT		(volatile unsigned short *)SPI_STAT
+#define pSPI_TDBR		(volatile unsigned short *)SPI_TDBR
+#define pSPI_RDBR		(volatile unsigned short *)SPI_RDBR
+#define pSPI_BAUD		(volatile unsigned short *)SPI_BAUD
+#define pSPI_SHADOW		(volatile unsigned short *)SPI_SHADOW
+
+/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
+#define pTIMER0_CONFIG		(volatile unsigned short *)TIMER0_CONFIG
+#define pTIMER0_COUNTER		(volatile unsigned long *)TIMER0_COUNTER
+#define pTIMER0_PERIOD		(volatile unsigned long *)TIMER0_PERIOD
+#define pTIMER0_WIDTH		(volatile unsigned long *)TIMER0_WIDTH
+#define pTIMER1_CONFIG		(volatile unsigned short *)TIMER1_CONFIG
+#define pTIMER1_COUNTER		(volatile unsigned long *)TIMER1_COUNTER
+#define pTIMER1_PERIOD		(volatile unsigned long *)TIMER1_PERIOD
+#define pTIMER1_WIDTH		(volatile unsigned long *)TIMER1_WIDTH
+#define pTIMER2_CONFIG		(volatile unsigned short *)TIMER2_CONFIG
+#define pTIMER2_COUNTER		(volatile unsigned long *)TIMER2_COUNTER
+#define pTIMER2_PERIOD		(volatile unsigned long *)TIMER2_PERIOD
+#define pTIMER2_WIDTH		(volatile unsigned long *)TIMER2_WIDTH
+#define pTIMER3_CONFIG		(volatile unsigned short *)TIMER3_CONFIG
+#define pTIMER3_COUNTER		(volatile unsigned long *)TIMER3_COUNTER
+#define pTIMER3_PERIOD		(volatile unsigned long *)TIMER3_PERIOD
+#define pTIMER3_WIDTH		(volatile unsigned long *)TIMER3_WIDTH
+#define pTIMER4_CONFIG		(volatile unsigned short *)TIMER4_CONFIG
+#define pTIMER4_COUNTER		(volatile unsigned long *)TIMER4_COUNTER
+#define pTIMER4_PERIOD		(volatile unsigned long *)TIMER4_PERIOD
+#define pTIMER4_WIDTH		(volatile unsigned long *)TIMER4_WIDTH
+#define pTIMER5_CONFIG		(volatile unsigned short *)TIMER5_CONFIG
+#define pTIMER5_COUNTER		(volatile unsigned long *)TIMER5_COUNTER
+#define pTIMER5_PERIOD		(volatile unsigned long *)TIMER5_PERIOD
+#define pTIMER5_WIDTH		(volatile unsigned long *)TIMER5_WIDTH
+#define pTIMER6_CONFIG		(volatile unsigned short *)TIMER6_CONFIG
+#define pTIMER6_COUNTER		(volatile unsigned long *)TIMER6_COUNTER
+#define pTIMER6_PERIOD		(volatile unsigned long *)TIMER6_PERIOD
+#define pTIMER6_WIDTH		(volatile unsigned long *)TIMER6_WIDTH
+#define pTIMER7_CONFIG		(volatile unsigned short *)TIMER7_CONFIG
+#define pTIMER7_COUNTER		(volatile unsigned long *)TIMER7_COUNTER
+#define pTIMER7_PERIOD		(volatile unsigned long *)TIMER7_PERIOD
+#define pTIMER7_WIDTH		(volatile unsigned long *)TIMER7_WIDTH
+
+/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
+#define pTMRS8_ENABLE		(volatile unsigned short *)TMRS8_ENABLE
+#define pTMRS8_DISABLE		(volatile unsigned short *)TMRS8_DISABLE
+#define pTMRS8_STATUS		(volatile unsigned long *)TMRS8_STATUS
+#define pTIMER8_CONFIG		(volatile unsigned short *)TIMER8_CONFIG
+#define pTIMER8_COUNTER		(volatile unsigned long *)TIMER8_COUNTER
+#define pTIMER8_PERIOD		(volatile unsigned long *)TIMER8_PERIOD
+#define pTIMER8_WIDTH		(volatile unsigned long *)TIMER8_WIDTH
+#define pTIMER9_CONFIG		(volatile unsigned short *)TIMER9_CONFIG
+#define pTIMER9_COUNTER		(volatile unsigned long *)TIMER9_COUNTER
+#define pTIMER9_PERIOD		(volatile unsigned long *)TIMER9_PERIOD
+#define pTIMER9_WIDTH		(volatile unsigned long *)TIMER9_WIDTH
+#define pTIMER10_CONFIG		(volatile unsigned short *)TIMER10_CONFIG
+#define pTIMER10_COUNTER	(volatile unsigned long *)TIMER10_COUNTER
+#define pTIMER10_PERIOD		(volatile unsigned long *)TIMER10_PERIOD
+#define pTIMER10_WIDTH		(volatile unsigned long *)TIMER10_WIDTH
+#define pTIMER11_CONFIG		(volatile unsigned short *)TIMER11_CONFIG
+#define pTIMER11_COUNTER	(volatile unsigned long *)TIMER11_COUNTER
+#define pTIMER11_PERIOD		(volatile unsigned long *)TIMER11_PERIOD
+#define pTIMER11_WIDTH		(volatile unsigned long *)TIMER11_WIDTH
+#define pTMRS4_ENABLE		(volatile unsigned short *)TMRS4_ENABLE
+#define pTMRS4_DISABLE		(volatile unsigned short *)TMRS4_DISABLE
+#define pTMRS4_STATUS		(volatile unsigned long *)TMRS4_STATUS
+
+/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
+#define pFIO0_FLAG_D		(volatile unsigned short *)FIO0_FLAG_D
+#define pFIO0_FLAG_C		(volatile unsigned short *)FIO0_FLAG_C
+#define pFIO0_FLAG_S		(volatile unsigned short *)FIO0_FLAG_S
+#define pFIO0_FLAG_T		(volatile unsigned short *)FIO0_FLAG_T
+#define pFIO0_MASKA_D		(volatile unsigned short *)FIO0_MASKA_D
+#define pFIO0_MASKA_C		(volatile unsigned short *)FIO0_MASKA_C
+#define pFIO0_MASKA_S		(volatile unsigned short *)FIO0_MASKA_S
+#define pFIO0_MASKA_T		(volatile unsigned short *)FIO0_MASKA_T
+#define pFIO0_MASKB_D		(volatile unsigned short *)FIO0_MASKB_D
+#define pFIO0_MASKB_C		(volatile unsigned short *)FIO0_MASKB_C
+#define pFIO0_MASKB_S		(volatile unsigned short *)FIO0_MASKB_S
+#define pFIO0_MASKB_T		(volatile unsigned short *)FIO0_MASKB_T
+#define pFIO0_DIR		(volatile unsigned short *)FIO0_DIR
+#define pFIO0_POLAR		(volatile unsigned short *)FIO0_POLAR
+#define pFIO0_EDGE		(volatile unsigned short *)FIO0_EDGE
+#define pFIO0_BOTH		(volatile unsigned short *)FIO0_BOTH
+#define pFIO0_INEN		(volatile unsigned short *)FIO0_INEN
+
+/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
+#define pFIO1_FLAG_D		(volatile unsigned short *)FIO1_FLAG_D
+#define pFIO1_FLAG_C		(volatile unsigned short *)FIO1_FLAG_C
+#define pFIO1_FLAG_S		(volatile unsigned short *)FIO1_FLAG_S
+#define pFIO1_FLAG_T		(volatile unsigned short *)FIO1_FLAG_T
+#define pFIO1_MASKA_D		(volatile unsigned short *)FIO1_MASKA_D
+#define pFIO1_MASKA_C		(volatile unsigned short *)FIO1_MASKA_C
+#define pFIO1_MASKA_S		(volatile unsigned short *)FIO1_MASKA_S
+#define pFIO1_MASKA_T		(volatile unsigned short *)FIO1_MASKA_T
+#define pFIO1_MASKB_D		(volatile unsigned short *)FIO1_MASKB_D
+#define pFIO1_MASKB_C		(volatile unsigned short *)FIO1_MASKB_C
+#define pFIO1_MASKB_S		(volatile unsigned short *)FIO1_MASKB_S
+#define pFIO1_MASKB_T		(volatile unsigned short *)FIO1_MASKB_T
+#define pFIO1_DIR		(volatile unsigned short *)FIO1_DIR
+#define pFIO1_POLAR		(volatile unsigned short *)FIO1_POLAR
+#define pFIO1_EDGE		(volatile unsigned short *)FIO1_EDGE
+#define pFIO1_BOTH		(volatile unsigned short *)FIO1_BOTH
+#define pFIO1_INEN		(volatile unsigned short *)FIO1_INEN
+
+/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
+#define pFIO2_FLAG_D		(volatile unsigned short *)FIO2_FLAG_D
+#define pFIO2_FLAG_C		(volatile unsigned short *)FIO2_FLAG_C
+#define pFIO2_FLAG_S		(volatile unsigned short *)FIO2_FLAG_S
+#define pFIO2_FLAG_T		(volatile unsigned short *)FIO2_FLAG_T
+#define pFIO2_MASKA_D		(volatile unsigned short *)FIO2_MASKA_D
+#define pFIO2_MASKA_C		(volatile unsigned short *)FIO2_MASKA_C
+#define pFIO2_MASKA_S		(volatile unsigned short *)FIO2_MASKA_S
+#define pFIO2_MASKA_T		(volatile unsigned short *)FIO2_MASKA_T
+#define pFIO2_MASKB_D		(volatile unsigned short *)FIO2_MASKB_D
+#define pFIO2_MASKB_C		(volatile unsigned short *)FIO2_MASKB_C
+#define pFIO2_MASKB_S		(volatile unsigned short *)FIO2_MASKB_S
+#define pFIO2_MASKB_T		(volatile unsigned short *)FIO2_MASKB_T
+#define pFIO2_DIR		(volatile unsigned short *)FIO2_DIR
+#define pFIO2_POLAR		(volatile unsigned short *)FIO2_POLAR
+#define pFIO2_EDGE		(volatile unsigned short *)FIO2_EDGE
+#define pFIO2_BOTH		(volatile unsigned short *)FIO2_BOTH
+#define pFIO2_INEN		(volatile unsigned short *)FIO2_INEN
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define pSPORT0_TCR1		(volatile unsigned short *)SPORT0_TCR1
+#define pSPORT0_TCR2		(volatile unsigned short *)SPORT0_TCR2
+#define pSPORT0_TCLKDIV		(volatile unsigned short *)SPORT0_TCLKDIV
+#define pSPORT0_TFSDIV		(volatile unsigned short *)SPORT0_TFSDIV
+#define pSPORT0_TX		(volatile unsigned long *)SPORT0_TX
+#define pSPORT0_RX		(volatile unsigned long *)SPORT0_RX
+#define pSPORT0_TX32		((volatile long *)SPORT0_TX)
+#define pSPORT0_RX32		((volatile long *)SPORT0_RX)
+#define pSPORT0_TX16		((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16		((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1		(volatile unsigned short *)SPORT0_RCR1
+#define pSPORT0_RCR2		(volatile unsigned short *)SPORT0_RCR2
+#define pSPORT0_RCLKDIV		(volatile unsigned short *)SPORT0_RCLKDIV
+#define pSPORT0_RFSDIV		(volatile unsigned short *)SPORT0_RFSDIV
+#define pSPORT0_STAT		(volatile unsigned short *)SPORT0_STAT
+#define pSPORT0_CHNL		(volatile unsigned short *)SPORT0_CHNL
+#define pSPORT0_MCMC1		(volatile unsigned short *)SPORT0_MCMC1
+#define pSPORT0_MCMC2		(volatile unsigned short *)SPORT0_MCMC2
+#define pSPORT0_MTCS0		(volatile unsigned long *)SPORT0_MTCS0
+#define pSPORT0_MTCS1		(volatile unsigned long *)SPORT0_MTCS1
+#define pSPORT0_MTCS2		(volatile unsigned long *)SPORT0_MTCS2
+#define pSPORT0_MTCS3		(volatile unsigned long *)SPORT0_MTCS3
+#define pSPORT0_MRCS0		(volatile unsigned long *)SPORT0_MRCS0
+#define pSPORT0_MRCS1		(volatile unsigned long *)SPORT0_MRCS1
+#define pSPORT0_MRCS2		(volatile unsigned long *)SPORT0_MRCS2
+#define pSPORT0_MRCS3		(volatile unsigned long *)SPORT0_MRCS3
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define pSPORT1_TCR1		(volatile unsigned short *)SPORT1_TCR1
+#define pSPORT1_TCR2		(volatile unsigned short *)SPORT1_TCR2
+#define pSPORT1_TCLKDIV		(volatile unsigned short *)SPORT1_TCLKDIV
+#define pSPORT1_TFSDIV		(volatile unsigned short *)SPORT1_TFSDIV
+#define pSPORT1_TX		(volatile unsigned long *)SPORT1_TX
+#define pSPORT1_RX		(volatile unsigned long *)SPORT1_RX
+#define pSPORT1_TX32		((volatile long *)SPORT1_TX)
+#define pSPORT1_RX32		((volatile long *)SPORT1_RX)
+#define pSPORT1_TX16		((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16		((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1		(volatile unsigned short *)SPORT1_RCR1
+#define pSPORT1_RCR2		(volatile unsigned short *)SPORT1_RCR2
+#define pSPORT1_RCLKDIV		(volatile unsigned short *)SPORT1_RCLKDIV
+#define pSPORT1_RFSDIV		(volatile unsigned short *)SPORT1_RFSDIV
+#define pSPORT1_STAT		(volatile unsigned short *)SPORT1_STAT
+#define pSPORT1_CHNL		(volatile unsigned short *)SPORT1_CHNL
+#define pSPORT1_MCMC1		(volatile unsigned short *)SPORT1_MCMC1
+#define pSPORT1_MCMC2		(volatile unsigned short *)SPORT1_MCMC2
+#define pSPORT1_MTCS0		(volatile unsigned long *)SPORT1_MTCS0
+#define pSPORT1_MTCS1		(volatile unsigned long *)SPORT1_MTCS1
+#define pSPORT1_MTCS2		(volatile unsigned long *)SPORT1_MTCS2
+#define pSPORT1_MTCS3		(volatile unsigned long *)SPORT1_MTCS3
+#define pSPORT1_MRCS0		(volatile unsigned long *)SPORT1_MRCS0
+#define pSPORT1_MRCS1		(volatile unsigned long *)SPORT1_MRCS1
+#define pSPORT1_MRCS2		(volatile unsigned long *)SPORT1_MRCS2
+#define pSPORT1_MRCS3		(volatile unsigned long *)SPORT1_MRCS3
+
+/* Asynchronous Memory Controller - External Bus Interface Unit */
+#define pEBIU_AMGCTL		(volatile unsigned short *)EBIU_AMGCTL
+#define pEBIU_AMBCTL0		(volatile unsigned long *)EBIU_AMBCTL0
+#define pEBIU_AMBCTL1		(volatile unsigned long *)EBIU_AMBCTL1
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define pEBIU_SDGCTL		(volatile unsigned long *)EBIU_SDGCTL
+#define pEBIU_SDBCTL		(volatile unsigned long *)EBIU_SDBCTL
+#define pEBIU_SDRRC		(volatile unsigned short *)EBIU_SDRRC
+#define pEBIU_SDSTAT		(volatile unsigned short *)EBIU_SDSTAT
+
+/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/
+#define pPPI0_CONTROL		(volatile unsigned short *)PPI0_CONTROL
+#define pPPI0_STATUS		(volatile unsigned short *)PPI0_STATUS
+#define pPPI0_COUNT		(volatile unsigned short *)PPI0_COUNT
+#define pPPI0_DELAY		(volatile unsigned short *)PPI0_DELAY
+#define pPPI0_FRAME		(volatile unsigned short *)PPI0_FRAME
+
+/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF)*/
+#define pPPI1_CONTROL		(volatile unsigned short *)PPI1_CONTROL
+#define pPPI1_STATUS		(volatile unsigned short *)PPI1_STATUS
+#define pPPI1_COUNT		(volatile unsigned short *)PPI1_COUNT
+#define pPPI1_DELAY		(volatile unsigned short *)PPI1_DELAY
+#define pPPI1_FRAME		(volatile unsigned short *)PPI1_FRAME
+
+/*DMA Traffic controls*/
+#define pDMA_TCPER		((volatile unsigned short *)DMA_TCPER)
+#define pDMA_TCCNT		((volatile unsigned short *)DMA_TCCNT)
+#define pDMA_TC_PER		((volatile unsigned short *)DMA_TC_PER)
+#define pDMA_TC_CNT		((volatile unsigned short *)DMA_TC_CNT)
+
+/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
+#define pDMA1_0_CONFIG		(volatile unsigned short *)DMA1_0_CONFIG
+#define pDMA1_0_NEXT_DESC_PTR	(volatile void **)DMA1_0_NEXT_DESC_PTR
+#define pDMA1_0_START_ADDR	(volatile void **)DMA1_0_START_ADDR
+#define pDMA1_0_X_COUNT		(volatile unsigned short *)DMA1_0_X_COUNT
+#define pDMA1_0_Y_COUNT		(volatile unsigned short *)DMA1_0_Y_COUNT
+#define pDMA1_0_X_MODIFY	(volatile unsigned short *)DMA1_0_X_MODIFY
+#define pDMA1_0_Y_MODIFY	(volatile unsigned short *)DMA1_0_Y_MODIFY
+#define pDMA1_0_CURR_DESC_PTR	(volatile void **)DMA1_0_CURR_DESC_PTR
+#define pDMA1_0_CURR_ADDR	(volatile void **)DMA1_0_CURR_ADDR
+#define pDMA1_0_CURR_X_COUNT	(volatile unsigned short *)DMA1_0_CURR_X_COUNT
+#define pDMA1_0_CURR_Y_COUNT	(volatile unsigned short *)DMA1_0_CURR_Y_COUNT
+#define pDMA1_0_IRQ_STATUS	(volatile unsigned short *)DMA1_0_IRQ_STATUS
+#define pDMA1_0_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
+#define pDMA1_1_CONFIG		(volatile unsigned short *)DMA1_1_CONFIG
+#define pDMA1_1_NEXT_DESC_PTR	(volatile void **)DMA1_1_NEXT_DESC_PTR
+#define pDMA1_1_START_ADDR	(volatile void **)DMA1_1_START_ADDR
+#define pDMA1_1_X_COUNT		(volatile unsigned short *)DMA1_1_X_COUNT
+#define pDMA1_1_Y_COUNT		(volatile unsigned short *)DMA1_1_Y_COUNT
+#define pDMA1_1_X_MODIFY	(volatile unsigned short *)DMA1_1_X_MODIFY
+#define pDMA1_1_Y_MODIFY	(volatile unsigned short *)DMA1_1_Y_MODIFY
+#define pDMA1_1_CURR_DESC_PTR	(volatile void **)DMA1_1_CURR_DESC_PTR
+#define pDMA1_1_CURR_ADDR	(volatile void **)DMA1_1_CURR_ADDR
+#define pDMA1_1_CURR_X_COUNT	(volatile unsigned short *)DMA1_1_CURR_X_COUNT
+#define pDMA1_1_CURR_Y_COUNT	(volatile unsigned short *)DMA1_1_CURR_Y_COUNT
+#define pDMA1_1_IRQ_STATUS	(volatile unsigned short *)DMA1_1_IRQ_STATUS
+#define pDMA1_1_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_1_PERIPHERAL_MAP
+#define pDMA1_2_CONFIG		(volatile unsigned short *)DMA1_2_CONFIG
+#define pDMA1_2_NEXT_DESC_PTR	(volatile void **)DMA1_2_NEXT_DESC_PTR
+#define pDMA1_2_START_ADDR	(volatile void **)DMA1_2_START_ADDR
+#define pDMA1_2_X_COUNT		(volatile unsigned short *)DMA1_2_X_COUNT
+#define pDMA1_2_Y_COUNT		(volatile unsigned short *)DMA1_2_Y_COUNT
+#define pDMA1_2_X_MODIFY	(volatile unsigned short *)DMA1_2_X_MODIFY
+#define pDMA1_2_Y_MODIFY	(volatile unsigned short *)DMA1_2_Y_MODIFY
+#define pDMA1_2_CURR_DESC_PTR	(volatile void **)DMA1_2_CURR_DESC_PTR
+#define pDMA1_2_CURR_ADDR	(volatile void **)DMA1_2_CURR_ADDR
+#define pDMA1_2_CURR_X_COUNT	(volatile unsigned short *)DMA1_2_CURR_X_COUNT
+#define pDMA1_2_CURR_Y_COUNT	(volatile unsigned short *)DMA1_2_CURR_Y_COUNT
+#define pDMA1_2_IRQ_STATUS	(volatile unsigned short *)DMA1_2_IRQ_STATUS
+#define pDMA1_2_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_2_PERIPHERAL_MAP
+#define pDMA1_3_CONFIG		(volatile unsigned short *)DMA1_3_CONFIG
+#define pDMA1_3_NEXT_DESC_PTR	(volatile void **)DMA1_3_NEXT_DESC_PTR
+#define pDMA1_3_START_ADDR	(volatile void **)DMA1_3_START_ADDR
+#define pDMA1_3_X_COUNT		(volatile unsigned short *)DMA1_3_X_COUNT
+#define pDMA1_3_Y_COUNT		(volatile unsigned short *)DMA1_3_Y_COUNT
+#define pDMA1_3_X_MODIFY	(volatile unsigned short *)DMA1_3_X_MODIFY
+#define pDMA1_3_Y_MODIFY	(volatile unsigned short *)DMA1_3_Y_MODIFY
+#define pDMA1_3_CURR_DESC_PTR	(volatile void **)DMA1_3_CURR_DESC_PTR
+#define pDMA1_3_CURR_ADDR	(volatile void **)DMA1_3_CURR_ADDR
+#define pDMA1_3_CURR_X_COUNT	(volatile unsigned short *)DMA1_3_CURR_X_COUNT
+#define pDMA1_3_CURR_Y_COUNT	(volatile unsigned short *)DMA1_3_CURR_Y_COUNT
+#define pDMA1_3_IRQ_STATUS	(volatile unsigned short *)DMA1_3_IRQ_STATUS
+#define pDMA1_3_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_3_PERIPHERAL_MAP
+#define pDMA1_4_CONFIG		(volatile unsigned short *)DMA1_4_CONFIG
+#define pDMA1_4_NEXT_DESC_PTR	(volatile void **)DMA1_4_NEXT_DESC_PTR
+#define pDMA1_4_START_ADDR	(volatile void **)DMA1_4_START_ADDR
+#define pDMA1_4_X_COUNT		(volatile unsigned short *)DMA1_4_X_COUNT
+#define pDMA1_4_Y_COUNT		(volatile unsigned short *)DMA1_4_Y_COUNT
+#define pDMA1_4_X_MODIFY	(volatile unsigned short *)DMA1_4_X_MODIFY
+#define pDMA1_4_Y_MODIFY	(volatile unsigned short *)DMA1_4_Y_MODIFY
+#define pDMA1_4_CURR_DESC_PTR	(volatile void **)DMA1_4_CURR_DESC_PTR
+#define pDMA1_4_CURR_ADDR	(volatile void **)DMA1_4_CURR_ADDR
+#define pDMA1_4_CURR_X_COUNT	(volatile unsigned short *)DMA1_4_CURR_X_COUNT
+#define pDMA1_4_CURR_Y_COUNT	(volatile unsigned short *)DMA1_4_CURR_Y_COUNT
+#define pDMA1_4_IRQ_STATUS	(volatile unsigned short *)DMA1_4_IRQ_STATUS
+#define pDMA1_4_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_4_PERIPHERAL_MAP
+#define pDMA1_5_CONFIG		(volatile unsigned short *)DMA1_5_CONFIG
+#define pDMA1_5_NEXT_DESC_PTR	(volatile void **)DMA1_5_NEXT_DESC_PTR
+#define pDMA1_5_START_ADDR	(volatile void **)DMA1_5_START_ADDR
+#define pDMA1_5_X_COUNT		(volatile unsigned short *)DMA1_5_X_COUNT
+#define pDMA1_5_Y_COUNT		(volatile unsigned short *)DMA1_5_Y_COUNT
+#define pDMA1_5_X_MODIFY	(volatile unsigned short *)DMA1_5_X_MODIFY
+#define pDMA1_5_Y_MODIFY	(volatile unsigned short *)DMA1_5_Y_MODIFY
+#define pDMA1_5_CURR_DESC_PTR	(volatile void **)DMA1_5_CURR_DESC_PTR
+#define pDMA1_5_CURR_ADDR	(volatile void **)DMA1_5_CURR_ADDR
+#define pDMA1_5_CURR_X_COUNT	(volatile unsigned short *)DMA1_5_CURR_X_COUNT
+#define pDMA1_5_CURR_Y_COUNT	(volatile unsigned short *)DMA1_5_CURR_Y_COUNT
+#define pDMA1_5_IRQ_STATUS	(volatile unsigned short *)DMA1_5_IRQ_STATUS
+#define pDMA1_5_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_5_PERIPHERAL_MAP
+#define pDMA1_6_CONFIG		(volatile unsigned short *)DMA1_6_CONFIG
+#define pDMA1_6_NEXT_DESC_PTR	(volatile void **)DMA1_6_NEXT_DESC_PTR
+#define pDMA1_6_START_ADDR	(volatile void **)DMA1_6_START_ADDR
+#define pDMA1_6_X_COUNT		(volatile unsigned short *)DMA1_6_X_COUNT
+#define pDMA1_6_Y_COUNT		(volatile unsigned short *)DMA1_6_Y_COUNT
+#define pDMA1_6_X_MODIFY	(volatile unsigned short *)DMA1_6_X_MODIFY
+#define pDMA1_6_Y_MODIFY	(volatile unsigned short *)DMA1_6_Y_MODIFY
+#define pDMA1_6_CURR_DESC_PTR	(volatile void **)DMA1_6_CURR_DESC_PTR
+#define pDMA1_6_CURR_ADDR	(volatile void **)DMA1_6_CURR_ADDR
+#define pDMA1_6_CURR_X_COUNT	(volatile unsigned short *)DMA1_6_CURR_X_COUNT
+#define pDMA1_6_CURR_Y_COUNT	(volatile unsigned short *)DMA1_6_CURR_Y_COUNT
+#define pDMA1_6_IRQ_STATUS	(volatile unsigned short *)DMA1_6_IRQ_STATUS
+#define pDMA1_6_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_6_PERIPHERAL_MAP
+#define pDMA1_7_CONFIG		(volatile unsigned short *)DMA1_7_CONFIG
+#define pDMA1_7_NEXT_DESC_PTR	(volatile void **)DMA1_7_NEXT_DESC_PTR
+#define pDMA1_7_START_ADDR	(volatile void **)DMA1_7_START_ADDR
+#define pDMA1_7_X_COUNT		(volatile unsigned short *)DMA1_7_X_COUNT
+#define pDMA1_7_Y_COUNT		(volatile unsigned short *)DMA1_7_Y_COUNT
+#define pDMA1_7_X_MODIFY	(volatile unsigned short *)DMA1_7_X_MODIFY
+#define pDMA1_7_Y_MODIFY	(volatile unsigned short *)DMA1_7_Y_MODIFY
+#define pDMA1_7_CURR_DESC_PTR	(volatile void **)DMA1_7_CURR_DESC_PTR
+#define pDMA1_7_CURR_ADDR	(volatile void **)DMA1_7_CURR_ADDR
+#define pDMA1_7_CURR_X_COUNT	(volatile unsigned short *)DMA1_7_CURR_X_COUNT
+#define pDMA1_7_CURR_Y_COUNT	(volatile unsigned short *)DMA1_7_CURR_Y_COUNT
+#define pDMA1_7_IRQ_STATUS	(volatile unsigned short *)DMA1_7_IRQ_STATUS
+#define pDMA1_7_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_7_PERIPHERAL_MAP
+#define pDMA1_8_CONFIG		(volatile unsigned short *)DMA1_8_CONFIG
+#define pDMA1_8_NEXT_DESC_PTR	(volatile void **)DMA1_8_NEXT_DESC_PTR
+#define pDMA1_8_START_ADDR	(volatile void **)DMA1_8_START_ADDR
+#define pDMA1_8_X_COUNT		(volatile unsigned short *)DMA1_8_X_COUNT
+#define pDMA1_8_Y_COUNT		(volatile unsigned short *)DMA1_8_Y_COUNT
+#define pDMA1_8_X_MODIFY	(volatile unsigned short *)DMA1_8_X_MODIFY
+#define pDMA1_8_Y_MODIFY	(volatile unsigned short *)DMA1_8_Y_MODIFY
+#define pDMA1_8_CURR_DESC_PTR	(volatile void **)DMA1_8_CURR_DESC_PTR
+#define pDMA1_8_CURR_ADDR	(volatile void **)DMA1_8_CURR_ADDR
+#define pDMA1_8_CURR_X_COUNT	(volatile unsigned short *)DMA1_8_CURR_X_COUNT
+#define pDMA1_8_CURR_Y_COUNT	(volatile unsigned short *)DMA1_8_CURR_Y_COUNT
+#define pDMA1_8_IRQ_STATUS	(volatile unsigned short *)DMA1_8_IRQ_STATUS
+#define pDMA1_8_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_8_PERIPHERAL_MAP
+#define pDMA1_9_CONFIG		(volatile unsigned short *)DMA1_9_CONFIG
+#define pDMA1_9_NEXT_DESC_PTR	(volatile void **)DMA1_9_NEXT_DESC_PTR
+#define pDMA1_9_START_ADDR	(volatile void **)DMA1_9_START_ADDR
+#define pDMA1_9_X_COUNT		(volatile unsigned short *)DMA1_9_X_COUNT
+#define pDMA1_9_Y_COUNT		(volatile unsigned short *)DMA1_9_Y_COUNT
+#define pDMA1_9_X_MODIFY	(volatile unsigned short *)DMA1_9_X_MODIFY
+#define pDMA1_9_Y_MODIFY	(volatile unsigned short *)DMA1_9_Y_MODIFY
+#define pDMA1_9_CURR_DESC_PTR	(volatile void **)DMA1_9_CURR_DESC_PTR
+#define pDMA1_9_CURR_ADDR	(volatile void **)DMA1_9_CURR_ADDR
+#define pDMA1_9_CURR_X_COUNT	(volatile unsigned short *)DMA1_9_CURR_X_COUNT
+#define pDMA1_9_CURR_Y_COUNT	(volatile unsigned short *)DMA1_9_CURR_Y_COUNT
+#define pDMA1_9_IRQ_STATUS	(volatile unsigned short *)DMA1_9_IRQ_STATUS
+#define pDMA1_9_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_9_PERIPHERAL_MAP
+#define pDMA1_10_CONFIG		(volatile unsigned short *)DMA1_10_CONFIG
+#define pDMA1_10_NEXT_DESC_PTR	(volatile void **)DMA1_10_NEXT_DESC_PTR
+#define pDMA1_10_START_ADDR	(volatile void **)DMA1_10_START_ADDR
+#define pDMA1_10_X_COUNT	(volatile unsigned short *)DMA1_10_X_COUNT
+#define pDMA1_10_Y_COUNT	(volatile unsigned short *)DMA1_10_Y_COUNT
+#define pDMA1_10_X_MODIFY	(volatile unsigned short *)DMA1_10_X_MODIFY
+#define pDMA1_10_Y_MODIFY	(volatile unsigned short *)DMA1_10_Y_MODIFY
+#define pDMA1_10_CURR_DESC_PTR	(volatile void **)DMA1_10_CURR_DESC_PTR
+#define pDMA1_10_CURR_ADDR	(volatile void **)DMA1_10_CURR_ADDR
+#define pDMA1_10_CURR_X_COUNT	(volatile unsigned short *)DMA1_10_CURR_X_COUNT
+#define pDMA1_10_CURR_Y_COUNT	(volatile unsigned short *)DMA1_10_CURR_Y_COUNT
+#define pDMA1_10_IRQ_STATUS	(volatile unsigned short *)DMA1_10_IRQ_STATUS
+#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP
+#define pDMA1_11_CONFIG		(volatile unsigned short *)DMA1_11_CONFIG
+#define pDMA1_11_NEXT_DESC_PTR	(volatile void **)DMA1_11_NEXT_DESC_PTR
+#define pDMA1_11_START_ADDR	(volatile void **)DMA1_11_START_ADDR
+#define pDMA1_11_X_COUNT	(volatile unsigned short *)DMA1_11_X_COUNT
+#define pDMA1_11_Y_COUNT	(volatile unsigned short *)DMA1_11_Y_COUNT
+#define pDMA1_11_X_MODIFY	(volatile signed short *)DMA1_11_X_MODIFY
+#define pDMA1_11_Y_MODIFY	(volatile signed short *)DMA1_11_Y_MODIFY
+#define pDMA1_11_CURR_DESC_PTR	(volatile void **)DMA1_11_CURR_DESC_PTR
+#define pDMA1_11_CURR_ADDR	(volatile void **)DMA1_11_CURR_ADDR
+#define pDMA1_11_CURR_X_COUNT	(volatile unsigned short *)DMA1_11_CURR_X_COUNT
+#define pDMA1_11_CURR_Y_COUNT	(volatile unsigned short *)DMA1_11_CURR_Y_COUNT
+#define pDMA1_11_IRQ_STATUS	(volatile unsigned short *)DMA1_11_IRQ_STATUS
+#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP
+
+/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF)*/
+#define pMDMA1_D0_CONFIG	(volatile unsigned short *)MDMA1_D0_CONFIG
+#define pMDMA1_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR
+#define pMDMA1_D0_START_ADDR	(volatile void **)MDMA1_D0_START_ADDR
+#define pMDMA1_D0_X_COUNT	(volatile unsigned short *)MDMA1_D0_X_COUNT
+#define pMDMA1_D0_Y_COUNT	(volatile unsigned short *)MDMA1_D0_Y_COUNT
+#define pMDMA1_D0_X_MODIFY	(volatile signed short *)MDMA1_D0_X_MODIFY
+#define pMDMA1_D0_Y_MODIFY	(volatile signed short *)MDMA1_D0_Y_MODIFY
+#define pMDMA1_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR
+#define pMDMA1_D0_CURR_ADDR	(volatile void **)MDMA1_D0_CURR_ADDR
+#define pMDMA1_D0_CURR_X_COUNT	(volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
+#define pMDMA1_D0_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
+#define pMDMA1_D0_IRQ_STATUS	(volatile unsigned short *)MDMA1_D0_IRQ_STATUS
+#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
+#define pMDMA1_S0_CONFIG	(volatile unsigned short *)MDMA1_S0_CONFIG
+#define pMDMA1_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR
+#define pMDMA1_S0_START_ADDR	(volatile void **)MDMA1_S0_START_ADDR
+#define pMDMA1_S0_X_COUNT	(volatile unsigned short *)MDMA1_S0_X_COUNT
+#define pMDMA1_S0_Y_COUNT	(volatile unsigned short *)MDMA1_S0_Y_COUNT
+#define pMDMA1_S0_X_MODIFY	(volatile signed short *)MDMA1_S0_X_MODIFY
+#define pMDMA1_S0_Y_MODIFY	(volatile signed short *)MDMA1_S0_Y_MODIFY
+#define pMDMA1_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR
+#define pMDMA1_S0_CURR_ADDR	(volatile void **)MDMA1_S0_CURR_ADDR
+#define pMDMA1_S0_CURR_X_COUNT	(volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
+#define pMDMA1_S0_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
+#define pMDMA1_S0_IRQ_STATUS	(volatile unsigned short *)MDMA1_S0_IRQ_STATUS
+#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
+#define pMDMA1_D1_CONFIG	(volatile unsigned short *)MDMA1_D1_CONFIG
+#define pMDMA1_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR
+#define pMDMA1_D1_START_ADDR	(volatile void **)MDMA1_D1_START_ADDR
+#define pMDMA1_D1_X_COUNT	(volatile unsigned short *)MDMA1_D1_X_COUNT
+#define pMDMA1_D1_Y_COUNT	(volatile unsigned short *)MDMA1_D1_Y_COUNT
+#define pMDMA1_D1_X_MODIFY	(volatile signed short *)MDMA1_D1_X_MODIFY
+#define pMDMA1_D1_Y_MODIFY	(volatile signed short *)MDMA1_D1_Y_MODIFY
+#define pMDMA1_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR
+#define pMDMA1_D1_CURR_ADDR	(volatile void **)MDMA1_D1_CURR_ADDR
+#define pMDMA1_D1_CURR_X_COUNT	(volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
+#define pMDMA1_D1_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
+#define pMDMA1_D1_IRQ_STATUS	(volatile unsigned short *)MDMA1_D1_IRQ_STATUS
+#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
+#define pMDMA1_S1_CONFIG	(volatile unsigned short *)MDMA1_S1_CONFIG
+#define pMDMA1_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR
+#define pMDMA1_S1_START_ADDR	(volatile void **)MDMA1_S1_START_ADDR
+#define pMDMA1_S1_X_COUNT	(volatile unsigned short *)MDMA1_S1_X_COUNT
+#define pMDMA1_S1_Y_COUNT	(volatile unsigned short *)MDMA1_S1_Y_COUNT
+#define pMDMA1_S1_X_MODIFY	(volatile signed short *)MDMA1_S1_X_MODIFY
+#define pMDMA1_S1_Y_MODIFY	(volatile signed short *)MDMA1_S1_Y_MODIFY
+#define pMDMA1_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR
+#define pMDMA1_S1_CURR_ADDR	(volatile void **)MDMA1_S1_CURR_ADDR
+#define pMDMA1_S1_CURR_X_COUNT	(volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
+#define pMDMA1_S1_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
+#define pMDMA1_S1_IRQ_STATUS	(volatile unsigned short *)MDMA1_S1_IRQ_STATUS
+#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
+
+/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
+#define pDMA2_0_CONFIG		(volatile unsigned short *)DMA2_0_CONFIG
+#define pDMA2_0_NEXT_DESC_PTR	(volatile void **)DMA2_0_NEXT_DESC_PTR
+#define pDMA2_0_START_ADDR	(volatile void **)DMA2_0_START_ADDR
+#define pDMA2_0_X_COUNT		(volatile unsigned short *)DMA2_0_X_COUNT
+#define pDMA2_0_Y_COUNT		(volatile unsigned short *)DMA2_0_Y_COUNT
+#define pDMA2_0_X_MODIFY	(volatile signed short *)DMA2_0_X_MODIFY
+#define pDMA2_0_Y_MODIFY	(volatile signed short *)DMA2_0_Y_MODIFY
+#define pDMA2_0_CURR_DESC_PTR	(volatile void **)DMA2_0_CURR_DESC_PTR
+#define pDMA2_0_CURR_ADDR	(volatile void **)DMA2_0_CURR_ADDR
+#define pDMA2_0_CURR_X_COUNT	(volatile unsigned short *)DMA2_0_CURR_X_COUNT
+#define pDMA2_0_CURR_Y_COUNT	(volatile unsigned short *)DMA2_0_CURR_Y_COUNT
+#define pDMA2_0_IRQ_STATUS	(volatile unsigned short *)DMA2_0_IRQ_STATUS
+#define pDMA2_0_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
+#define pDMA2_1_CONFIG		(volatile unsigned short *)DMA2_1_CONFIG
+#define pDMA2_1_NEXT_DESC_PTR	(volatile void **)DMA2_1_NEXT_DESC_PTR
+#define pDMA2_1_START_ADDR	(volatile void **)DMA2_1_START_ADDR
+#define pDMA2_1_X_COUNT		(volatile unsigned short *)DMA2_1_X_COUNT
+#define pDMA2_1_Y_COUNT		(volatile unsigned short *)DMA2_1_Y_COUNT
+#define pDMA2_1_X_MODIFY	(volatile signed short *)DMA2_1_X_MODIFY
+#define pDMA2_1_Y_MODIFY	(volatile signed short *)DMA2_1_Y_MODIFY
+#define pDMA2_1_CURR_DESC_PTR	(volatile void **)DMA2_1_CURR_DESC_PTR
+#define pDMA2_1_CURR_ADDR	(volatile void **)DMA2_1_CURR_ADDR
+#define pDMA2_1_CURR_X_COUNT	(volatile unsigned short *)DMA2_1_CURR_X_COUNT
+#define pDMA2_1_CURR_Y_COUNT	(volatile unsigned short *)DMA2_1_CURR_Y_COUNT
+#define pDMA2_1_IRQ_STATUS	(volatile unsigned short *)DMA2_1_IRQ_STATUS
+#define pDMA2_1_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
+#define pDMA2_2_CONFIG		(volatile unsigned short *)DMA2_2_CONFIG
+#define pDMA2_2_NEXT_DESC_PTR	(volatile void **)DMA2_2_NEXT_DESC_PTR
+#define pDMA2_2_START_ADDR	(volatile void **)DMA2_2_START_ADDR
+#define pDMA2_2_X_COUNT		(volatile unsigned short *)DMA2_2_X_COUNT
+#define pDMA2_2_Y_COUNT		(volatile unsigned short *)DMA2_2_Y_COUNT
+#define pDMA2_2_X_MODIFY	(volatile signed short *)DMA2_2_X_MODIFY
+#define pDMA2_2_Y_MODIFY	(volatile signed short *)DMA2_2_Y_MODIFY
+#define pDMA2_2_CURR_DESC_PTR	(volatile void **)DMA2_2_CURR_DESC_PTR
+#define pDMA2_2_CURR_ADDR	(volatile void **)DMA2_2_CURR_ADDR
+#define pDMA2_2_CURR_X_COUNT	(volatile unsigned short *)DMA2_2_CURR_X_COUNT
+#define pDMA2_2_CURR_Y_COUNT	(volatile unsigned short *)DMA2_2_CURR_Y_COUNT
+#define pDMA2_2_IRQ_STATUS	(volatile unsigned short *)DMA2_2_IRQ_STATUS
+#define pDMA2_2_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
+#define pDMA2_3_CONFIG		(volatile unsigned short *)DMA2_3_CONFIG
+#define pDMA2_3_NEXT_DESC_PTR	(volatile void **)DMA2_3_NEXT_DESC_PTR
+#define pDMA2_3_START_ADDR	(volatile void **)DMA2_3_START_ADDR
+#define pDMA2_3_X_COUNT		(volatile unsigned short *)DMA2_3_X_COUNT
+#define pDMA2_3_Y_COUNT		(volatile unsigned short *)DMA2_3_Y_COUNT
+#define pDMA2_3_X_MODIFY	(volatile signed short *)DMA2_3_X_MODIFY
+#define pDMA2_3_Y_MODIFY	(volatile signed short *)DMA2_3_Y_MODIFY
+#define pDMA2_3_CURR_DESC_PTR	(volatile void **)DMA2_3_CURR_DESC_PTR
+#define pDMA2_3_CURR_ADDR	(volatile void **)DMA2_3_CURR_ADDR
+#define pDMA2_3_CURR_X_COUNT	(volatile unsigned short *)DMA2_3_CURR_X_COUNT
+#define pDMA2_3_CURR_Y_COUNT	(volatile unsigned short *)DMA2_3_CURR_Y_COUNT
+#define pDMA2_3_IRQ_STATUS	(volatile unsigned short *)DMA2_3_IRQ_STATUS
+#define pDMA2_3_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
+#define pDMA2_4_CONFIG		(volatile unsigned short *)DMA2_4_CONFIG
+#define pDMA2_4_NEXT_DESC_PTR	(volatile void **)DMA2_4_NEXT_DESC_PTR
+#define pDMA2_4_START_ADDR	(volatile void **)DMA2_4_START_ADDR
+#define pDMA2_4_X_COUNT		(volatile unsigned short *)DMA2_4_X_COUNT
+#define pDMA2_4_Y_COUNT		(volatile unsigned short *)DMA2_4_Y_COUNT
+#define pDMA2_4_X_MODIFY	(volatile signed short *)DMA2_4_X_MODIFY
+#define pDMA2_4_Y_MODIFY	(volatile signed short *)DMA2_4_Y_MODIFY
+#define pDMA2_4_CURR_DESC_PTR	(volatile void **)DMA2_4_CURR_DESC_PTR
+#define pDMA2_4_CURR_ADDR	(volatile void **)DMA2_4_CURR_ADDR
+#define pDMA2_4_CURR_X_COUNT	(volatile unsigned short *)DMA2_4_CURR_X_COUNT
+#define pDMA2_4_CURR_Y_COUNT	(volatile unsigned short *)DMA2_4_CURR_Y_COUNT
+#define pDMA2_4_IRQ_STATUS	(volatile unsigned short *)DMA2_4_IRQ_STATUS
+#define pDMA2_4_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
+#define pDMA2_5_CONFIG		(volatile unsigned short *)DMA2_5_CONFIG
+#define pDMA2_5_NEXT_DESC_PTR	(volatile void **)DMA2_5_NEXT_DESC_PTR
+#define pDMA2_5_START_ADDR	(volatile void **)DMA2_5_START_ADDR
+#define pDMA2_5_X_COUNT		(volatile unsigned short *)DMA2_5_X_COUNT
+#define pDMA2_5_Y_COUNT		(volatile unsigned short *)DMA2_5_Y_COUNT
+#define pDMA2_5_X_MODIFY	(volatile signed short *)DMA2_5_X_MODIFY
+#define pDMA2_5_Y_MODIFY	(volatile signed short *)DMA2_5_Y_MODIFY
+#define pDMA2_5_CURR_DESC_PTR	(volatile void **)DMA2_5_CURR_DESC_PTR
+#define pDMA2_5_CURR_ADDR	(volatile void **)DMA2_5_CURR_ADDR
+#define pDMA2_5_CURR_X_COUNT	(volatile unsigned short *)DMA2_5_CURR_X_COUNT
+#define pDMA2_5_CURR_Y_COUNT	(volatile unsigned short *)DMA2_5_CURR_Y_COUNT
+#define pDMA2_5_IRQ_STATUS	(volatile unsigned short *)DMA2_5_IRQ_STATUS
+#define pDMA2_5_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
+#define pDMA2_6_CONFIG		(volatile unsigned short *)DMA2_6_CONFIG
+#define pDMA2_6_NEXT_DESC_PTR	(volatile void **)DMA2_6_NEXT_DESC_PTR
+#define pDMA2_6_START_ADDR	(volatile void **)DMA2_6_START_ADDR
+#define pDMA2_6_X_COUNT		(volatile unsigned short *)DMA2_6_X_COUNT
+#define pDMA2_6_Y_COUNT		(volatile unsigned short *)DMA2_6_Y_COUNT
+#define pDMA2_6_X_MODIFY	(volatile signed short *)DMA2_6_X_MODIFY
+#define pDMA2_6_Y_MODIFY	(volatile signed short *)DMA2_6_Y_MODIFY
+#define pDMA2_6_CURR_DESC_PTR	(volatile void **)DMA2_6_CURR_DESC_PTR
+#define pDMA2_6_CURR_ADDR	(volatile void **)DMA2_6_CURR_ADDR
+#define pDMA2_6_CURR_X_COUNT	(volatile unsigned short *)DMA2_6_CURR_X_COUNT
+#define pDMA2_6_CURR_Y_COUNT	(volatile unsigned short *)DMA2_6_CURR_Y_COUNT
+#define pDMA2_6_IRQ_STATUS	(volatile unsigned short *)DMA2_6_IRQ_STATUS
+#define pDMA2_6_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
+#define pDMA2_7_CONFIG		(volatile unsigned short *)DMA2_7_CONFIG
+#define pDMA2_7_NEXT_DESC_PTR	(volatile void **)DMA2_7_NEXT_DESC_PTR
+#define pDMA2_7_START_ADDR	(volatile void **)DMA2_7_START_ADDR
+#define pDMA2_7_X_COUNT		(volatile unsigned short *)DMA2_7_X_COUNT
+#define pDMA2_7_Y_COUNT		(volatile unsigned short *)DMA2_7_Y_COUNT
+#define pDMA2_7_X_MODIFY	(volatile signed short *)DMA2_7_X_MODIFY
+#define pDMA2_7_Y_MODIFY	(volatile signed short *)DMA2_7_Y_MODIFY
+#define pDMA2_7_CURR_DESC_PTR	(volatile void **)DMA2_7_CURR_DESC_PTR
+#define pDMA2_7_CURR_ADDR	(volatile void **)DMA2_7_CURR_ADDR
+#define pDMA2_7_CURR_X_COUNT	(volatile unsigned short *)DMA2_7_CURR_X_COUNT
+#define pDMA2_7_CURR_Y_COUNT	(volatile unsigned short *)DMA2_7_CURR_Y_COUNT
+#define pDMA2_7_IRQ_STATUS	(volatile unsigned short *)DMA2_7_IRQ_STATUS
+#define pDMA2_7_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_7_PERIPHERAL_MAP
+#define pDMA2_8_CONFIG		(volatile unsigned short *)DMA2_8_CONFIG
+#define pDMA2_8_NEXT_DESC_PTR	(volatile void **)DMA2_8_NEXT_DESC_PTR
+#define pDMA2_8_START_ADDR	(volatile void **)DMA2_8_START_ADDR
+#define pDMA2_8_X_COUNT		(volatile unsigned short *)DMA2_8_X_COUNT
+#define pDMA2_8_Y_COUNT		(volatile unsigned short *)DMA2_8_Y_COUNT
+#define pDMA2_8_X_MODIFY	(volatile signed short *)DMA2_8_X_MODIFY
+#define pDMA2_8_Y_MODIFY	(volatile signed short *)DMA2_8_Y_MODIFY
+#define pDMA2_8_CURR_DESC_PTR	(volatile void **)DMA2_8_CURR_DESC_PTR
+#define pDMA2_8_CURR_ADDR	(volatile void **)DMA2_8_CURR_ADDR
+#define pDMA2_8_CURR_X_COUNT	(volatile unsigned short *)DMA2_8_CURR_X_COUNT
+#define pDMA2_8_CURR_Y_COUNT	(volatile unsigned short *)DMA2_8_CURR_Y_COUNT
+#define pDMA2_8_IRQ_STATUS	(volatile unsigned short *)DMA2_8_IRQ_STATUS
+#define pDMA2_8_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_8_PERIPHERAL_MAP
+#define pDMA2_9_CONFIG		(volatile unsigned short *)DMA2_9_CONFIG
+#define pDMA2_9_NEXT_DESC_PTR	(volatile void **)DMA2_9_NEXT_DESC_PTR
+#define pDMA2_9_START_ADDR	(volatile void **)DMA2_9_START_ADDR
+#define pDMA2_9_X_COUNT		(volatile unsigned short *)DMA2_9_X_COUNT
+#define pDMA2_9_Y_COUNT		(volatile unsigned short *)DMA2_9_Y_COUNT
+#define pDMA2_9_X_MODIFY	(volatile signed short *)DMA2_9_X_MODIFY
+#define pDMA2_9_Y_MODIFY	(volatile signed short *)DMA2_9_Y_MODIFY
+#define pDMA2_9_CURR_DESC_PTR	(volatile void **)DMA2_9_CURR_DESC_PTR
+#define pDMA2_9_CURR_ADDR	(volatile void **)DMA2_9_CURR_ADDR
+#define pDMA2_9_CURR_X_COUNT	(volatile unsigned short *)DMA2_9_CURR_X_COUNT
+#define pDMA2_9_CURR_Y_COUNT	(volatile unsigned short *)DMA2_9_CURR_Y_COUNT
+#define pDMA2_9_IRQ_STATUS	(volatile unsigned short *)DMA2_9_IRQ_STATUS
+#define pDMA2_9_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_9_PERIPHERAL_MAP
+#define pDMA2_10_CONFIG		(volatile unsigned short *)DMA2_10_CONFIG
+#define pDMA2_10_NEXT_DESC_PTR	(volatile void **)DMA2_10_NEXT_DESC_PTR
+#define pDMA2_10_START_ADDR	(volatile void **)DMA2_10_START_ADDR
+#define pDMA2_10_X_COUNT	(volatile unsigned short *)DMA2_10_X_COUNT
+#define pDMA2_10_Y_COUNT	(volatile unsigned short *)DMA2_10_Y_COUNT
+#define pDMA2_10_X_MODIFY	(volatile signed short *)DMA2_10_X_MODIFY
+#define pDMA2_10_Y_MODIFY	(volatile signed short *)DMA2_10_Y_MODIFY
+#define pDMA2_10_CURR_DESC_PTR	(volatile void **)DMA2_10_CURR_DESC_PTR
+#define pDMA2_10_CURR_ADDR	(volatile void **)DMA2_10_CURR_ADDR
+#define pDMA2_10_CURR_X_COUNT	(volatile unsigned short *)DMA2_10_CURR_X_COUNT
+#define pDMA2_10_CURR_Y_COUNT	(volatile unsigned short *)DMA2_10_CURR_Y_COUNT
+#define pDMA2_10_IRQ_STATUS	(volatile unsigned short *)DMA2_10_IRQ_STATUS
+#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP
+#define pDMA2_11_CONFIG		(volatile unsigned short *)DMA2_11_CONFIG
+#define pDMA2_11_NEXT_DESC_PTR	(volatile void **)DMA2_11_NEXT_DESC_PTR
+#define pDMA2_11_START_ADDR	(volatile void **)DMA2_11_START_ADDR
+#define pDMA2_11_X_COUNT	(volatile unsigned short *)DMA2_11_X_COUNT
+#define pDMA2_11_Y_COUNT	(volatile unsigned short *)DMA2_11_Y_COUNT
+#define pDMA2_11_X_MODIFY	(volatile signed short *)DMA2_11_X_MODIFY
+#define pDMA2_11_Y_MODIFY	(volatile signed short *)DMA2_11_Y_MODIFY
+#define pDMA2_11_CURR_DESC_PTR	(volatile void **)DMA2_11_CURR_DESC_PTR
+#define pDMA2_11_CURR_ADDR	(volatile void **)DMA2_11_CURR_ADDR
+#define pDMA2_11_CURR_X_COUNT	(volatile unsigned short *)DMA2_11_CURR_X_COUNT
+#define pDMA2_11_CURR_Y_COUNT	(volatile unsigned short *)DMA2_11_CURR_Y_COUNT
+#define pDMA2_11_IRQ_STATUS	(volatile unsigned short *)DMA2_11_IRQ_STATUS
+#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP
+
+/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
+#define pMDMA2_D0_CONFIG	(volatile unsigned short *)MDMA2_D0_CONFIG
+#define pMDMA2_D0_NEXT_DESC_PTR (volatile void **)MDMA2_D0_NEXT_DESC_PTR
+#define pMDMA2_D0_START_ADDR	(volatile void **)MDMA2_D0_START_ADDR
+#define pMDMA2_D0_X_COUNT	(volatile unsigned short *)MDMA2_D0_X_COUNT
+#define pMDMA2_D0_Y_COUNT	(volatile unsigned short *)MDMA2_D0_Y_COUNT
+#define pMDMA2_D0_X_MODIFY	(volatile signed short *)MDMA2_D0_X_MODIFY
+#define pMDMA2_D0_Y_MODIFY	(volatile signed short *)MDMA2_D0_Y_MODIFY
+#define pMDMA2_D0_CURR_DESC_PTR (volatile void **)MDMA2_D0_CURR_DESC_PTR
+#define pMDMA2_D0_CURR_ADDR	(volatile void **)MDMA2_D0_CURR_ADDR
+#define pMDMA2_D0_CURR_X_COUNT	(volatile unsigned short *)MDMA2_D0_CURR_X_COUNT
+#define pMDMA2_D0_CURR_Y_COUNT	(volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT
+#define pMDMA2_D0_IRQ_STATUS	(volatile unsigned short *)MDMA2_D0_IRQ_STATUS
+#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP
+#define pMDMA2_S0_CONFIG	(volatile unsigned short *)MDMA2_S0_CONFIG
+#define pMDMA2_S0_NEXT_DESC_PTR (volatile void **)MDMA2_S0_NEXT_DESC_PTR
+#define pMDMA2_S0_START_ADDR	(volatile void **)MDMA2_S0_START_ADDR
+#define pMDMA2_S0_X_COUNT	(volatile unsigned short *)MDMA2_S0_X_COUNT
+#define pMDMA2_S0_Y_COUNT	(volatile unsigned short *)MDMA2_S0_Y_COUNT
+#define pMDMA2_S0_X_MODIFY	(volatile signed short *)MDMA2_S0_X_MODIFY
+#define pMDMA2_S0_Y_MODIFY	(volatile signed short *)MDMA2_S0_Y_MODIFY
+#define pMDMA2_S0_CURR_DESC_PTR (volatile void **)MDMA2_S0_CURR_DESC_PTR
+#define pMDMA2_S0_CURR_ADDR	(volatile void **)MDMA2_S0_CURR_ADDR
+#define pMDMA2_S0_CURR_X_COUNT	(volatile unsigned short *)MDMA2_S0_CURR_X_COUNT
+#define pMDMA2_S0_CURR_Y_COUNT	(volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT
+#define pMDMA2_S0_IRQ_STATUS	(volatile unsigned short *)MDMA2_S0_IRQ_STATUS
+#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP
+#define pMDMA2_D1_CONFIG	(volatile unsigned short *)MDMA2_D1_CONFIG
+#define pMDMA2_D1_NEXT_DESC_PTR (volatile void **)MDMA2_D1_NEXT_DESC_PTR
+#define pMDMA2_D1_START_ADDR	(volatile void **)MDMA2_D1_START_ADDR
+#define pMDMA2_D1_X_COUNT	(volatile unsigned short *)MDMA2_D1_X_COUNT
+#define pMDMA2_D1_Y_COUNT	(volatile unsigned short *)MDMA2_D1_Y_COUNT
+#define pMDMA2_D1_X_MODIFY	(volatile signed short *)MDMA2_D1_X_MODIFY
+#define pMDMA2_D1_Y_MODIFY	(volatile signed short *)MDMA2_D1_Y_MODIFY
+#define pMDMA2_D1_CURR_DESC_PTR (volatile void **)MDMA2_D1_CURR_DESC_PTR
+#define pMDMA2_D1_CURR_ADDR	(volatile void **)MDMA2_D1_CURR_ADDR
+#define pMDMA2_D1_CURR_X_COUNT	(volatile unsigned short *)MDMA2_D1_CURR_X_COUNT
+#define pMDMA2_D1_CURR_Y_COUNT	(volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT
+#define pMDMA2_D1_IRQ_STATUS	(volatile unsigned short *)MDMA2_D1_IRQ_STATUS
+#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP
+#define pMDMA2_S1_CONFIG	(volatile unsigned short *)MDMA2_S1_CONFIG
+#define pMDMA2_S1_NEXT_DESC_PTR (volatile void **)MDMA2_S1_NEXT_DESC_PTR
+#define pMDMA2_S1_START_ADDR	(volatile void **)MDMA2_S1_START_ADDR
+#define pMDMA2_S1_X_COUNT	(volatile unsigned short *)MDMA2_S1_X_COUNT
+#define pMDMA2_S1_Y_COUNT	(volatile unsigned short *)MDMA2_S1_Y_COUNT
+#define pMDMA2_S1_X_MODIFY	(volatile signed short *)MDMA2_S1_X_MODIFY
+#define pMDMA2_S1_Y_MODIFY	(volatile signed short *)MDMA2_S1_Y_MODIFY
+#define pMDMA2_S1_CURR_DESC_PTR (volatile void **)MDMA2_S1_CURR_DESC_PTR
+#define pMDMA2_S1_CURR_ADDR	(volatile void **)MDMA2_S1_CURR_ADDR
+#define pMDMA2_S1_CURR_X_COUNT	(volatile unsigned short *)MDMA2_S1_CURR_X_COUNT
+#define pMDMA2_S1_CURR_Y_COUNT	(volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT
+#define pMDMA2_S1_IRQ_STATUS	(volatile unsigned short *)MDMA2_S1_IRQ_STATUS
+#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP
+
+/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
+#define pIMDMA_D0_CONFIG	(volatile unsigned short *)IMDMA_D0_CONFIG
+#define pIMDMA_D0_NEXT_DESC_PTR (volatile void **)IMDMA_D0_NEXT_DESC_PTR
+#define pIMDMA_D0_START_ADDR	(volatile void **)IMDMA_D0_START_ADDR
+#define pIMDMA_D0_X_COUNT	(volatile unsigned short *)IMDMA_D0_X_COUNT
+#define pIMDMA_D0_Y_COUNT	(volatile unsigned short *)IMDMA_D0_Y_COUNT
+#define pIMDMA_D0_X_MODIFY	(volatile signed short *)IMDMA_D0_X_MODIFY
+#define pIMDMA_D0_Y_MODIFY	(volatile signed short *)IMDMA_D0_Y_MODIFY
+#define pIMDMA_D0_CURR_DESC_PTR (volatile void **)IMDMA_D0_CURR_DESC_PTR
+#define pIMDMA_D0_CURR_ADDR	(volatile void **)IMDMA_D0_CURR_ADDR
+#define pIMDMA_D0_CURR_X_COUNT	(volatile unsigned short *)IMDMA_D0_CURR_X_COUNT
+#define pIMDMA_D0_CURR_Y_COUNT	(volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT
+#define pIMDMA_D0_IRQ_STATUS	(volatile unsigned short *)IMDMA_D0_IRQ_STATUS
+#define pIMDMA_S0_CONFIG	(volatile unsigned short *)IMDMA_S0_CONFIG
+#define pIMDMA_S0_NEXT_DESC_PTR (volatile void **)IMDMA_S0_NEXT_DESC_PTR
+#define pIMDMA_S0_START_ADDR	(volatile void **)IMDMA_S0_START_ADDR
+#define pIMDMA_S0_X_COUNT	(volatile unsigned short *)IMDMA_S0_X_COUNT
+#define pIMDMA_S0_Y_COUNT	(volatile unsigned short *)IMDMA_S0_Y_COUNT
+#define pIMDMA_S0_X_MODIFY	(volatile signed short *)IMDMA_S0_X_MODIFY
+#define pIMDMA_S0_Y_MODIFY	(volatile signed short *)IMDMA_S0_Y_MODIFY
+#define pIMDMA_S0_CURR_DESC_PTR (volatile void **)IMDMA_S0_CURR_DESC_PTR
+#define pIMDMA_S0_CURR_ADDR	(volatile void **)IMDMA_S0_CURR_ADDR
+#define pIMDMA_S0_CURR_X_COUNT	(volatile unsigned short *)IMDMA_S0_CURR_X_COUNT
+#define pIMDMA_S0_CURR_Y_COUNT	(volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT
+#define pIMDMA_S0_IRQ_STATUS	(volatile unsigned short *)IMDMA_S0_IRQ_STATUS
+#define pIMDMA_D1_CONFIG	(volatile unsigned short *)IMDMA_D1_CONFIG
+#define pIMDMA_D1_NEXT_DESC_PTR (volatile void **)IMDMA_D1_NEXT_DESC_PTR
+#define pIMDMA_D1_START_ADDR	(volatile void **)IMDMA_D1_START_ADDR
+#define pIMDMA_D1_X_COUNT	(volatile unsigned short *)IMDMA_D1_X_COUNT
+#define pIMDMA_D1_Y_COUNT	(volatile unsigned short *)IMDMA_D1_Y_COUNT
+#define pIMDMA_D1_X_MODIFY	(volatile signed short *)IMDMA_D1_X_MODIFY
+#define pIMDMA_D1_Y_MODIFY	(volatile signed short *)IMDMA_D1_Y_MODIFY
+#define pIMDMA_D1_CURR_DESC_PTR (volatile void **)IMDMA_D1_CURR_DESC_PTR
+#define pIMDMA_D1_CURR_ADDR	(volatile void **)IMDMA_D1_CURR_ADDR
+#define pIMDMA_D1_CURR_X_COUNT	(volatile unsigned short *)IMDMA_D1_CURR_X_COUNT
+#define pIMDMA_D1_CURR_Y_COUNT	(volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT
+#define pIMDMA_D1_IRQ_STATUS	(volatile unsigned short *)IMDMA_D1_IRQ_STATUS
+#define pIMDMA_S1_CONFIG	(volatile unsigned short *)IMDMA_S1_CONFIG
+#define pIMDMA_S1_NEXT_DESC_PTR (volatile void **)IMDMA_S1_NEXT_DESC_PTR
+#define pIMDMA_S1_START_ADDR	(volatile void **)IMDMA_S1_START_ADDR
+#define pIMDMA_S1_X_COUNT	(volatile unsigned short *)IMDMA_S1_X_COUNT
+#define pIMDMA_S1_Y_COUNT	(volatile unsigned short *)IMDMA_S1_Y_COUNT
+#define pIMDMA_S1_X_MODIFY	(volatile signed short *)IMDMA_S1_X_MODIFY
+#define pIMDMA_S1_Y_MODIFY	(volatile signed short *)IMDMA_S1_Y_MODIFY
+#define pIMDMA_S1_CURR_DESC_PTR (volatile void **)IMDMA_S1_CURR_DESC_PTR
+#define pIMDMA_S1_CURR_ADDR	(volatile void **)IMDMA_S1_CURR_ADDR
+#define pIMDMA_S1_CURR_X_COUNT	(volatile unsigned short *)IMDMA_S1_CURR_X_COUNT
+#define pIMDMA_S1_CURR_Y_COUNT	(volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT
+#define pIMDMA_S1_IRQ_STATUS	(volatile unsigned short *)IMDMA_S1_IRQ_STATUS
+
+/*
+ * System Reset and Interrupt Controller registers for
+ * core A (0xFFC0 0100-0xFFC0 01FF)
+ */
+#define pSWRST			(volatile unsigned short *)SICA_SWRST
+#define pSYSCR			(volatile unsigned short *)SICA_SYSCR
+#define pRVECT			(volatile unsigned short *)SICA_RVECT
+#define pSIC_SWRST		(volatile unsigned short *)SICA_SWRST
+#define pSIC_SYSCR		(volatile unsigned short *)SICA_SYSCR
+#define pSIC_RVECT		(volatile unsigned short *)SICA_RVECT
+#define pSIC_IMASK		(volatile unsigned long *)SICA_IMASK
+#define pSIC_IAR0		((volatile unsigned long *)SICA_IAR0)
+#define pSIC_IAR1		(volatile unsigned long *)SICA_IAR1
+#define pSIC_IAR2		(volatile unsigned long *)SICA_IAR2
+#define pSIC_ISR		(volatile unsigned long *)SICA_ISR0
+#define pSIC_IWR		(volatile unsigned long *)SICA_IWR0
+
+/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
+#define pWDOG_CTL		(volatile unsigned short *)WDOGA_CTL
+#define pWDOG_CNT		(volatile unsigned long *)WDOGA_CNT
+#define pWDOG_STAT		(volatile unsigned long *)WDOGA_STAT
+
+/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
+#define pFIO_FLAG_D		(volatile unsigned short *)FIO0_FLAG_D
+#define pFIO_FLAG_C		(volatile unsigned short *)FIO0_FLAG_C
+#define pFIO_FLAG_S		(volatile unsigned short *)FIO0_FLAG_S
+#define pFIO_FLAG_T		(volatile unsigned short *)FIO0_FLAG_T
+#define pFIO_MASKA_D		(volatile unsigned short *)FIO0_MASKA_D
+#define pFIO_MASKA_C		(volatile unsigned short *)FIO0_MASKA_C
+#define pFIO_MASKA_S		(volatile unsigned short *)FIO0_MASKA_S
+#define pFIO_MASKA_T		(volatile unsigned short *)FIO0_MASKA_T
+#define pFIO_MASKB_D		(volatile unsigned short *)FIO0_MASKB_D
+#define pFIO_MASKB_C		(volatile unsigned short *)FIO0_MASKB_C
+#define pFIO_MASKB_S		(volatile unsigned short *)FIO0_MASKB_S
+#define pFIO_MASKB_T		(volatile unsigned short *)FIO0_MASKB_T
+#define pFIO_DIR		(volatile unsigned short *)FIO0_DIR
+#define pFIO_POLAR		(volatile unsigned short *)FIO0_POLAR
+#define pFIO_EDGE		(volatile unsigned short *)FIO0_EDGE
+#define pFIO_BOTH		(volatile unsigned short *)FIO0_BOTH
+#define pFIO_INEN		(volatile unsigned short *)FIO0_INEN
+
+/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/
+#define pPPI_CONTROL		(volatile unsigned short *)PPI0_CONTROL
+#define pPPI_STATUS		(volatile unsigned short *)PPI0_STATUS
+#define pPPI_COUNT		(volatile unsigned short *)PPI0_COUNT
+#define pPPI_DELAY		(volatile unsigned short *)PPI0_DELAY
+#define pPPI_FRAME		(volatile unsigned short *)PPI0_FRAME
+
+/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
+#define pDMA0_CONFIG		(volatile unsigned short *)DMA1_0_CONFIG
+#define pDMA0_NEXT_DESC_PTR	(volatile void **)DMA1_0_NEXT_DESC_PTR
+#define pDMA0_START_ADDR	(volatile void **)DMA1_0_START_ADDR
+#define pDMA0_X_COUNT		(volatile unsigned short *)DMA1_0_X_COUNT
+#define pDMA0_Y_COUNT		(volatile unsigned short *)DMA1_0_Y_COUNT
+#define pDMA0_X_MODIFY		(volatile unsigned short *)DMA1_0_X_MODIFY
+#define pDMA0_Y_MODIFY		(volatile unsigned short *)DMA1_0_Y_MODIFY
+#define pDMA0_CURR_DESC_PTR	(volatile void **)DMA1_0_CURR_DESC_PTR
+#define pDMA0_CURR_ADDR		(volatile void **)DMA1_0_CURR_ADDR
+#define pDMA0_CURR_X_COUNT	(volatile unsigned short *)DMA1_0_CURR_X_COUNT
+#define pDMA0_CURR_Y_COUNT	(volatile unsigned short *)DMA1_0_CURR_Y_COUNT
+#define pDMA0_IRQ_STATUS	(volatile unsigned short *)DMA1_0_IRQ_STATUS
+#define pDMA0_PERIPHERAL_MAP	(volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
+
+/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
+#define pMDMA_D0_CONFIG		(volatile unsigned short *)MDMA1_D0_CONFIG
+#define pMDMA_D0_NEXT_DESC_PTR	(volatile void **)MDMA1_D0_NEXT_DESC_PTR
+#define pMDMA_D0_START_ADDR	(volatile void **)MDMA1_D0_START_ADDR
+#define pMDMA_D0_X_COUNT	(volatile unsigned short *)MDMA1_D0_X_COUNT
+#define pMDMA_D0_Y_COUNT	(volatile unsigned short *)MDMA1_D0_Y_COUNT
+#define pMDMA_D0_X_MODIFY	(volatile unsigned short *)MDMA1_D0_X_MODIFY
+#define pMDMA_D0_Y_MODIFY	(volatile unsigned short *)MDMA1_D0_Y_MODIFY
+#define pMDMA_D0_CURR_DESC_PTR	(volatile void **)MDMA1_D0_CURR_DESC_PTR
+#define pMDMA_D0_CURR_ADDR	(volatile void **)MDMA1_D0_CURR_ADDR
+#define pMDMA_D0_CURR_X_COUNT	(volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
+#define pMDMA_D0_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
+#define pMDMA_D0_IRQ_STATUS	(volatile unsigned short *)MDMA1_D0_IRQ_STATUS
+#define pMDMA_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
+#define pMDMA_S0_CONFIG		(volatile unsigned short *)MDMA1_S0_CONFIG
+#define pMDMA_S0_NEXT_DESC_PTR	(volatile void **)MDMA1_S0_NEXT_DESC_PTR
+#define pMDMA_S0_START_ADDR	(volatile void **)MDMA1_S0_START_ADDR
+#define pMDMA_S0_X_COUNT	(volatile unsigned short *)MDMA1_S0_X_COUNT
+#define pMDMA_S0_Y_COUNT	(volatile unsigned short *)MDMA1_S0_Y_COUNT
+#define pMDMA_S0_X_MODIFY	(volatile unsigned short *)MDMA1_S0_X_MODIFY
+#define pMDMA_S0_Y_MODIFY	(volatile unsigned short *)MDMA1_S0_Y_MODIFY
+#define pMDMA_S0_CURR_DESC_PTR	(volatile void **)MDMA1_S0_CURR_DESC_PTR
+#define pMDMA_S0_CURR_ADDR	(volatile void **)MDMA1_S0_CURR_ADDR
+#define pMDMA_S0_CURR_X_COUNT	(volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
+#define pMDMA_S0_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
+#define pMDMA_S0_IRQ_STATUS	(volatile unsigned short *)MDMA1_S0_IRQ_STATUS
+#define pMDMA_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
+#define pMDMA_D1_CONFIG		(volatile unsigned short *)MDMA1_D1_CONFIG
+#define pMDMA_D1_NEXT_DESC_PTR	(volatile void **)MDMA1_D1_NEXT_DESC_PTR
+#define pMDMA_D1_START_ADDR	(volatile void **)MDMA1_D1_START_ADDR
+#define pMDMA_D1_X_COUNT	(volatile unsigned short *)MDMA1_D1_X_COUNT
+#define pMDMA_D1_Y_COUNT	(volatile unsigned short *)MDMA1_D1_Y_COUNT
+#define pMDMA_D1_X_MODIFY	(volatile unsigned short *)MDMA1_D1_X_MODIFY
+#define pMDMA_D1_Y_MODIFY	(volatile unsigned short *)MDMA1_D1_Y_MODIFY
+#define pMDMA_D1_CURR_DESC_PTR	(volatile void **)MDMA1_D1_CURR_DESC_PTR
+#define pMDMA_D1_CURR_ADDR	(volatile void **)MDMA1_D1_CURR_ADDR
+#define pMDMA_D1_CURR_X_COUNT	(volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
+#define pMDMA_D1_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
+#define pMDMA_D1_IRQ_STATUS	(volatile unsigned short *)MDMA1_D1_IRQ_STATUS
+#define pMDMA_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
+#define pMDMA_S1_CONFIG		(volatile unsigned short *)MDMA1_S1_CONFIG
+#define pMDMA_S1_NEXT_DESC_PTR	(volatile void **)MDMA1_S1_NEXT_DESC_PTR
+#define pMDMA_S1_START_ADDR	(volatile void **)MDMA1_S1_START_ADDR
+#define pMDMA_S1_X_COUNT	(volatile unsigned short *)MDMA1_S1_X_COUNT
+#define pMDMA_S1_Y_COUNT	(volatile unsigned short *)MDMA1_S1_Y_COUNT
+#define pMDMA_S1_X_MODIFY	(volatile unsigned short *)MDMA1_S1_X_MODIFY
+#define pMDMA_S1_Y_MODIFY	(volatile unsigned short *)MDMA1_S1_Y_MODIFY
+#define pMDMA_S1_CURR_DESC_PTR	(volatile void **)MDMA1_S1_CURR_DESC_PTR
+#define pMDMA_S1_CURR_ADDR	(volatile void **)MDMA1_S1_CURR_ADDR
+#define pMDMA_S1_CURR_X_COUNT	(volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
+#define pMDMA_S1_CURR_Y_COUNT	(volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
+#define pMDMA_S1_IRQ_STATUS	(volatile unsigned short *)MDMA1_S1_IRQ_STATUS
+#define pMDMA_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
+
+/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
+#define pDMA1_CONFIG		(volatile unsigned short *)DMA2_0_CONFIG
+#define pDMA1_NEXT_DESC_PTR	(volatile void **)DMA2_0_NEXT_DESC_PTR
+#define pDMA1_START_ADDR	(volatile void **)DMA2_0_START_ADDR
+#define pDMA1_X_COUNT		(volatile unsigned short *)DMA2_0_X_COUNT
+#define pDMA1_Y_COUNT		(volatile unsigned short *)DMA2_0_Y_COUNT
+#define pDMA1_X_MODIFY		(volatile unsigned short *)DMA2_0_X_MODIFY
+#define pDMA1_Y_MODIFY		(volatile unsigned short *)DMA2_0_Y_MODIFY
+#define pDMA1_CURR_DESC_PTR	(volatile void **)DMA2_0_CURR_DESC_PTR
+#define pDMA1_CURR_ADDR		(volatile void **)DMA2_0_CURR_ADDR
+#define pDMA1_CURR_X_COUNT	(volatile unsigned short *)DMA2_0_CURR_X_COUNT
+#define pDMA1_CURR_Y_COUNT	(volatile unsigned short *)DMA2_0_CURR_Y_COUNT
+#define pDMA1_IRQ_STATUS	(volatile unsigned short *)DMA2_0_IRQ_STATUS
+#define pDMA1_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
+#define pDMA2_CONFIG		(volatile unsigned short *)DMA2_1_CONFIG
+#define pDMA2_NEXT_DESC_PTR	(volatile void **)DMA2_1_NEXT_DESC_PTR
+#define pDMA2_START_ADDR	(volatile void **)DMA2_1_START_ADDR
+#define pDMA2_X_COUNT		(volatile unsigned short *)DMA2_1_X_COUNT
+#define pDMA2_Y_COUNT		(volatile unsigned short *)DMA2_1_Y_COUNT
+#define pDMA2_X_MODIFY		(volatile unsigned short *)DMA2_1_X_MODIFY
+#define pDMA2_Y_MODIFY		(volatile unsigned short *)DMA2_1_Y_MODIFY
+#define pDMA2_CURR_DESC_PTR	(volatile void **)DMA2_1_CURR_DESC_PTR
+#define pDMA2_CURR_ADDR		(volatile void **)DMA2_1_CURR_ADDR
+#define pDMA2_CURR_X_COUNT	(volatile unsigned short *)DMA2_1_CURR_X_COUNT
+#define pDMA2_CURR_Y_COUNT	(volatile unsigned short *)DMA2_1_CURR_Y_COUNT
+#define pDMA2_IRQ_STATUS	(volatile unsigned short *)DMA2_1_IRQ_STATUS
+#define pDMA2_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
+#define pDMA3_CONFIG		(volatile unsigned short *)DMA2_2_CONFIG
+#define pDMA3_NEXT_DESC_PTR	(volatile void **)DMA2_2_NEXT_DESC_PTR
+#define pDMA3_START_ADDR	(volatile void **)DMA2_2_START_ADDR
+#define pDMA3_X_COUNT		(volatile unsigned short *)DMA2_2_X_COUNT
+#define pDMA3_Y_COUNT		(volatile unsigned short *)DMA2_2_Y_COUNT
+#define pDMA3_X_MODIFY		(volatile unsigned short *)DMA2_2_X_MODIFY
+#define pDMA3_Y_MODIFY		(volatile unsigned short *)DMA2_2_Y_MODIFY
+#define pDMA3_CURR_DESC_PTR	(volatile void **)DMA2_2_CURR_DESC_PTR
+#define pDMA3_CURR_ADDR		(volatile void **)DMA2_2_CURR_ADDR
+#define pDMA3_CURR_X_COUNT	(volatile unsigned short *)DMA2_2_CURR_X_COUNT
+#define pDMA3_CURR_Y_COUNT	(volatile unsigned short *)DMA2_2_CURR_Y_COUNT
+#define pDMA3_IRQ_STATUS	(volatile unsigned short *)DMA2_2_IRQ_STATUS
+#define pDMA3_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
+#define pDMA4_CONFIG		(volatile unsigned short *)DMA2_3_CONFIG
+#define pDMA4_NEXT_DESC_PTR	(volatile void **)DMA2_3_NEXT_DESC_PTR
+#define pDMA4_START_ADDR	(volatile void **)DMA2_3_START_ADDR
+#define pDMA4_X_COUNT		(volatile unsigned short *)DMA2_3_X_COUNT
+#define pDMA4_Y_COUNT		(volatile unsigned short *)DMA2_3_Y_COUNT
+#define pDMA4_X_MODIFY		(volatile unsigned short *)DMA2_3_X_MODIFY
+#define pDMA4_Y_MODIFY		(volatile unsigned short *)DMA2_3_Y_MODIFY
+#define pDMA4_CURR_DESC_PTR	(volatile void **)DMA2_3_CURR_DESC_PTR
+#define pDMA4_CURR_ADDR		(volatile void **)DMA2_3_CURR_ADDR
+#define pDMA4_CURR_X_COUNT	(volatile unsigned short *)DMA2_3_CURR_X_COUNT
+#define pDMA4_CURR_Y_COUNT	(volatile unsigned short *)DMA2_3_CURR_Y_COUNT
+#define pDMA4_IRQ_STATUS	(volatile unsigned short *)DMA2_3_IRQ_STATUS
+#define pDMA4_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
+#define pDMA5_CONFIG		(volatile unsigned short *)DMA2_4_CONFIG
+#define pDMA5_NEXT_DESC_PTR	(volatile void **)DMA2_4_NEXT_DESC_PTR
+#define pDMA5_START_ADDR	(volatile void **)DMA2_4_START_ADDR
+#define pDMA5_X_COUNT		(volatile unsigned short *)DMA2_4_X_COUNT
+#define pDMA5_Y_COUNT		(volatile unsigned short *)DMA2_4_Y_COUNT
+#define pDMA5_X_MODIFY		(volatile unsigned short *)DMA2_4_X_MODIFY
+#define pDMA5_Y_MODIFY		(volatile unsigned short *)DMA2_4_Y_MODIFY
+#define pDMA5_CURR_DESC_PTR	(volatile void **)DMA2_4_CURR_DESC_PTR
+#define pDMA5_CURR_ADDR		(volatile void **)DMA2_4_CURR_ADDR
+#define pDMA5_CURR_X_COUNT	(volatile unsigned short *)DMA2_4_CURR_X_COUNT
+#define pDMA5_CURR_Y_COUNT	(volatile unsigned short *)DMA2_4_CURR_Y_COUNT
+#define pDMA5_IRQ_STATUS	(volatile unsigned short *)DMA2_4_IRQ_STATUS
+#define pDMA5_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
+#define pDMA6_CONFIG		(volatile unsigned short *)DMA2_5_CONFIG
+#define pDMA6_NEXT_DESC_PTR	(volatile void **)DMA2_5_NEXT_DESC_PTR
+#define pDMA6_START_ADDR	(volatile void **)DMA2_5_START_ADDR
+#define pDMA6_X_COUNT		(volatile unsigned short *)DMA2_5_X_COUNT
+#define pDMA6_Y_COUNT		(volatile unsigned short *)DMA2_5_Y_COUNT
+#define pDMA6_X_MODIFY		(volatile unsigned short *)DMA2_5_X_MODIFY
+#define pDMA6_Y_MODIFY		(volatile unsigned short *)DMA2_5_Y_MODIFY
+#define pDMA6_CURR_DESC_PTR	(volatile void **)DMA2_5_CURR_DESC_PTR
+#define pDMA6_CURR_ADDR		(volatile void **)DMA2_5_CURR_ADDR
+#define pDMA6_CURR_X_COUNT	(volatile unsigned short *)DMA2_5_CURR_X_COUNT
+#define pDMA6_CURR_Y_COUNT	(volatile unsigned short *)DMA2_5_CURR_Y_COUNT
+#define pDMA6_IRQ_STATUS	(volatile unsigned short *)DMA2_5_IRQ_STATUS
+#define pDMA6_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
+#define pDMA7_CONFIG		(volatile unsigned short *)DMA2_6_CONFIG
+#define pDMA7_NEXT_DESC_PTR	(volatile void **)DMA2_6_NEXT_DESC_PTR
+#define pDMA7_START_ADDR	(volatile void **)DMA2_6_START_ADDR
+#define pDMA7_X_COUNT		(volatile unsigned short *)DMA2_6_X_COUNT
+#define pDMA7_Y_COUNT		(volatile unsigned short *)DMA2_6_Y_COUNT
+#define pDMA7_X_MODIFY		(volatile unsigned short *)DMA2_6_X_MODIFY
+#define pDMA7_Y_MODIFY		(volatile unsigned short *)DMA2_6_Y_MODIFY
+#define pDMA7_CURR_DESC_PTR	(volatile void **)DMA2_6_CURR_DESC_PTR
+#define pDMA7_CURR_ADDR		(volatile void **)DMA2_6_CURR_ADDR
+#define pDMA7_CURR_X_COUNT	(volatile unsigned short *)DMA2_6_CURR_X_COUNT
+#define pDMA7_CURR_Y_COUNT	(volatile unsigned short *)DMA2_6_CURR_Y_COUNT
+#define pDMA7_IRQ_STATUS	(volatile unsigned short *)DMA2_6_IRQ_STATUS
+#define pDMA7_PERIPHERAL_MAP	(volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
+
+#endif				/* _CDEF_BF561_H */
diff --git a/include/asm-blackfin/arch-bf561/defBF561.h b/include/asm-blackfin/arch-bf561/defBF561.h
new file mode 100644
index 0000000..c6e3de5
--- /dev/null
+++ b/include/asm-blackfin/arch-bf561/defBF561.h
@@ -0,0 +1,1941 @@
+/*
+ * defBF561.h
+ *
+ * (c) Copyright 2001-2003 Analog Devices, Inc.  All rights reserved.
+ *
+ */
+
+/* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
+
+#ifndef _DEF_BF561_H
+#define _DEF_BF561_H
+
+/*
+ * #if !defined(__ADSPBF561__)
+ * #warning defBF561.h should only be included for BF561 chip.
+ * #endif
+ */
+
+/* include all Core registers and bit definitions */
+#include <asm/arch-common/def_LPBlackfin.h>
+
+/*
+ * Helper macros
+ * usage:
+ * P0.H = HI(UART_THR);
+ * P0.L = LO(UART_THR);
+ */
+
+#define LO(con32) ((con32) & 0xFFFF)
+#define lo(con32) ((con32) & 0xFFFF)
+#define HI(con32) (((con32) >> 16) & 0xFFFF)
+#define hi(con32) (((con32) >> 16) & 0xFFFF)
+
+/*
+ * System MMR Register Map
+ */
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL			0xFFC00000	/* PLL Control register */
+#define PLL_DIV			0xFFC00004	/* PLL Divide Register */
+#define VR_CTL			0xFFC00008	/* Voltage Regulator Control Register */
+#define PLL_STAT		0xFFC0000C	/* PLL Status register */
+#define PLL_LOCKCNT		0xFFC00010	/* PLL Lock Count register */
+
+/*
+ * System Reset and Interrupt Controller registers for
+ * core A (0xFFC0 0100-0xFFC0 01FF)
+ */
+#define SICA_SWRST		0xFFC00100	/* Software Reset register */
+#define SICA_SYSCR		0xFFC00104	/* System Reset Configuration register */
+#define SICA_RVECT		0xFFC00108	/* SIC Reset Vector Address Register */
+#define SICA_IMASK		0xFFC0010C	/* SIC Interrupt Mask register 0 */
+#define SICA_IMASK0		0xFFC0010C	/* SIC Interrupt Mask register 0 */
+#define SICA_IMASK1		0xFFC00110	/* SIC Interrupt Mask register 1 */
+#define SICA_IAR0		0xFFC00124	/* SIC Interrupt Assignment Register 0 */
+#define SICA_IAR1		0xFFC00128	/* SIC Interrupt Assignment Register 1 */
+#define SICA_IAR2		0xFFC0012C	/* SIC Interrupt Assignment Register 2 */
+#define SICA_IAR3		0xFFC00130	/* SIC Interrupt Assignment Register 3 */
+#define SICA_IAR4		0xFFC00134	/* SIC Interrupt Assignment Register 4 */
+#define SICA_IAR5		0xFFC00138	/* SIC Interrupt Assignment Register 5 */
+#define SICA_IAR6		0xFFC0013C	/* SIC Interrupt Assignment Register 6 */
+#define SICA_IAR7		0xFFC00140	/* SIC Interrupt Assignment Register 7 */
+#define SICA_ISR0		0xFFC00114	/* SIC Interrupt Status register 0 */
+#define SICA_ISR1		0xFFC00118	/* SIC Interrupt Status register 1 */
+#define SICA_IWR0		0xFFC0011C	/* SIC Interrupt Wakeup-Enable register 0 */
+#define SICA_IWR1		0xFFC00120	/* SIC Interrupt Wakeup-Enable register 1 */
+
+/*
+ * System Reset and Interrupt Controller registers for
+ * Core B (0xFFC0 1100-0xFFC0 11FF)
+ */
+#define SICB_SWRST		0xFFC01100	/* reserved */
+#define SICB_SYSCR		0xFFC01104	/* reserved */
+#define SICB_RVECT		0xFFC01108	/* SIC Reset Vector Address Register */
+#define SICB_IMASK0		0xFFC0110C	/* SIC Interrupt Mask register 0 */
+#define SICB_IMASK1		0xFFC01110	/* SIC Interrupt Mask register 1 */
+#define SICB_IAR0		0xFFC01124	/* SIC Interrupt Assignment Register 0 */
+#define SICB_IAR1		0xFFC01128	/* SIC Interrupt Assignment Register 1 */
+#define SICB_IAR2		0xFFC0112C	/* SIC Interrupt Assignment Register 2 */
+#define SICB_IAR3		0xFFC01130	/* SIC Interrupt Assignment Register 3 */
+#define SICB_IAR4		0xFFC01134	/* SIC Interrupt Assignment Register 4 */
+#define SICB_IAR5		0xFFC01138	/* SIC Interrupt Assignment Register 5 */
+#define SICB_IAR6		0xFFC0113C	/* SIC Interrupt Assignment Register 6 */
+#define SICB_IAR7		0xFFC01140	/* SIC Interrupt Assignment Register 7 */
+#define SICB_ISR0		0xFFC01114	/* SIC Interrupt Status register 0 */
+#define SICB_ISR1		0xFFC01118	/* SIC Interrupt Status register 1 */
+#define SICB_IWR0		0xFFC0111C	/* SIC Interrupt Wakeup-Enable register 0 */
+#define SICB_IWR1		0xFFC01120	/* SIC Interrupt Wakeup-Enable register 1 */
+
+/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
+#define WDOGA_CTL		0xFFC00200	/* Watchdog Control register */
+#define WDOGA_CNT		0xFFC00204	/* Watchdog Count register */
+#define WDOGA_STAT		0xFFC00208	/* Watchdog Status register */
+
+/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
+#define WDOGB_CTL		0xFFC01200	/* Watchdog Control register */
+#define WDOGB_CNT		0xFFC01204	/* Watchdog Count register */
+#define WDOGB_STAT		0xFFC01208	/* Watchdog Status register */
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART_THR		0xFFC00400	/* Transmit Holding register */
+#define UART_RBR		0xFFC00400	/* Receive Buffer register */
+#define UART_DLL		0xFFC00400	/* Divisor Latch (Low-Byte) */
+#define UART_IER		0xFFC00404	/* Interrupt Enable Register */
+#define UART_DLH		0xFFC00404	/* Divisor Latch (High-Byte) */
+#define UART_IIR		0xFFC00408	/* Interrupt Identification Register */
+#define UART_LCR		0xFFC0040C	/* Line Control Register */
+#define UART_MCR		0xFFC00410	/* Modem Control Register */
+#define UART_LSR		0xFFC00414	/* Line Status Register */
+#define UART_MSR		0xFFC00418	/* Modem Status Register */
+#define UART_SCR		0xFFC0041C	/* SCR Scratch Register */
+#define UART_GCTL		0xFFC00424	/* Global Control Register */
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL			0xFFC00500	/* SPI Control Register */
+#define SPI_FLG			0xFFC00504	/* SPI Flag register */
+#define SPI_STAT		0xFFC00508	/* SPI Status register */
+#define SPI_TDBR		0xFFC0050C	/* SPI Transmit Data Buffer Register */
+#define SPI_RDBR		0xFFC00510	/* SPI Receive Data Buffer Register */
+#define SPI_BAUD		0xFFC00514	/* SPI Baud rate Register */
+#define SPI_SHADOW		0xFFC00518	/* SPI_RDBR Shadow Register */
+
+/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
+#define TIMER0_CONFIG		0xFFC00600	/* Timer0 Configuration register */
+#define TIMER0_COUNTER		0xFFC00604	/* Timer0 Counter register */
+#define TIMER0_PERIOD		0xFFC00608	/* Timer0 Period register */
+#define TIMER0_WIDTH		0xFFC0060C	/* Timer0 Width register */
+#define TIMER1_CONFIG		0xFFC00610	/* Timer1 Configuration register */
+#define TIMER1_COUNTER		0xFFC00614	/* Timer1 Counter register */
+#define TIMER1_PERIOD		0xFFC00618	/* Timer1 Period register */
+#define TIMER1_WIDTH		0xFFC0061C	/* Timer1 Width register */
+#define TIMER2_CONFIG		0xFFC00620	/* Timer2 Configuration register */
+#define TIMER2_COUNTER		0xFFC00624	/* Timer2 Counter register */
+#define TIMER2_PERIOD		0xFFC00628	/* Timer2 Period register */
+#define TIMER2_WIDTH		0xFFC0062C	/* Timer2 Width register */
+#define TIMER3_CONFIG		0xFFC00630	/* Timer3 Configuration register */
+#define TIMER3_COUNTER		0xFFC00634	/* Timer3 Counter register */
+#define TIMER3_PERIOD		0xFFC00638	/* Timer3 Period register */
+#define TIMER3_WIDTH		0xFFC0063C	/* Timer3 Width register */
+#define TIMER4_CONFIG		0xFFC00640	/* Timer4 Configuration register */
+#define TIMER4_COUNTER		0xFFC00644	/* Timer4 Counter register */
+#define TIMER4_PERIOD		0xFFC00648	/* Timer4 Period register */
+#define TIMER4_WIDTH		0xFFC0064C	/* Timer4 Width register */
+#define TIMER5_CONFIG		0xFFC00650	/* Timer5 Configuration register */
+#define TIMER5_COUNTER		0xFFC00654	/* Timer5 Counter register */
+#define TIMER5_PERIOD		0xFFC00658	/* Timer5 Period register */
+#define TIMER5_WIDTH		0xFFC0065C	/* Timer5 Width register */
+#define TIMER6_CONFIG		0xFFC00660	/* Timer6 Configuration register */
+#define TIMER6_COUNTER		0xFFC00664	/* Timer6 Counter register */
+#define TIMER6_PERIOD		0xFFC00668	/* Timer6 Period register */
+#define TIMER6_WIDTH		0xFFC0066C	/* Timer6 Width register */
+#define TIMER7_CONFIG		0xFFC00670	/* Timer7 Configuration register */
+#define TIMER7_COUNTER		0xFFC00674	/* Timer7 Counter register */
+#define TIMER7_PERIOD		0xFFC00678	/* Timer7 Period register */
+#define TIMER7_WIDTH		0xFFC0067C	/* Timer7 Width register */
+#define TMRS8_ENABLE		0xFFC00680	/* Timer Enable Register */
+#define TMRS8_DISABLE		0xFFC00684	/* Timer Disable register */
+#define TMRS8_STATUS		0xFFC00688	/* Timer Status register */
+
+/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
+#define TIMER8_CONFIG		0xFFC01600	/* Timer8 Configuration register */
+#define TIMER8_COUNTER		0xFFC01604	/* Timer8 Counter register */
+#define TIMER8_PERIOD		0xFFC01608	/* Timer8 Period register */
+#define TIMER8_WIDTH		0xFFC0160C	/* Timer8 Width register */
+#define TIMER9_CONFIG		0xFFC01610	/* Timer9 Configuration register */
+#define TIMER9_COUNTER		0xFFC01614	/* Timer9 Counter register */
+#define TIMER9_PERIOD		0xFFC01618	/* Timer9 Period register */
+#define TIMER9_WIDTH		0xFFC0161C	/* Timer9 Width register */
+#define TIMER10_CONFIG		0xFFC01620	/* Timer10 Configuration register */
+#define TIMER10_COUNTER		0xFFC01624	/* Timer10 Counter register */
+#define TIMER10_PERIOD		0xFFC01628	/* Timer10 Period register */
+#define TIMER10_WIDTH		0xFFC0162C	/* Timer10 Width register */
+#define TIMER11_CONFIG		0xFFC01630	/* Timer11 Configuration register */
+#define TIMER11_COUNTER		0xFFC01634	/* Timer11 Counter register */
+#define TIMER11_PERIOD		0xFFC01638	/* Timer11 Period register */
+#define TIMER11_WIDTH		0xFFC0163C	/* Timer11 Width register */
+#define TMRS4_ENABLE		0xFFC01640	/* Timer Enable Register */
+#define TMRS4_DISABLE		0xFFC01644	/* Timer Disable register */
+#define TMRS4_STATUS		0xFFC01648	/* Timer Status register */
+
+/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
+#define FIO0_FLAG_D		0xFFC00700	/* Flag Data register */
+#define FIO0_FLAG_C		0xFFC00704	/* Flag Clear register */
+#define FIO0_FLAG_S		0xFFC00708	/* Flag Set register */
+#define FIO0_FLAG_T		0xFFC0070C	/* Flag Toggle register */
+#define FIO0_MASKA_D		0xFFC00710	/* Flag Mask Interrupt A Data register */
+#define FIO0_MASKA_C		0xFFC00714	/* Flag Mask Interrupt A Clear register */
+#define FIO0_MASKA_S		0xFFC00718	/* Flag Mask Interrupt A Set register */
+#define FIO0_MASKA_T		0xFFC0071C	/* Flag Mask Interrupt A Toggle register */
+#define FIO0_MASKB_D		0xFFC00720	/* Flag Mask Interrupt B Data register */
+#define FIO0_MASKB_C		0xFFC00724	/* Flag Mask Interrupt B Clear register */
+#define FIO0_MASKB_S		0xFFC00728	/* Flag Mask Interrupt B Set register */
+#define FIO0_MASKB_T		0xFFC0072C	/* Flag Mask Interrupt B Toggle register */
+#define FIO0_DIR		0xFFC00730	/* Flag Direction  register */
+#define FIO0_POLAR		0xFFC00734	/* Flag Polarity register */
+#define FIO0_EDGE		0xFFC00738	/* Flag Interrupt Sensitivity register */
+#define FIO0_BOTH		0xFFC0073C	/* Flag Set on Both Edges register */
+#define FIO0_INEN		0xFFC00740	/* Flag Input Enable register */
+
+/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
+#define FIO1_FLAG_D		0xFFC01500	/* Flag Data register */
+#define FIO1_FLAG_C		0xFFC01504	/* Flag Clear register */
+#define FIO1_FLAG_S		0xFFC01508	/* Flag Set register */
+#define FIO1_FLAG_T		0xFFC0150C	/* Flag Toggle register */
+#define FIO1_MASKA_D		0xFFC01510	/* Flag Mask Interrupt A Data register */
+#define FIO1_MASKA_C		0xFFC01514	/* Flag Mask Interrupt A Clear register */
+#define FIO1_MASKA_S		0xFFC01518	/* Flag Mask Interrupt A Set register */
+#define FIO1_MASKA_T		0xFFC0151C	/* Flag Mask Interrupt A Toggle register */
+#define FIO1_MASKB_D		0xFFC01520	/* Flag Mask Interrupt B Data register */
+#define FIO1_MASKB_C		0xFFC01524	/* Flag Mask Interrupt B Clear register */
+#define FIO1_MASKB_S		0xFFC01528	/* Flag Mask Interrupt B Set register */
+#define FIO1_MASKB_T		0xFFC0152C	/* Flag Mask Interrupt B Toggle register */
+#define FIO1_DIR		0xFFC01530	/* Flag Direction register */
+#define FIO1_POLAR		0xFFC01534	/* Flag Polarity register */
+#define FIO1_EDGE		0xFFC01538	/* Flag  Interrupt Sensitivity register */
+#define FIO1_BOTH		0xFFC0153C	/* Flag Set on Both Edges register */
+#define FIO1_INEN		0xFFC01540	/* Flag Input Enable register */
+
+/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
+#define FIO2_FLAG_D		0xFFC01700	/* Flag Data register */
+#define FIO2_FLAG_C		0xFFC01704	/* Flag Clear register */
+#define FIO2_FLAG_S		0xFFC01708	/* Flag Set register */
+#define FIO2_FLAG_T		0xFFC0170C	/* Flag Toggle register */
+#define FIO2_MASKA_D		0xFFC01710	/* Flag Mask Interrupt A Data register */
+#define FIO2_MASKA_C		0xFFC01714	/* Flag Mask Interrupt A Clear register */
+#define FIO2_MASKA_S		0xFFC01718	/* Flag Mask Interrupt A Set register */
+#define FIO2_MASKA_T		0xFFC0171C	/* Flag Mask Interrupt A Toggle register */
+#define FIO2_MASKB_D		0xFFC01720	/* Flag Mask Interrupt B Data register */
+#define FIO2_MASKB_C		0xFFC01724	/* Flag Mask Interrupt B Clear register */
+#define FIO2_MASKB_S		0xFFC01728	/* Flag Mask Interrupt B Set register */
+#define FIO2_MASKB_T		0xFFC0172C	/* Flag Mask Interrupt B Toggle register */
+#define FIO2_DIR		0xFFC01730	/* Flag Direction register */
+#define FIO2_POLAR		0xFFC01734	/* Flag Polarity register */
+#define FIO2_EDGE		0xFFC01738	/* Flag Interrupt Sensitivity register */
+#define FIO2_BOTH		0xFFC0173C	/* Flag Set on Both Edges register */
+#define FIO2_INEN		0xFFC01740	/* Flag Input Enable register */
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1		0xFFC00800	/* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2		0xFFC00804	/* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX		0xFFC00810	/* SPORT0 TX Data Register */
+#define SPORT0_RX		0xFFC00818	/* SPORT0 RX Data Register */
+#define SPORT0_RCR1		0xFFC00820	/* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2		0xFFC00824	/* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT		0xFFC00830	/* SPORT0 Status Register */
+#define SPORT0_CHNL		0xFFC00834	/* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3 */
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1		0xFFC00900	/* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2		0xFFC00904	/* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX		0xFFC00910	/* SPORT1 TX Data Register */
+#define SPORT1_RX		0xFFC00918	/* SPORT1 RX Data Register */
+#define SPORT1_RCR1		0xFFC00920	/* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2		0xFFC00924	/* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT		0xFFC00930	/* SPORT1 Status Register */
+#define SPORT1_CHNL		0xFFC00934	/* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3 */
+
+/* Asynchronous Memory Controller - External Bus Interface Unit */
+#define EBIU_AMGCTL		0xFFC00A00	/* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_SDGCTL		0xFFC00A10	/* SDRAM Global Control Register */
+#define EBIU_SDBCTL		0xFFC00A14	/* SDRAM Bank Control Register */
+#define EBIU_SDRRC		0xFFC00A18	/* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT		0xFFC00A1C	/* SDRAM Status Register */
+
+/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
+#define PPI0_CONTROL		0xFFC01000	/* PPI0 Control register */
+#define PPI0_STATUS		0xFFC01004	/* PPI0 Status register */
+#define PPI0_COUNT		0xFFC01008	/* PPI0 Transfer Count register */
+#define PPI0_DELAY		0xFFC0100C	/* PPI0 Delay Count register */
+#define PPI0_FRAME		0xFFC01010	/* PPI0 Frame Length register */
+
+/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
+#define PPI1_CONTROL		0xFFC01300	/* PPI1 Control register */
+#define PPI1_STATUS		0xFFC01304	/* PPI1 Status register */
+#define PPI1_COUNT		0xFFC01308	/* PPI1 Transfer Count register */
+#define PPI1_DELAY		0xFFC0130C	/* PPI1 Delay Count register */
+#define PPI1_FRAME		0xFFC01310	/* PPI1 Frame Length register */
+
+/* DMA Traffic controls */
+#define DMA_TCPER		0xFFC00B0C	/* Traffic Control Periods Register */
+#define DMA_TCCNT		0xFFC00B10	/* Traffic Control Current Counts Register */
+#define DMA_TC_PER		0xFFC00B0C	/* Traffic Control Periods Register */
+#define DMA_TC_CNT		0xFFC00B10	/* Traffic Control Current Counts Register */
+
+/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
+#define DMA1_0_CONFIG		0xFFC01C08	/* DMA1 Channel 0 Configuration register */
+#define DMA1_0_NEXT_DESC_PTR	0xFFC01C00	/* DMA1 Channel 0 Next Descripter Ptr Reg */
+#define DMA1_0_START_ADDR	0xFFC01C04	/* DMA1 Channel 0 Start Address */
+#define DMA1_0_X_COUNT		0xFFC01C10	/* DMA1 Channel 0 Inner Loop Count */
+#define DMA1_0_Y_COUNT		0xFFC01C18	/* DMA1 Channel 0 Outer Loop Count */
+#define DMA1_0_X_MODIFY		0xFFC01C14	/* DMA1 Channel 0 Inner Loop Addr Increment */
+#define DMA1_0_Y_MODIFY		0xFFC01C1C	/* DMA1 Channel 0 Outer Loop Addr Increment */
+#define DMA1_0_CURR_DESC_PTR	0xFFC01C20	/* DMA1 Channel 0 Current Descriptor Pointer */
+#define DMA1_0_CURR_ADDR	0xFFC01C24	/* DMA1 Channel 0 Current Address Pointer */
+#define DMA1_0_CURR_X_COUNT	0xFFC01C30	/* DMA1 Channel 0 Current Inner Loop Count */
+#define DMA1_0_CURR_Y_COUNT	0xFFC01C38	/* DMA1 Channel 0 Current Outer Loop Count */
+#define DMA1_0_IRQ_STATUS	0xFFC01C28	/* DMA1 Channel 0 Interrupt Status Register */
+#define DMA1_0_PERIPHERAL_MAP	0xFFC01C2C	/* DMA1 Channel 0 Peripheral Map Register */
+
+#define DMA1_1_CONFIG		0xFFC01C48	/* DMA1 Channel 1 Configuration register */
+#define DMA1_1_NEXT_DESC_PTR	0xFFC01C40	/* DMA1 Channel 1 Next Descripter Ptr Reg */
+#define DMA1_1_START_ADDR	0xFFC01C44	/* DMA1 Channel 1 Start Address */
+#define DMA1_1_X_COUNT		0xFFC01C50	/* DMA1 Channel 1 Inner Loop Count */
+#define DMA1_1_Y_COUNT		0xFFC01C58	/* DMA1 Channel 1 Outer Loop Count */
+#define DMA1_1_X_MODIFY		0xFFC01C54	/* DMA1 Channel 1 Inner Loop Addr Increment */
+#define DMA1_1_Y_MODIFY		0xFFC01C5C	/* DMA1 Channel 1 Outer Loop Addr Increment */
+#define DMA1_1_CURR_DESC_PTR	0xFFC01C60	/* DMA1 Channel 1 Current Descriptor Pointer */
+#define DMA1_1_CURR_ADDR	0xFFC01C64	/* DMA1 Channel 1 Current Address Pointer */
+#define DMA1_1_CURR_X_COUNT	0xFFC01C70	/* DMA1 Channel 1 Current Inner Loop Count */
+#define DMA1_1_CURR_Y_COUNT	0xFFC01C78	/* DMA1 Channel 1 Current Outer Loop Count */
+#define DMA1_1_IRQ_STATUS	0xFFC01C68	/* DMA1 Channel 1 Interrupt Status Register */
+#define DMA1_1_PERIPHERAL_MAP	0xFFC01C6C	/* DMA1 Channel 1 Peripheral Map Register */
+
+#define DMA1_2_CONFIG		0xFFC01C88	/* DMA1 Channel 2 Configuration register */
+#define DMA1_2_NEXT_DESC_PTR	0xFFC01C80	/* DMA1 Channel 2 Next Descripter Ptr Reg */
+#define DMA1_2_START_ADDR	0xFFC01C84	/* DMA1 Channel 2 Start Address */
+#define DMA1_2_X_COUNT		0xFFC01C90	/* DMA1 Channel 2 Inner Loop Count */
+#define DMA1_2_Y_COUNT		0xFFC01C98	/* DMA1 Channel 2 Outer Loop Count */
+#define DMA1_2_X_MODIFY		0xFFC01C94	/* DMA1 Channel 2 Inner Loop Addr Increment */
+#define DMA1_2_Y_MODIFY		0xFFC01C9C	/* DMA1 Channel 2 Outer Loop Addr Increment */
+#define DMA1_2_CURR_DESC_PTR	0xFFC01CA0	/* DMA1 Channel 2 Current Descriptor Pointer */
+#define DMA1_2_CURR_ADDR	0xFFC01CA4	/* DMA1 Channel 2 Current Address Pointer */
+#define DMA1_2_CURR_X_COUNT	0xFFC01CB0	/* DMA1 Channel 2 Current Inner Loop Count */
+#define DMA1_2_CURR_Y_COUNT	0xFFC01CB8	/* DMA1 Channel 2 Current Outer Loop Count */
+#define DMA1_2_IRQ_STATUS	0xFFC01CA8	/* DMA1 Channel 2 Interrupt Status Register */
+#define DMA1_2_PERIPHERAL_MAP	0xFFC01CAC	/* DMA1 Channel 2 Peripheral Map Register */
+
+#define DMA1_3_CONFIG		0xFFC01CC8	/* DMA1 Channel 3 Configuration register */
+#define DMA1_3_NEXT_DESC_PTR	0xFFC01CC0	/* DMA1 Channel 3 Next Descripter Ptr Reg */
+#define DMA1_3_START_ADDR	0xFFC01CC4	/* DMA1 Channel 3 Start Address */
+#define DMA1_3_X_COUNT		0xFFC01CD0	/* DMA1 Channel 3 Inner Loop Count */
+#define DMA1_3_Y_COUNT		0xFFC01CD8	/* DMA1 Channel 3 Outer Loop Count */
+#define DMA1_3_X_MODIFY		0xFFC01CD4	/* DMA1 Channel 3 Inner Loop Addr Increment */
+#define DMA1_3_Y_MODIFY		0xFFC01CDC	/* DMA1 Channel 3 Outer Loop Addr Increment */
+#define DMA1_3_CURR_DESC_PTR	0xFFC01CE0	/* DMA1 Channel 3 Current Descriptor Pointer */
+#define DMA1_3_CURR_ADDR	0xFFC01CE4	/* DMA1 Channel 3 Current Address Pointer */
+#define DMA1_3_CURR_X_COUNT	0xFFC01CF0	/* DMA1 Channel 3 Current Inner Loop Count */
+#define DMA1_3_CURR_Y_COUNT	0xFFC01CF8	/* DMA1 Channel 3 Current Outer Loop Count */
+#define DMA1_3_IRQ_STATUS	0xFFC01CE8	/* DMA1 Channel 3 Interrupt Status Register */
+#define DMA1_3_PERIPHERAL_MAP	0xFFC01CEC	/* DMA1 Channel 3 Peripheral Map Register */
+
+#define DMA1_4_CONFIG		0xFFC01D08	/* DMA1 Channel 4 Configuration register */
+#define DMA1_4_NEXT_DESC_PTR	0xFFC01D00	/* DMA1 Channel 4 Next Descripter Ptr Reg */
+#define DMA1_4_START_ADDR	0xFFC01D04	/* DMA1 Channel 4 Start Address */
+#define DMA1_4_X_COUNT		0xFFC01D10	/* DMA1 Channel 4 Inner Loop Count */
+#define DMA1_4_Y_COUNT		0xFFC01D18	/* DMA1 Channel 4 Outer Loop Count */
+#define DMA1_4_X_MODIFY		0xFFC01D14	/* DMA1 Channel 4 Inner Loop Addr Increment */
+#define DMA1_4_Y_MODIFY		0xFFC01D1C	/* DMA1 Channel 4 Outer Loop Addr Increment */
+#define DMA1_4_CURR_DESC_PTR	0xFFC01D20	/* DMA1 Channel 4 Current Descriptor Pointer */
+#define DMA1_4_CURR_ADDR	0xFFC01D24	/* DMA1 Channel 4 Current Address Pointer */
+#define DMA1_4_CURR_X_COUNT	0xFFC01D30	/* DMA1 Channel 4 Current Inner Loop Count */
+#define DMA1_4_CURR_Y_COUNT	0xFFC01D38	/* DMA1 Channel 4 Current Outer Loop Count */
+#define DMA1_4_IRQ_STATUS	0xFFC01D28	/* DMA1 Channel 4 Interrupt Status Register */
+#define DMA1_4_PERIPHERAL_MAP	0xFFC01D2C	/* DMA1 Channel 4 Peripheral Map Register */
+
+#define DMA1_5_CONFIG		0xFFC01D48	/* DMA1 Channel 5 Configuration register */
+#define DMA1_5_NEXT_DESC_PTR	0xFFC01D40	/* DMA1 Channel 5 Next Descripter Ptr Reg */
+#define DMA1_5_START_ADDR	0xFFC01D44	/* DMA1 Channel 5 Start Address */
+#define DMA1_5_X_COUNT		0xFFC01D50	/* DMA1 Channel 5 Inner Loop Count */
+#define DMA1_5_Y_COUNT		0xFFC01D58	/* DMA1 Channel 5 Outer Loop Count */
+#define DMA1_5_X_MODIFY		0xFFC01D54	/* DMA1 Channel 5 Inner Loop Addr Increment */
+#define DMA1_5_Y_MODIFY		0xFFC01D5C	/* DMA1 Channel 5 Outer Loop Addr Increment */
+#define DMA1_5_CURR_DESC_PTR	0xFFC01D60	/* DMA1 Channel 5 Current Descriptor Pointer */
+#define DMA1_5_CURR_ADDR	0xFFC01D64	/* DMA1 Channel 5 Current Address Pointer */
+#define DMA1_5_CURR_X_COUNT	0xFFC01D70	/* DMA1 Channel 5 Current Inner Loop Count */
+#define DMA1_5_CURR_Y_COUNT	0xFFC01D78	/* DMA1 Channel 5 Current Outer Loop Count */
+#define DMA1_5_IRQ_STATUS	0xFFC01D68	/* DMA1 Channel 5 Interrupt Status Register */
+#define DMA1_5_PERIPHERAL_MAP	0xFFC01D6C	/* DMA1 Channel 5 Peripheral Map Register */
+
+#define DMA1_6_CONFIG		0xFFC01D88	/* DMA1 Channel 6 Configuration register */
+#define DMA1_6_NEXT_DESC_PTR	0xFFC01D80	/* DMA1 Channel 6 Next Descripter Ptr Reg */
+#define DMA1_6_START_ADDR	0xFFC01D84	/* DMA1 Channel 6 Start Address */
+#define DMA1_6_X_COUNT		0xFFC01D90	/* DMA1 Channel 6 Inner Loop Count */
+#define DMA1_6_Y_COUNT		0xFFC01D98	/* DMA1 Channel 6 Outer Loop Count */
+#define DMA1_6_X_MODIFY		0xFFC01D94	/* DMA1 Channel 6 Inner Loop Addr Increment */
+#define DMA1_6_Y_MODIFY		0xFFC01D9C	/* DMA1 Channel 6 Outer Loop Addr Increment */
+#define DMA1_6_CURR_DESC_PTR	0xFFC01DA0	/* DMA1 Channel 6 Current Descriptor Pointer */
+#define DMA1_6_CURR_ADDR	0xFFC01DA4	/* DMA1 Channel 6 Current Address Pointer */
+#define DMA1_6_CURR_X_COUNT	0xFFC01DB0	/* DMA1 Channel 6 Current Inner Loop Count */
+#define DMA1_6_CURR_Y_COUNT	0xFFC01DB8	/* DMA1 Channel 6 Current Outer Loop Count */
+#define DMA1_6_IRQ_STATUS	0xFFC01DA8	/* DMA1 Channel 6 Interrupt Status Register */
+#define DMA1_6_PERIPHERAL_MAP	0xFFC01DAC	/* DMA1 Channel 6 Peripheral Map Register */
+
+#define DMA1_7_CONFIG		0xFFC01DC8	/* DMA1 Channel 7 Configuration register */
+#define DMA1_7_NEXT_DESC_PTR	0xFFC01DC0	/* DMA1 Channel 7 Next Descripter Ptr Reg */
+#define DMA1_7_START_ADDR	0xFFC01DC4	/* DMA1 Channel 7 Start Address */
+#define DMA1_7_X_COUNT		0xFFC01DD0	/* DMA1 Channel 7 Inner Loop Count */
+#define DMA1_7_Y_COUNT		0xFFC01DD8	/* DMA1 Channel 7 Outer Loop Count */
+#define DMA1_7_X_MODIFY		0xFFC01DD4	/* DMA1 Channel 7 Inner Loop Addr Increment */
+#define DMA1_7_Y_MODIFY		0xFFC01DDC	/* DMA1 Channel 7 Outer Loop Addr Increment */
+#define DMA1_7_CURR_DESC_PTR	0xFFC01DE0	/* DMA1 Channel 7 Current Descriptor Pointer */
+#define DMA1_7_CURR_ADDR	0xFFC01DE4	/* DMA1 Channel 7 Current Address Pointer */
+#define DMA1_7_CURR_X_COUNT	0xFFC01DF0	/* DMA1 Channel 7 Current Inner Loop Count */
+#define DMA1_7_CURR_Y_COUNT	0xFFC01DF8	/* DMA1 Channel 7 Current Outer Loop Count */
+#define DMA1_7_IRQ_STATUS	0xFFC01DE8	/* DMA1 Channel 7 Interrupt Status Register */
+#define DMA1_7_PERIPHERAL_MAP	0xFFC01DEC	/* DMA1 Channel 7 Peripheral Map Register */
+
+#define DMA1_8_CONFIG		0xFFC01E08	/* DMA1 Channel 8 Configuration register */
+#define DMA1_8_NEXT_DESC_PTR	0xFFC01E00	/* DMA1 Channel 8 Next Descripter Ptr Reg */
+#define DMA1_8_START_ADDR	0xFFC01E04	/* DMA1 Channel 8 Start Address */
+#define DMA1_8_X_COUNT		0xFFC01E10	/* DMA1 Channel 8 Inner Loop Count */
+#define DMA1_8_Y_COUNT		0xFFC01E18	/* DMA1 Channel 8 Outer Loop Count */
+#define DMA1_8_X_MODIFY		0xFFC01E14	/* DMA1 Channel 8 Inner Loop Addr Increment */
+#define DMA1_8_Y_MODIFY		0xFFC01E1C	/* DMA1 Channel 8 Outer Loop Addr Increment */
+#define DMA1_8_CURR_DESC_PTR	0xFFC01E20	/* DMA1 Channel 8 Current Descriptor Pointer */
+#define DMA1_8_CURR_ADDR	0xFFC01E24	/* DMA1 Channel 8 Current Address Pointer */
+#define DMA1_8_CURR_X_COUNT	0xFFC01E30	/* DMA1 Channel 8 Current Inner Loop Count */
+#define DMA1_8_CURR_Y_COUNT	0xFFC01E38	/* DMA1 Channel 8 Current Outer Loop Count */
+#define DMA1_8_IRQ_STATUS	0xFFC01E28	/* DMA1 Channel 8 Interrupt Status Register */
+#define DMA1_8_PERIPHERAL_MAP	0xFFC01E2C	/* DMA1 Channel 8 Peripheral Map Register */
+
+#define DMA1_9_CONFIG		0xFFC01E48	/* DMA1 Channel 9 Configuration register */
+#define DMA1_9_NEXT_DESC_PTR	0xFFC01E40	/* DMA1 Channel 9 Next Descripter Ptr Reg */
+#define DMA1_9_START_ADDR	0xFFC01E44	/* DMA1 Channel 9 Start Address */
+#define DMA1_9_X_COUNT		0xFFC01E50	/* DMA1 Channel 9 Inner Loop Count */
+#define DMA1_9_Y_COUNT		0xFFC01E58	/* DMA1 Channel 9 Outer Loop Count */
+#define DMA1_9_X_MODIFY		0xFFC01E54	/* DMA1 Channel 9 Inner Loop Addr Increment */
+#define DMA1_9_Y_MODIFY		0xFFC01E5C	/* DMA1 Channel 9 Outer Loop Addr Increment */
+#define DMA1_9_CURR_DESC_PTR	0xFFC01E60	/* DMA1 Channel 9 Current Descriptor Pointer */
+#define DMA1_9_CURR_ADDR	0xFFC01E64	/* DMA1 Channel 9 Current Address Pointer */
+#define DMA1_9_CURR_X_COUNT	0xFFC01E70	/* DMA1 Channel 9 Current Inner Loop Count */
+#define DMA1_9_CURR_Y_COUNT	0xFFC01E78	/* DMA1 Channel 9 Current Outer Loop Count */
+#define DMA1_9_IRQ_STATUS	0xFFC01E68	/* DMA1 Channel 9 Interrupt Status Register */
+#define DMA1_9_PERIPHERAL_MAP	0xFFC01E6C	/* DMA1 Channel 9 Peripheral Map Register */
+
+#define DMA1_10_CONFIG		0xFFC01E88	/* DMA1 Channel 10 Configuration register */
+#define DMA1_10_NEXT_DESC_PTR	0xFFC01E80	/* DMA1 Channel 10 Next Descripter Ptr Reg */
+#define DMA1_10_START_ADDR	0xFFC01E84	/* DMA1 Channel 10 Start Address */
+#define DMA1_10_X_COUNT		0xFFC01E90	/* DMA1 Channel 10 Inner Loop Count */
+#define DMA1_10_Y_COUNT		0xFFC01E98	/* DMA1 Channel 10 Outer Loop Count */
+#define DMA1_10_X_MODIFY	0xFFC01E94	/* DMA1 Channel 10 Inner Loop Addr Increment */
+#define DMA1_10_Y_MODIFY	0xFFC01E9C	/* DMA1 Channel 10 Outer Loop Addr Increment */
+#define DMA1_10_CURR_DESC_PTR	0xFFC01EA0	/* DMA1 Channel 10 Current Descriptor Pointer */
+#define DMA1_10_CURR_ADDR	0xFFC01EA4	/* DMA1 Channel 10 Current Address Pointer */
+#define DMA1_10_CURR_X_COUNT	0xFFC01EB0	/* DMA1 Channel 10 Current Inner Loop Count */
+#define DMA1_10_CURR_Y_COUNT	0xFFC01EB8	/* DMA1 Channel 10 Current Outer Loop Count */
+#define DMA1_10_IRQ_STATUS	0xFFC01EA8	/* DMA1 Channel 10 Interrupt Status Register */
+#define DMA1_10_PERIPHERAL_MAP	0xFFC01EAC	/* DMA1 Channel 10 Peripheral Map Register */
+
+#define DMA1_11_CONFIG		0xFFC01EC8	/* DMA1 Channel 11 Configuration register */
+#define DMA1_11_NEXT_DESC_PTR	0xFFC01EC0	/* DMA1 Channel 11 Next Descripter Ptr Reg */
+#define DMA1_11_START_ADDR	0xFFC01EC4	/* DMA1 Channel 11 Start Address */
+#define DMA1_11_X_COUNT		0xFFC01ED0	/* DMA1 Channel 11 Inner Loop Count */
+#define DMA1_11_Y_COUNT		0xFFC01ED8	/* DMA1 Channel 11 Outer Loop Count */
+#define DMA1_11_X_MODIFY	0xFFC01ED4	/* DMA1 Channel 11 Inner Loop Addr Increment */
+#define DMA1_11_Y_MODIFY	0xFFC01EDC	/* DMA1 Channel 11 Outer Loop Addr Increment */
+#define DMA1_11_CURR_DESC_PTR	0xFFC01EE0	/* DMA1 Channel 11 Current Descriptor Pointer */
+#define DMA1_11_CURR_ADDR	0xFFC01EE4	/* DMA1 Channel 11 Current Address Pointer */
+#define DMA1_11_CURR_X_COUNT	0xFFC01EF0	/* DMA1 Channel 11 Current Inner Loop Count */
+#define DMA1_11_CURR_Y_COUNT	0xFFC01EF8	/* DMA1 Channel 11 Current Outer Loop Count */
+#define DMA1_11_IRQ_STATUS	0xFFC01EE8	/* DMA1 Channel 11 Interrupt Status Register */
+#define DMA1_11_PERIPHERAL_MAP	0xFFC01EEC	/* DMA1 Channel 11 Peripheral Map Register */
+
+/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
+#define MDMA1_D0_CONFIG		0xFFC01F08	/* MemDMA1 Stream 0 Destination Configuration */
+#define MDMA1_D0_NEXT_DESC_PTR	0xFFC01F00	/* MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA1_D0_START_ADDR	0xFFC01F04	/* MemDMA1 Stream 0 Destination Start Address */
+#define MDMA1_D0_X_COUNT	0xFFC01F10	/* MemDMA1 Stream 0 Destination Inner-Loop Count */
+#define MDMA1_D0_Y_COUNT	0xFFC01F18	/* MemDMA1 Stream 0 Destination Outer-Loop Count */
+#define MDMA1_D0_X_MODIFY	0xFFC01F14	/* MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA1_D0_Y_MODIFY	0xFFC01F1C	/* MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA1_D0_CURR_DESC_PTR	0xFFC01F20	/* MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA1_D0_CURR_ADDR	0xFFC01F24	/* MemDMA1 Stream 0 Destination Current Address */
+#define MDMA1_D0_CURR_X_COUNT	0xFFC01F30	/* MemDMA1 Stream 0 Dest Current Inner-Loop Count */
+#define MDMA1_D0_CURR_Y_COUNT	0xFFC01F38	/* MemDMA1 Stream 0 Dest Current Outer-Loop Count */
+#define MDMA1_D0_IRQ_STATUS	0xFFC01F28	/* MemDMA1 Stream 0 Destination Interrupt/Status */
+#define MDMA1_D0_PERIPHERAL_MAP	0xFFC01F2C	/* MemDMA1 Stream 0 Destination Peripheral Map */
+
+#define MDMA1_S0_CONFIG		0xFFC01F48	/* MemDMA1 Stream 0 Source Configuration */
+#define MDMA1_S0_NEXT_DESC_PTR	0xFFC01F40	/* MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA1_S0_START_ADDR	0xFFC01F44	/* MemDMA1 Stream 0 Source Start Address */
+#define MDMA1_S0_X_COUNT	0xFFC01F50	/* MemDMA1 Stream 0 Source Inner-Loop Count */
+#define MDMA1_S0_Y_COUNT	0xFFC01F58	/* MemDMA1 Stream 0 Source Outer-Loop Count */
+#define MDMA1_S0_X_MODIFY	0xFFC01F54	/* MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
+#define MDMA1_S0_Y_MODIFY	0xFFC01F5C	/* MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
+#define MDMA1_S0_CURR_DESC_PTR	0xFFC01F60	/* MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA1_S0_CURR_ADDR	0xFFC01F64	/* MemDMA1 Stream 0 Source Current Address */
+#define MDMA1_S0_CURR_X_COUNT	0xFFC01F70	/* MemDMA1 Stream 0 Source Current Inner-Loop Count */
+#define MDMA1_S0_CURR_Y_COUNT `	0xFFC01F78	/* MemDMA1 Stream 0 Source Current Outer-Loop Count */
+#define MDMA1_S0_IRQ_STATUS	0xFFC01F68	/* MemDMA1 Stream 0 Source Interrupt/Status */
+#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C	/* MemDMA1 Stream 0 Source Peripheral Map */
+
+#define MDMA1_D1_CONFIG		0xFFC01F88	/* MemDMA1 Stream 1 Destination Configuration */
+#define MDMA1_D1_NEXT_DESC_PTR	0xFFC01F80	/* MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA1_D1_START_ADDR	0xFFC01F84	/* MemDMA1 Stream 1 Destination Start Address */
+#define MDMA1_D1_X_COUNT	0xFFC01F90	/* MemDMA1 Stream 1 Destination Inner-Loop Count */
+#define MDMA1_D1_Y_COUNT	0xFFC01F98	/* MemDMA1 Stream 1 Destination Outer-Loop Count */
+#define MDMA1_D1_X_MODIFY	0xFFC01F94	/* MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA1_D1_Y_MODIFY	0xFFC01F9C	/* MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA1_D1_CURR_DESC_PTR	0xFFC01FA0	/* MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
+#define MDMA1_D1_CURR_ADDR	0xFFC01FA4	/* MemDMA1 Stream 1 Dest Current Address */
+#define MDMA1_D1_CURR_X_COUNT	0xFFC01FB0	/* MemDMA1 Stream 1 Dest Current Inner-Loop Count */
+#define MDMA1_D1_CURR_Y_COUNT	0xFFC01FB8	/* MemDMA1 Stream 1 Dest Current Outer-Loop Count */
+#define MDMA1_D1_IRQ_STATUS	0xFFC01FA8	/* MemDMA1 Stream 1 Dest Interrupt/Status */
+#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC	/* MemDMA1 Stream 1 Dest Peripheral Map */
+
+#define MDMA1_S1_CONFIG		0xFFC01FC8	/* MemDMA1 Stream 1 Source Configuration */
+#define MDMA1_S1_NEXT_DESC_PTR	0xFFC01FC0	/* MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA1_S1_START_ADDR	0xFFC01FC4	/* MemDMA1 Stream 1 Source Start Address */
+#define MDMA1_S1_X_COUNT	0xFFC01FD0	/* MemDMA1 Stream 1 Source Inner-Loop Count */
+#define MDMA1_S1_Y_COUNT	0xFFC01FD8	/* MemDMA1 Stream 1 Source Outer-Loop Count */
+#define MDMA1_S1_X_MODIFY	0xFFC01FD4	/* MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
+#define MDMA1_S1_Y_MODIFY	0xFFC01FDC	/* MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA1_S1_CURR_DESC_PTR	0xFFC01FE0	/* MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA1_S1_CURR_ADDR	0xFFC01FE4	/* MemDMA1 Stream 1 Source Current Address */
+#define MDMA1_S1_CURR_X_COUNT	0xFFC01FF0	/* MemDMA1 Stream 1 Source Current Inner-Loop Count */
+#define MDMA1_S1_CURR_Y_COUNT	0xFFC01FF8	/* MemDMA1 Stream 1 Source Current Outer-Loop Count */
+#define MDMA1_S1_IRQ_STATUS	0xFFC01FE8	/* MemDMA1 Stream 1 Source Interrupt/Status */
+#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC	/* MemDMA1 Stream 1 Source Peripheral Map */
+
+/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
+#define DMA2_0_CONFIG		0xFFC00C08	/* DMA2 Channel 0 Configuration register */
+#define DMA2_0_NEXT_DESC_PTR	0xFFC00C00	/* DMA2 Channel 0 Next Descripter Ptr Reg */
+#define DMA2_0_START_ADDR	0xFFC00C04	/* DMA2 Channel 0 Start Address */
+#define DMA2_0_X_COUNT		0xFFC00C10	/* DMA2 Channel 0 Inner Loop Count */
+#define DMA2_0_Y_COUNT		0xFFC00C18	/* DMA2 Channel 0 Outer Loop Count */
+#define DMA2_0_X_MODIFY		0xFFC00C14	/* DMA2 Channel 0 Inner Loop Addr Increment */
+#define DMA2_0_Y_MODIFY		0xFFC00C1C	/* DMA2 Channel 0 Outer Loop Addr Increment */
+#define DMA2_0_CURR_DESC_PTR	0xFFC00C20	/* DMA2 Channel 0 Current Descriptor Pointer */
+#define DMA2_0_CURR_ADDR	0xFFC00C24	/* DMA2 Channel 0 Current Address Pointer */
+#define DMA2_0_CURR_X_COUNT	0xFFC00C30	/* DMA2 Channel 0 Current Inner Loop Count */
+#define DMA2_0_CURR_Y_COUNT	0xFFC00C38	/* DMA2 Channel 0 Current Outer Loop Count */
+#define DMA2_0_IRQ_STATUS	0xFFC00C28	/* DMA2 Channel 0 Interrupt Status Register */
+#define DMA2_0_PERIPHERAL_MAP	0xFFC00C2C	/* DMA2 Channel 0 Peripheral Map Register */
+
+#define DMA2_1_CONFIG		0xFFC00C48	/* DMA2 Channel 1 Configuration register */
+#define DMA2_1_NEXT_DESC_PTR	0xFFC00C40	/* DMA2 Channel 1 Next Descripter Ptr Reg */
+#define DMA2_1_START_ADDR	0xFFC00C44	/* DMA2 Channel 1 Start Address */
+#define DMA2_1_X_COUNT		0xFFC00C50	/* DMA2 Channel 1 Inner Loop Count */
+#define DMA2_1_Y_COUNT		0xFFC00C58	/* DMA2 Channel 1 Outer Loop Count */
+#define DMA2_1_X_MODIFY		0xFFC00C54	/* DMA2 Channel 1 Inner Loop Addr Increment */
+#define DMA2_1_Y_MODIFY		0xFFC00C5C	/* DMA2 Channel 1 Outer Loop Addr Increment */
+#define DMA2_1_CURR_DESC_PTR	0xFFC00C60	/* DMA2 Channel 1 Current Descriptor Pointer */
+#define DMA2_1_CURR_ADDR	0xFFC00C64	/* DMA2 Channel 1 Current Address Pointer */
+#define DMA2_1_CURR_X_COUNT	0xFFC00C70	/* DMA2 Channel 1 Current Inner Loop Count */
+#define DMA2_1_CURR_Y_COUNT	0xFFC00C78	/* DMA2 Channel 1 Current Outer Loop Count */
+#define DMA2_1_IRQ_STATUS	0xFFC00C68	/* DMA2 Channel 1 Interrupt Status Register */
+#define DMA2_1_PERIPHERAL_MAP	0xFFC00C6C	/* DMA2 Channel 1 Peripheral Map Register */
+
+#define DMA2_2_CONFIG		0xFFC00C88	/* DMA2 Channel 2 Configuration register */
+#define DMA2_2_NEXT_DESC_PTR	0xFFC00C80	/* DMA2 Channel 2 Next Descripter Ptr Reg */
+#define DMA2_2_START_ADDR	0xFFC00C84	/* DMA2 Channel 2 Start Address */
+#define DMA2_2_X_COUNT		0xFFC00C90	/* DMA2 Channel 2 Inner Loop Count */
+#define DMA2_2_Y_COUNT		0xFFC00C98	/* DMA2 Channel 2 Outer Loop Count */
+#define DMA2_2_X_MODIFY		0xFFC00C94	/* DMA2 Channel 2 Inner Loop Addr Increment */
+#define DMA2_2_Y_MODIFY		0xFFC00C9C	/* DMA2 Channel 2 Outer Loop Addr Increment */
+#define DMA2_2_CURR_DESC_PTR	0xFFC00CA0	/* DMA2 Channel 2 Current Descriptor Pointer */
+#define DMA2_2_CURR_ADDR	0xFFC00CA4	/* DMA2 Channel 2 Current Address Pointer */
+#define DMA2_2_CURR_X_COUNT	0xFFC00CB0	/* DMA2 Channel 2 Current Inner Loop Count */
+#define DMA2_2_CURR_Y_COUNT	0xFFC00CB8	/* DMA2 Channel 2 Current Outer Loop Count */
+#define DMA2_2_IRQ_STATUS	0xFFC00CA8	/* DMA2 Channel 2 Interrupt Status Register */
+#define DMA2_2_PERIPHERAL_MAP	0xFFC00CAC	/* DMA2 Channel 2 Peripheral Map Register */
+
+#define DMA2_3_CONFIG		0xFFC00CC8	/* DMA2 Channel 3 Configuration register */
+#define DMA2_3_NEXT_DESC_PTR	0xFFC00CC0	/* DMA2 Channel 3 Next Descripter Ptr Reg */
+#define DMA2_3_START_ADDR	0xFFC00CC4	/* DMA2 Channel 3 Start Address */
+#define DMA2_3_X_COUNT		0xFFC00CD0	/* DMA2 Channel 3 Inner Loop Count */
+#define DMA2_3_Y_COUNT		0xFFC00CD8	/* DMA2 Channel 3 Outer Loop Count */
+#define DMA2_3_X_MODIFY		0xFFC00CD4	/* DMA2 Channel 3 Inner Loop Addr Increment */
+#define DMA2_3_Y_MODIFY		0xFFC00CDC	/* DMA2 Channel 3 Outer Loop Addr Increment */
+#define DMA2_3_CURR_DESC_PTR	0xFFC00CE0	/* DMA2 Channel 3 Current Descriptor Pointer */
+#define DMA2_3_CURR_ADDR	0xFFC00CE4	/* DMA2 Channel 3 Current Address Pointer */
+#define DMA2_3_CURR_X_COUNT	0xFFC00CF0	/* DMA2 Channel 3 Current Inner Loop Count */
+#define DMA2_3_CURR_Y_COUNT	0xFFC00CF8	/* DMA2 Channel 3 Current Outer Loop Count */
+#define DMA2_3_IRQ_STATUS	0xFFC00CE8	/* DMA2 Channel 3 Interrupt Status Register */
+#define DMA2_3_PERIPHERAL_MAP	0xFFC00CEC	/* DMA2 Channel 3 Peripheral Map Register */
+
+#define DMA2_4_CONFIG		0xFFC00D08	/* DMA2 Channel 4 Configuration register */
+#define DMA2_4_NEXT_DESC_PTR	0xFFC00D00	/* DMA2 Channel 4 Next Descripter Ptr Reg */
+#define DMA2_4_START_ADDR	0xFFC00D04	/* DMA2 Channel 4 Start Address */
+#define DMA2_4_X_COUNT		0xFFC00D10	/* DMA2 Channel 4 Inner Loop Count */
+#define DMA2_4_Y_COUNT		0xFFC00D18	/* DMA2 Channel 4 Outer Loop Count */
+#define DMA2_4_X_MODIFY		0xFFC00D14	/* DMA2 Channel 4 Inner Loop Addr Increment */
+#define DMA2_4_Y_MODIFY		0xFFC00D1C	/* DMA2 Channel 4 Outer Loop Addr Increment */
+#define DMA2_4_CURR_DESC_PTR	0xFFC00D20	/* DMA2 Channel 4 Current Descriptor Pointer */
+#define DMA2_4_CURR_ADDR	0xFFC00D24	/* DMA2 Channel 4 Current Address Pointer */
+#define DMA2_4_CURR_X_COUNT	0xFFC00D30	/* DMA2 Channel 4 Current Inner Loop Count */
+#define DMA2_4_CURR_Y_COUNT	0xFFC00D38	/* DMA2 Channel 4 Current Outer Loop Count */
+#define DMA2_4_IRQ_STATUS	0xFFC00D28	/* DMA2 Channel 4 Interrupt Status Register */
+#define DMA2_4_PERIPHERAL_MAP	0xFFC00D2C	/* DMA2 Channel 4 Peripheral Map Register */
+
+#define DMA2_5_CONFIG		0xFFC00D48	/* DMA2 Channel 5 Configuration register */
+#define DMA2_5_NEXT_DESC_PTR	0xFFC00D40	/* DMA2 Channel 5 Next Descripter Ptr Reg */
+#define DMA2_5_START_ADDR	0xFFC00D44	/* DMA2 Channel 5 Start Address */
+#define DMA2_5_X_COUNT		0xFFC00D50	/* DMA2 Channel 5 Inner Loop Count */
+#define DMA2_5_Y_COUNT		0xFFC00D58	/* DMA2 Channel 5 Outer Loop Count */
+#define DMA2_5_X_MODIFY		0xFFC00D54	/* DMA2 Channel 5 Inner Loop Addr Increment */
+#define DMA2_5_Y_MODIFY		0xFFC00D5C	/* DMA2 Channel 5 Outer Loop Addr Increment */
+#define DMA2_5_CURR_DESC_PTR	0xFFC00D60	/* DMA2 Channel 5 Current Descriptor Pointer */
+#define DMA2_5_CURR_ADDR	0xFFC00D64	/* DMA2 Channel 5 Current Address Pointer */
+#define DMA2_5_CURR_X_COUNT	0xFFC00D70	/* DMA2 Channel 5 Current Inner Loop Count */
+#define DMA2_5_CURR_Y_COUNT	0xFFC00D78	/* DMA2 Channel 5 Current Outer Loop Count */
+#define DMA2_5_IRQ_STATUS	0xFFC00D68	/* DMA2 Channel 5 Interrupt Status Register */
+#define DMA2_5_PERIPHERAL_MAP	0xFFC00D6C	/* DMA2 Channel 5 Peripheral Map Register */
+
+#define DMA2_6_CONFIG		0xFFC00D88	/* DMA2 Channel 6 Configuration register */
+#define DMA2_6_NEXT_DESC_PTR	0xFFC00D80	/* DMA2 Channel 6 Next Descripter Ptr Reg */
+#define DMA2_6_START_ADDR	0xFFC00D84	/* DMA2 Channel 6 Start Address */
+#define DMA2_6_X_COUNT		0xFFC00D90	/* DMA2 Channel 6 Inner Loop Count */
+#define DMA2_6_Y_COUNT		0xFFC00D98	/* DMA2 Channel 6 Outer Loop Count */
+#define DMA2_6_X_MODIFY		0xFFC00D94	/* DMA2 Channel 6 Inner Loop Addr Increment */
+#define DMA2_6_Y_MODIFY		0xFFC00D9C	/* DMA2 Channel 6 Outer Loop Addr Increment */
+#define DMA2_6_CURR_DESC_PTR	0xFFC00DA0	/* DMA2 Channel 6 Current Descriptor Pointer */
+#define DMA2_6_CURR_ADDR	0xFFC00DA4	/* DMA2 Channel 6 Current Address Pointer */
+#define DMA2_6_CURR_X_COUNT	0xFFC00DB0	/* DMA2 Channel 6 Current Inner Loop Count */
+#define DMA2_6_CURR_Y_COUNT	0xFFC00DB8	/* DMA2 Channel 6 Current Outer Loop Count */
+#define DMA2_6_IRQ_STATUS	0xFFC00DA8	/* DMA2 Channel 6 Interrupt Status Register */
+#define DMA2_6_PERIPHERAL_MAP	0xFFC00DAC	/* DMA2 Channel 6 Peripheral Map Register */
+
+#define DMA2_7_CONFIG		0xFFC00DC8	/* DMA2 Channel 7 Configuration register */
+#define DMA2_7_NEXT_DESC_PTR	0xFFC00DC0	/* DMA2 Channel 7 Next Descripter Ptr Reg */
+#define DMA2_7_START_ADDR	0xFFC00DC4	/* DMA2 Channel 7 Start Address */
+#define DMA2_7_X_COUNT		0xFFC00DD0	/* DMA2 Channel 7 Inner Loop Count */
+#define DMA2_7_Y_COUNT		0xFFC00DD8	/* DMA2 Channel 7 Outer Loop Count */
+#define DMA2_7_X_MODIFY		0xFFC00DD4	/* DMA2 Channel 7 Inner Loop Addr Increment */
+#define DMA2_7_Y_MODIFY		0xFFC00DDC	/* DMA2 Channel 7 Outer Loop Addr Increment */
+#define DMA2_7_CURR_DESC_PTR	0xFFC00DE0	/* DMA2 Channel 7 Current Descriptor Pointer */
+#define DMA2_7_CURR_ADDR	0xFFC00DE4	/* DMA2 Channel 7 Current Address Pointer */
+#define DMA2_7_CURR_X_COUNT	0xFFC00DF0	/* DMA2 Channel 7 Current Inner Loop Count */
+#define DMA2_7_CURR_Y_COUNT	0xFFC00DF8	/* DMA2 Channel 7 Current Outer Loop Count */
+#define DMA2_7_IRQ_STATUS	0xFFC00DE8	/* DMA2 Channel 7 Interrupt Status Register */
+#define DMA2_7_PERIPHERAL_MAP	0xFFC00DEC	/* DMA2 Channel 7 Peripheral Map Register */
+
+#define DMA2_8_CONFIG		0xFFC00E08	/* DMA2 Channel 8 Configuration register */
+#define DMA2_8_NEXT_DESC_PTR	0xFFC00E00	/* DMA2 Channel 8 Next Descripter Ptr Reg */
+#define DMA2_8_START_ADDR	0xFFC00E04	/* DMA2 Channel 8 Start Address */
+#define DMA2_8_X_COUNT		0xFFC00E10	/* DMA2 Channel 8 Inner Loop Count */
+#define DMA2_8_Y_COUNT		0xFFC00E18	/* DMA2 Channel 8 Outer Loop Count */
+#define DMA2_8_X_MODIFY		0xFFC00E14	/* DMA2 Channel 8 Inner Loop Addr Increment */
+#define DMA2_8_Y_MODIFY		0xFFC00E1C	/* DMA2 Channel 8 Outer Loop Addr Increment */
+#define DMA2_8_CURR_DESC_PTR	0xFFC00E20	/* DMA2 Channel 8 Current Descriptor Pointer */
+#define DMA2_8_CURR_ADDR	0xFFC00E24	/* DMA2 Channel 8 Current Address Pointer */
+#define DMA2_8_CURR_X_COUNT	0xFFC00E30	/* DMA2 Channel 8 Current Inner Loop Count */
+#define DMA2_8_CURR_Y_COUNT	0xFFC00E38	/* DMA2 Channel 8 Current Outer Loop Count */
+#define DMA2_8_IRQ_STATUS	0xFFC00E28	/* DMA2 Channel 8 Interrupt Status Register */
+#define DMA2_8_PERIPHERAL_MAP	0xFFC00E2C	/* DMA2 Channel 8 Peripheral Map Register */
+
+#define DMA2_9_CONFIG		0xFFC00E48	/* DMA2 Channel 9 Configuration register */
+#define DMA2_9_NEXT_DESC_PTR	0xFFC00E40	/* DMA2 Channel 9 Next Descripter Ptr Reg */
+#define DMA2_9_START_ADDR	0xFFC00E44	/* DMA2 Channel 9 Start Address */
+#define DMA2_9_X_COUNT		0xFFC00E50	/* DMA2 Channel 9 Inner Loop Count */
+#define DMA2_9_Y_COUNT		0xFFC00E58	/* DMA2 Channel 9 Outer Loop Count */
+#define DMA2_9_X_MODIFY		0xFFC00E54	/* DMA2 Channel 9 Inner Loop Addr Increment */
+#define DMA2_9_Y_MODIFY		0xFFC00E5C	/* DMA2 Channel 9 Outer Loop Addr Increment */
+#define DMA2_9_CURR_DESC_PTR	0xFFC00E60	/* DMA2 Channel 9 Current Descriptor Pointer */
+#define DMA2_9_CURR_ADDR	0xFFC00E64	/* DMA2 Channel 9 Current Address Pointer */
+#define DMA2_9_CURR_X_COUNT	0xFFC00E70	/* DMA2 Channel 9 Current Inner Loop Count */
+#define DMA2_9_CURR_Y_COUNT	0xFFC00E78	/* DMA2 Channel 9 Current Outer Loop Count */
+#define DMA2_9_IRQ_STATUS	0xFFC00E68	/* DMA2 Channel 9 Interrupt Status Register */
+#define DMA2_9_PERIPHERAL_MAP	0xFFC00E6C	/* DMA2 Channel 9 Peripheral Map Register */
+
+#define DMA2_10_CONFIG		0xFFC00E88	/* DMA2 Channel 10 Configuration register */
+#define DMA2_10_NEXT_DESC_PTR	0xFFC00E80	/* DMA2 Channel 10 Next Descripter Ptr Reg */
+#define DMA2_10_START_ADDR	0xFFC00E84	/* DMA2 Channel 10 Start Address */
+#define DMA2_10_X_COUNT		0xFFC00E90	/* DMA2 Channel 10 Inner Loop Count */
+#define DMA2_10_Y_COUNT		0xFFC00E98	/* DMA2 Channel 10 Outer Loop Count */
+#define DMA2_10_X_MODIFY	0xFFC00E94	/* DMA2 Channel 10 Inner Loop Addr Increment */
+#define DMA2_10_Y_MODIFY	0xFFC00E9C	/* DMA2 Channel 10 Outer Loop Addr Increment */
+#define DMA2_10_CURR_DESC_PTR	0xFFC00EA0	/* DMA2 Channel 10 Current Descriptor Pointer */
+#define DMA2_10_CURR_ADDR	0xFFC00EA4	/* DMA2 Channel 10 Current Address Pointer */
+#define DMA2_10_CURR_X_COUNT	0xFFC00EB0	/* DMA2 Channel 10 Current Inner Loop Count */
+#define DMA2_10_CURR_Y_COUNT	0xFFC00EB8	/* DMA2 Channel 10 Current Outer Loop Count */
+#define DMA2_10_IRQ_STATUS	0xFFC00EA8	/* DMA2 Channel 10 Interrupt Status Register */
+#define DMA2_10_PERIPHERAL_MAP	0xFFC00EAC	/* DMA2 Channel 10 Peripheral Map Register */
+
+#define DMA2_11_CONFIG		0xFFC00EC8	/* DMA2 Channel 11 Configuration register */
+#define DMA2_11_NEXT_DESC_PTR	0xFFC00EC0	/* DMA2 Channel 11 Next Descripter Ptr Reg */
+#define DMA2_11_START_ADDR	0xFFC00EC4	/* DMA2 Channel 11 Start Address */
+#define DMA2_11_X_COUNT		0xFFC00ED0	/* DMA2 Channel 11 Inner Loop Count */
+#define DMA2_11_Y_COUNT		0xFFC00ED8	/* DMA2 Channel 11 Outer Loop Count */
+#define DMA2_11_X_MODIFY	0xFFC00ED4	/* DMA2 Channel 11 Inner Loop Addr Increment */
+#define DMA2_11_Y_MODIFY	0xFFC00EDC	/* DMA2 Channel 11 Outer Loop Addr Increment */
+#define DMA2_11_CURR_DESC_PTR	0xFFC00EE0	/* DMA2 Channel 11 Current Descriptor Pointer */
+#define DMA2_11_CURR_ADDR	0xFFC00EE4	/* DMA2 Channel 11 Current Address Pointer */
+#define DMA2_11_CURR_X_COUNT	0xFFC00EF0	/* DMA2 Channel 11 Current Inner Loop Count */
+#define DMA2_11_CURR_Y_COUNT	0xFFC00EF8	/* DMA2 Channel 11 Current Outer Loop Count */
+#define DMA2_11_IRQ_STATUS	0xFFC00EE8	/* DMA2 Channel 11 Interrupt Status Register */
+#define DMA2_11_PERIPHERAL_MAP	0xFFC00EEC	/* DMA2 Channel 11 Peripheral Map Register */
+
+/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
+#define MDMA2_D0_CONFIG		0xFFC00F08	/* MemDMA2 Stream 0 Destination Configuration register */
+#define MDMA2_D0_NEXT_DESC_PTR	0xFFC00F00	/* MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA2_D0_START_ADDR	0xFFC00F04	/* MemDMA2 Stream 0 Destination Start Address */
+#define MDMA2_D0_X_COUNT	0xFFC00F10	/* MemDMA2 Stream 0 Dest Inner-Loop Count register */
+#define MDMA2_D0_Y_COUNT	0xFFC00F18	/* MemDMA2 Stream 0 Dest Outer-Loop Count register */
+#define MDMA2_D0_X_MODIFY	0xFFC00F14	/* MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA2_D0_Y_MODIFY	0xFFC00F1C	/* MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA2_D0_CURR_DESC_PTR	0xFFC00F20	/* MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA2_D0_CURR_ADDR	0xFFC00F24	/* MemDMA2 Stream 0 Destination Current Address */
+#define MDMA2_D0_CURR_X_COUNT	0xFFC00F30	/* MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
+#define MDMA2_D0_CURR_Y_COUNT	0xFFC00F38	/* MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
+#define MDMA2_D0_IRQ_STATUS	0xFFC00F28	/* MemDMA2 Stream 0 Dest Interrupt/Status Register */
+#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C	/* MemDMA2 Stream 0 Destination Peripheral Map register */
+
+#define MDMA2_S0_CONFIG		0xFFC00F48	/* MemDMA2 Stream 0 Source Configuration register */
+#define MDMA2_S0_NEXT_DESC_PTR	0xFFC00F40	/* MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA2_S0_START_ADDR	0xFFC00F44	/* MemDMA2 Stream 0 Source Start Address */
+#define MDMA2_S0_X_COUNT	0xFFC00F50	/* MemDMA2 Stream 0 Source Inner-Loop Count register */
+#define MDMA2_S0_Y_COUNT	0xFFC00F58	/* MemDMA2 Stream 0 Source Outer-Loop Count register */
+#define MDMA2_S0_X_MODIFY	0xFFC00F54	/* MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
+#define MDMA2_S0_Y_MODIFY	0xFFC00F5C	/* MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
+#define MDMA2_S0_CURR_DESC_PTR	0xFFC00F60	/* MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA2_S0_CURR_ADDR	0xFFC00F64	/* MemDMA2 Stream 0 Source Current Address */
+#define MDMA2_S0_CURR_X_COUNT	0xFFC00F70	/* MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
+#define MDMA2_S0_CURR_Y_COUNT	0xFFC00F78	/* MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
+#define MDMA2_S0_IRQ_STATUS	0xFFC00F68	/* MemDMA2 Stream 0 Source Interrupt/Status Register */
+#define MDMA2_S0_PERIPHERAL_MAP	0xFFC00F6C	/* MemDMA2 Stream 0 Source Peripheral Map register */
+
+#define MDMA2_D1_CONFIG		0xFFC00F88	/* MemDMA2 Stream 1 Destination Configuration register */
+#define MDMA2_D1_NEXT_DESC_PTR	0xFFC00F80	/* MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA2_D1_START_ADDR	0xFFC00F84	/* MemDMA2 Stream 1 Destination Start Address */
+#define MDMA2_D1_X_COUNT	0xFFC00F90	/* MemDMA2 Stream 1 Dest Inner-Loop Count register */
+#define MDMA2_D1_Y_COUNT	0xFFC00F98	/* MemDMA2 Stream 1 Dest Outer-Loop Count register */
+#define MDMA2_D1_X_MODIFY	0xFFC00F94	/* MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA2_D1_Y_MODIFY	0xFFC00F9C	/* MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA2_D1_CURR_DESC_PTR	0xFFC00FA0	/* MemDMA2 Stream 1 Destination Current Descriptor Ptr */
+#define MDMA2_D1_CURR_ADDR	0xFFC00FA4	/* MemDMA2 Stream 1 Destination Current Address reg */
+#define MDMA2_D1_CURR_X_COUNT	0xFFC00FB0	/* MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
+#define MDMA2_D1_CURR_Y_COUNT	0xFFC00FB8	/* MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
+#define MDMA2_D1_IRQ_STATUS	0xFFC00FA8	/* MemDMA2 Stream 1 Destination Interrupt/Status Reg */
+#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC	/* MemDMA2 Stream 1 Destination Peripheral Map register */
+
+#define MDMA2_S1_CONFIG		0xFFC00FC8	/* MemDMA2 Stream 1 Source Configuration register */
+#define MDMA2_S1_NEXT_DESC_PTR	0xFFC00FC0	/* MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA2_S1_START_ADDR	0xFFC00FC4	/* MemDMA2 Stream 1 Source Start Address */
+#define MDMA2_S1_X_COUNT	0xFFC00FD0	/* MemDMA2 Stream 1 Source Inner-Loop Count register */
+#define MDMA2_S1_Y_COUNT	0xFFC00FD8	/* MemDMA2 Stream 1 Source Outer-Loop Count register */
+#define MDMA2_S1_X_MODIFY	0xFFC00FD4	/* MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
+#define MDMA2_S1_Y_MODIFY	0xFFC00FDC	/* MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA2_S1_CURR_DESC_PTR	0xFFC00FE0	/* MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA2_S1_CURR_ADDR	0xFFC00FE4	/* MemDMA2 Stream 1 Source Current Address */
+#define MDMA2_S1_CURR_X_COUNT	0xFFC00FF0	/* MemDMA2 Stream 1 Source Current Inner-Loop Count */
+#define MDMA2_S1_CURR_Y_COUNT	0xFFC00FF8	/* MemDMA2 Stream 1 Source Current Outer-Loop Count */
+#define MDMA2_S1_IRQ_STATUS	0xFFC00FE8	/* MemDMA2 Stream 1 Source Interrupt/Status Register */
+#define MDMA2_S1_PERIPHERAL_MAP	0xFFC00FEC	/* MemDMA2 Stream 1 Source Peripheral Map register */
+
+/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
+#define IMDMA_D0_CONFIG		0xFFC01808	/* IMDMA Stream 0 Destination Configuration */
+#define IMDMA_D0_NEXT_DESC_PTR	0xFFC01800	/* IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
+#define IMDMA_D0_START_ADDR	0xFFC01804	/* IMDMA Stream 0 Destination Start Address */
+#define IMDMA_D0_X_COUNT	0xFFC01810	/* IMDMA Stream 0 Destination Inner-Loop Count */
+#define IMDMA_D0_Y_COUNT	0xFFC01818	/* IMDMA Stream 0 Destination Outer-Loop Count */
+#define IMDMA_D0_X_MODIFY	0xFFC01814	/* IMDMA Stream 0 Dest Inner-Loop Address-Increment */
+#define IMDMA_D0_Y_MODIFY	0xFFC0181C	/* IMDMA Stream 0 Dest Outer-Loop Address-Increment */
+#define IMDMA_D0_CURR_DESC_PTR	0xFFC01820	/* IMDMA Stream 0 Destination Current Descriptor Ptr */
+#define IMDMA_D0_CURR_ADDR	0xFFC01824	/* IMDMA Stream 0 Destination Current Address */
+#define IMDMA_D0_CURR_X_COUNT	0xFFC01830	/* IMDMA Stream 0 Destination Current Inner-Loop Count */
+#define IMDMA_D0_CURR_Y_COUNT	0xFFC01838	/* IMDMA Stream 0 Destination Current Outer-Loop Count */
+#define IMDMA_D0_IRQ_STATUS	0xFFC01828	/* IMDMA Stream 0 Destination Interrupt/Status */
+
+#define IMDMA_S0_CONFIG		0xFFC01848	/* IMDMA Stream 0 Source Configuration */
+#define IMDMA_S0_NEXT_DESC_PTR	0xFFC01840	/* IMDMA Stream 0 Source Next Descriptor Ptr Reg */
+#define IMDMA_S0_START_ADDR	0xFFC01844	/* IMDMA Stream 0 Source Start Address */
+#define IMDMA_S0_X_COUNT	0xFFC01850	/* IMDMA Stream 0 Source Inner-Loop Count */
+#define IMDMA_S0_Y_COUNT	0xFFC01858	/* IMDMA Stream 0 Source Outer-Loop Count */
+#define IMDMA_S0_X_MODIFY	0xFFC01854	/* IMDMA Stream 0 Source Inner-Loop Address-Increment */
+#define IMDMA_S0_Y_MODIFY	0xFFC0185C	/* IMDMA Stream 0 Source Outer-Loop Address-Increment */
+#define IMDMA_S0_CURR_DESC_PTR	0xFFC01860	/* IMDMA Stream 0 Source Current Descriptor Ptr reg */
+#define IMDMA_S0_CURR_ADDR	0xFFC01864	/* IMDMA Stream 0 Source Current Address */
+#define IMDMA_S0_CURR_X_COUNT	0xFFC01870	/* IMDMA Stream 0 Source Current Inner-Loop Count */
+#define IMDMA_S0_CURR_Y_COUNT	0xFFC01878	/* IMDMA Stream 0 Source Current Outer-Loop Count */
+#define IMDMA_S0_IRQ_STATUS	0xFFC01868	/* IMDMA Stream 0 Source Interrupt/Status */
+
+#define IMDMA_D1_CONFIG		0xFFC01888	/* IMDMA Stream 1 Destination Configuration */
+#define IMDMA_D1_NEXT_DESC_PTR	0xFFC01880	/* IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
+#define IMDMA_D1_START_ADDR	0xFFC01884	/* IMDMA Stream 1 Destination Start Address */
+#define IMDMA_D1_X_COUNT	0xFFC01890	/* IMDMA Stream 1 Destination Inner-Loop Count */
+#define IMDMA_D1_Y_COUNT	0xFFC01898	/* IMDMA Stream 1 Destination Outer-Loop Count */
+#define IMDMA_D1_X_MODIFY	0xFFC01894	/* IMDMA Stream 1 Dest Inner-Loop Address-Increment */
+#define IMDMA_D1_Y_MODIFY	0xFFC0189C	/* IMDMA Stream 1 Dest Outer-Loop Address-Increment */
+#define IMDMA_D1_CURR_DESC_PTR	0xFFC018A0	/* IMDMA Stream 1 Destination Current Descriptor Ptr */
+#define IMDMA_D1_CURR_ADDR	0xFFC018A4	/* IMDMA Stream 1 Destination Current Address */
+#define IMDMA_D1_CURR_X_COUNT	0xFFC018B0	/* IMDMA Stream 1 Destination Current Inner-Loop Count */
+#define IMDMA_D1_CURR_Y_COUNT	0xFFC018B8	/* IMDMA Stream 1 Destination Current Outer-Loop Count */
+#define IMDMA_D1_IRQ_STATUS	0xFFC018A8	/* IMDMA Stream 1 Destination Interrupt/Status */
+
+#define IMDMA_S1_CONFIG		0xFFC018C8	/* IMDMA Stream 1 Source Configuration */
+#define IMDMA_S1_NEXT_DESC_PTR	0xFFC018C0	/* IMDMA Stream 1 Source Next Descriptor Ptr Reg */
+#define IMDMA_S1_START_ADDR	0xFFC018C4	/* IMDMA Stream 1 Source Start Address */
+#define IMDMA_S1_X_COUNT	0xFFC018D0	/* IMDMA Stream 1 Source Inner-Loop Count */
+#define IMDMA_S1_Y_COUNT	0xFFC018D8	/* IMDMA Stream 1 Source Outer-Loop Count */
+#define IMDMA_S1_X_MODIFY	0xFFC018D4	/* IMDMA Stream 1 Source Inner-Loop Address-Increment */
+#define IMDMA_S1_Y_MODIFY	0xFFC018DC	/* IMDMA Stream 1 Source Outer-Loop Address-Increment */
+#define IMDMA_S1_CURR_DESC_PTR	0xFFC018E0	/* IMDMA Stream 1 Source Current Descriptor Ptr reg */
+#define IMDMA_S1_CURR_ADDR	0xFFC018E4	/* IMDMA Stream 1 Source Current Address */
+#define IMDMA_S1_CURR_X_COUNT	0xFFC018F0	/* IMDMA Stream 1 Source Current Inner-Loop Count */
+#define IMDMA_S1_CURR_Y_COUNT	0xFFC018F8	/* IMDMA Stream 1 Source Current Outer-Loop Count */
+#define IMDMA_S1_IRQ_STATUS	0xFFC018E8	/* IMDMA Stream 1 Source Interrupt/Status */
+
+/*
+ * System MMR Register Bits
+ */
+
+/* PLL AND RESET MASKS */
+
+/* PLL_CTL Masks */
+#define PLL_CLKIN		0x00000000	/* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2		0x00000001	/* Pass CLKIN/2 to PLL */
+#define PLL_OFF			0x00000002	/* Shut off PLL clocks */
+#define STOPCK_OFF		0x00000008	/* Core clock off */
+#define PDWN			0x00000020	/* Put the PLL in a Deep Sleep state */
+#define BYPASS			0x00000100	/* Bypass the PLL */
+
+/* PLL_DIV Masks */
+
+#define SCLK_DIV(x)		(x)		/* SCLK = VCO / x */
+
+#define CCLK_DIV1		0x00000000	/* CCLK = VCO / 1 */
+#define CCLK_DIV2		0x00000010	/* CCLK = VCO / 2 */
+#define CCLK_DIV4		0x00000020	/* CCLK = VCO / 4 */
+#define CCLK_DIV8		0x00000030	/* CCLK = VCO / 8 */
+
+/* SWRST Mask */
+#define SYSTEM_RESET		0x00000007	/* Initiates a system software reset */
+#define SWRST_DBL_FAULT_B	0x00000800	/* SWRST Core B Double Fault */
+#define SWRST_DBL_FAULT_A	0x00001000	/* SWRST Core A Double Fault */
+#define SWRST_WDT_B		0x00002000	/* SWRST Watchdog B */
+#define SWRST_WDT_A		0x00004000	/* SWRST Watchdog A */
+#define SWRST_OCCURRED		0x00008000	/* SWRST Status */
+
+/*
+ * SYSTEM INTERRUPT CONTROLLER MASKS
+ * SICu_IARv Masks
+ * u = A or B
+ * v = 0 to 7
+ * w = 0 or 1
+
+ * Per_number = 0 to 63
+ * IVG_number = 7 to 15
+ * Peripheral #Per_number assigned IVG #IVG_number
+ * Usage:
+ *      r0.l = lo(Peripheral_IVG(62, 10));
+ *      r0.h = hi(Peripheral_IVG(62, 10));
+ */
+#define Peripheral_IVG(Per_number, IVG_number)    \
+				( (IVG_number) -7) << ( ((Per_number)%8) *4)
+
+/* SICx_IMASKw Masks */
+/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
+#define SIC_UNMASK_ALL		0x00000000	/* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL		0xFFFFFFFF	/* Mask all peripheral interrupts */
+#define SIC_MASK(x)		(1 << (x))	/* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x)		(0xFFFFFFFF ^ (1 << (x)))/* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL		0x00000000	/* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL		0xFFFFFFFF	/* Wakeup Enable all peripherals */
+/* x = pos 0 to 31, for 32-63 use value-32 */
+#define IWR_ENABLE(x)		(1 << (x))	/* Wakeup Enable Peripheral #x */
+/* Wakeup Disable Peripheral #x */
+#define IWR_DISABLE(x)		(0xFFFFFFFF ^ (1 << (x)))
+
+/*
+ * WATCHDOG TIMER MASKS
+ */
+
+/* Watchdog Timer WDOG_CTL Register */
+#define	WDOGA_CTL		0xFFC00200
+#define	WDOGA_CNT		0xFFC00204
+#define	WDOGA_STAT		0xFFC00208
+#define	WDOGB_CTL		0xFFC01200
+#define	WDOGB_CNT		0xFFC01204
+#define	WDOGB_STAT		0xFFC01208
+#define ICTL(x)			((x<<1) & 0x0006)
+#define ENABLE_RESET		0x00000000	/* Set Watchdog Timer to generate reset */
+#define ENABLE_NMI		0x00000002	/* Set Watchdog Timer to generate non-maskable interrupt */
+#define ENABLE_GPI		0x00000004	/* Set Watchdog Timer to generate general-purpose interrupt */
+#define DISABLE_EVT		0x00000006	/* Disable Watchdog Timer interrupts */
+
+#define TMR_EN			0x0000
+#define TMR_DIS			0x0AD0
+#define TRO			0x8000
+
+#define ICTL_P0			0x01
+#define ICTL_P1			0x02
+#define TRO_P			0x0F
+
+/*
+ * UART CONTROLLER MASKS
+ */
+
+/* UART_LCR Register */
+
+#define DLAB			0x80
+#define SB			0x40
+#define STP			0x20
+#define EPS			0x10
+#define PEN			0x08
+#define STB			0x04
+#define WLS(x)			((x-5) & 0x03)
+
+#define DLAB_P			0x07
+#define SB_P			0x06
+#define STP_P			0x05
+#define EPS_P			0x04
+#define PEN_P			0x03
+#define STB_P			0x02
+#define WLS_P1			0x01
+#define WLS_P0			0x00
+
+/* UART_MCR Register */
+#define LOOP_ENA		0x10
+#define LOOP_ENA_P		0x04
+
+/* UART_LSR Register */
+#define TEMT			0x40
+#define THRE			0x20
+#define BI			0x10
+#define FE			0x08
+#define PE			0x04
+#define OE			0x02
+#define DR			0x01
+
+#define TEMP_P			0x06
+#define THRE_P			0x05
+#define BI_P			0x04
+#define FE_P			0x03
+#define PE_P			0x02
+#define OE_P			0x01
+#define DR_P			0x00
+
+/* UART_IER Register */
+#define ELSI			0x04
+#define ETBEI			0x02
+#define ERBFI			0x01
+
+#define ELSI_P			0x02
+#define ETBEI_P			0x01
+#define ERBFI_P			0x00
+
+/* UART_IIR Register */
+#define STATUS(x)		((x << 1) & 0x06)
+#define NINT			0x01
+#define STATUS_P1		0x02
+#define STATUS_P0		0x01
+#define NINT_P			0x00
+
+/* UART_GCTL Register */
+#define FFE			0x20
+#define FPE			0x10
+#define RPOLC			0x08
+#define TPOLC			0x04
+#define IREN			0x02
+#define UCEN			0x01
+
+#define FFE_P			0x05
+#define FPE_P			0x04
+#define RPOLC_P			0x03
+#define TPOLC_P			0x02
+#define IREN_P			0x01
+#define UCEN_P			0x00
+
+/*
+ * SERIAL PORT MASKS
+ */
+
+/* SPORTx_TCR1 Masks */
+#define TSPEN			0x0001	/* TX enable */
+#define ITCLK			0x0002	/* Internal TX Clock Select */
+#define TDTYPE			0x000C	/* TX Data Formatting Select */
+#define TLSBIT			0x0010	/* TX Bit Order */
+#define ITFS			0x0200	/* Internal TX Frame Sync Select */
+#define TFSR			0x0400	/* TX Frame Sync Required Select */
+#define DITFS			0x0800	/* Data Independent TX Frame Sync Select */
+#define LTFS			0x1000	/* Low TX Frame Sync Select */
+#define LATFS			0x2000	/* Late TX Frame Sync Select */
+#define TCKFE			0x4000	/* TX Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks */
+#define SLEN			0x001F	/* TX Word Length */
+#define TXSE			0x0100	/* TX Secondary Enable */
+#define TSFSE			0x0200	/* TX Stereo Frame Sync Enable */
+#define TRFST			0x0400	/* TX Right-First Data Order */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN			0x0001	/* RX enable */
+#define IRCLK			0x0002	/* Internal RX Clock Select */
+#define RDTYPE			0x000C	/* RX Data Formatting Select */
+#define RULAW			0x0008	/* u-Law enable */
+#define RALAW			0x000C	/* A-Law enable */
+#define RLSBIT			0x0010	/* RX Bit Order */
+#define IRFS			0x0200	/* Internal RX Frame Sync Select */
+#define RFSR			0x0400	/* RX Frame Sync Required Select */
+#define LRFS			0x1000	/* Low RX Frame Sync Select */
+#define LARFS			0x2000	/* Late RX Frame Sync Select */
+#define RCKFE			0x4000	/* RX Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN			0x001F	/* RX Word Length */
+#define RXSE			0x0100	/* RX Secondary Enable */
+#define RSFSE			0x0200	/* RX Stereo Frame Sync Enable */
+#define RRFST			0x0400	/* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE			0x0001	/* RX FIFO Not Empty Status */
+#define RUVF			0x0002	/* RX Underflow Status */
+#define ROVF			0x0004	/* RX Overflow Status */
+#define TXF			0x0008	/* TX FIFO Full Status */
+#define TUVF			0x0010	/* TX Underflow Status */
+#define TOVF			0x0020	/* TX Overflow Status */
+#define TXHRE			0x0040	/* TX Hold Register Empty */
+
+/* SPORTx_MCMC1 Masks */
+#define WSIZE			0x0000F000	/* Multichannel Window Size Field */
+#define WOFF			0x000003FF	/* Multichannel Window Offset Field */
+
+/* SPORTx_MCMC2 Masks */
+#define MCCRM			0x00000003	/* Multichannel Clock Recovery Mode */
+#define MCDTXPE			0x00000004	/* Multichannel DMA Transmit Packing */
+#define MCDRXPE			0x00000008	/* Multichannel DMA Receive Packing */
+#define MCMEN			0x00000010	/* Multichannel Frame Mode Enable */
+#define FSDR			0x00000080	/* Multichannel Frame Sync to Data Relationship */
+#define MFD			0x0000F000	/* Multichannel Frame Delay */
+
+/*
+ * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS
+ */
+
+/* PPI_CONTROL Masks */
+#define PORT_EN			0x00000001	/* PPI Port Enable */
+#define PORT_DIR		0x00000002	/* PPI Port Direction */
+#define XFR_TYPE		0x0000000C	/* PPI Transfer Type */
+#define PORT_CFG		0x00000030	/* PPI Port Configuration */
+#define FLD_SEL			0x00000040	/* PPI Active Field Select */
+#define PACK_EN			0x00000080	/* PPI Packing Mode */
+#define DMA32			0x00000100	/* PPI 32-bit DMA Enable */
+#define SKIP_EN			0x00000200	/* PPI Skip Element Enable */
+#define SKIP_EO			0x00000400	/* PPI Skip Even/Odd Elements */
+#define DLENGTH			0x00003800	/* PPI Data Length */
+#define DLEN_8			0x0		/* PPI Data Length mask for DLEN=8 */
+#define DLEN(x)			(((x-9) & 0x07) << 11)	/* PPI Data Length (only works for x=10-->x=16) */
+#define POL			0x0000C000	/* PPI Signal Polarities */
+
+/* PPI_STATUS Masks */
+#define FLD			0x00000400	/* Field Indicator */
+#define FT_ERR			0x00000800	/* Frame Track Error */
+#define OVR			0x00001000	/* FIFO Overflow Error */
+#define UNDR			0x00002000	/* FIFO Underrun Error */
+#define ERR_DET			0x00004000	/* Error Detected Indicator */
+#define ERR_NCOR		0x00008000	/* Error Not Corrected Indicator */
+
+/*
+ * DMA CONTROLLER MASKS
+ */
+
+/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
+#define DMAEN			0x00000001	/* Channel Enable */
+#define WNR			0x00000002	/* Channel Direction (W/R*) */
+#define WDSIZE_8		0x00000000	/* Word Size 8 bits */
+#define WDSIZE_16		0x00000004	/* Word Size 16 bits */
+#define WDSIZE_32		0x00000008	/* Word Size 32 bits */
+#define DMA2D			0x00000010	/* 2D/1D* Mode */
+#define RESTART			0x00000020	/* Restart */
+#define DI_SEL			0x00000040	/* Data Interrupt Select */
+#define DI_EN			0x00000080	/* Data Interrupt Enable */
+#define NDSIZE			0x00000900	/* Next Descriptor Size */
+#define FLOW			0x00007000	/* Flow Control */
+
+#define DMAEN_P			0		/* Channel Enable */
+#define WNR_P			1		/* Channel Direction (W/R*) */
+#define DMA2D_P			4		/* 2D/1D* Mode */
+#define RESTART_P		5		/* Restart */
+#define DI_SEL_P		6		/* Data Interrupt Select */
+#define DI_EN_P			7		/* Data Interrupt Enable */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
+
+#define DMA_DONE		0x00000001	/* DMA Done Indicator */
+#define DMA_ERR			0x00000002	/* DMA Error Indicator */
+#define DFETCH			0x00000004	/* Descriptor Fetch Indicator */
+#define DMA_RUN			0x00000008	/* DMA Running Indicator */
+
+#define DMA_DONE_P		0		/* DMA Done Indicator */
+#define DMA_ERR_P		1		/* DMA Error Indicator */
+#define DFETCH_P		2		/* Descriptor Fetch Indicator */
+#define DMA_RUN_P		3		/* DMA Running Indicator */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
+
+#define CTYPE			0x00000040	/* DMA Channel Type Indicator */
+#define CTYPE_P			6		/* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8			0x00000080	/* DMA 8-bit Operation Indicator */
+#define PCAP16			0x00000100	/* DMA 16-bit Operation Indicator */
+#define PCAP32			0x00000200	/* DMA 32-bit Operation Indicator */
+#define PCAPWR			0x00000400	/* DMA Write Operation Indicator */
+#define PCAPRD			0x00000800	/* DMA Read Operation Indicator */
+#define PMAP			0x00007000	/* DMA Peripheral Map Field */
+
+/*
+ * GENERAL PURPOSE TIMER MASKS
+ */
+
+/* PWM Timer bit definitions */
+
+/* TIMER_ENABLE Register */
+#define TIMEN0			0x0001
+#define TIMEN1			0x0002
+#define TIMEN2			0x0004
+#define TIMEN3			0x0008
+#define TIMEN4			0x0010
+#define TIMEN5			0x0020
+#define TIMEN6			0x0040
+#define TIMEN7			0x0080
+#define TIMEN8			0x0001
+#define TIMEN9			0x0002
+#define TIMEN10			0x0004
+#define TIMEN11			0x0008
+
+#define TIMEN0_P		0x00
+#define TIMEN1_P		0x01
+#define TIMEN2_P		0x02
+#define TIMEN3_P		0x03
+#define TIMEN4_P		0x04
+#define TIMEN5_P		0x05
+#define TIMEN6_P		0x06
+#define TIMEN7_P		0x07
+#define TIMEN8_P		0x00
+#define TIMEN9_P		0x01
+#define TIMEN10_P		0x02
+#define TIMEN11_P		0x03
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0			0x0001
+#define TIMDIS1			0x0002
+#define TIMDIS2			0x0004
+#define TIMDIS3			0x0008
+#define TIMDIS4			0x0010
+#define TIMDIS5			0x0020
+#define TIMDIS6			0x0040
+#define TIMDIS7			0x0080
+#define TIMDIS8			0x0001
+#define TIMDIS9			0x0002
+#define TIMDIS10		0x0004
+#define TIMDIS11		0x0008
+
+#define TIMDIS0_P		0x00
+#define TIMDIS1_P		0x01
+#define TIMDIS2_P		0x02
+#define TIMDIS3_P		0x03
+#define TIMDIS4_P		0x04
+#define TIMDIS5_P		0x05
+#define TIMDIS6_P		0x06
+#define TIMDIS7_P		0x07
+#define TIMDIS8_P		0x00
+#define TIMDIS9_P		0x01
+#define TIMDIS10_P		0x02
+#define TIMDIS11_P		0x03
+
+/* TIMER_STATUS Register */
+#define TIMIL0			0x00000001
+#define TIMIL1			0x00000002
+#define TIMIL2			0x00000004
+#define TIMIL3			0x00000008
+#define TIMIL4			0x00010000
+#define TIMIL5			0x00020000
+#define TIMIL6			0x00040000
+#define TIMIL7			0x00080000
+#define TIMIL8			0x0001
+#define TIMIL9			0x0002
+#define TIMIL10			0x0004
+#define TIMIL11			0x0008
+#define TOVL_ERR0		0x00000010
+#define TOVL_ERR1		0x00000020
+#define TOVL_ERR2		0x00000040
+#define TOVL_ERR3		0x00000080
+#define TOVL_ERR4		0x00100000
+#define TOVL_ERR5		0x00200000
+#define TOVL_ERR6		0x00400000
+#define TOVL_ERR7		0x00800000
+#define TOVL_ERR8		0x0010
+#define TOVL_ERR9		0x0020
+#define TOVL_ERR10		0x0040
+#define TOVL_ERR11		0x0080
+#define TRUN0			0x00001000
+#define TRUN1			0x00002000
+#define TRUN2			0x00004000
+#define TRUN3			0x00008000
+#define TRUN4			0x10000000
+#define TRUN5			0x20000000
+#define TRUN6			0x40000000
+#define TRUN7			0x80000000
+#define TRUN8			0x1000
+#define TRUN9			0x2000
+#define TRUN10			0x4000
+#define TRUN11			0x8000
+
+#define TIMIL0_P		0x00
+#define TIMIL1_P		0x01
+#define TIMIL2_P		0x02
+#define TIMIL3_P		0x03
+#define TIMIL4_P		0x10
+#define TIMIL5_P		0x11
+#define TIMIL6_P		0x12
+#define TIMIL7_P		0x13
+#define TIMIL8_P		0x00
+#define TIMIL9_P		0x01
+#define TIMIL10_P		0x02
+#define TIMIL11_P		0x03
+#define TOVL_ERR0_P		0x04
+#define TOVL_ERR1_P		0x05
+#define TOVL_ERR2_P		0x06
+#define TOVL_ERR3_P		0x07
+#define TOVL_ERR4_P		0x14
+#define TOVL_ERR5_P		0x15
+#define TOVL_ERR6_P		0x16
+#define TOVL_ERR7_P		0x17
+#define TOVL_ERR8_P		0x04
+#define TOVL_ERR9_P		0x05
+#define TOVL_ERR10_P		0x06
+#define TOVL_ERR11_P		0x07
+#define TRUN0_P			0x0C
+#define TRUN1_P			0x0D
+#define TRUN2_P			0x0E
+#define TRUN3_P			0x0F
+#define TRUN4_P			0x1C
+#define TRUN5_P			0x1D
+#define TRUN6_P			0x1E
+#define TRUN7_P			0x1F
+#define TRUN8_P			0x0C
+#define TRUN9_P			0x0D
+#define TRUN10_P		0x0E
+#define TRUN11_P		0x0F
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT			0x0001
+#define WDTH_CAP		0x0002
+#define EXT_CLK			0x0003
+#define PULSE_HI		0x0004
+#define PERIOD_CNT		0x0008
+#define IRQ_ENA			0x0010
+#define TIN_SEL			0x0020
+#define OUT_DIS			0x0040
+#define CLK_SEL			0x0080
+#define TOGGLE_HI		0x0100
+#define EMU_RUN			0x0200
+#define ERR_TYP(x)		((x & 0x03) << 14)
+
+#define TMODE_P0		0x00
+#define TMODE_P1		0x01
+#define PULSE_HI_P		0x02
+#define PERIOD_CNT_P		0x03
+#define IRQ_ENA_P		0x04
+#define TIN_SEL_P		0x05
+#define OUT_DIS_P		0x06
+#define CLK_SEL_P		0x07
+#define TOGGLE_HI_P		0x08
+#define EMU_RUN_P		0x09
+#define ERR_TYP_P0		0x0E
+#define ERR_TYP_P1		0x0F
+
+/*
+ * PROGRAMMABLE FLAG MASKS
+ */
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
+#define PF0			0x0001
+#define PF1			0x0002
+#define PF2			0x0004
+#define PF3			0x0008
+#define PF4			0x0010
+#define PF5			0x0020
+#define PF6			0x0040
+#define PF7			0x0080
+#define PF8			0x0100
+#define PF9			0x0200
+#define PF10			0x0400
+#define PF11			0x0800
+#define PF12			0x1000
+#define PF13			0x2000
+#define PF14			0x4000
+#define PF15			0x8000
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
+#define PF0_P			0
+#define PF1_P			1
+#define PF2_P			2
+#define PF3_P			3
+#define PF4_P			4
+#define PF5_P			5
+#define PF6_P			6
+#define PF7_P			7
+#define PF8_P			8
+#define PF9_P			9
+#define PF10_P			10
+#define PF11_P			11
+#define PF12_P			12
+#define PF13_P			13
+#define PF14_P			14
+#define PF15_P			15
+
+/*
+ * SERIAL PERIPHERAL INTERFACE (SPI) MASKS
+ */
+
+/* SPI_CTL Masks */
+#define TIMOD		0x00000003	/* Transfer initiation mode and interrupt generation */
+#define SZ		0x00000004	/* Send Zero (=0) or last (=1) word when TDBR empty. */
+#define GM		0x00000008	/* When RDBR full, get more (=1) data or discard (=0) incoming Data */
+#define PSSE		0x00000010	/* Enable (=1) Slave-Select input for Master. */
+#define EMISO		0x00000020	/* Enable (=1) MISO pin as an output. */
+#define SIZE		0x00000100	/* Word length (0 => 8 bits, 1 => 16 bits) */
+#define LSBF		0x00000200	/* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
+
+/* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer.*/
+#define CPHA		0x00000400
+#define CPOL		0x00000800	/* Clock polarity (0 => active-high, 1 => active-low) */
+#define MSTR		0x00001000	/* Configures SPI as master (=1) or slave (=0) */
+#define WOM		0x00002000	/* Open drain (=1) data output enable (for MOSI and MISO) */
+#define SPE		0x00004000	/* SPI module enable (=1), disable (=0) */
+
+/* SPI_FLG Masks */
+#define FLS1		0x00000002	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2		0x00000004	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3		0x00000008	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4		0x00000010	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5		0x00000020	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6		0x00000040	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7		0x00000080	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1		0x00000200	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2		0x00000400	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3		0x00000800	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4		0x00001000	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5		0x00002000	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6		0x00004000	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7		0x00008000	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_FLG Bit Positions */
+#define FLS1_P		0x00000001	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P		0x00000002	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P		0x00000003	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P		0x00000004	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P		0x00000005	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P		0x00000006	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P		0x00000007	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P		0x00000009	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2_P		0x0000000A	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P		0x0000000B	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4_P		0x0000000C	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5_P		0x0000000D	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6_P		0x0000000E	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7_P		0x0000000F	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_STAT Masks */
+#define SPIF		0x00000001	/* Set (=1) when SPI single-word transfer complete */
+#define MODF		0x00000002	/* Set (=1) in a master device when some other device tries to become master */
+#define TXE		0x00000004	/* Set (=1) when transmission occurs with no new data in SPI_TDBR */
+#define TXS		0x00000008	/* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
+#define RBSY		0x00000010	/* Set (=1) when data is received with RDBR full */
+#define RXS		0x00000020	/* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
+#define TXCOL		0x00000040	/* When set (=1), corrupt data may have been transmitted */
+
+/*
+ * ASYNCHRONOUS MEMORY CONTROLLER MASKS
+ */
+
+/* AMGCTL Masks */
+#define AMCKEN		0x0001		/* Enable CLKOUT */
+#define AMBEN_B0	0x0002		/* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1	0x0004		/* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2	0x0006		/* Enable Asynchronous Memory Banks 0,/ 1, and 2 */
+#define AMBEN_ALL	0x0008		/* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+#define B0_PEN		0x0010		/* Enable 16-bit packing Bank 0 */
+#define B1_PEN		0x0020		/* Enable 16-bit packing Bank 1 */
+#define B2_PEN		0x0040		/* Enable 16-bit packing Bank 2 */
+#define B3_PEN		0x0080		/* Enable 16-bit packing Bank 3 */
+
+/* AMGCTL Bit Positions */
+#define AMCKEN_P	0x00000000	/* Enable CLKOUT */
+#define AMBEN_P0	0x00000001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1	0x00000002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
+#define AMBEN_P2	0x00000003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+#define B0_PEN_P	0x004		/* Enable 16-bit packing Bank 0 */
+#define B1_PEN_P	0x005		/* Enable 16-bit packing Bank 1 */
+#define B2_PEN_P	0x006		/* Enable 16-bit packing Bank 2 */
+#define B3_PEN_P	0x007		/* Enable 16-bit packing Bank 3 */
+
+/* AMBCTL0 Masks */
+#define B0RDYEN		0x00000001	/* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL	0x00000002	/* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1		0x00000004	/* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2		0x00000008	/* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3		0x0000000C	/* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4		0x00000000	/* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1		0x00000010	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2		0x00000020	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3		0x00000030	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4		0x00000000	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1		0x00000040	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2		0x00000080	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3		0x000000C0	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0		0x00000000	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1		0x00000100	/* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2		0x00000200	/* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3		0x00000300	/* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4		0x00000400	/* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5		0x00000500	/* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6		0x00000600	/* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7		0x00000700	/* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8		0x00000800	/* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9		0x00000900	/* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10	0x00000A00	/* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11	0x00000B00	/* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12	0x00000C00	/* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13	0x00000D00	/* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14	0x00000E00	/* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15	0x00000F00	/* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1		0x00001000	/* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2		0x00002000	/* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3		0x00003000	/* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4		0x00004000	/* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5		0x00005000	/* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6		0x00006000	/* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7		0x00007000	/* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8		0x00008000	/* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9		0x00009000	/* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10	0x0000A000	/* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11	0x0000B000	/* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12	0x0000C000	/* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13	0x0000D000	/* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14	0x0000E000	/* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15	0x0000F000	/* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN		0x00010000	/* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL	0x00020000	/* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1		0x00040000	/* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2		0x00080000	/* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3		0x000C0000	/* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4		0x00000000	/* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1		0x00100000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2		0x00200000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3		0x00300000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4		0x00000000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1		0x00400000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2		0x00800000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3		0x00C00000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0		0x00000000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1		0x01000000	/* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2		0x02000000	/* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3		0x03000000	/* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4		0x04000000	/* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5		0x05000000	/* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6		0x06000000	/* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7		0x07000000	/* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8		0x08000000	/* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9		0x09000000	/* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10	0x0A000000	/* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11	0x0B000000	/* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12	0x0C000000	/* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13	0x0D000000	/* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14	0x0E000000	/* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15	0x0F000000	/* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1		0x10000000	/* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2		0x20000000	/* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3		0x30000000	/* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4		0x40000000	/* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5		0x50000000	/* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6		0x60000000	/* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7		0x70000000	/* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8		0x80000000	/* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9		0x90000000	/* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10	0xA0000000	/* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11	0xB0000000	/* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12	0xC0000000	/* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13	0xD0000000	/* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14	0xE0000000	/* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15	0xF0000000	/* Bank 1 Write Access Time = 15 cycles */
+
+/* AMBCTL1 Masks */
+#define B2RDYEN		0x00000001	/* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL	0x00000002	/* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1		0x00000004	/* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2		0x00000008	/* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3		0x0000000C	/* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4		0x00000000	/* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1		0x00000010	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2		0x00000020	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3		0x00000030	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4		0x00000000	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1		0x00000040	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2		0x00000080	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3		0x000000C0	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0		0x00000000	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1		0x00000100	/* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2		0x00000200	/* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3		0x00000300	/* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4		0x00000400	/* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5		0x00000500	/* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6		0x00000600	/* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7		0x00000700	/* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8		0x00000800	/* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9		0x00000900	/* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10	0x00000A00	/* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11	0x00000B00	/* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12	0x00000C00	/* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13	0x00000D00	/* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14	0x00000E00	/* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15	0x00000F00	/* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1		0x00001000	/* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2		0x00002000	/* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3		0x00003000	/* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4		0x00004000	/* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5		0x00005000	/* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6		0x00006000	/* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7		0x00007000	/* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8		0x00008000	/* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9		0x00009000	/* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10	0x0000A000	/* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11	0x0000B000	/* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12	0x0000C000	/* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13	0x0000D000	/* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14	0x0000E000	/* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15	0x0000F000	/* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN		0x00010000	/* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL	0x00020000	/* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1		0x00040000	/* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2		0x00080000	/* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3		0x000C0000	/* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4		0x00000000	/* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1		0x00100000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2		0x00200000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3		0x00300000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4		0x00000000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1		0x00400000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2		0x00800000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3		0x00C00000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0		0x00000000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1		0x01000000	/* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2		0x02000000	/* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3		0x03000000	/* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4		0x04000000	/* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5		0x05000000	/* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6		0x06000000	/* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7		0x07000000	/* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8		0x08000000	/* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9		0x09000000	/* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10	0x0A000000	/* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11	0x0B000000	/* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12	0x0C000000	/* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13	0x0D000000	/* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14	0x0E000000	/* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15	0x0F000000	/* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1		0x10000000	/* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2		0x20000000	/* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3		0x30000000	/* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4		0x40000000	/* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5		0x50000000	/* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6		0x60000000	/* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7		0x70000000	/* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8		0x80000000	/* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9		0x90000000	/* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10	0xA0000000	/* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11	0xB0000000	/* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12	0xC0000000	/* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13	0xD0000000	/* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14	0xE0000000	/* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15	0xF0000000	/* Bank 3 Write Access Time = 15 cycles */
+
+/*
+ * SDRAM CONTROLLER MASKS
+ */
+
+/* EBIU_SDGCTL Masks */
+#define SCTLE		0x00000001	/* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2		0x00000008	/* SDRAM CAS latency = 2 cycles */
+#define CL_3		0x0000000C	/* SDRAM CAS latency = 3 cycles */
+#define PFE		0x00000010	/* Enable SDRAM prefetch */
+#define PFP		0x00000020	/* Prefetch has priority over AMC requests */
+#define TRAS_1		0x00000040	/* SDRAM tRAS = 1 cycle */
+#define TRAS_2		0x00000080	/* SDRAM tRAS = 2 cycles */
+#define TRAS_3		0x000000C0	/* SDRAM tRAS = 3 cycles */
+#define TRAS_4		0x00000100	/* SDRAM tRAS = 4 cycles */
+#define TRAS_5		0x00000140	/* SDRAM tRAS = 5 cycles */
+#define TRAS_6		0x00000180	/* SDRAM tRAS = 6 cycles */
+#define TRAS_7		0x000001C0	/* SDRAM tRAS = 7 cycles */
+#define TRAS_8		0x00000200	/* SDRAM tRAS = 8 cycles */
+#define TRAS_9		0x00000240	/* SDRAM tRAS = 9 cycles */
+#define TRAS_10		0x00000280	/* SDRAM tRAS = 10 cycles */
+#define TRAS_11		0x000002C0	/* SDRAM tRAS = 11 cycles */
+#define TRAS_12		0x00000300	/* SDRAM tRAS = 12 cycles */
+#define TRAS_13		0x00000340	/* SDRAM tRAS = 13 cycles */
+#define TRAS_14		0x00000380	/* SDRAM tRAS = 14 cycles */
+#define TRAS_15		0x000003C0	/* SDRAM tRAS = 15 cycles */
+#define TRP_1		0x00000800	/* SDRAM tRP = 1 cycle */
+#define TRP_2		0x00001000	/* SDRAM tRP = 2 cycles */
+#define TRP_3		0x00001800	/* SDRAM tRP = 3 cycles */
+#define TRP_4		0x00002000	/* SDRAM tRP = 4 cycles */
+#define TRP_5		0x00002800	/* SDRAM tRP = 5 cycles */
+#define TRP_6		0x00003000	/* SDRAM tRP = 6 cycles */
+#define TRP_7		0x00003800	/* SDRAM tRP = 7 cycles */
+#define TRCD_1		0x00008000	/* SDRAM tRCD = 1 cycle */
+#define TRCD_2		0x00010000	/* SDRAM tRCD = 2 cycles */
+#define TRCD_3		0x00018000	/* SDRAM tRCD = 3 cycles */
+#define TRCD_4		0x00020000	/* SDRAM tRCD = 4 cycles */
+#define TRCD_5		0x00028000	/* SDRAM tRCD = 5 cycles */
+#define TRCD_6		0x00030000	/* SDRAM tRCD = 6 cycles */
+#define TRCD_7		0x00038000	/* SDRAM tRCD = 7 cycles */
+#define TWR_1		0x00080000	/* SDRAM tWR = 1 cycle */
+#define TWR_2		0x00100000	/* SDRAM tWR = 2 cycles */
+#define TWR_3		0x00180000	/* SDRAM tWR = 3 cycles */
+#define PUPSD		0x00200000	/* Power-up start delay */
+#define PSM		0x00400000	/* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS		0x00800000	/* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS		0x01000000	/* Start SDRAM self-refresh mode */
+#define EBUFE		0x02000000	/* Enable external buffering timing */
+#define FBBRW		0x04000000	/* Fast back-to-back read write enable */
+#define EMREN		0x10000000	/* Extended mode register enable */
+#define TCSR		0x20000000	/* Temp compensated self refresh value 85 deg C */
+#define CDDBG		0x40000000	/* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EB0_E		0x00000001	/* Enable SDRAM external bank 0 */
+#define EB0_SZ_16	0x00000000	/* SDRAM external bank size = 16MB */
+#define EB0_SZ_32	0x00000002	/* SDRAM external bank size = 32MB */
+#define EB0_SZ_64	0x00000004	/* SDRAM external bank size = 64MB */
+#define EB0_SZ_128	0x00000006	/* SDRAM external bank size = 128MB */
+#define EB0_CAW_8	0x00000000	/* SDRAM external bank column address width = 8 bits */
+#define EB0_CAW_9	0x00000010	/* SDRAM external bank column address width = 9 bits */
+#define EB0_CAW_10	0x00000020	/* SDRAM external bank column address width = 9 bits */
+#define EB0_CAW_11	0x00000030	/* SDRAM external bank column address width = 9 bits */
+
+#define EB1_E		0x00000100	/* Enable SDRAM external bank 1 */
+#define EB1__SZ_16	0x00000000	/* SDRAM external bank size = 16MB */
+#define EB1__SZ_32	0x00000200	/* SDRAM external bank size = 32MB */
+#define EB1__SZ_64	0x00000400	/* SDRAM external bank size = 64MB */
+#define EB1__SZ_128	0x00000600	/* SDRAM external bank size = 128MB */
+#define EB1__CAW_8	0x00000000	/* SDRAM external bank column address width = 8 bits */
+#define EB1__CAW_9	0x00001000	/* SDRAM external bank column address width = 9 bits */
+#define EB1__CAW_10	0x00002000	/* SDRAM external bank column address width = 9 bits */
+#define EB1__CAW_11	0x00003000	/* SDRAM external bank column address width = 9 bits */
+
+#define EB2__E		0x00010000	/* Enable SDRAM external bank 2 */
+#define EB2__SZ_16	0x00000000	/* SDRAM external bank size = 16MB */
+#define EB2__SZ_32	0x00020000	/* SDRAM external bank size = 32MB */
+#define EB2__SZ_64	0x00040000	/* SDRAM external bank size = 64MB */
+#define EB2__SZ_128	0x00060000	/* SDRAM external bank size = 128MB */
+#define EB2__CAW_8	0x00000000	/* SDRAM external bank column address width = 8 bits */
+#define EB2__CAW_9	0x00100000	/* SDRAM external bank column address width = 9 bits */
+#define EB2__CAW_10	0x00200000	/* SDRAM external bank column address width = 9 bits */
+#define EB2__CAW_11	0x00300000	/* SDRAM external bank column address width = 9 bits */
+
+#define EB3__E		0x01000000	/* Enable SDRAM external bank 3 */
+#define EB3__SZ_16	0x00000000	/* SDRAM external bank size = 16MB */
+#define EB3__SZ_32	0x02000000	/* SDRAM external bank size = 32MB */
+#define EB3__SZ_64	0x04000000	/* SDRAM external bank size = 64MB */
+#define EB3__SZ_128	0x06000000	/* SDRAM external bank size = 128MB */
+#define EB3__CAW_8	0x00000000	/* SDRAM external bank column address width = 8 bits */
+#define EB3__CAW_9	0x10000000	/* SDRAM external bank column address width = 9 bits */
+#define EB3__CAW_10	0x20000000	/* SDRAM external bank column address width = 9 bits */
+#define EB3__CAW_11	0x30000000	/* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI		0x00000001	/* SDRAM controller is idle */
+#define SDSRA		0x00000002	/* SDRAM SDRAM self refresh is active */
+#define SDPUA		0x00000004	/* SDRAM power up active */
+#define SDRS		0x00000008	/* SDRAM is in reset state */
+#define SDEASE		0x00000010	/* SDRAM EAB sticky error status - W1C */
+#define BGSTAT		0x00000020	/* Bus granted */
+
+#define COREMMR_BASE	0xFFE00000	/* Core MMRs */
+#define SYSMMR_BASE	0xFFC00000	/* System MMRs */
+
+/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
+#define WDOG_CTL 	0xFFC00200	/* Watchdog Control register */
+#define WDOG_CNT 	0xFFC00204	/* Watchdog Count register */
+#define WDOG_STAT 	0xFFC00208	/* Watchdog Status register */
+
+/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
+#define FIO_FLAG_D 	0xFFC00700	/* Flag Data register */
+#define FIO_FLAG_C 	0xFFC00704	/* Flag Clear register */
+#define FIO_FLAG_S 	0xFFC00708	/* Flag Set register */
+#define FIO_FLAG_T 	0xFFC0070C	/* Flag Toggle register */
+#define FIO_MASKA_D 	0xFFC00710	/* Flag Mask Interrupt A Data register */
+#define FIO_MASKA_C 	0xFFC00714	/* Flag Mask Interrupt A Clear register */
+#define FIO_MASKA_S 	0xFFC00718	/* Flag Mask Interrupt A Set register */
+#define FIO_MASKA_T 	0xFFC0071C	/* Flag Mask Interrupt A Toggle register */
+#define FIO_MASKB_D 	0xFFC00720	/* Flag Mask Interrupt B Data register */
+#define FIO_MASKB_C 	0xFFC00724	/* Flag Mask Interrupt B Clear register */
+#define FIO_MASKB_S 	0xFFC00728	/* Flag Mask Interrupt B Set register */
+#define FIO_MASKB_T 	0xFFC0072C	/* Flag Mask Interrupt B Toggle register */
+#define FIO_DIR 	0xFFC00730	/* Flag Direction  register */
+#define FIO_POLAR 	0xFFC00734	/* Flag Polarity register */
+#define FIO_EDGE 	0xFFC00738	/* Flag Interrupt Sensitivity register */
+#define FIO_BOTH 	0xFFC0073C	/* Flag Set on Both Edges register */
+#define FIO_INEN 	0xFFC00740	/* Flag Input Enable register */
+
+/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
+#define PPI_CONTROL 	0xFFC01000	/* PPI0 Control register */
+#define PPI_STATUS 	0xFFC01004	/* PPI0 Status register */
+#define PPI_COUNT 	0xFFC01008	/* PPI0 Transfer Count register */
+#define PPI_DELAY 	0xFFC0100C	/* PPI0 Delay Count register */
+#define PPI_FRAME 	0xFFC01010	/* PPI0 Frame Length register */
+
+/*
+ * System Reset and Interrupt Controller registers for
+ * core A (0xFFC0 0100-0xFFC0 01FF)
+ */
+#define SWRST		0xFFC00100	/* Software Reset register */
+#define SYSCR		0xFFC00104	/* System Reset Configuration register */
+#define RVECT		0xFFC00108	/* SIC Reset Vector Address Register */
+#define SIC_SWRST	0xFFC00100	/* Software Reset register */
+#define SIC_SYSCR	0xFFC00104	/* System Reset Configuration register */
+#define SIC_RVECT	0xFFC00108	/* SIC Reset Vector Address Register */
+#define SIC_IMASK	0xFFC0010C	/* SIC Interrupt Mask register 0 - hack to fix old tests */
+#define SIC_IAR		0xFFC00124	/* SIC Interrupt Assignment Register 0 */
+#define SIC_IAR1	0xFFC00128	/* SIC Interrupt Assignment Register 1 */
+#define SIC_IAR2	0xFFC0012C	/* SIC Interrupt Assignment Register 2 */
+#define SIC_ISR		0xFFC00114	/* SIC Interrupt Status register 0 */
+#define SIC_IWR		0xFFC0011C	/* SIC Interrupt Wakeup-Enable register 0 */
+
+/* EBIU_SDBCTL Masks */
+#define EB_E		0x00000001	/* Enable SDRAM external bank 0 */
+#define EB_SZ_16	0x00000000	/* SDRAM external bank size = 16MB */
+#define EB_SZ_32	0x00000002	/* SDRAM external bank size = 32MB */
+#define EB_SZ_64	0x00000004	/* SDRAM external bank size = 64MB */
+#define EB_SZ_128	0x00000006	/* SDRAM external bank size = 128MB */
+#define EB_CAW_8	0x00000000	/* SDRAM external bank column address width = 8 bits */
+#define EB_CAW_9	0x00000010	/* SDRAM external bank column address width = 9 bits */
+#define EB_CAW_10	0x00000020	/* SDRAM external bank column address width = 9 bits */
+#define EB_CAW_11	0x00000030	/* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDBCTL Masks */
+#define EBE		0x00000001	/* Enable SDRAM external bank 0 */
+#define EBSZ_16		0x00000000	/* SDRAM external bank size = 16MB */
+#define EBSZ_32		0x00000002	/* SDRAM external bank size = 32MB */
+#define EBSZ_64		0x00000004	/* SDRAM external bank size = 64MB */
+#define EBSZ_128	0x00000006	/* SDRAM external bank size = 128MB */
+#define EBCAW_8		0x00000000	/* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9		0x00000010	/* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10	0x00000020	/* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11	0x00000030	/* SDRAM external bank column address width = 9 bits */
+
+/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
+#define MDMA_D0_CONFIG		0xFFC01F08	/* MemDMA1 Stream 0 Destination Configuration */
+#define MDMA_D0_NEXT_DESC_PTR	0xFFC01F00	/* MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA_D0_START_ADDR	0xFFC01F04	/* MemDMA1 Stream 0 Destination Start Address */
+#define MDMA_D0_X_COUNT		0xFFC01F10	/* MemDMA1 Stream 0 Destination Inner-Loop Count */
+#define MDMA_D0_Y_COUNT		0xFFC01F18	/* MemDMA1 Stream 0 Destination Outer-Loop Count */
+#define MDMA_D0_X_MODIFY	0xFFC01F14	/* MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA_D0_Y_MODIFY	0xFFC01F1C	/* MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA_D0_CURR_DESC_PTR	0xFFC01F20	/* MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA_D0_CURR_ADDR	0xFFC01F24	/* MemDMA1 Stream 0 Destination Current Address */
+#define MDMA_D0_CURR_X_COUNT	0xFFC01F30	/* MemDMA1 Stream 0 Dest Current Inner-Loop Count */
+#define MDMA_D0_CURR_Y_COUNT	0xFFC01F38	/* MemDMA1 Stream 0 Dest Current Outer-Loop Count */
+#define MDMA_D0_IRQ_STATUS	0xFFC01F28	/* MemDMA1 Stream 0 Destination Interrupt/Status */
+#define MDMA_D0_PERIPHERAL_MAP	0xFFC01F2C	/* MemDMA1 Stream 0 Destination Peripheral Map */
+
+#define MDMA_S0_CONFIG		0xFFC01F48	/* MemDMA1 Stream 0 Source Configuration */
+#define MDMA_S0_NEXT_DESC_PTR	0xFFC01F40	/* MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA_S0_START_ADDR	0xFFC01F44	/* MemDMA1 Stream 0 Source Start Address */
+#define MDMA_S0_X_COUNT		0xFFC01F50	/* MemDMA1 Stream 0 Source Inner-Loop Count */
+#define MDMA_S0_Y_COUNT		0xFFC01F58	/* MemDMA1 Stream 0 Source Outer-Loop Count */
+#define MDMA_S0_X_MODIFY	0xFFC01F54	/* MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
+#define MDMA_S0_Y_MODIFY	0xFFC01F5C	/* MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
+#define MDMA_S0_CURR_DESC_PTR	0xFFC01F60	/* MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA_S0_CURR_ADDR	0xFFC01F64	/* MemDMA1 Stream 0 Source Current Address */
+#define MDMA_S0_CURR_X_COUNT	0xFFC01F70	/* MemDMA1 Stream 0 Source Current Inner-Loop Count */
+#define MDMA_S0_CURR_Y_COUNT `	0xFFC01F78	/* MemDMA1 Stream 0 Source Current Outer-Loop Count */
+#define MDMA_S0_IRQ_STATUS	0xFFC01F68	/* MemDMA1 Stream 0 Source Interrupt/Status */
+#define MDMA_S0_PERIPHERAL_MAP	0xFFC01F6C	/* MemDMA1 Stream 0 Source Peripheral Map */
+
+#define MDMA_D1_CONFIG		0xFFC01F88	/* MemDMA1 Stream 1 Destination Configuration */
+#define MDMA_D1_NEXT_DESC_PTR	0xFFC01F80	/* MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA_D1_START_ADDR	0xFFC01F84	/* MemDMA1 Stream 1 Destination Start Address */
+#define MDMA_D1_X_COUNT		0xFFC01F90	/* MemDMA1 Stream 1 Destination Inner-Loop Count */
+#define MDMA_D1_Y_COUNT		0xFFC01F98	/* MemDMA1 Stream 1 Destination Outer-Loop Count */
+#define MDMA_D1_X_MODIFY	0xFFC01F94	/* MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA_D1_Y_MODIFY	0xFFC01F9C	/* MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA_D1_CURR_DESC_PTR	0xFFC01FA0	/* MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
+#define MDMA_D1_CURR_ADDR	0xFFC01FA4	/* MemDMA1 Stream 1 Dest Current Address */
+#define MDMA_D1_CURR_X_COUNT	0xFFC01FB0	/* MemDMA1 Stream 1 Dest Current Inner-Loop Count */
+#define MDMA_D1_CURR_Y_COUNT	0xFFC01FB8	/* MemDMA1 Stream 1 Dest Current Outer-Loop Count */
+#define MDMA_D1_IRQ_STATUS	0xFFC01FA8	/* MemDMA1 Stream 1 Dest Interrupt/Status */
+#define MDMA_D1_PERIPHERAL_MAP	0xFFC01FAC	/* MemDMA1 Stream 1 Dest Peripheral Map */
+
+#define MDMA_S1_CONFIG		0xFFC01FC8	/* MemDMA1 Stream 1 Source Configuration */
+#define MDMA_S1_NEXT_DESC_PTR	0xFFC01FC0	/* MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA_S1_START_ADDR	0xFFC01FC4	/* MemDMA1 Stream 1 Source Start Address */
+#define MDMA_S1_X_COUNT		0xFFC01FD0	/* MemDMA1 Stream 1 Source Inner-Loop Count */
+#define MDMA_S1_Y_COUNT		0xFFC01FD8	/* MemDMA1 Stream 1 Source Outer-Loop Count */
+#define MDMA_S1_X_MODIFY	0xFFC01FD4	/* MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
+#define MDMA_S1_Y_MODIFY	0xFFC01FDC	/* MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA_S1_CURR_DESC_PTR	0xFFC01FE0	/* MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA_S1_CURR_ADDR	0xFFC01FE4	/* MemDMA1 Stream 1 Source Current Address */
+#define MDMA_S1_CURR_X_COUNT	0xFFC01FF0	/* MemDMA1 Stream 1 Source Current Inner-Loop Count */
+#define MDMA_S1_CURR_Y_COUNT	0xFFC01FF8	/* MemDMA1 Stream 1 Source Current Outer-Loop Count */
+#define MDMA_S1_IRQ_STATUS	0xFFC01FE8	/* MemDMA1 Stream 1 Source Interrupt/Status */
+#define MDMA_S1_PERIPHERAL_MAP	0xFFC01FEC	/* MemDMA1 Stream 1 Source Peripheral Map */
+
+#define DMA0_CONFIG		0xFFC01C08	/* DMA1 Channel 0 Configuration register */
+#define DMA0_NEXT_DESC_PTR	0xFFC01C00	/* DMA1 Channel 0 Next Descripter Ptr Reg */
+#define DMA0_START_ADDR		0xFFC01C04	/* DMA1 Channel 0 Start Address */
+#define DMA0_X_COUNT		0xFFC01C10	/* DMA1 Channel 0 Inner Loop Count */
+#define DMA0_Y_COUNT		0xFFC01C18	/* DMA1 Channel 0 Outer Loop Count */
+#define DMA0_X_MODIFY		0xFFC01C14	/* DMA1 Channel 0 Inner Loop Addr Increment */
+#define DMA0_Y_MODIFY		0xFFC01C1C	/* DMA1 Channel 0 Outer Loop Addr Increment */
+#define DMA0_CURR_DESC_PTR	0xFFC01C20	/* DMA1 Channel 0 Current Descriptor Pointer */
+#define DMA0_CURR_ADDR		0xFFC01C24	/* DMA1 Channel 0 Current Address Pointer */
+#define DMA0_CURR_X_COUNT	0xFFC01C30	/* DMA1 Channel 0 Current Inner Loop Count */
+#define DMA0_CURR_Y_COUNT	0xFFC01C38	/* DMA1 Channel 0 Current Outer Loop Count */
+#define DMA0_IRQ_STATUS		0xFFC01C28	/* DMA1 Channel 0 Interrupt Status Register */
+#define DMA0_PERIPHERAL_MAP	0xFFC01C2C	/* DMA1 Channel 0 Peripheral Map Register */
+
+#define DMA1_CONFIG		0xFFC00C08	/* DMA2 Channel 0 Configuration register */
+#define DMA1_NEXT_DESC_PTR	0xFFC00C00	/* DMA2 Channel 0 Next Descripter Ptr Reg */
+#define DMA1_START_ADDR		0xFFC00C04	/* DMA2 Channel 0 Start Address */
+#define DMA1_X_COUNT		0xFFC00C10	/* DMA2 Channel 0 Inner Loop Count */
+#define DMA1_Y_COUNT		0xFFC00C18	/* DMA2 Channel 0 Outer Loop Count */
+#define DMA1_X_MODIFY		0xFFC00C14	/* DMA2 Channel 0 Inner Loop Addr Increment */
+#define DMA1_Y_MODIFY		0xFFC00C1C	/* DMA2 Channel 0 Outer Loop Addr Increment */
+#define DMA1_CURR_DESC_PTR	0xFFC00C20	/* DMA2 Channel 0 Current Descriptor Pointer */
+#define DMA1_CURR_ADDR		0xFFC00C24	/* DMA2 Channel 0 Current Address Pointer */
+#define DMA1_CURR_X_COUNT	0xFFC00C30	/* DMA2 Channel 0 Current Inner Loop Count */
+#define DMA1_CURR_Y_COUNT	0xFFC00C38	/* DMA2 Channel 0 Current Outer Loop Count */
+#define DMA1_IRQ_STATUS		0xFFC00C28	/* DMA2 Channel 0 Interrupt /Status Register */
+#define DMA1_PERIPHERAL_MAP	0xFFC00C2C	/* DMA2 Channel 0 Peripheral Map Register */
+
+#define DMA2_CONFIG		0xFFC00C48	/* DMA2 Channel 1 Configuration register */
+#define DMA2_NEXT_DESC_PTR	0xFFC00C40	/* DMA2 Channel 1 Next Descripter Ptr Reg */
+#define DMA2_START_ADDR		0xFFC00C44	/* DMA2 Channel 1 Start Address */
+#define DMA2_X_COUNT		0xFFC00C50	/* DMA2 Channel 1 Inner Loop Count */
+#define DMA2_Y_COUNT		0xFFC00C58	/* DMA2 Channel 1 Outer Loop Count */
+#define DMA2_X_MODIFY		0xFFC00C54	/* DMA2 Channel 1 Inner Loop Addr Increment */
+#define DMA2_Y_MODIFY		0xFFC00C5C	/* DMA2 Channel 1 Outer Loop Addr Increment */
+#define DMA2_CURR_DESC_PTR	0xFFC00C60	/* DMA2 Channel 1 Current Descriptor Pointer */
+#define DMA2_CURR_ADDR		0xFFC00C64	/* DMA2 Channel 1 Current Address Pointer */
+#define DMA2_CURR_X_COUNT	0xFFC00C70	/* DMA2 Channel 1 Current Inner Loop Count */
+#define DMA2_CURR_Y_COUNT	0xFFC00C78	/* DMA2 Channel 1 Current Outer Loop Count */
+#define DMA2_IRQ_STATUS		0xFFC00C68	/* DMA2 Channel 1 Interrupt /Status Register */
+#define DMA2_PERIPHERAL_MAP	0xFFC00C6C	/* DMA2 Channel 1 Peripheral Map Register */
+
+#define DMA3_CONFIG		0xFFC00C88	/* DMA2 Channel 2 Configuration register */
+#define DMA3_NEXT_DESC_PTR	0xFFC00C80	/* DMA2 Channel 2 Next Descripter Ptr Reg */
+#define DMA3_START_ADDR		0xFFC00C84	/* DMA2 Channel 2 Start Address */
+#define DMA3_X_COUNT		0xFFC00C90	/* DMA2 Channel 2 Inner Loop Count */
+#define DMA3_Y_COUNT		0xFFC00C98	/* DMA2 Channel 2 Outer Loop Count */
+#define DMA3_X_MODIFY		0xFFC00C94	/* DMA2 Channel 2 Inner Loop Addr Increment */
+#define DMA3_Y_MODIFY		0xFFC00C9C	/* DMA2 Channel 2 Outer Loop Addr Increment */
+#define DMA3_CURR_DESC_PTR	0xFFC00CA0	/* DMA2 Channel 2 Current Descriptor Pointer */
+#define DMA3_CURR_ADDR		0xFFC00CA4	/* DMA2 Channel 2 Current Address Pointer */
+#define DMA3_CURR_X_COUNT	0xFFC00CB0	/* DMA2 Channel 2 Current Inner Loop Count */
+#define DMA3_CURR_Y_COUNT	0xFFC00CB8	/* DMA2 Channel 2 Current Outer Loop Count */
+#define DMA3_IRQ_STATUS		0xFFC00CA8	/* DMA2 Channel 2 Interrupt /Status Register */
+#define DMA3_PERIPHERAL_MAP	0xFFC00CAC	/* DMA2 Channel 2 Peripheral Map Register */
+
+#define DMA4_CONFIG		0xFFC00CC8	/* DMA2 Channel 3 Configuration register */
+#define DMA4_NEXT_DESC_PTR	0xFFC00CC0	/* DMA2 Channel 3 Next Descripter Ptr Reg */
+#define DMA4_START_ADDR		0xFFC00CC4	/* DMA2 Channel 3 Start Address */
+#define DMA4_X_COUNT		0xFFC00CD0	/* DMA2 Channel 3 Inner Loop Count */
+#define DMA4_Y_COUNT		0xFFC00CD8	/* DMA2 Channel 3 Outer Loop Count */
+#define DMA4_X_MODIFY		0xFFC00CD4	/* DMA2 Channel 3 Inner Loop Addr Increment */
+#define DMA4_Y_MODIFY		0xFFC00CDC	/* DMA2 Channel 3 Outer Loop Addr Increment */
+#define DMA4_CURR_DESC_PTR	0xFFC00CE0	/* DMA2 Channel 3 Current Descriptor Pointer */
+#define DMA4_CURR_ADDR		0xFFC00CE4	/* DMA2 Channel 3 Current Address Pointer */
+#define DMA4_CURR_X_COUNT	0xFFC00CF0	/* DMA2 Channel 3 Current Inner Loop Count */
+#define DMA4_CURR_Y_COUNT	0xFFC00CF8	/* DMA2 Channel 3 Current Outer Loop Count */
+#define DMA4_IRQ_STATUS		0xFFC00CE8	/* DMA2 Channel 3 Interrupt /Status Register */
+#define DMA4_PERIPHERAL_MAP	0xFFC00CEC	/* DMA2 Channel 3 Peripheral Map Register */
+
+#define DMA5_CONFIG		0xFFC00D08	/* DMA2 Channel 4 Configuration register */
+#define DMA5_NEXT_DESC_PTR	0xFFC00D00	/* DMA2 Channel 4 Next Descripter Ptr Reg */
+#define DMA5_START_ADDR		0xFFC00D04	/* DMA2 Channel 4 Start Address */
+#define DMA5_X_COUNT		0xFFC00D10	/* DMA2 Channel 4 Inner Loop Count */
+#define DMA5_Y_COUNT		0xFFC00D18	/* DMA2 Channel 4 Outer Loop Count */
+#define DMA5_X_MODIFY		0xFFC00D14	/* DMA2 Channel 4 Inner Loop Addr Increment */
+#define DMA5_Y_MODIFY		0xFFC00D1C	/* DMA2 Channel 4 Outer Loop Addr Increment */
+#define DMA5_CURR_DESC_PTR	0xFFC00D20	/* DMA2 Channel 4 Current Descriptor Pointer */
+#define DMA5_CURR_ADDR		0xFFC00D24	/* DMA2 Channel 4 Current Address Pointer */
+#define DMA5_CURR_X_COUNT	0xFFC00D30	/* DMA2 Channel 4 Current Inner Loop Count */
+#define DMA5_CURR_Y_COUNT	0xFFC00D38	/* DMA2 Channel 4 Current Outer Loop Count */
+#define DMA5_IRQ_STATUS		0xFFC00D28	/* DMA2 Channel 4 Interrupt /Status Register */
+#define DMA5_PERIPHERAL_MAP	0xFFC00D2C	/* DMA2 Channel 4 Peripheral Map Register */
+
+#define DMA6_CONFIG		0xFFC00D48	/* DMA2 Channel 5 Configuration register */
+#define DMA6_NEXT_DESC_PTR	0xFFC00D40	/* DMA2 Channel 5 Next Descripter Ptr Reg */
+#define DMA6_START_ADDR		0xFFC00D44	/* DMA2 Channel 5 Start Address */
+#define DMA6_X_COUNT		0xFFC00D50	/* DMA2 Channel 5 Inner Loop Count */
+#define DMA6_Y_COUNT		0xFFC00D58	/* DMA2 Channel 5 Outer Loop Count */
+#define DMA6_X_MODIFY		0xFFC00D54	/* DMA2 Channel 5 Inner Loop Addr Increment */
+#define DMA6_Y_MODIFY		0xFFC00D5C	/* DMA2 Channel 5 Outer Loop Addr Increment */
+#define DMA6_CURR_DESC_PTR	0xFFC00D60	/* DMA2 Channel 5 Current Descriptor Pointer */
+#define DMA6_CURR_ADDR		0xFFC00D64	/* DMA2 Channel 5 Current Address Pointer */
+#define DMA6_CURR_X_COUNT	0xFFC00D70	/* DMA2 Channel 5 Current Inner Loop Count */
+#define DMA6_CURR_Y_COUNT	0xFFC00D78	/* DMA2 Channel 5 Current Outer Loop Count */
+#define DMA6_IRQ_STATUS		0xFFC00D68	/* DMA2 Channel 5 Interrupt /Status Register */
+#define DMA6_PERIPHERAL_MAP	0xFFC00D6C	/* DMA2 Channel 5 Peripheral Map Register */
+
+#define DMA7_CONFIG		0xFFC00D88	/* DMA2 Channel 6 Configuration register */
+#define DMA7_NEXT_DESC_PTR	0xFFC00D80	/* DMA2 Channel 6 Next Descripter Ptr Reg */
+#define DMA7_START_ADDR		0xFFC00D84	/* DMA2 Channel 6 Start Address */
+#define DMA7_X_COUNT		0xFFC00D90	/* DMA2 Channel 6 Inner Loop Count */
+#define DMA7_Y_COUNT		0xFFC00D98	/* DMA2 Channel 6 Outer Loop Count */
+#define DMA7_X_MODIFY		0xFFC00D94	/* DMA2 Channel 6 Inner Loop Addr Increment */
+#define DMA7_Y_MODIFY		0xFFC00D9C	/* DMA2 Channel 6 Outer Loop Addr Increment */
+#define DMA7_CURR_DESC_PTR	0xFFC00DA0	/* DMA2 Channel 6 Current Descriptor Pointer */
+#define DMA7_CURR_ADDR		0xFFC00DA4	/* DMA2 Channel 6 Current Address Pointer */
+#define DMA7_CURR_X_COUNT	0xFFC00DB0	/* DMA2 Channel 6 Current Inner Loop Count */
+#define DMA7_CURR_Y_COUNT	0xFFC00DB8	/* DMA2 Channel 6 Current Outer Loop Count */
+#define DMA7_IRQ_STATUS		0xFFC00DA8	/* DMA2 Channel 6 Interrupt /Status Register */
+#define DMA7_PERIPHERAL_MAP	0xFFC00DAC	/* DMA2 Channel 6 Peripheral Map Register */
+
+#define TIMER_ENABLE 		0xFFC00680	/* Timer Enable Register */
+#define TIMER_DISABLE 		0xFFC00684	/* Timer Disable register */
+#define TIMER_STATUS 		0xFFC00688	/* Timer Status register */
+
+/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
+#define WDSIZE8			0x00000000	/* Word Size 8 bits */
+#define WDSIZE16		0x00000004	/* Word Size 16 bits */
+#define WDSIZE32		0x00000008	/* Word Size 32 bits */
+
+#endif				/* _DEF_BF561_H */
diff --git a/include/asm-blackfin/arch-bf561/defBF561_extn.h b/include/asm-blackfin/arch-bf561/defBF561_extn.h
new file mode 100644
index 0000000..b309b74
--- /dev/null
+++ b/include/asm-blackfin/arch-bf561/defBF561_extn.h
@@ -0,0 +1,76 @@
+/*
+ * defBF561_extn.h
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ *
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ */
+
+#ifndef _DEF_BF561_EXTN_H
+#define _DEF_BF561_EXTN_H
+
+#define OFFSET_( x )		((x) & 0x0000FFFF) /* define macro for offset */
+/* Delay inserted for PLL transition */
+#define PLL_DELAY		0x1000
+
+#define L1_ISRAM		0xFFA00000
+#define L1_ISRAM_END		0xFFA10000
+#define DATA_BANKA_SRAM		0xFF800000
+#define DATA_BANKA_SRAM_END	0xFF808000
+#define DATA_BANKB_SRAM		0xFF900000
+#define DATA_BANKB_SRAM_END	0xFF908000
+#define SYSMMR_BASE		0xFFC00000
+#define WDSIZE16		0x00000004
+
+/* Event Vector Table Address */
+#define EVT_EMULATION_ADDR	0xffe02000
+#define EVT_RESET_ADDR		0xffe02004
+#define EVT_NMI_ADDR		0xffe02008
+#define EVT_EXCEPTION_ADDR	0xffe0200c
+#define EVT_GLOBAL_INT_ENB_ADDR	0xffe02010
+#define EVT_HARDWARE_ERROR_ADDR	0xffe02014
+#define EVT_TIMER_ADDR		0xffe02018
+#define EVT_IVG7_ADDR		0xffe0201c
+#define EVT_IVG8_ADDR		0xffe02020
+#define EVT_IVG9_ADDR		0xffe02024
+#define EVT_IVG10_ADDR		0xffe02028
+#define EVT_IVG11_ADDR		0xffe0202c
+#define EVT_IVG12_ADDR		0xffe02030
+#define EVT_IVG13_ADDR		0xffe02034
+#define EVT_IVG14_ADDR		0xffe02038
+#define EVT_IVG15_ADDR		0xffe0203c
+#define EVT_OVERRIDE_ADDR	0xffe02100
+
+/* IMASK Bit values */
+#define IVG15_POS		0x00008000
+#define IVG14_POS		0x00004000
+#define IVG13_POS		0x00002000
+#define IVG12_POS		0x00001000
+#define IVG11_POS		0x00000800
+#define IVG10_POS		0x00000400
+#define IVG9_POS		0x00000200
+#define IVG8_POS		0x00000100
+#define IVG7_POS		0x00000080
+#define IVGTMR_POS		0x00000040
+#define IVGHW_POS		0x00000020
+
+#define WDOG_TMR_DISABLE	(0xAD << 4)
+#define ICTL_RST		0x00000000
+#define ICTL_NMI		0x00000002
+#define ICTL_GP			0x00000004
+#define ICTL_DISABLE		0x00000003
+
+/* Watch Dog timer values setup */
+#define WATCHDOG_DISABLE	WDOG_TMR_DISABLE | ICTL_DISABLE
+
+#endif	/* _DEF_BF561_EXTN_H */
diff --git a/include/asm-blackfin/arch-bf561/irq.h b/include/asm-blackfin/arch-bf561/irq.h
new file mode 100644
index 0000000..2f7dd99
--- /dev/null
+++ b/include/asm-blackfin/arch-bf561/irq.h
@@ -0,0 +1,137 @@
+/*
+ * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ * Changed by HuTao Apr18, 2003
+ *
+ * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
+ *
+ * Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl>
+ * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
+ * Copyright (c) 2004 LG Soft India.
+ * Copyright (c) 2004 HHTech.
+ *
+ * Adapted for BlackFin BF561 by Bas Vermeulen <bas@buyways.nl>
+ * Copyright (c) 2005 BuyWays B.V. (www.buyways.nl)
+ */
+
+#ifndef _BF561_IRQ_H_
+#define _BF561_IRQ_H_
+
+/*
+ * Interrupt source definitions:
+ *	Event Source		Core Event Name	    IRQ No
+ *	Emulation Events		EMU		0
+ *	Reset				RST		1
+ *	NMI				NMI		2
+ *	Exception			EVX		3
+ *	Reserved			--		4
+ *	Hardware Error			IVHW		5
+ *	Core Timer			IVTMR		6
+ *
+ *	PLL Wakeup Interrupt		IVG7		7
+ *	DMA1 Error (generic)		IVG7		8
+ *	DMA2 Error (generic)		IVG7		9
+ *	IMDMA Error (generic)		IVG7		10
+ *	PPI1 Error Interrupt		IVG7		11
+ *	PPI2 Error Interrupt		IVG7		12
+ *	SPORT0 Error Interrupt		IVG7		13
+ *	SPORT1 Error Interrupt		IVG7		14
+ *	SPI Error Interrupt		IVG7		15
+ *	UART Error Interrupt		IVG7		16
+ *	Reserved Interrupt		IVG7		17
+ *
+ *	DMA1 0  Interrupt(PPI1)		IVG8		18
+ *	DMA1 1  Interrupt(PPI2)		IVG8		19
+ *	DMA1 2  Interrupt		IVG8		20
+ *	DMA1 3  Interrupt		IVG8		21
+ *	DMA1 4  Interrupt		IVG8		22
+ *	DMA1 5  Interrupt		IVG8		23
+ *	DMA1 6  Interrupt		IVG8		24
+ *	DMA1 7  Interrupt		IVG8		25
+ *	DMA1 8  Interrupt		IVG8		26
+ *	DMA1 9  Interrupt		IVG8		27
+ *	DMA1 10 Interrupt		IVG8		28
+ *	DMA1 11 Interrupt		IVG8		29
+ *
+ *	DMA2 0  (SPORT0 RX)		IVG9		30
+ *	DMA2 1  (SPORT0 TX)		IVG9		31
+ *	DMA2 2  (SPORT1 RX)		IVG9		32
+ *	DMA2 3  (SPORT2 TX)		IVG9		33
+ *	DMA2 4  (SPI)			IVG9		34
+ *	DMA2 5  (UART RX)		IVG9		35
+ *	DMA2 6  (UART TX)		IVG9		36
+ *	DMA2 7  Interrupt		IVG9		37
+ *	DMA2 8  Interrupt		IVG9		38
+ *	DMA2 9  Interrupt		IVG9		39
+ *	DMA2 10 Interrupt		IVG9		40
+ *	DMA2 11 Interrupt		IVG9		41
+ *
+ *	TIMER 0  Interrupt		IVG10		42
+ *	TIMER 1  Interrupt		IVG10		43
+ *	TIMER 2  Interrupt		IVG10		44
+ *	TIMER 3  Interrupt		IVG10		45
+ *	TIMER 4  Interrupt		IVG10		46
+ *	TIMER 5  Interrupt		IVG10		47
+ *	TIMER 6  Interrupt		IVG10		48
+ *	TIMER 7  Interrupt		IVG10		49
+ *	TIMER 8  Interrupt		IVG10		50
+ *	TIMER 9  Interrupt		IVG10		51
+ *	TIMER 10 Interrupt		IVG10		52
+ *	TIMER 11 Interrupt		IVG10		53
+ *
+ *	Programmable Flags0 A (8)	IVG11		54
+ *	Programmable Flags0 B (8)	IVG11		55
+ *	Programmable Flags1 A (8)	IVG11		56
+ *	Programmable Flags1 B (8)	IVG11		57
+ *	Programmable Flags2 A (8)	IVG11		58
+ *	Programmable Flags2 B (8)	IVG11		59
+ *
+ *	MDMA1 0 write/read INT		IVG8		60
+ *	MDMA1 1 write/read INT		IVG8		61
+ *
+ *	MDMA2 0 write/read INT		IVG9		62
+ *	MDMA2 1 write/read INT		IVG9		63
+ *
+ *	IMDMA 0 write/read INT		IVG12		64
+ *	IMDMA 1 write/read INT		IVG12		65
+ *
+ *	Watch Dog Timer			IVG13		66
+ *
+ *	Reserved interrupt		IVG7		67
+ *	Reserved interrupt		IVG7		68
+ *	Supplemental interrupt 0	IVG7		69
+ *	supplemental interrupt 1	IVG7		70
+ *
+ *	Software Interrupt 1		IVG14		71
+ *	Software Interrupt 2		IVG15		72
+ */
+
+/*
+ * The ABSTRACT IRQ definitions
+ *  the first seven of the following are fixed,
+ *  the rest you change if you need to.
+ */
+/* IVG 0-6 */
+#define	IRQ_EMU			0	/* Emulation */
+#define	IRQ_RST			1	/* Reset */
+#define	IRQ_NMI			2	/* Non Maskable Interrupt */
+#define	IRQ_EVX			3	/* Exception */
+#define	IRQ_UNUSED		4	/* Reserved interrupt */
+#define	IRQ_HWERR		5	/* Hardware Error */
+#define	IRQ_CORETMR		6	/* Core timer */
+
+#define	IRQ_UART_RX_BIT		0x10000000
+#define	IRQ_UART_TX_BIT		0x20000000
+#define	IRQ_UART_ERROR_BIT	0x200
+
+#endif				/* _BF561_IRQ_H_ */
diff --git a/include/asm-blackfin/arch-common/bf53x_rtc.h b/include/asm-blackfin/arch-common/bf53x_rtc.h
new file mode 100644
index 0000000..bc09922
--- /dev/null
+++ b/include/asm-blackfin/arch-common/bf53x_rtc.h
@@ -0,0 +1,46 @@
+/*
+ * U-boot - bf533_rtc.h
+ *
+ * Copyright (c) 2005 blackfin.uclinux.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BF533_RTC_H_
+#define _BF533_RTC_H_
+
+void rtc_init(void);
+void wait_for_complete(void);
+void rtc_reset(void);
+
+#define MIN_TO_SECS(_x_)	(60 * _x_)
+#define HRS_TO_SECS(_x_)	(60 * 60 * _x_)
+#define DAYS_TO_SECS(_x_)	(24 * 60 * 60 * _x_)
+
+#define NUM_SECS_IN_DAY		(24 * 3600)
+#define NUM_SECS_IN_HOUR	(3600)
+#define NUM_SECS_IN_MIN		(60)
+
+/* Shift values for RTC_STAT register */
+#define DAY_BITS_OFF		17
+#define HOUR_BITS_OFF		12
+#define MIN_BITS_OFF		6
+#define SEC_BITS_OFF		0
+
+#endif
diff --git a/include/asm-blackfin/arch-common/cdefBF5xx.h b/include/asm-blackfin/arch-common/cdefBF5xx.h
new file mode 100644
index 0000000..aec70ce
--- /dev/null
+++ b/include/asm-blackfin/arch-common/cdefBF5xx.h
@@ -0,0 +1,40 @@
+/************************************************************************
+ *
+ * cdefBF53x.h
+ *
+ * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
+ *
+ ************************************************************************/
+
+#ifndef _CDEFBF53x_H
+#define _CDEFBF53x_H
+
+#if defined(__ADSPBF531__)
+	#include <asm/arch-bf533/cdefBF531.h>
+#elif defined(__ADSPBF532__)
+	#include <asm/arch-bf533/cdefBF532.h>
+#elif defined(__ADSPBF533__)
+	#include <asm/arch-bf533/cdefBF533.h>
+	#include <asm/arch-bf533/defBF533_extn.h>
+	#include <asm/arch-bf533/bf533_serial.h>
+#elif defined(__ADSPBF537__)
+	#include <asm/arch-bf537/cdefBF537.h>
+	#include <asm/arch-bf537/defBF537_extn.h>
+	#include <asm/arch-bf537/bf537_serial.h>
+#elif defined(__ADSPBF561__)
+	#include <asm/arch-bf561/cdefBF561.h>
+	#include <asm/arch-bf561/defBF561_extn.h>
+	#include <asm/arch-bf561/bf561_serial.h>
+#elif defined(__ADSPBF535__)
+	#include <asm/cpu/cdefBF5d35.h>
+#elif defined(__AD6532__)
+	#include <asm/cpu/cdefAD6532.h>
+#else
+	#if defined(__ADSPLPBLACKFIN__)
+		#include <asm/arch-bf533/cdefBF532.h>
+	#else
+		#include <asm/arch-bf533/cdefBF535.h>
+	#endif
+#endif
+
+#endif	/* _CDEFBF53x_H */
diff --git a/include/asm-blackfin/cpu/cdef_LPBlackfin.h b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h
index e6471cb..90b21e5 100644
--- a/include/asm-blackfin/cpu/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h
@@ -1,38 +1,24 @@
-/*
- * cdef_LPBlackfin.h
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
+/************************************************************************
  *
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ * cdef_LPBlackfin.h
  *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@analog.com
+ * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
  *
- */
+ ************************************************************************/
 
 #ifndef _CDEF_LPBLACKFIN_H
 #define _CDEF_LPBLACKFIN_H
 
-/*
- * #if !defined(__ADSPLPBLACKFIN__)
- * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
- * #endif
- */
-#include <asm/cpu/def_LPBlackfin.h>
+#if !defined(__ADSPLPBLACKFIN__)
+#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
+#endif
+#include <asm/arch-common/def_LPBlackfin.h>
 
-/* Cache & SRAM Memory */
+/* Cache & SRAM Memory	*/
 #define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
 #define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
 #define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
 #define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
-
-/* #define MMR_TIMEOUT 0xFFE00010 */	/* Memory-Mapped Register Timeout Register */
 #define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
 #define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
 #define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
@@ -66,15 +52,8 @@
 #define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
 #define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
 #define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
-
-/* #define DTEST_INDEX            0xFFE00304 */ 	/* Data Test Index Register */
 #define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
 #define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
-
-/*
- * # define DTEST_DATA2	0xFFE00408   Data Test Data Register
- * #define DTEST_DATA3	0xFFE0040C   Data Test Data Register
- */
 #define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
 #define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
 #define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
@@ -111,8 +90,6 @@
 #define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
 #define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
 #define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
-
-/* #define ITEST_INDEX 0xFFE01304 */	/* Instruction Test Index Register */
 #define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
 #define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
 
@@ -180,6 +157,4 @@
 #define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
 #define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
 
-/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */
-
-#endif	/* _CDEF_LPBLACKFIN_H */
+#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/arch-common/def_LPBlackfin.h
index 9ac78c8..ebeeea0 100644
--- a/include/asm-blackfin/cpu/def_LPBlackfin.h
+++ b/include/asm-blackfin/arch-common/def_LPBlackfin.h
@@ -92,13 +92,13 @@
 
 /* ** Masks */
 /* Exception cause */
-#define SEQSTAT_EXCAUSE		MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
+#define SEQSTAT_EXCAUSE		( MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
 				MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
 				MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
 				MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
 				MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
 				MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
-				0
+				0 )
 
 /* Indicates whether the last reset was a software reset (=1) */
 #define SEQSTAT_SFTRESET	MK_BMSK_(SEQSTAT_SFTRESET_P )
diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h
index 65d2c25..7766c4a 100644
--- a/include/asm-blackfin/bitops.h
+++ b/include/asm-blackfin/bitops.h
@@ -59,7 +59,7 @@ static __inline__ unsigned long ffz(unsigned long word)
 
 static __inline__ void set_bit(int nr, volatile void *addr)
 {
-	int *a = (int *) addr;
+	int *a = (int *)addr;
 	int mask;
 	unsigned long flags;
 
@@ -72,7 +72,7 @@ static __inline__ void set_bit(int nr, volatile void *addr)
 
 static __inline__ void __set_bit(int nr, volatile void *addr)
 {
-	int *a = (int *) addr;
+	int *a = (int *)addr;
 	int mask;
 
 	a += nr >> 5;
@@ -88,7 +88,7 @@ static __inline__ void __set_bit(int nr, volatile void *addr)
 
 static __inline__ void clear_bit(int nr, volatile void *addr)
 {
-	int *a = (int *) addr;
+	int *a = (int *)addr;
 	int mask;
 	unsigned long flags;
 
@@ -102,7 +102,7 @@ static __inline__ void clear_bit(int nr, volatile void *addr)
 static __inline__ void change_bit(int nr, volatile void *addr)
 {
 	int mask, flags;
-	unsigned long *ADDR = (unsigned long *) addr;
+	unsigned long *ADDR = (unsigned long *)addr;
 
 	ADDR += nr >> 5;
 	mask = 1 << (nr & 31);
@@ -114,7 +114,7 @@ static __inline__ void change_bit(int nr, volatile void *addr)
 static __inline__ void __change_bit(int nr, volatile void *addr)
 {
 	int mask;
-	unsigned long *ADDR = (unsigned long *) addr;
+	unsigned long *ADDR = (unsigned long *)addr;
 
 	ADDR += nr >> 5;
 	mask = 1 << (nr & 31);
@@ -124,7 +124,7 @@ static __inline__ void __change_bit(int nr, volatile void *addr)
 static __inline__ int test_and_set_bit(int nr, volatile void *addr)
 {
 	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *) addr;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
 	unsigned long flags;
 
 	a += nr >> 5;
@@ -140,7 +140,7 @@ static __inline__ int test_and_set_bit(int nr, volatile void *addr)
 static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
 {
 	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *) addr;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
 
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
@@ -152,7 +152,7 @@ static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
 static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
 {
 	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *) addr;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
 	unsigned long flags;
 
 	a += nr >> 5;
@@ -168,7 +168,7 @@ static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
 static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
 {
 	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *) addr;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
 
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
@@ -180,7 +180,7 @@ static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
 static __inline__ int test_and_change_bit(int nr, volatile void *addr)
 {
 	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *) addr;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
 	unsigned long flags;
 
 	a += nr >> 5;
@@ -196,7 +196,7 @@ static __inline__ int test_and_change_bit(int nr, volatile void *addr)
 static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
 {
 	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *) addr;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
 
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
@@ -208,16 +208,15 @@ static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
 /*
  * This routine doesn't need to be atomic.
  */
-static __inline__ int __constant_test_bit(int nr,
-					  const volatile void *addr)
+static __inline__ int __constant_test_bit(int nr, const volatile void *addr)
 {
 	return ((1UL << (nr & 31)) &
-		(((const volatile unsigned int *) addr)[nr >> 5])) != 0;
+		(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
 }
 
 static __inline__ int __test_bit(int nr, volatile void *addr)
 {
-	int *a = (int *) addr;
+	int *a = (int *)addr;
 	int mask;
 
 	a += nr >> 5;
@@ -235,7 +234,7 @@ static __inline__ int __test_bit(int nr, volatile void *addr)
 
 static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
 {
-	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
 	unsigned long result = offset & ~31UL;
 	unsigned long tmp;
 
@@ -290,7 +289,7 @@ static __inline__ int ext2_set_bit(int nr, volatile void *addr)
 {
 	int mask, retval;
 	unsigned long flags;
-	volatile unsigned char *ADDR = (unsigned char *) addr;
+	volatile unsigned char *ADDR = (unsigned char *)addr;
 
 	ADDR += nr >> 3;
 	mask = 1 << (nr & 0x07);
@@ -305,7 +304,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
 {
 	int mask, retval;
 	unsigned long flags;
-	volatile unsigned char *ADDR = (unsigned char *) addr;
+	volatile unsigned char *ADDR = (unsigned char *)addr;
 
 	ADDR += nr >> 3;
 	mask = 1 << (nr & 0x07);
@@ -319,7 +318,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
 static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
 {
 	int mask;
-	const volatile unsigned char *ADDR = (const unsigned char *) addr;
+	const volatile unsigned char *ADDR = (const unsigned char *)addr;
 
 	ADDR += nr >> 3;
 	mask = 1 << (nr & 0x07);
@@ -331,10 +330,9 @@ static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
 
 static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
 							unsigned long size,
-							unsigned long
-							offset)
+							unsigned long offset)
 {
-	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
 	unsigned long result = offset & ~31UL;
 	unsigned long tmp;
 
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
index fbdbf30..0ec9207 100644
--- a/include/asm-blackfin/blackfin.h
+++ b/include/asm-blackfin/blackfin.h
@@ -25,22 +25,16 @@
 #ifndef _BLACKFIN_H_
 #define _BLACKFIN_H_
 
-#include <asm/cpu/defBF533.h>
-#include <asm/cpu/bf533_serial.h>
+#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
+# ifdef SHARED_RESOURCES
+#  include <asm/shared_resources.h>
+# endif
 
-#ifndef __ASSEMBLY__
-#ifndef ASSEMBLY
+# include <linux/types.h>
 
-#ifdef SHARED_RESOURCES
- #include <asm/shared_resources.h>
+extern u_long get_sclk(void);
 #endif
-#include <asm/cpu/cdefBF53x.h>
 
-#endif
-#endif
-
-#include <asm/cpu/defBF533.h>
-#include <asm/cpu/defBF533_extn.h>
-#include <asm/cpu/bf533_serial.h>
+#include <asm/arch-common/cdefBF5xx.h>
 
 #endif
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 7715f64..dd695e1 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -7,14 +7,15 @@
  ************************************************************************/
 
 /* Defines necessary for cplb initialisation routines. */
-
 #ifndef _CPLB_H
 #define _CPLB_H
 
+#define CONFIG_BLKFIN_WT
+
 #define CPLB_ENABLE_ICACHE_P	0
 #define CPLB_ENABLE_DCACHE_P	1
 #define CPLB_ENABLE_DCACHE2_P	2
-#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated!*/
+#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated! */
 #define CPLB_ENABLE_ICPLBS_P	4
 #define CPLB_ENABLE_DCPLBS_P	5
 
@@ -45,4 +46,35 @@
 #define CPLB_INOCACHE   	CPLB_USER_RD | CPLB_VALID
 #define CPLB_IDOCACHE   	CPLB_INOCACHE | CPLB_L1_CHBL
 
-#endif /* _CPLB_H */
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158                0x200
+
+#ifdef CONFIG_BLKFIN_WB		/*Write Back Policy */
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+
+#else				/*Write Through */
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
+#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
+#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
+#endif
+
+#if defined(CONFIG_BF561)
+#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2)	/* SDRAM +L1 + ASYNC_Memory */
+#else
+#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 3)	/* SDRAM + L1 + ASYNC_Memory */
+#endif
+#endif				/* _CPLB_H */
diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h
deleted file mode 100644
index ab7d989..0000000
--- a/include/asm-blackfin/cplbtab.h
+++ /dev/null
@@ -1,572 +0,0 @@
-/*This file is subject to the terms and conditions of the GNU General Public
- * License.
- *
- * Blackfin BF533/2.6 support : LG Soft India
- * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
- * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
- *	        shouldn't be victimized. cplbmgr.S search logic is corrected
- *	        to findout the appropriate victim.
- *	     2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
- *	     : LG Soft India
- */
-#include <config.h>
-
-#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
-#define __ARCH_BFINNOMMU_CPLBTAB_H
-
-/*************************************************************************
- *  			ICPLB TABLE
- *************************************************************************/
-
-.data
-
-/* This table is configurable */
-
-.align 4;
-
-/* Data Attibutes*/
-
-#define SDRAM_IGENERIC		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
-#define SDRAM_IKERNEL		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define L1_IMEMORY            	(PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL		(PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
-
-/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
-
-#define ANOMALY_05000158		0x200
-#ifdef CONFIG_BLKFIN_WB 	/*Write Back Policy */
-	#define SDRAM_DGENERIC  	(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-	#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-	#define SDRAM_DKERNEL 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
-	#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-	#define SDRAM_EBIU		(PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-
-#else  /*Write Through*/
-	#define SDRAM_DGENERIC 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-	#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
-	#define SDRAM_DKERNEL 		(PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
-	#define L1_DMEMORY		(PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
-	#define SDRAM_EBIU		(PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
-#endif
-
-.global icplb_table
-icplb_table:
-.byte4 0xFFA00000;
-.byte4 (L1_IMEMORY);
-.byte4 0x00000000;
-.byte4 (SDRAM_IKERNEL);			/*SDRAM_Page1*/
-.byte4 0x00400000;
-.byte4 (SDRAM_IKERNEL);		/*SDRAM_Page1*/
-.byte4 0x07C00000;
-.byte4 (SDRAM_IKERNEL);		/*SDRAM_Page14*/
-.byte4 0x00800000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page2*/
-.byte4 0x00C00000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page2*/
-.byte4 0x01000000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page4*/
-.byte4 0x01400000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page5*/
-.byte4 0x01800000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page6*/
-.byte4 0x01C00000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page7*/
-#ifndef CONFIG_EZKIT			/*STAMP Memory regions*/
-.byte4 0x02000000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page8*/
-.byte4 0x02400000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page9*/
-.byte4 0x02800000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page10*/
-.byte4 0x02C00000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page11*/
-.byte4 0x03000000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page12*/
-.byte4 0x03400000;
-.byte4 (SDRAM_IGENERIC);		/*SDRAM_Page13*/
-#endif
-.byte4 0xffffffff;			/* end of section - termination*/
-
-.align 4;
-.global ipdt_table
-ipdt_table:
-#ifdef CONFIG_CPLB_INFO
-.byte4 0x00000000;
-.byte4 (SDRAM_IKERNEL);               /*SDRAM_Page0*/
-.byte4 0x00400000;
-.byte4 (SDRAM_IKERNEL);               /*SDRAM_Page1*/
-#endif
-.byte4 0x00800000;
-.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page2*/
-.byte4 0x00C00000;
-.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page3*/
-.byte4 0x01000000;
-.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page4*/
-.byte4 0x01400000;
-.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page5*/
-.byte4 0x01800000;
-.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page6*/
-.byte4 0x01C00000;
-.byte4 (SDRAM_IGENERIC);              /*SDRAM_Page7*/
-#ifndef CONFIG_EZKIT                  /*STAMP Memory regions*/
-.byte4  0x02000000;
-.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page8*/
-.byte4  0x02400000;
-.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page9*/
-.byte4  0x02800000;
-.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page10*/
-.byte4  0x02C00000;
-.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page11*/
-.byte4  0x03000000;
-.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page12*/
-.byte4  0x03400000;
-.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page13*/
-.byte4  0x03800000;
-.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page14*/
-.byte4  0x03C00000;
-.byte4  (SDRAM_IGENERIC);              /*SDRAM_Page15*/
-#endif
-.byte4  0x20200000;
-.byte4  (SDRAM_EBIU);      /* Async Memory Bank 2 (Secnd)*/
-.byte4  0x20100000;
-.byte4  (SDRAM_EBIU);      /* Async Memory Bank 1 (Prim B)*/
-.byte4  0x20000000;
-.byte4  (SDRAM_EBIU);      /* Async Memory Bank 0 (Prim A)*/
-.byte4  0x20300000;             /*Fix for Network*/
-.byte4  (SDRAM_EBIU);    /*Async Memory bank 3*/
-
-#ifdef CONFIG_STAMP
-.byte4        0x04000000;
-.byte4  (SDRAM_IGENERIC);
-.byte4        0x04400000;
-.byte4  (SDRAM_IGENERIC);
-.byte4        0x04800000;
-.byte4  (SDRAM_IGENERIC);
-.byte4        0x04C00000;
-.byte4  (SDRAM_IGENERIC);
-.byte4        0x05000000;
-.byte4  (SDRAM_IGENERIC);
-.byte4        0x05400000;
-.byte4  (SDRAM_IGENERIC);
-.byte4        0x05800000;
-.byte4  (SDRAM_IGENERIC);
-.byte4        0x05C00000;
-.byte4  (SDRAM_IGENERIC);
-.byte4        0x06000000;
-.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page25*/
-.byte4        0x06400000;
-.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page26*/
-.byte4        0x06800000;
-.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page27*/
-.byte4        0x06C00000;
-.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page28*/
-.byte4        0x07000000;
-.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page29*/
-.byte4        0x07400000;
-.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page30*/
-.byte4        0x07800000;
-.byte4  (SDRAM_IGENERIC);       /*SDRAM_Page31*/
-#ifdef CONFIG_CPLB_INFO
-.byte4        0x07C00000;
-.byte4  (SDRAM_IKERNEL);        /*SDRAM_Page32*/
-#endif
-#endif
-.byte4 0xffffffff;                    /* end of section - termination*/
-
-/*********************************************************************
- *			DCPLB TABLE
- ********************************************************************/
-
-.global dcplb_table
-dcplb_table:
-.byte4	0x00000000;
-.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page1*/
-.byte4	0x00400000;
-.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page1*/
-.byte4	0x07C00000;
-.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page15*/
-.byte4	0x00800000;
-.byte4 	(SDRAM_DGENERIC);	/*SDRAM_Page2*/
-.byte4 	0x00C00000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page3*/
-.byte4	0x01000000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page4*/
-.byte4	0x01400000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page5*/
-.byte4	0x01800000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page6*/
-.byte4	0x01C00000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page7*/
-#ifndef CONFIG_EZKIT
-.byte4	0x02000000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page8*/
-.byte4	0x02400000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page9*/
-.byte4	0x02800000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page10*/
-.byte4	0x02C00000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page11*/
-.byte4	0x03000000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page12*/
-.byte4	0x03400000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page13*/
-.byte4	0x03800000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page14*/
-#endif
-.byte4	0xffffffff;		/*end of section - termination*/
-
-/**********************************************************************
- *		PAGE DESCRIPTOR TABLE
- *
- **********************************************************************/
-
-/* Till here we are discussing about the static memory management model.
- * However, the operating envoronments commonly define more CPLB
- * descriptors to cover the entire addressable memory than will fit into
- * the available on-chip 16 CPLB MMRs. When this happens, the below table
- * will be used which will hold all the potentially required CPLB descriptors
- *
- * This is how Page descriptor Table is implemented in uClinux/Blackfin.
- */
-.global dpdt_table
-dpdt_table:
-#ifdef CONFIG_CPLB_INFO
-.byte4        0x00000000;
-.byte4        (SDRAM_DKERNEL);        /*SDRAM_Page0*/
-.byte4        0x00400000;
-.byte4        (SDRAM_DKERNEL);        /*SDRAM_Page1*/
-#endif
-.byte4        0x00800000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page2*/
-.byte4        0x00C00000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page3*/
-.byte4        0x01000000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page4*/
-.byte4        0x01400000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page5*/
-.byte4        0x01800000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page6*/
-.byte4        0x01C00000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page7*/
-
-#ifndef CONFIG_EZKIT
-.byte4        0x02000000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page8*/
-.byte4        0x02400000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page9*/
-.byte4        0x02800000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page10*/
-.byte4        0x02C00000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page11*/
-.byte4        0x03000000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page12*/
-.byte4        0x03400000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page13*/
-.byte4        0x03800000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page14*/
-.byte4        0x03C00000;
-.byte4        (SDRAM_DGENERIC);       /*SDRAM_Page15*/
-#endif
-.byte4	0x20200000;
-.byte4	(SDRAM_EBIU);	/* Async Memory Bank 2 (Secnd)*/
-.byte4	0x20100000;
-.byte4	(SDRAM_EBIU);	/* Async Memory Bank 1 (Prim B)*/
-.byte4	0x20000000;
-.byte4	(SDRAM_EBIU);	/* Async Memory Bank 0 (Prim A)*/
-.byte4	0x20300000;		/*Fix for Network*/
-.byte4  (SDRAM_EBIU);	/*Async Memory bank 3*/
-
-#ifdef CONFIG_STAMP
-.byte4	0x04000000;
-.byte4  (SDRAM_DGENERIC);
-.byte4	0x04400000;
-.byte4  (SDRAM_DGENERIC);
-.byte4	0x04800000;
-.byte4  (SDRAM_DGENERIC);
-.byte4	0x04C00000;
-.byte4  (SDRAM_DGENERIC);
-.byte4	0x05000000;
-.byte4  (SDRAM_DGENERIC);
-.byte4	0x05400000;
-.byte4  (SDRAM_DGENERIC);
-.byte4	0x05800000;
-.byte4  (SDRAM_DGENERIC);
-.byte4	0x05C00000;
-.byte4  (SDRAM_DGENERIC);
-.byte4	0x06000000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page25*/
-.byte4	0x06400000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page26*/
-.byte4	0x06800000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page27*/
-.byte4	0x06C00000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page28*/
-.byte4	0x07000000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page29*/
-.byte4	0x07400000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page30*/
-.byte4	0x07800000;
-.byte4	(SDRAM_DGENERIC);	/*SDRAM_Page31*/
-#ifdef CONFIG_CPLB_INFO
-.byte4	0x07C00000;
-.byte4	(SDRAM_DKERNEL);	/*SDRAM_Page32*/
-#endif
-#endif
-
-.byte4  0xFF900000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF901000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF902000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF903000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF904000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF905000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF906000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF907000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF800000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF801000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF802000;
-.byte4  (L1_DMEMORY);
-.byte4  0xFF803000;
-.byte4  (L1_DMEMORY);
-
-.byte4	0xffffffff;		/*end of section - termination*/
-
-#ifdef CONFIG_CPLB_INFO
-.global ipdt_swapcount_table;	/* swapin count first, then swapout count*/
-ipdt_swapcount_table:
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 10 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 20 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 30 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 40 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 50 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 60 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 70 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 80 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 90 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 100 */
-
-.global dpdt_swapcount_table;	/* swapin count first, then swapout count*/
-dpdt_swapcount_table:
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 10 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 20 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 30 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 40 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 50 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 60 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 70 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 80 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 80 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 100 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 110 */
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;
-.byte4        0x00000000;	/* 120 */
-
-#endif
-
-#endif	/*__ARCH_BFINNOMMU_CPLBTAB_H*/
diff --git a/include/asm-blackfin/cpu/cdefBF53x.h b/include/asm-blackfin/cpu/cdefBF53x.h
deleted file mode 100644
index db4eaa9..0000000
--- a/include/asm-blackfin/cpu/cdefBF53x.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/************************************************************************
- *
- * cdefBF53x.h
- *
- * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _CDEFBF53x_H
-#define _CDEFBF53x_H
-
-#if defined(__ADSPBF531__)
-	#include <asm/cpu/cdefBF531.h>
-#elif defined(__ADSPBF532__)
-	#include <asm/cpu/cdefBF532.h>
-#elif defined(__ADSPBF533__)
-	#include <asm/cpu/cdefBF533.h>
-#elif defined(__ADSPBF561__)
-	#include <asm/cpu/cdefBF561.h>
-#elif defined(__ADSPBF535__)
-	#include <asm/cpu/cdefBF535.h>
-#elif defined(__AD6532__)
-	#include <sam/cpu/cdefAD6532.h>
-#else
-	#if defined(__ADSPLPBLACKFIN__)
-		#include <asm/cpu/cdefBF532.h>
-	#else
-		#include <asm/cpu/cdefBF535.h>
-	#endif
-#endif
-
-#endif	/* _CDEFBF53x_H */
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
index dbb7388..0c01e9f 100644
--- a/include/asm-blackfin/delay.h
+++ b/include/asm-blackfin/delay.h
@@ -35,9 +35,9 @@
 extern __inline__ void __delay(unsigned long loops)
 {
 	__asm__ __volatile__("1:\t%0 += -1;\n\t"
-				"cc = %0 == 0;\n\t"
-				"if ! cc jump 1b;\n":"=d"(loops)
-				:"0"(loops));
+			     "cc = %0 == 0;\n\t"
+			     "if ! cc jump 1b;\n":"=d"(loops)
+			     :"0"(loops));
 }
 
 /*
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
index 607a5b8..b64d406 100644
--- a/include/asm-blackfin/entry.h
+++ b/include/asm-blackfin/entry.h
@@ -370,16 +370,12 @@
 #define STR1(X) 		#X
 
 #if defined(NEW_PT_REGS)
-
 #define PT_OFF_ORIG_R0		208
 #define PT_OFF_SR		8
-
 #else
-
 #define PT_OFF_ORIG_R0		0x54
 #define PT_OFF_SR		0x38	/* seqstat in pt_regs */
-
-#endif
 #endif
 
 #endif
+#endif
diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
index 56a12f0..1c73853 100644
--- a/include/asm-blackfin/global_data.h
+++ b/include/asm-blackfin/global_data.h
@@ -45,11 +45,16 @@ typedef struct global_data {
 	unsigned long board_type;
 	unsigned long baudrate;
 	unsigned long have_console;	/* serial_init() was called */
-	unsigned long ram_size;		/* RAM size */
+	unsigned long ram_size;	/* RAM size */
 	unsigned long reloc_off;	/* Relocation Offset */
-	unsigned long env_addr;		/* Address  of Environment struct */
+	unsigned long env_addr;	/* Address  of Environment struct */
 	unsigned long env_valid;	/* Checksum of Environment valid? */
-	void **jt;			/* jump table */
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+	unsigned long post_log_word;	/* Record POST activities */
+	unsigned long post_init_f_time;	/* When post_init_f started */
+#endif
+
+	void **jt;		/* jump table */
 } gd_t;
 
 /*
@@ -59,6 +64,6 @@ typedef struct global_data {
 #define	GD_FLG_DEVINIT	0x00002	/* Devices have been initialized */
 #define	GD_FLG_SILENT	0x00004	/* Silent mode                   */
 
-#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("P5")
+#define DECLARE_GLOBAL_DATA_PTR     register gd_t * volatile gd asm ("P5")
 
 #endif
diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h
index 1ee050e..baa3e0c 100644
--- a/include/asm-blackfin/hw_irq.h
+++ b/include/asm-blackfin/hw_irq.h
@@ -30,8 +30,14 @@
 
 #include <linux/config.h>
 #ifdef CONFIG_EZKIT533
-#include <asm/board/bf533_irq.h>
+#include <asm/arch-bf533/irq.h>
+#endif
+#ifdef CONFIG_EZKIT561
+#include <asm/arch-bf561/irq.h>
 #endif
 #ifdef CONFIG_STAMP
-#include <asm/board/bf533_irq.h>
+#include <asm/arch-bf533/irq.h>
+#endif
+#ifdef CONFIG_BF537
+#include <asm/arch-bf537/irq.h>
 #endif
diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h
index 0b0572f..3c087c3 100644
--- a/include/asm-blackfin/io-kernel.h
+++ b/include/asm-blackfin/io-kernel.h
@@ -87,7 +87,8 @@
 #define IOMAP_WRITETHROUGH		3
 
 #ifndef __ASSEMBLY__
-extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
+extern void *__ioremap(unsigned long physaddr, unsigned long size,
+		       int cacheflag);
 extern void __iounmap(void *addr, unsigned long size);
 extern inline void *ioremap(unsigned long physaddr, unsigned long size)
 {
@@ -97,11 +98,13 @@ extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
 {
 	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
 }
-extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
+extern inline void *ioremap_writethrough(unsigned long physaddr,
+					 unsigned long size)
 {
 	return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
 }
-extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
+extern inline void *ioremap_fullcache(unsigned long physaddr,
+				      unsigned long size)
 {
 	return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
 }
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index e5b388e..6bab6e7 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -33,7 +33,11 @@
 extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
 extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
 extern unsigned char cf_inb(volatile unsigned char *addr);
-extern void cf_outb(unsigned char val, volatile unsigned char* addr);
+extern void cf_outb(unsigned char val, volatile unsigned char *addr);
+
+static inline void sync(void)
+{
+}
 
 /*
  * These are for ISA/PCI shared memory _only_ and should never be used
@@ -46,7 +50,6 @@ extern void cf_outb(unsigned char val, volatile unsigned char* addr);
  * memory location directly.
  */
 
-
 #define readb(addr)		({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
 #define readw(addr)		({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
 #define readl(addr)		({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
@@ -95,8 +98,7 @@ extern inline void *ioremap(unsigned long physaddr, unsigned long size)
 {
 	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
 }
-extern inline void *ioremap_nocache(unsigned long physaddr,
-				    unsigned long size)
+extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
 {
 	return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
 }
diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
index 5fbc5a3..aede742 100644
--- a/include/asm-blackfin/irq.h
+++ b/include/asm-blackfin/irq.h
@@ -39,7 +39,7 @@
 #define _BLACKFIN_IRQ_H_
 
 #include <linux/config.h>
-#include <asm/cpu/bf533_irq.h>
+#include <asm/hw_irq.h>
 
 /*
  *   On the Blackfin, the interrupt structure allows remmapping of the hardware
@@ -85,8 +85,8 @@ static __inline__ int irq_cannonicalize(int irq)
 extern void (*mach_enable_irq) (unsigned int);
 extern void (*mach_disable_irq) (unsigned int);
 extern int sys_request_irq(unsigned int,
-			void (*)(int, void *, struct pt_regs *),
-			unsigned long, const char *, void *);
+			   void (*)(int, void *, struct pt_regs *),
+			   unsigned long, const char *, void *);
 extern void sys_free_irq(unsigned int, void *);
 
 /*
diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h
index 0a43ba1..4fea74c 100644
--- a/include/asm-blackfin/machdep.h
+++ b/include/asm-blackfin/machdep.h
@@ -39,7 +39,8 @@ struct hwclk_time;
 struct gendisk;
 struct buffer_head;
 
-extern void (*mach_sched_init) (void (*handler)	(int, void *, struct pt_regs *));
+extern
+    void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *));
 
 /* machine dependent keyboard functions */
 extern int (*mach_keyb_init) (void);
diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h
index 1a13d90..d9d8bf9 100644
--- a/include/asm-blackfin/mem_init.h
+++ b/include/asm-blackfin/mem_init.h
@@ -22,7 +22,13 @@
  * MA 02111-1307 USA
  */
 
-#if ( CONFIG_MEM_MT48LC16M16A2TG_75  ||  CONFIG_MEM_MT48LC64M4A2FB_7E )
+#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
+	CONFIG_MEM_MT48LC64M4A2FB_7E || \
+	CONFIG_MEM_MT48LC16M8A2TG_75 || \
+	CONFIG_MEM_MT48LC8M16A2TG_7E || \
+	CONFIG_MEM_MT48LC8M32B2B5_7  || \
+	CONFIG_MEM_MT48LC32M8A2_75)
+
 	#if ( CONFIG_SCLK_HZ > 119402985 )
 		#define SDRAM_tRP	TRP_2
 		#define SDRAM_tRP_num	2
@@ -66,7 +72,7 @@
 	#if ( CONFIG_SCLK_HZ >  59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
 		#define SDRAM_tRP	TRP_1
 		#define SDRAM_tRP_num	1
-		#define SDRAM_tRAS	TRAS_4
+		#define SDRAM_tRAS	TRAS_3
 		#define SDRAM_tRAS_num	3
 		#define SDRAM_tRCD	TRCD_1
 		#define SDRAM_tWR	TWR_2
@@ -99,18 +105,46 @@
 
 #if (CONFIG_MEM_MT48LC16M16A2TG_75)
 	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	8192	/* Number of row addresses in SDRAM */
 	#define SDRAM_CL	CL_3
 #endif
 
 #if (CONFIG_MEM_MT48LC64M4A2FB_7E)
 	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	8192	/* Number of row addresses in SDRAM */
+	#define SDRAM_CL	CL_2
+#endif
+
+#if (CONFIG_MEM_MT48LC16M8A2TG_75)
+	/*SDRAM INFORMATION: */
+	#define SDRAM_Tref      64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA       4096	/* Number of row addresses in SDRAM */
+	#define SDRAM_CL        CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC32M8A2_75)
+/*SDRAM INFORMATION: */
+#define SDRAM_Tref  64			/* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192		/* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
+	/*SDRAM INFORMATION: */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	4096	/* Number of row addresses in SDRAM */
 	#define SDRAM_CL	CL_2
 #endif
 
+#if (CONFIG_MEM_MT48LC8M32B2B5_7)
+	/*SDRAM INFORMATION: */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	4096	/* Number of row addresses in SDRAM */
+	#define SDRAM_CL	CL_3
+#endif
+
 #if ( CONFIG_MEM_SIZE == 128 )
 	#define SDRAM_SIZE	EBSZ_128
 #endif
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
index 406ece5..d59828c 100644
--- a/include/asm-blackfin/page.h
+++ b/include/asm-blackfin/page.h
@@ -112,11 +112,6 @@ extern __inline__ int get_order(unsigned long size)
 #define virt_to_page(addr)		(mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
 #define VALID_PAGE(page)		((page - mem_map) < max_mapnr)
 
-#define BUG() do	{ \
-	 \
-	while (1);	/* dead-loop */ \
-} while (0)
-
 #define PAGE_BUG(page) do	{ \
 	BUG(); \
 } while (0)
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
index 19bd720..df49bed 100644
--- a/include/asm-blackfin/processor.h
+++ b/include/asm-blackfin/processor.h
@@ -126,8 +126,7 @@ static inline void release_thread(struct task_struct *dead_task)
 {
 }
 
-extern int kernel_thread(int (*fn) (void *), void *arg,
-			 unsigned long flags);
+extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
 
 #define copy_segments(tsk, mm)		do { } while (0)
 #define release_segments(mm)		do { } while (0)
diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h
index 6ce9688..a3c1715 100644
--- a/include/asm-blackfin/setup.h
+++ b/include/asm-blackfin/setup.h
@@ -75,12 +75,13 @@ extern unsigned long vme_brdtype;
 
 extern int blackfin_num_memory;	/* # of memory blocks found (and used) */
 extern int blackfin_realnum_memory;	/* real # of memory blocks found */
-extern struct mem_info blackfin_memory[NUM_MEMINFO];	/* memory description */
 
 struct mem_info {
 	unsigned long addr;	/* physical address of memory chunk */
 	unsigned long size;	/* length of memory chunk (in bytes) */
 };
+
+extern struct mem_info blackfin_memory[NUM_MEMINFO];	/* memory description */
 #endif
 
 #endif
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
index ffd81d6..aac6bc9 100644
--- a/include/asm-blackfin/string.h
+++ b/include/asm-blackfin/string.h
@@ -31,21 +31,26 @@
 
 #include <asm/setup.h>
 #include <asm/page.h>
-#include <asm/cpu/defBF533.h>
+#include <config.h>
+#include <asm/blackfin.h>
 
 #define __HAVE_ARCH_STRCPY
 #define __HAVE_ARCH_STRNCPY
 #define __HAVE_ARCH_STRCMP
 #define __HAVE_ARCH_STRNCMP
 #define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMMOVE
 
 extern char *strcpy(char *dest, const char *src);
 extern char *strncpy(char *dest, const char *src, size_t n);
 extern int strcmp(const char *cs, const char *ct);
 extern int strncmp(const char *cs, const char *ct, size_t count);
-extern void * memcpy(void * dest,const void *src,size_t count);
+extern void *memcpy(void *dest, const void *src, size_t count);
 extern void *memset(void *s, int c, size_t count);
 extern int memcmp(const void *, const void *, __kernel_size_t);
+extern void *memmove(void *dest, const void *src, size_t count);
 
 #else				/* KERNEL */
 
diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h
index ec39338..e1a435a 100644
--- a/include/asm-blackfin/u-boot.h
+++ b/include/asm-blackfin/u-boot.h
@@ -29,7 +29,7 @@
 #define _U_BOOT_H_	1
 
 typedef struct bd_info {
-	int bi_baudrate;		/* serial console baudrate */
+	int bi_baudrate;	/* serial console baudrate */
 	unsigned long bi_ip_addr;	/* IP Address */
 	unsigned char bi_enetaddr[6];	/* Ethernet adress */
 	unsigned long bi_arch_number;	/* unique id for this board */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
index 8578166..61e2bfe 100644
--- a/include/asm-blackfin/uaccess.h
+++ b/include/asm-blackfin/uaccess.h
@@ -41,11 +41,10 @@
 /* We let the MMU do all checking */
 static inline int access_ok(int type, const void *addr, unsigned long size)
 {
-	return ((unsigned long) addr < 0x10f00000);	/* need final decision - Tony */
+	return ((unsigned long)addr < 0x10f00000);	/* need final decision - Tony */
 }
 
-static inline int verify_area(int type, const void *addr,
-			      unsigned long size)
+static inline int verify_area(int type, const void *addr, unsigned long size)
 {
 	return access_ok(type, addr, size) ? 0 : -EFAULT;
 }
@@ -173,12 +172,11 @@ static inline int bad_user_access_length(void)
  * Copy a null terminated string from userspace.
  */
 
-static inline long strncpy_from_user(char *dst, const char *src,
-				     long count)
+static inline long strncpy_from_user(char *dst, const char *src, long count)
 {
 	char *tmp;
 	strncpy(dst, src, count);
-	for (tmp = dst; *tmp && count > 0; tmp++, count--);
+	for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
 	return (tmp - dst);	/* DAVIDM should we count a NUL ?  check getname */
 }
 
diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h
index 85d44aa..e64d788 100644
--- a/include/asm-i386/io.h
+++ b/include/asm-i386/io.h
@@ -201,4 +201,8 @@ __OUTS(b)
 __OUTS(w)
 __OUTS(l)
 
+static inline void sync(void)
+{
+}
+
 #endif
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index 79a9626..7bbdefb 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -1 +1,8 @@
-/* */
+#ifndef __ASM_M68K_IO_H_
+#define __ASM_M68K_IO_H_
+
+static inline void sync(void)
+{
+}
+
+#endif /* __ASM_M68K_IO_H_ */
diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h
index 765414f..e0f02cf 100644
--- a/include/asm-m68k/m5271.h
+++ b/include/asm-m68k/m5271.h
@@ -57,6 +57,12 @@
 #define MCF_GPIO_PAR_FECI2C			0x100047
 #define MCF_GPIO_PAR_UART			0x100048
 
+#define MCF_CCM_CIR				0x11000A
+#define MCF_CCM_CIR_PRN_MASK			0x3F
+#define MCF_CCM_CIR_PIN_LEN			6
+#define MCF_CCM_CIR_PIN_MCF5270			0x2e
+#define MCF_CCM_CIR_PIN_MCF5271			0x80
+
 #define MCF_GPIO_AD_ADDR23			0x80
 #define MCF_GPIO_AD_ADDR22			0x40
 #define MCF_GPIO_AD_ADDR21			0x20
diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h
index 3359045..1c77ade 100644
--- a/include/asm-microblaze/io.h
+++ b/include/asm-microblaze/io.h
@@ -125,4 +125,8 @@ io_outsl (unsigned long port, const void *src, unsigned long count)
 #define ioremap_writethrough(physaddr, size)	(physaddr)
 #define ioremap_fullcache(physaddr, size)	(physaddr)
 
+static inline void sync(void)
+{
+}
+
 #endif /* __MICROBLAZE_IO_H__ */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 857fb03..cd4d5dc 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -447,4 +447,8 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 #define dma_cache_wback(start,size)	_dma_cache_wback(start,size)
 #define dma_cache_inv(start,size)	_dma_cache_inv(start,size)
 
+static inline void sync(void)
+{
+}
+
 #endif /* _ASM_IO_H */
diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h
index 07499d9..d77695a 100644
--- a/include/asm-nios/io.h
+++ b/include/asm-nios/io.h
@@ -97,4 +97,8 @@ static inline void outsl (unsigned long port, const void *src, unsigned long cou
 	while (count--) outl (*p++, port);
 }
 
+static inline void sync(void)
+{
+}
+
 #endif /* __ASM_NIOS_IO_H_ */
diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h
index 0fab53b..5bb5322 100644
--- a/include/asm-nios2/io.h
+++ b/include/asm-nios2/io.h
@@ -24,7 +24,10 @@
 #ifndef __ASM_NIOS2_IO_H_
 #define __ASM_NIOS2_IO_H_
 
-#define sync() asm volatile ("sync" : : : "memory");
+static inline void sync(void)
+{
+	__asm__ __volatile__ ("sync" : : : "memory");
+}
 
 extern unsigned char inb (unsigned char *port);
 extern unsigned short inw (unsigned short *port);
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index 908007c..ff9512f 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -12,6 +12,13 @@
 #define PVR_83xx 0x80830000
 #define PVR_8349_REV10 (PVR_83xx | 0x0010)
 #define PVR_8349_REV11 (PVR_83xx | 0x0011)
+#define PVR_8360_REV10 (PVR_83xx | 0x0020)
+#define PVR_8360_REV11 (PVR_83xx | 0x0020)
+
+#if defined(CONFIG_MPC832X)
+#undef PVR_83xx
+#define PVR_83xx 0x80840000
+#endif
 
 /*
  * Hardware Implementation-Dependent Register 0 (HID0)
diff --git a/include/asm-ppc/fsl_i2c.h b/include/asm-ppc/fsl_i2c.h
index 76b1c43..4f71341 100644
--- a/include/asm-ppc/fsl_i2c.h
+++ b/include/asm-ppc/fsl_i2c.h
@@ -83,8 +83,4 @@ typedef struct fsl_i2c {
 	u8 res6[0xE8];
 } fsl_i2c_t;
 
-
-#define I2C_READ  1
-#define I2C_WRITE 0
-
 #endif	/* _ASM_I2C_H_ */
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index b73af96..c113b7e 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -52,17 +52,29 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC83XX)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
+#if defined (CONFIG_MPC834X)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
-	u32 core_clk;
 	u32 usbmph_clk;
 	u32 usbdr_clk;
-	u32 i2c_clk;
+#endif /* CONFIG_MPC834X */
+	u32 core_clk;
+	u32 i2c1_clk;
+	u32 i2c2_clk;
 	u32 enc_clk;
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 ddr_clk;
 	u32 pci_clk;
+#if defined(CONFIG_QE)
+	u32 qe_clk;
+	u32 brg_clk;
+	uint mp_alloc_base;
+	uint mp_alloc_top;
+#endif /* CONFIG_QE */
+#if defined (CONFIG_MPC8360)
+	u32  ddr_sec_clk;
+#endif /* CONFIG_MPC8360 */
 #endif
 #if defined(CONFIG_MPC5xxx)
 	unsigned long	ipb_clk;
diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h
deleted file mode 100644
index 1680d3a..0000000
--- a/include/asm-ppc/i2c.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Freescale I2C Controller
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2003, Motorola, Inc.
- * author: Eran Liberty (liberty@freescale.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_I2C_H_
-#define _ASM_I2C_H_
-
-#include <asm/types.h>
-
-typedef struct i2c
-{
-    u8 adr;          /**< I2C slave address              */
-#define I2C_ADR	      0xFE
-#define I2C_ADR_SHIFT 1
-#define I2C_ADR_RES   ~(I2C_ADR)
-    u8 res0[3];
-    u8 fdr;          /**< I2C frequency divider register */
-#define IC2_FDR       0x3F
-#define IC2_FDR_SHIFT 0
-#define IC2_FDR_RES   ~(IC2_FDR)
-    u8 res1[3];
-    u8 cr;           /**< I2C control redister           */
-#define I2C_CR_MEN	  0x80
-#define I2C_CR_MIEN	  0x40
-#define I2C_CR_MSTA   0x20
-#define I2C_CR_MTX    0x10
-#define I2C_CR_TXAK   0x08
-#define I2C_CR_RSTA   0x04
-#define I2C_CR_BCST   0x01
-    u8 res2[3];
-    u8 sr;           /**< I2C status register            */
-#define I2C_SR_MCF    0x80
-#define I2C_SR_MAAS   0x40
-#define I2C_SR_MBB    0x20
-#define I2C_SR_MAL    0x10
-#define I2C_SR_BCSTM  0x08
-#define I2C_SR_SRW    0x04
-#define I2C_SR_MIF    0x02
-#define I2C_SR_RXAK   0x01
-    u8 res3[3];
-    u8 dr;           /**< I2C data register              */
-#define I2C_DR 0xFF
-#define I2C_DR_SHIFT 0
-#define I2C_DR_RES ~(I2C_DR)
-    u8 res4[3];
-    u8 dfsrr;        /**< I2C digital filter sampling rate register */
-#define I2C_DFSRR 0x3F
-#define I2C_DFSRR_SHIFT 0
-#define I2C_DFSRR_RES ~(I2C_DR)
-    u8 res5[3];
-    u8 res6[0xE8];
-} i2c_t;
-
-#ifndef CFG_HZ
-#error CFG_HZ is not defined in /include/configs/${BOARD}.h
-#endif
-#define I2C_TIMEOUT (CFG_HZ/4)
-
-#ifndef CFG_IMMRBAR
-#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h
-#endif
-
-#ifndef CFG_I2C_OFFSET
-#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
-#endif
-
-#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X)
-/*
- * MPC8349 have two i2c bus
- */
-extern i2c_t * mpc8349_i2c;
-#define I2C mpc8349_i2c
-#else
-#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET))
-#endif
-
-#define I2C_READ  1
-#define I2C_WRITE 0
-
-#endif	/* _ASM_I2C_H_ */
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index c2b4c5c..5e088d6 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -1,1186 +1,662 @@
 /*
- * MPC8349 Internal Memory Map
- * Copyright (c) 2004 Freescale Semiconductor.
- * Eran Liberty (liberty@freescale.com)
+ * (C) Copyright 2004-2006 Freescale Semiconductor, Inc.
+ *
+ * MPC83xx Internal Memory Map
+ *
+ * Contributors:
+ *	Dave Liu <daveliu@freescale.com>
+ *	Tanya Jiang <tanya.jiang@freescale.com>
+ *	Mandy Lavi <mandy.lavi@freescale.com>
+ *	Eran Liberty <liberty@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
  *
- * based on:
- * - MPC8260 Internal Memory Map
- *   Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- * - MPC85xx Internal Memory Map
- *   Copyright(c) 2002,2003 Motorola Inc.
- *   Xianghua Xiao (x.xiao@motorola.com)
  */
-#ifndef __IMMAP_8349__
-#define __IMMAP_8349__
+#ifndef __IMMAP_83xx__
+#define __IMMAP_83xx__
 
 #include <asm/types.h>
-#include <asm/i2c.h>
+#include <asm/fsl_i2c.h>
 
 /*
- * Local Access Window.
- */
-typedef struct law8349 {
-	u32 bar; /* LBIU local access window base address register */
-/* Identifies the 20 most-significant address bits of the base of local
- * access window n. The specified base address should be aligned to the
- * window size, as defined by LBLAWARn[SIZE].
+ * Local Access Window
  */
-#define LAWBAR_BAR         0xFFFFF000
-#define LAWBAR_RES	     ~(LAWBAR_BAR)
-	u32 ar; /* LBIU local access window attribute register */
-} law8349_t;
+typedef struct law83xx {
+	u32 bar;		/* LBIU local access window base address register */
+	u32 ar;			/* LBIU local access window attribute register */
+} law83xx_t;
 
 /*
- * System configuration registers.
+ * System configuration registers
  */
-typedef struct sysconf8349 {
-	u32 immrbar; /* Internal memory map base address register */
+typedef struct sysconf83xx {
+	u32 immrbar;		/* Internal memory map base address register */
 	u8 res0[0x04];
-	u32 altcbar; /* Alternate configuration base address register */
-/* Identifies the12 most significant address bits of an alternate base
- * address used for boot sequencer configuration accesses.
- */
-#define ALTCBAR_BASE_ADDR     0xFFF00000
-#define ALTCBAR_RES           ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
+	u32 altcbar;		/* Alternate configuration base address register */
 	u8 res1[0x14];
-	law8349_t lblaw[4]; /* LBIU local access window */
+	law83xx_t lblaw[4];	/* LBIU local access window */
 	u8 res2[0x20];
-	law8349_t pcilaw[2]; /* PCI local access window */
+	law83xx_t pcilaw[2];	/* PCI local access window */
 	u8 res3[0x30];
-	law8349_t ddrlaw[2]; /* DDR local access window */
+	law83xx_t ddrlaw[2];	/* DDR local access window */
 	u8 res4[0x50];
-	u32 sgprl; /* System General Purpose Register Low */
-	u32 sgprh; /* System General Purpose Register High */
-	u32 spridr; /* System Part and Revision ID Register */
-#define SPRIDR_PARTID         0xFFFF0000 /* Part Identification. */
-#define SPRIDR_REVID          0x0000FFFF /* Revision Identification. */
+	u32 sgprl;		/* System General Purpose Register Low */
+	u32 sgprh;		/* System General Purpose Register High */
+	u32 spridr;		/* System Part and Revision ID Register */
 	u8 res5[0x04];
-	u32 spcr; /* System Priority Configuration Register */
-#define SPCR_PCIHPE   0x10000000 /* PCI Highest Priority Enable. */
-#define SPCR_PCIPR    0x03000000 /* PCI bridge system bus request priority. */
-#define SPCR_TBEN     0x00400000 /* E300 PowerPC core time base unit enable. */
-#define SPCR_COREPR   0x00300000 /* E300 PowerPC Core system bus request priority. */
-#define SPCR_TSEC1DP  0x00003000 /* TSEC1 data priority. */
-#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
-#define SPCR_TSEC1EP  0x00000300 /* TSEC1 emergency priority. */
-#define SPCR_TSEC2DP  0x00000030 /* TSEC2 data priority. */
-#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
-#define SPCR_TSEC2EP  0x00000003 /* TSEC2 emergency priority. */
-#define SPCR_RES      ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
-			| SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
-			| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
-	u32 sicrl; /* System General Purpose Register Low */
-#define SICRL_LDP_A   0x80000000
-#define SICRL_USB1    0x40000000
-#define SICRL_USB0    0x20000000
-#define SICRL_UART    0x0C000000
-#define SICRL_GPIO1_A 0x02000000
-#define SICRL_GPIO1_B 0x01000000
-#define SICRL_GPIO1_C 0x00800000
-#define SICRL_GPIO1_D 0x00400000
-#define SICRL_GPIO1_E 0x00200000
-#define SICRL_GPIO1_F 0x00180000
-#define SICRL_GPIO1_G 0x00040000
-#define SICRL_GPIO1_H 0x00020000
-#define SICRL_GPIO1_I 0x00010000
-#define SICRL_GPIO1_J 0x00008000
-#define SICRL_GPIO1_K 0x00004000
-#define SICRL_GPIO1_L 0x00003000
-#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
-			| SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
-			| SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
-			| SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
-			| SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
-	u32 sicrh; /* System General Purpose Register High */
-#define SICRH_DDR     0x80000000
-#define SICRH_TSEC1_A 0x10000000
-#define SICRH_TSEC1_B 0x08000000
-#define SICRH_TSEC1_C 0x04000000
-#define SICRH_TSEC1_D 0x02000000
-#define SICRH_TSEC1_E 0x01000000
-#define SICRH_TSEC1_F 0x00800000
-#define SICRH_TSEC2_A 0x00400000
-#define SICRH_TSEC2_B 0x00200000
-#define SICRH_TSEC2_C 0x00100000
-#define SICRH_TSEC2_D 0x00080000
-#define SICRH_TSEC2_E 0x00040000
-#define SICRH_TSEC2_F 0x00020000
-#define SICRH_TSEC2_G 0x00010000
-#define SICRH_TSEC2_H 0x00008000
-#define SICRH_GPIO2_A 0x00004000
-#define SICRH_GPIO2_B 0x00002000
-#define SICRH_GPIO2_C 0x00001000
-#define SICRH_GPIO2_D 0x00000800
-#define SICRH_GPIO2_E 0x00000400
-#define SICRH_GPIO2_F 0x00000200
-#define SICRH_GPIO2_G 0x00000180
-#define SICRH_GPIO2_H 0x00000060
-#define SICRH_TSOBI1  0x00000002
-#define SICRH_TSOBI2  0x00000001
-#define SICRh_RES     ~(  SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
-			| SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
-			| SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
-			| SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
-			| SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
-			| SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
-			| SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
-			| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
-			| SICRH_TSOBI2)
-	u8 res6[0xE4];
-} sysconf8349_t;
+	u32 spcr;		/* System Priority Configuration Register */
+	u32 sicrl;		/* System I/O Configuration Register Low */
+	u32 sicrh;		/* System I/O Configuration Register High */
+	u8 res6[0x0C];
+	u32 ddrcdr;		/* DDR Control Driver Register */
+	u32 ddrdsr;		/* DDR Debug Status Register */
+	u8 res7[0xD0];
+} sysconf83xx_t;
 
 /*
  * Watch Dog Timer (WDT) Registers
  */
-typedef struct wdt8349 {
+typedef struct wdt83xx {
 	u8 res0[4];
-	u32 swcrr; /* System watchdog control register */
-	u32 swcnr; /* System watchdog count register */
-#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
-#define SWCNR_RES  ~(SWCNR_SWCN)
+	u32 swcrr;		/* System watchdog control register */
+	u32 swcnr;		/* System watchdog count register */
 	u8 res1[2];
-	u16 swsrr; /* System watchdog service register */
+	u16 swsrr;		/* System watchdog service register */
 	u8 res2[0xF0];
-} wdt8349_t;
+} wdt83xx_t;
 
 /*
  * RTC/PIT Module Registers
  */
-typedef struct rtclk8349 {
-	u32 cnr; /* control register */
-#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit  */
-#define CNR_CLIN 0x00000040 /* Input Clock Control Bit  */
-#define CNR_AIM  0x00000002 /* Alarm Interrupt Mask Bit  */
-#define CNR_SIM  0x00000001 /* Second Interrupt Mask Bit  */
-#define CNR_RES  ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
-	u32 ldr; /* load register */
-	u32 psr; /* prescale register */
-	u32 ctr; /* register */
-	u32 evr; /* event register */
-#define RTEVR_SIF  0x00000001 /* Second Interrupt Flag Bit  */
-#define RTEVR_AIF  0x00000002 /* Alarm Interrupt Flag Bit  */
-#define RTEVR_RES  ~(EVR_SIF | EVR_AIF)
-	u32 alr; /* alarm register */
+typedef struct rtclk83xx {
+	u32 cnr;		/* control register */
+	u32 ldr;		/* load register */
+	u32 psr;		/* prescale register */
+	u32 ctr;		/* counter value field register */
+	u32 evr;		/* event register */
+	u32 alr;		/* alarm register */
 	u8 res0[0xE8];
-} rtclk8349_t;
+} rtclk83xx_t;
 
 /*
- * Global timper module
+ * Global timer module
  */
-
-typedef struct gtm8349 {
-	u8    cfr1; /* Timer1/2 Configuration  */
-#define CFR1_PCAS 0x80 /* Pair Cascade mode  */
-#define CFR1_BCM  0x40  /* Backward compatible mode  */
-#define CFR1_STP2 0x20 /* Stop timer  */
-#define CFR1_RST2 0x10 /* Reset timer  */
-#define CFR1_GM2  0x08 /* Gate mode for pin 2  */
-#define CFR1_GM1  0x04 /* Gate mode for pin 1  */
-#define CFR1_STP1 0x02 /* Stop timer  */
-#define CFR1_RST1 0x01 /* Reset timer  */
-	u8    res0[3];
-	u8    cfr2; /* Timer3/4 Configuration  */
-#define CFR2_PCAS 0x80 /* Pair Cascade mode  */
-#define CFR2_SCAS 0x40 /* Super Cascade mode  */
-#define CFR2_STP4 0x20 /* Stop timer  */
-#define CFR2_RST4 0x10 /* Reset timer  */
-#define CFR2_GM4  0x08 /* Gate mode for pin 4  */
-#define CFR2_GM3  0x04 /* Gate mode for pin 3  */
-#define CFR2_STP3 0x02 /* Stop timer  */
-#define CFR2_RST3 0x01 /* Reset timer  */
-	u8    res1[10];
-	u16   mdr1; /* Timer1 Mode Register  */
-#define MDR_SPS  0xff00 /* Secondary Prescaler value  */
-#define MDR_CE   0x00c0 /* Capture edge and enable interrupt  */
-#define MDR_OM   0x0020 /* Output mode  */
-#define MDR_ORI  0x0010 /* Output reference interrupt enable  */
-#define MDR_FRR  0x0008 /* Free run/restart  */
-#define MDR_ICLK 0x0006 /* Input clock source for the timer  */
-#define MDR_GE   0x0001 /* Gate enable  */
-	u16   mdr2; /* Timer2 Mode Register  */
-	u16   rfr1; /* Timer1 Reference Register  */
-	u16   rfr2; /* Timer2 Reference Register  */
-	u16   cpr1; /* Timer1 Capture Register  */
-	u16   cpr2; /* Timer2 Capture Register  */
-	u16   cnr1; /* Timer1 Counter Register  */
-	u16   cnr2; /* Timer2 Counter Register  */
-	u16   mdr3; /* Timer3 Mode Register  */
-	u16   mdr4; /* Timer4 Mode Register  */
-	u16   rfr3; /* Timer3 Reference Register  */
-	u16   rfr4; /* Timer4 Reference Register  */
-	u16   cpr3; /* Timer3 Capture Register  */
-	u16   cpr4; /* Timer4 Capture Register  */
-	u16   cnr3; /* Timer3 Counter Register  */
-	u16   cnr4; /* Timer4 Counter Register  */
-	u16   evr1; /* Timer1 Event Register  */
-	u16   evr2; /* Timer2 Event Register  */
-	u16   evr3; /* Timer3 Event Register  */
-	u16   evr4; /* Timer4 Event Register  */
-#define GTEVR_REF 0x0002 /* Output reference event  */
-#define GTEVR_CAP 0x0001 /* Counter Capture event   */
-#define GTEVR_RES ~(EVR_CAP|EVR_REF)
-	u16   psr1; /* Timer1 Prescaler Register  */
-	u16   psr2; /* Timer2 Prescaler Register  */
-	u16   psr3; /* Timer3 Prescaler Register  */
-	u16   psr4; /* Timer4 Prescaler Register  */
-	u8    res[0xC0];
-} gtm8349_t;
+typedef struct gtm83xx {
+	u8 cfr1;		/* Timer1/2 Configuration */
+	u8 res0[3];
+	u8 cfr2;		/* Timer3/4 Configuration */
+	u8 res1[10];
+	u16 mdr1;		/* Timer1 Mode Register */
+	u16 mdr2;		/* Timer2 Mode Register */
+	u16 rfr1;		/* Timer1 Reference Register */
+	u16 rfr2;		/* Timer2 Reference Register */
+	u16 cpr1;		/* Timer1 Capture Register */
+	u16 cpr2;		/* Timer2 Capture Register */
+	u16 cnr1;		/* Timer1 Counter Register */
+	u16 cnr2;		/* Timer2 Counter Register */
+	u16 mdr3;		/* Timer3 Mode Register */
+	u16 mdr4;		/* Timer4 Mode Register */
+	u16 rfr3;		/* Timer3 Reference Register */
+	u16 rfr4;		/* Timer4 Reference Register */
+	u16 cpr3;		/* Timer3 Capture Register */
+	u16 cpr4;		/* Timer4 Capture Register */
+	u16 cnr3;		/* Timer3 Counter Register */
+	u16 cnr4;		/* Timer4 Counter Register */
+	u16 evr1;		/* Timer1 Event Register */
+	u16 evr2;		/* Timer2 Event Register */
+	u16 evr3;		/* Timer3 Event Register */
+	u16 evr4;		/* Timer4 Event Register */
+	u16 psr1;		/* Timer1 Prescaler Register */
+	u16 psr2;		/* Timer2 Prescaler Register */
+	u16 psr3;		/* Timer3 Prescaler Register */
+	u16 psr4;		/* Timer4 Prescaler Register */
+	u8 res[0xC0];
+} gtm83xx_t;
 
 /*
  * Integrated Programmable Interrupt Controller
  */
-typedef struct ipic8349 {
-	u32    sicfr; /*  System Global Interrupt Configuration Register (SICFR)  */
-#define SICFR_HPI  0x7f000000 /*  Highest Priority Interrupt  */
-#define SICFR_MPSB 0x00400000 /*  Mixed interrupts Priority Scheme for group B  */
-#define SICFR_MPSA 0x00200000 /*  Mixed interrupts Priority Scheme for group A  */
-#define SICFR_IPSD 0x00080000 /*  Internal interrupts Priority Scheme for group D  */
-#define SICFR_IPSA 0x00010000 /*  Internal interrupts Priority Scheme for group A  */
-#define SICFR_HPIT 0x00000300 /*  HPI priority position IPIC output interrupt Type  */
-#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
-	u32    sivcr; /*  System Global Interrupt Vector Register (SIVCR)  */
-#define SICVR_IVECX 0xfc000000 /*  Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation)  */
-#define SICVR_IVEC  0x0000007f /*  Interrupt vector  */
-#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
-	u32    sipnr_h; /*  System Internal Interrupt Pending Register - High (SIPNR_H)  */
-#define SIIH_TSEC1TX 0x80000000 /*  TSEC1 Tx interrupt  */
-#define SIIH_TSEC1RX 0x40000000 /*  TSEC1 Rx interrupt  */
-#define SIIH_TSEC1ER 0x20000000 /*  TSEC1 Eror interrupt  */
-#define SIIH_TSEC2TX 0x10000000 /*  TSEC2 Tx interrupt  */
-#define SIIH_TSEC2RX 0x08000000 /*  TSEC2 Rx interrupt  */
-#define SIIH_TSEC2ER 0x04000000 /*  TSEC2 Eror interrupt  */
-#define SIIH_USB2DR  0x02000000 /*  USB2 DR interrupt  */
-#define SIIH_USB2MPH 0x01000000 /*  USB2 MPH interrupt  */
-#define SIIH_UART1   0x00000080 /*  UART1 interrupt  */
-#define SIIH_UART2   0x00000040 /*  UART2 interrupt  */
-#define SIIH_SEC     0x00000020 /*  SEC interrupt  */
-#define SIIH_I2C1    0x00000004 /*  I2C1 interrupt  */
-#define SIIH_I2C2    0x00000002 /*  I2C1 interrupt  */
-#define SIIH_SPI     0x00000001 /*  SPI interrupt  */
-#define SIIH_RES	~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
-			| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
-			| SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
-			| SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
-			| SIIH_I2C2 | SIIH_SPI)
-	u32    sipnr_l; /*  System Internal Interrupt Pending Register - Low (SIPNR_L)  */
-#define SIIL_RTCS  0x80000000 /*  RTC SECOND interrupt  */
-#define SIIL_PIT   0x40000000 /*  PIT interrupt  */
-#define SIIL_PCI1  0x20000000 /*  PCI1 interrupt  */
-#define SIIL_PCI2  0x10000000 /*  PCI2 interrupt  */
-#define SIIL_RTCA  0x08000000 /*  RTC ALARM interrupt  */
-#define SIIL_MU    0x04000000 /*  Message Unit interrupt  */
-#define SIIL_SBA   0x02000000 /*  System Bus Arbiter interrupt  */
-#define SIIL_DMA   0x01000000 /*  DMA interrupt  */
-#define SIIL_GTM4  0x00800000 /*  GTM4 interrupt  */
-#define SIIL_GTM8  0x00400000 /*  GTM8 interrupt  */
-#define SIIL_GPIO1 0x00200000 /*  GPIO1 interrupt  */
-#define SIIL_GPIO2 0x00100000 /*  GPIO2 interrupt  */
-#define SIIL_DDR   0x00080000 /*  DDR interrupt  */
-#define SIIL_LBC   0x00040000 /*  LBC interrupt  */
-#define SIIL_GTM2  0x00020000 /*  GTM2 interrupt  */
-#define SIIL_GTM6  0x00010000 /*  GTM6 interrupt  */
-#define SIIL_PMC   0x00008000 /*  PMC interrupt  */
-#define SIIL_GTM3  0x00000800 /*  GTM3 interrupt  */
-#define SIIL_GTM7  0x00000400 /*  GTM7 interrupt  */
-#define SIIL_GTM1  0x00000020 /*  GTM1 interrupt  */
-#define SIIL_GTM5  0x00000010 /*  GTM5 interrupt  */
-#define SIIL_DPTC  0x00000001 /*  DPTC interrupt (!!! Invisible for user !!!)  */
-#define SIIL_RES	~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
-			| SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
-			| SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
-			| SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
-			| SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
-			| SIIL_GTM5 |SIIL_DPTC )
-	u32    siprr_a; /*  System Internal Interrupt Group A Priority Register (PRR)  */
-	u8     res0[8];
-	u32    siprr_d; /*  System Internal Interrupt Group D Priority Register (PRR)  */
-	u32    simsr_h; /*  System Internal Interrupt Mask Register - High (SIIH)  */
-	u32    simsr_l; /*  System Internal Interrupt Mask Register - Low (SIIL)  */
-	u8     res1[4];
-	u32    sepnr;   /*  System External Interrupt Pending Register (SEI)  */
-	u32    smprr_a; /*  System Mixed Interrupt Group A Priority Register (PRR)  */
-	u32    smprr_b; /*  System Mixed Interrupt Group B Priority Register (PRR)  */
-#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
-#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
-#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
-#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
-#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
-#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
-#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
-#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
-#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
-	u32    semsr; /*  System External Interrupt Mask Register (SEI)  */
-#define SEI_IRQ0  0x80000000 /*  IRQ0 external interrupt  */
-#define SEI_IRQ1  0x40000000 /*  IRQ1 external interrupt  */
-#define SEI_IRQ2  0x20000000 /*  IRQ2 external interrupt  */
-#define SEI_IRQ3  0x10000000 /*  IRQ3 external interrupt  */
-#define SEI_IRQ4  0x08000000 /*  IRQ4 external interrupt  */
-#define SEI_IRQ5  0x04000000 /*  IRQ5 external interrupt  */
-#define SEI_IRQ6  0x02000000 /*  IRQ6 external interrupt  */
-#define SEI_IRQ7  0x01000000 /*  IRQ7 external interrupt  */
-#define SEI_SIRQ0 0x00008000 /*  SIRQ0 external interrupt  */
-#define SEI_RES		~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
-			| SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
-			| SEI_SIRQ0)
-	u32    secnr; /*  System External Interrupt Control Register (SECNR) */
-#define SECNR_MIXB0T 0xc0000000 /*  MIXB0 priority position IPIC output interrupt type  */
-#define SECNR_MIXB1T 0x30000000 /*  MIXB1 priority position IPIC output interrupt type  */
-#define SECNR_MIXA0T 0x00c00000 /*  MIXA0 priority position IPIC output interrupt type  */
-#define SECNR_SYSA1T 0x00300000 /*  MIXA1 priority position IPIC output interrupt type  */
-#define SECNR_EDI0   0x00008000 /*  IRQ0 external interrupt edge/level detect  */
-#define SECNR_EDI1   0x00004000 /*  IRQ1 external interrupt edge/level detect  */
-#define SECNR_EDI2   0x00002000 /*  IRQ2 external interrupt edge/level detect  */
-#define SECNR_EDI3   0x00001000 /*  IRQ3 external interrupt edge/level detect  */
-#define SECNR_EDI4   0x00000800 /*  IRQ4 external interrupt edge/level detect  */
-#define SECNR_EDI5   0x00000400 /*  IRQ5 external interrupt edge/level detect  */
-#define SECNR_EDI6   0x00000200 /*  IRQ6 external interrupt edge/level detect  */
-#define SECNR_EDI7   0x00000100 /*  IRQ7 external interrupt edge/level detect  */
-#define SECNR_RES	~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
-			| SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
-			| SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
-			| SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
-	u32   sersr; /*  System Error Status Register (SERR)  */
-	u32   sermr; /*  System Error Mask Register (SERR)  */
-#define SERR_IRQ0 0x80000000 /*  IRQ0 MCP request  */
-#define SERR_WDT  0x40000000 /*  WDT MCP request  */
-#define SERR_SBA  0x20000000 /*  SBA MCP request  */
-#define SERR_DDR  0x10000000 /*  DDR MCP request  */
-#define SERR_LBC  0x08000000 /*  LBC MCP request  */
-#define SERR_PCI1 0x04000000 /*  PCI1 MCP request  */
-#define SERR_PCI2 0x02000000 /*  PCI2 MCP request  */
-#define SERR_MU   0x01000000 /*  MU MCP request  */
-#define SERR_RNC  0x00010000 /*  MU MCP request (!!! Non-visible for users !!!)  */
-#define SERR_RES	~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
-			|SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
-			|SERR_RNC )
-	u32    sercr; /*  System Error Control Register  (SERCR)  */
-#define SERCR_MCPR 0x00000001 /*  MCP Route  */
-#define SERCR_RES ~(SERCR_MCPR)
-	u8    res2[4];
-	u32   sifcr_h; /*  System Internal Interrupt Force Register - High (SIIH)  */
-	u32   sifcr_l; /*  System Internal Interrupt Force Register - Low (SIIL)  */
-	u32   sefcr;   /*  System External Interrupt Force Register (SEI)  */
-	u32   serfr;   /*  System Error Force Register (SERR)  */
-	u8    res3[0xA0];
-} ipic8349_t;
+typedef struct ipic83xx {
+	u32 sicfr;		/* System Global Interrupt Configuration Register */
+	u32 sivcr;		/* System Global Interrupt Vector Register */
+	u32 sipnr_h;		/* System Internal Interrupt Pending Register - High */
+	u32 sipnr_l;		/* System Internal Interrupt Pending Register - Low */
+	u32 siprr_a;		/* System Internal Interrupt Group A Priority Register */
+	u8 res0[8];
+	u32 siprr_d;		/* System Internal Interrupt Group D Priority Register */
+	u32 simsr_h;		/* System Internal Interrupt Mask Register - High */
+	u32 simsr_l;		/* System Internal Interrupt Mask Register - Low */
+	u8 res1[4];
+	u32 sepnr;		/* System External Interrupt Pending Register */
+	u32 smprr_a;		/* System Mixed Interrupt Group A Priority Register */
+	u32 smprr_b;		/* System Mixed Interrupt Group B Priority Register */
+	u32 semsr;		/* System External Interrupt Mask Register */
+	u32 secnr;		/* System External Interrupt Control Register */
+	u32 sersr;		/* System Error Status Register */
+	u32 sermr;		/* System Error Mask Register */
+	u32 sercr;		/* System Error Control Register */
+	u8 res2[4];
+	u32 sifcr_h;		/* System Internal Interrupt Force Register - High */
+	u32 sifcr_l;		/* System Internal Interrupt Force Register - Low */
+	u32 sefcr;		/* System External Interrupt Force Register */
+	u32 serfr;		/* System Error Force Register */
+	u32 scvcr;		/* System Critical Interrupt Vector Register */
+	u32 smvcr;		/* System Management Interrupt Vector Register */
+	u8 res3[0x98];
+} ipic83xx_t;
 
 /*
  * System Arbiter Registers
  */
-typedef struct arbiter8349 {
-	u32 acr; /* Arbiter Configuration Register */
-#define ACR_COREDIS    0x10000000 /* Core disable. */
-#define ACR_PIPE_DEP   0x00070000 /* Pipeline depth (number of outstanding transactions). */
-#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
-#define ACR_RPTCNT     0x00000700 /* Repeat count. */
-#define ACR_APARK      0x00000030 /* Address parking. */
-#define ACR_PARKM	   0x0000000F /* Parking master. */
-#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
-	u32 atr; /* Arbiter Timers Register */
-#define ATR_DTO 0x00FF0000 /* Data time out. */
-#define ATR_ATO	0x000000FF /* Address time out. */
-#define ATR_RES ~(ATR_DTO|ATR_ATO)
+typedef struct arbiter83xx {
+	u32 acr;		/* Arbiter Configuration Register */
+	u32 atr;		/* Arbiter Timers Register */
 	u8 res[4];
-	u32 aer; /* Arbiter Event Register (AE)*/
-	u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
-	u32 amr; /* Arbiter Mask Register (AE) */
-	u32 aeatr; /* Arbiter Event Attributes Register */
-#define AEATR_EVENT   0x07000000 /* Event type. */
-#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
-#define AEATR_TBST    0x00000800 /* Transfer burst. */
-#define AEATR_TSIZE   0x00000700 /* Transfer Size. */
-#define AEATR_TTYPE	  0x0000001F /* Transfer Type. */
-#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
-	u32 aeadr; /* Arbiter Event Address Register */
-	u32 aerr; /* Arbiter Event Response Register (AE)*/
-#define AE_ETEA 0x00000020 /* Transfer error. */
-#define AE_RES_ 0x00000010 /* Reserved transfer type. */
-#define AE_ECW  0x00000008 /* External control word transfer type. */
-#define AE_AO   0x00000004 /* Address Only transfer type. */
-#define AE_DTO  0x00000002 /* Data time out. */
-#define AE_ATO	0x00000001 /* Address time out. */
-#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
+	u32 aer;		/* Arbiter Event Register */
+	u32 aidr;		/* Arbiter Interrupt Definition Register */
+	u32 amr;		/* Arbiter Mask Register */
+	u32 aeatr;		/* Arbiter Event Attributes Register */
+	u32 aeadr;		/* Arbiter Event Address Register */
+	u32 aerr;		/* Arbiter Event Response Register */
 	u8 res1[0xDC];
-} arbiter8349_t;
+} arbiter83xx_t;
 
 /*
  * Reset Module
  */
-typedef struct reset8349 {
-	u32    rcwl; /* RCWL Register  */
-#define RCWL_LBIUCM  0x80000000 /* LBIUCM  */
-#define RCWL_LBIUCM_SHIFT    31
-#define RCWL_DDRCM   0x40000000 /* DDRCM  */
-#define RCWL_DDRCM_SHIFT     30
-#define RCWL_SVCOD   0x30000000 /* SVCOD  */
-#define RCWL_SPMF    0x0f000000 /* SPMF  */
-#define RCWL_SPMF_SHIFT      24
-#define RCWL_COREPLL 0x007F0000 /* COREPLL  */
-#define RCWL_COREPLL_SHIFT   16
-#define RCWL_CEVCOD  0x000000C0 /* CEVCOD  */
-#define RCWL_CEPDF   0x00000020 /* CEPDF  */
-#define RCWL_CEPMF   0x0000001F /* CEPMF  */
-#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
-	u32    rcwh; /* RCHL Register  */
-#define RCWH_PCIHOST 0x80000000 /* PCIHOST  */
-#define RCWH_PCIHOST_SHIFT   31
-#define RCWH_PCI64   0x40000000 /* PCI64  */
-#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB  */
-#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB  */
-#define RCWH_COREDIS 0x08000000 /* COREDIS  */
-#define RCWH_BMS     0x04000000 /* BMS  */
-#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ  */
-#define RCWH_SWEN    0x00800000 /* SWEN  */
-#define RCWH_ROMLOC  0x00700000 /* ROMLOC  */
-#define RCWH_TSEC1M  0x0000c000 /* TSEC1M  */
-#define RCWH_TSEC2M  0x00003000 /* TSEC2M  */
-#define RCWH_TPR     0x00000100 /* TPR  */
-#define RCWH_TLE     0x00000008 /* TLE  */
-#define RCWH_LALE    0x00000004 /* LALE  */
-#define RCWH_RES	~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
-			| RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
-			| RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
-			| RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
-			| RCWH_TLE | RCWH_LALE)
-	u8     res0[8];
-	u32    rsr; /* Reset status Register  */
-#define RSR_RSTSRC 0xE0000000 /* Reset source  */
-#define RSR_RSTSRC_SHIFT   29
-#define RSR_BSF    0x00010000 /* Boot seq. fail  */
-#define RSR_BSF_SHIFT      16
-#define RSR_SWSR   0x00002000 /* software soft reset  */
-#define RSR_SWSR_SHIFT     13
-#define RSR_SWHR   0x00001000 /* software hard reset  */
-#define RSR_SWHR_SHIFT     12
-#define RSR_JHRS   0x00000200 /* jtag hreset  */
-#define RSR_JHRS_SHIFT      9
-#define RSR_JSRS   0x00000100 /* jtag sreset status  */
-#define RSR_JSRS_SHIFT      8
-#define RSR_CSHR   0x00000010 /* checkstop reset status  */
-#define RSR_CSHR_SHIFT      4
-#define RSR_SWRS   0x00000008 /* software watchdog reset status  */
-#define RSR_SWRS_SHIFT      3
-#define RSR_BMRS   0x00000004 /* bus monitop reset status  */
-#define RSR_BMRS_SHIFT      2
-#define RSR_SRS    0x00000002 /* soft reset status  */
-#define RSR_SRS_SHIFT       1
-#define RSR_HRS    0x00000001 /* hard reset status  */
-#define RSR_HRS_SHIFT       0
-#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
-	u32    rmr; /* Reset mode Register  */
-#define RMR_CSRE   0x00000001 /* checkstop reset enable  */
-#define RMR_CSRE_SHIFT      0
-#define RMR_RES ~(RMR_CSRE)
-	u32    rpr; /* Reset protection Register  */
-	u32    rcr; /* Reset Control Register  */
-#define RCR_SWHR 0x00000002 /* software hard reset  */
-#define RCR_SWSR 0x00000001 /* software soft reset  */
-#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
-	u32    rcer; /* Reset Control Enable Register  */
-#define RCER_CRE 0x00000001 /* software hard reset  */
-#define RCER_RES ~(RCER_CRE)
-	u8     res1[0xDC];
-} reset8349_t;
+typedef struct reset83xx {
+	u32 rcwl;		/* Reset Configuration Word Low Register */
+	u32 rcwh;		/* Reset Configuration Word High Register */
+	u8 res0[8];
+	u32 rsr;		/* Reset Status Register */
+	u32 rmr;		/* Reset Mode Register */
+	u32 rpr;		/* Reset protection Register */
+	u32 rcr;		/* Reset Control Register */
+	u32 rcer;		/* Reset Control Enable Register */
+	u8 res1[0xDC];
+} reset83xx_t;
 
-typedef struct clk8349 {
-	u32    spmr; /* system PLL mode Register  */
-#define SPMR_LBIUCM  0x80000000 /* LBIUCM  */
-#define SPMR_DDRCM   0x40000000 /* DDRCM  */
-#define SPMR_SVCOD   0x30000000 /* SVCOD  */
-#define SPMR_SPMF    0x0F000000 /* SPMF  */
-#define SPMR_CKID    0x00800000 /* CKID  */
-#define SPMR_CKID_SHIFT 23
-#define SPMR_COREPLL 0x007F0000 /* COREPLL  */
-#define SPMR_CEVCOD  0x000000C0 /* CEVCOD  */
-#define SPMR_CEPDF   0x00000020 /* CEPDF  */
-#define SPMR_CEPMF   0x0000001F /* CEPMF  */
-#define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
-			| SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
-			| SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
-	u32    occr; /* output clock control Register  */
-#define OCCR_PCICOE0 0x80000000 /* PCICOE0  */
-#define OCCR_PCICOE1 0x40000000 /* PCICOE1  */
-#define OCCR_PCICOE2 0x20000000 /* PCICOE2  */
-#define OCCR_PCICOE3 0x10000000 /* PCICOE3  */
-#define OCCR_PCICOE4 0x08000000 /* PCICOE4  */
-#define OCCR_PCICOE5 0x04000000 /* PCICOE5  */
-#define OCCR_PCICOE6 0x02000000 /* PCICOE6  */
-#define OCCR_PCICOE7 0x01000000 /* PCICOE7  */
-#define OCCR_PCICD0  0x00800000 /* PCICD0  */
-#define OCCR_PCICD1  0x00400000 /* PCICD1  */
-#define OCCR_PCICD2  0x00200000 /* PCICD2  */
-#define OCCR_PCICD3  0x00100000 /* PCICD3  */
-#define OCCR_PCICD4  0x00080000 /* PCICD4  */
-#define OCCR_PCICD5  0x00040000 /* PCICD5  */
-#define OCCR_PCICD6  0x00020000 /* PCICD6  */
-#define OCCR_PCICD7  0x00010000 /* PCICD7  */
-#define OCCR_PCI1CR  0x00000002 /* PCI1CR  */
-#define OCCR_PCI2CR  0x00000001 /* PCI2CR  */
-#define OCCR_RES	~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
-			| OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
-			| OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
-			| OCCR_PCICD1 | OCCR_PCICD2  | OCCR_PCICD3 \
-			| OCCR_PCICD4  | OCCR_PCICD5 | OCCR_PCICD6  \
-			| OCCR_PCICD7  | OCCR_PCI1CR  | OCCR_PCI2CR )
-	u32    sccr; /* system clock control Register  */
-#define SCCR_TSEC1CM  0xc0000000 /* TSEC1CM  */
-#define SCCR_TSEC1CM_SHIFT 30
-#define SCCR_TSEC2CM  0x30000000 /* TSEC2CM  */
-#define SCCR_TSEC2CM_SHIFT 28
-#define SCCR_ENCCM    0x03000000 /* ENCCM  */
-#define SCCR_ENCCM_SHIFT 24
-#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM  */
-#define SCCR_USBMPHCM_SHIFT 22
-#define SCCR_USBDRCM  0x00300000 /* USBDRCM  */
-#define SCCR_USBDRCM_SHIFT 20
-#define SCCR_PCICM    0x00010000 /* PCICM  */
-#define SCCR_RES	~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
-			| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
-	u8     res0[0xF4];
-} clk8349_t;
+/*
+ * Clock Module
+ */
+typedef struct clk83xx {
+	u32 spmr;		/* system PLL mode Register */
+	u32 occr;		/* output clock control Register */
+	u32 sccr;		/* system clock control Register */
+	u8 res0[0xF4];
+} clk83xx_t;
 
 /*
  * Power Management Control Module
  */
-typedef struct pmc8349 {
-	u32    pmccr; /* PMC Configuration Register  */
-#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable  */
-#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable  */
-#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
-	u32    pmcer; /* PMC Event Register  */
-#define PMCER_PMCI  0x00000001 /* PMC Interrupt  */
-#define PMCER_RES ~(PMCER_PMCI)
-	u32    pmcmr; /* PMC Mask Register  */
-#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable  */
-#define PMCMR_RES ~(PMCMR_PMCIE)
+typedef struct pmc83xx {
+	u32 pmccr;		/* PMC Configuration Register */
+	u32 pmcer;		/* PMC Event Register */
+	u32 pmcmr;		/* PMC Mask Register */
 	u8 res0[0xF4];
-} pmc8349_t;
-
+} pmc83xx_t;
 
 /*
- * general purpose I/O module
+ * General purpose I/O module
  */
-typedef struct gpio8349 {
-	u32 dir; /* direction register */
-	u32 odr; /* open drain register */
-	u32 dat; /* data register */
-	u32 ier; /* interrupt event register */
-	u32 imr; /* interrupt mask register */
-	u32 icr; /* external interrupt control register */
+typedef struct gpio83xx {
+	u32 dir;		/* direction register */
+	u32 odr;		/* open drain register */
+	u32 dat;		/* data register */
+	u32 ier;		/* interrupt event register */
+	u32 imr;		/* interrupt mask register */
+	u32 icr;		/* external interrupt control register */
 	u8 res0[0xE8];
-} gpio8349_t;
+} gpio83xx_t;
+
+/*
+ * QE Ports Interrupts Registers
+ */
+typedef struct qepi83xx {
+	u8 res0[0xC];
+	u32 qepier;		/* QE Ports Interrupt Event Register */
+	u32 qepimr;		/* QE Ports Interrupt Mask Register */
+	u32 qepicr;		/* QE Ports Interrupt Control Register */
+	u8 res1[0xE8];
+} qepi83xx_t;
+
+/*
+ * QE Parallel I/O Ports
+ */
+typedef struct gpio_n {
+	u32 podr;		/* Open Drain Register */
+	u32 pdat;		/* Data Register */
+	u32 dir1;		/* direction register 1 */
+	u32 dir2;		/* direction register 2 */
+	u32 ppar1;		/* Pin Assignment Register 1 */
+	u32 ppar2;		/* Pin Assignment Register 2 */
+} gpio_n_t;
+
+typedef struct qegpio83xx {
+	gpio_n_t ioport[0x7];
+	u8 res0[0x358];
+} qepio83xx_t;
+
+/*
+ * QE Secondary Bus Access Windows
+ */
+typedef struct qesba83xx {
+	u32 lbmcsar;		/* Local bus memory controller start address */
+	u32 sdmcsar;		/* Secondary DDR memory controller start address */
+	u8 res0[0x38];
+	u32 lbmcear;		/* Local bus memory controller end address */
+	u32 sdmcear;		/* Secondary DDR memory controller end address */
+	u8 res1[0x38];
+	u32 lbmcar;		/* Local bus memory controller attributes */
+	u32 sdmcar;		/* Secondary DDR memory controller attributes */
+	u8 res2[0x378];
+} qesba83xx_t;
 
 /*
  * DDR Memory Controller Memory Map
  */
-typedef struct ddr_cs_bnds{
+typedef struct ddr_cs_bnds {
 	u32 csbnds;
-#define CSBNDS_SA 0x00FF0000
-#define CSBNDS_SA_SHIFT    8
-#define CSBNDS_EA 0x000000FF
-#define CSBNDS_EA_SHIFT   24
-	u8  res0[4];
+	u8 res0[4];
 } ddr_cs_bnds_t;
 
-typedef struct ddr8349{
-	ddr_cs_bnds_t csbnds[4];            /**< Chip Select x Memory Bounds */
+typedef struct ddr83xx {
+	ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
 	u8 res0[0x60];
-	u32 cs_config[4];       /**< Chip Select x Configuration */
-#define CSCONFIG_EN         0x80000000
-#define CSCONFIG_AP         0x00800000
-#define CSCONFIG_ROW_BIT    0x00000700
-#define CSCONFIG_ROW_BIT_12 0x00000000
-#define CSCONFIG_ROW_BIT_13 0x00000100
-#define CSCONFIG_ROW_BIT_14 0x00000200
-#define CSCONFIG_COL_BIT    0x00000007
-#define CSCONFIG_COL_BIT_8  0x00000000
-#define CSCONFIG_COL_BIT_9  0x00000001
-#define CSCONFIG_COL_BIT_10 0x00000002
-#define CSCONFIG_COL_BIT_11 0x00000003
-	u8 res1[0x78];
-	u32 timing_cfg_1;       /**< SDRAM Timing Configuration 1 */
-#define TIMING_CFG1_PRETOACT 0x70000000
-#define TIMING_CFG1_PRETOACT_SHIFT   28
-#define TIMING_CFG1_ACTTOPRE 0x0F000000
-#define TIMING_CFG1_ACTTOPRE_SHIFT   24
-#define TIMING_CFG1_ACTTORW  0x00700000
-#define TIMING_CFG1_ACTTORW_SHIFT    20
-#define TIMING_CFG1_CASLAT   0x00070000
-#define TIMING_CFG1_CASLAT_SHIFT     16
-#define TIMING_CFG1_REFREC   0x0000F000
-#define TIMING_CFG1_REFREC_SHIFT     12
-#define TIMING_CFG1_WRREC    0x00000700
-#define TIMING_CFG1_WRREC_SHIFT       8
-#define TIMING_CFG1_ACTTOACT 0x00000070
-#define TIMING_CFG1_ACTTOACT_SHIFT    4
-#define TIMING_CFG1_WRTORD   0x00000007
-#define TIMING_CFG1_WRTORD_SHIFT      0
-#define TIMING_CFG1_CASLAT_20 0x00030000  /* CAS latency = 2.0 */
-#define TIMING_CFG1_CASLAT_25 0x00040000  /* CAS latency = 2.5 */
-
-	u32 timing_cfg_2;       /**< SDRAM Timing Configuration 2 */
-#define TIMING_CFG2_CPO           0x0F000000
-#define TIMING_CFG2_CPO_SHIFT             24
-#define TIMING_CFG2_ACSM          0x00080000
-#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
-#define TIMING_CFG2_WR_DATA_DELAY_SHIFT   10
-#define TIMING_CFG2_CPO_DEF       0x00000000  /* default (= CASLAT + 1) */
-
-	u32 sdram_cfg;          /**< SDRAM Control Configuration */
-#define SDRAM_CFG_MEM_EN     0x80000000
-#define SDRAM_CFG_SREN       0x40000000
-#define SDRAM_CFG_ECC_EN     0x20000000
-#define SDRAM_CFG_RD_EN      0x10000000
-#define SDRAM_CFG_SDRAM_TYPE 0x03000000
-#define SDRAM_CFG_SDRAM_TYPE_SHIFT   24
-#define SDRAM_CFG_DYN_PWR    0x00200000
-#define SDRAM_CFG_32_BE      0x00080000
-#define SDRAM_CFG_8_BE       0x00040000
-#define SDRAM_CFG_NCAP       0x00020000
-#define SDRAM_CFG_2T_EN      0x00008000
-#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
-
+	u32 cs_config[4];	/* Chip Select x Configuration */
+	u8 res1[0x70];
+	u32 timing_cfg_3;	/* SDRAM Timing Configuration 3 */
+	u32 timing_cfg_0;	/* SDRAM Timing Configuration 0 */
+	u32 timing_cfg_1;	/* SDRAM Timing Configuration 1 */
+	u32 timing_cfg_2;	/* SDRAM Timing Configuration 2 */
+	u32 sdram_cfg;		/* SDRAM Control Configuration */
+	u32 sdram_cfg2;		/* SDRAM Control Configuration 2 */
+	u32 sdram_mode;		/* SDRAM Mode Configuration */
+	u32 sdram_mode2;	/* SDRAM Mode Configuration 2 */
+	u32 sdram_md_cntl;	/* SDRAM Mode Control */
+	u32 sdram_interval;	/* SDRAM Interval Configuration */
+	u32 ddr_data_init;	/* SDRAM Data Initialization */
 	u8 res2[4];
-	u32 sdram_mode;         /**< SDRAM Mode Configuration */
-#define SDRAM_MODE_ESD 0xFFFF0000
-#define SDRAM_MODE_ESD_SHIFT   16
-#define SDRAM_MODE_SD  0x0000FFFF
-#define SDRAM_MODE_SD_SHIFT     0
-#define DDR_MODE_EXT_MODEREG    0x4000  /* select extended mode reg */
-#define DDR_MODE_EXT_OPMODE     0x3FF8  /* operating mode, mask */
-#define DDR_MODE_EXT_OP_NORMAL  0x0000  /* normal operation */
-#define DDR_MODE_QFC            0x0004  /* QFC / compatibility, mask */
-#define DDR_MODE_QFC_COMP       0x0000  /* compatible to older SDRAMs */
-#define DDR_MODE_WEAK           0x0002  /* weak drivers */
-#define DDR_MODE_DLL_DIS        0x0001  /* disable DLL */
-#define DDR_MODE_CASLAT         0x0070  /* CAS latency, mask */
-#define DDR_MODE_CASLAT_15      0x0010  /* CAS latency 1.5 */
-#define DDR_MODE_CASLAT_20      0x0020  /* CAS latency 2 */
-#define DDR_MODE_CASLAT_25      0x0060  /* CAS latency 2.5 */
-#define DDR_MODE_CASLAT_30      0x0030  /* CAS latency 3 */
-#define DDR_MODE_BTYPE_SEQ      0x0000  /* sequential burst */
-#define DDR_MODE_BTYPE_ILVD     0x0008  /* interleaved burst */
-#define DDR_MODE_BLEN_2         0x0001  /* burst length 2 */
-#define DDR_MODE_BLEN_4         0x0002  /* burst length 4 */
-#define DDR_REFINT_166MHZ_7US   1302        /* exact value for 7.8125 µs */
-#define DDR_BSTOPRE     256     /* use 256 cycles as a starting point */
-#define DDR_MODE_MODEREG        0x0000  /* select mode register */
-
-	u8 res3[8];
-	u32 sdram_interval;     /**< SDRAM Interval Configuration */
-#define SDRAM_INTERVAL_REFINT  0x3FFF0000
-#define SDRAM_INTERVAL_REFINT_SHIFT    16
-#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
-#define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
-	u8   res9[8];
-	u32  sdram_clk_cntl;
-#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025	0x01000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075	0x03000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1		0x04000000
-
-	u8 res4[0xCCC];
-	u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
-	u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
-	u32 ecc_err_inject;     /**< Memory Data Path Error Injection Mask ECC */
-#define ECC_ERR_INJECT_EMB			(0x80000000>>22)	/* ECC Mirror Byte */
-#define ECC_ERR_INJECT_EIEN			(0x80000000>>23)	/* Error Injection Enable */
-#define ECC_ERR_INJECT_EEIM			(0xff000000>>24)	/* ECC Erroe Injection Enable */
-#define ECC_ERR_INJECT_EEIM_SHIFT		0
-	u8 res5[0x14];
-	u32 capture_data_hi;    /**< Memory Data Path Read Capture High */
-	u32 capture_data_lo;    /**< Memory Data Path Read Capture Low */
-	u32 capture_ecc;        /**< Memory Data Path Read Capture ECC */
-#define CAPTURE_ECC_ECE				(0xff000000>>24)
-#define CAPTURE_ECC_ECE_SHIFT			0
+	u32 sdram_clk_cntl;	/* SDRAM Clock Control */
+	u8 res3[0x14];
+	u32 ddr_init_addr;	/* DDR training initialization address */
+	u32 ddr_init_ext_addr;	/* DDR training initialization extended address */
+	u8 res4[0xAA8];
+	u32 ddr_ip_rev1;	/* DDR IP block revision 1 */
+	u32 ddr_ip_rev2;	/* DDR IP block revision 2 */
+	u8 res5[0x200];
+	u32 data_err_inject_hi;	/* Memory Data Path Error Injection Mask High */
+	u32 data_err_inject_lo;	/* Memory Data Path Error Injection Mask Low */
+	u32 ecc_err_inject;	/* Memory Data Path Error Injection Mask ECC */
 	u8 res6[0x14];
-	u32 err_detect;         /**< Memory Error Detect */
-#define ECC_ERROR_DETECT_MME			(0x80000000>>0)		/* Multiple Memory Errors */
-#define ECC_ERROR_DETECT_MBE			(0x80000000>>28)	/* Multiple-Bit Error */
-#define ECC_ERROR_DETECT_SBE			(0x80000000>>29)	/* Single-Bit ECC Error Pickup */
-#define ECC_ERROR_DETECT_MSE			(0x80000000>>31)	/* Memory Select Error */
-	u32 err_disable;        /**< Memory Error Disable */
-#define ECC_ERROR_DISABLE_MBED			(0x80000000>>28)	/* Multiple-Bit ECC Error Disable */
-#define ECC_ERROR_DISABLE_SBED			(0x80000000>>29)	/* Sinle-Bit ECC Error disable */
-#define ECC_ERROR_DISABLE_MSED			(0x80000000>>31)	/* Memory Select Error Disable */
-#define ECC_ERROR_ENABLE			~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED)
-	u32 err_int_en;         /**< Memory Error Interrupt Enable */
-#define ECC_ERR_INT_EN_MBEE			(0x80000000>>28)	/* Multiple-Bit ECC Error Interrupt Enable */
-#define ECC_ERR_INT_EN_SBEE			(0x80000000>>29)	/* Single-Bit ECC Error Interrupt Enable */
-#define ECC_ERR_INT_EN_MSEE			(0x80000000>>31)	/* Memory Select Error Interrupt Enable */
-#define ECC_ERR_INT_DISABLE			~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE)
-	u32 capture_attributes; /**< Memory Error Attributes Capture */
-#define ECC_CAPT_ATTR_BNUM			(0xe0000000>>1)		/* Data Beat Num */
-#define ECC_CAPT_ATTR_BNUM_SHIFT		28
-#define ECC_CAPT_ATTR_TSIZ			(0xc0000000>>6)		/* Transaction Size */
-#define ECC_CAPT_ATTR_TSIZ_FOUR_DW		0
-#define ECC_CAPT_ATTR_TSIZ_ONE_DW		1
-#define ECC_CAPT_ATTR_TSIZ_TWO_DW		2
-#define ECC_CAPT_ATTR_TSIZ_THREE_DW		3
-#define ECC_CAPT_ATTR_TSIZ_SHIFT		24
-#define ECC_CAPT_ATTR_TSRC			(0xf8000000>>11)	/* Transaction Source */
-#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT		0x0
-#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF		0x2
-#define ECC_CAPT_ATTR_TSRC_TSEC1		0x4
-#define ECC_CAPT_ATTR_TSRC_TSEC2		0x5
-#define ECC_CAPT_ATTR_TSRC_USB			(0x06|0x07)
-#define ECC_CAPT_ATTR_TSRC_ENCRYPT		0x8
-#define ECC_CAPT_ATTR_TSRC_I2C			0x9
-#define ECC_CAPT_ATTR_TSRC_JTAG			0xA
-#define ECC_CAPT_ATTR_TSRC_PCI1			0xD
-#define ECC_CAPT_ATTR_TSRC_PCI2			0xE
-#define ECC_CAPT_ATTR_TSRC_DMA			0xF
-#define ECC_CAPT_ATTR_TSRC_SHIFT		16
-#define ECC_CAPT_ATTR_TTYP			(0xe0000000>>18)	/* Transaction Type */
-#define ECC_CAPT_ATTR_TTYP_WRITE		0x1
-#define ECC_CAPT_ATTR_TTYP_READ			0x2
-#define ECC_CAPT_ATTR_TTYP_R_M_W		0x3
-#define ECC_CAPT_ATTR_TTYP_SHIFT		12
-#define ECC_CAPT_ATTR_VLD			(0x80000000>>31)	/* Valid */
-	u32 capture_address;    /**< Memory Error Address Capture */
-	u32 capture_ext_address;/**< Memory Error Extended Address Capture */
-	u32 err_sbe;            /**< Memory Single-Bit ECC Error Management */
-#define ECC_ERROR_MAN_SBET			(0xff000000>>8)		/* Single-Bit Error Threshold 0..255*/
-#define ECC_ERROR_MAN_SBET_SHIFT		16
-#define ECC_ERROR_MAN_SBEC			(0xff000000>>24)	/* Single Bit Error Counter 0..255*/
-#define ECC_ERROR_MAN_SBEC_SHIFT		0
-	u8 res7[0xA4];
+	u32 capture_data_hi;	/* Memory Data Path Read Capture High */
+	u32 capture_data_lo;	/* Memory Data Path Read Capture Low */
+	u32 capture_ecc;	/* Memory Data Path Read Capture ECC */
+	u8 res7[0x14];
+	u32 err_detect;		/* Memory Error Detect */
+	u32 err_disable;	/* Memory Error Disable */
+	u32 err_int_en;		/* Memory Error Interrupt Enable */
+	u32 capture_attributes;	/* Memory Error Attributes Capture */
+	u32 capture_address;	/* Memory Error Address Capture */
+	u32 capture_ext_address;/* Memory Error Extended Address Capture */
+	u32 err_sbe;		/* Memory Single-Bit ECC Error Management */
+	u8 res8[0xA4];
 	u32 debug_reg;
-	u8 res8[0xFC];
-} ddr8349_t;
-
-/*
- * I2C1 Controller
- */
-
+	u8 res9[0xFC];
+} ddr83xx_t;
 
 /*
  * DUART
  */
-typedef struct duart8349{
-	u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
-	u8 uier_udmb;      /**< combined register for UIER and UDMB */
-	u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
-	u8 ulcr;        /**< line control register */
-	u8 umcr;        /**< MODEM control register */
-	u8 ulsr;        /**< line status register */
-	u8 umsr;        /**< MODEM status register */
-	u8 uscr;        /**< scratch register */
+typedef struct duart83xx {
+	u8 urbr_ulcr_udlb;	/* combined register for URBR, UTHR and UDLB */
+	u8 uier_udmb;		/* combined register for UIER and UDMB */
+	u8 uiir_ufcr_uafr;	/* combined register for UIIR, UFCR and UAFR */
+	u8 ulcr;		/* line control register */
+	u8 umcr;		/* MODEM control register */
+	u8 ulsr;		/* line status register */
+	u8 umsr;		/* MODEM status register */
+	u8 uscr;		/* scratch register */
 	u8 res0[8];
-	u8 udsr;        /**< DMA status register */
+	u8 udsr;		/* DMA status register */
 	u8 res1[3];
 	u8 res2[0xEC];
-} duart8349_t;
+} duart83xx_t;
 
 /*
  * Local Bus Controller Registers
  */
-typedef struct lbus_bank{
-	u32 br;             /**< Base Register  */
-	u32 or;             /**< Base Register  */
+typedef struct lbus_bank {
+	u32 br;			/* Base Register */
+	u32 or;			/* Option Register */
 } lbus_bank_t;
 
-typedef struct lbus8349 {
+typedef struct lbus83xx {
 	lbus_bank_t bank[8];
 	u8 res0[0x28];
-	u32 mar;                /**< UPM Address Register */
+	u32 mar;		/* UPM Address Register */
 	u8 res1[0x4];
-	u32 mamr;               /**< UPMA Mode Register */
-	u32 mbmr;               /**< UPMB Mode Register */
-	u32 mcmr;               /**< UPMC Mode Register */
+	u32 mamr;		/* UPMA Mode Register */
+	u32 mbmr;		/* UPMB Mode Register */
+	u32 mcmr;		/* UPMC Mode Register */
 	u8 res2[0x8];
-	u32 mrtpr;              /**< Memory Refresh Timer Prescaler Register */
-	u32 mdr;                /**< UPM Data Register */
+	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
+	u32 mdr;		/* UPM Data Register */
 	u8 res3[0x8];
-	u32 lsdmr;              /**< SDRAM Mode Register */
+	u32 lsdmr;		/* SDRAM Mode Register */
 	u8 res4[0x8];
-	u32 lurt;               /**< UPM Refresh Timer */
-	u32 lsrt;               /**< SDRAM Refresh Timer */
+	u32 lurt;		/* UPM Refresh Timer */
+	u32 lsrt;		/* SDRAM Refresh Timer */
 	u8 res5[0x8];
-	u32 ltesr;              /**< Transfer Error Status Register */
-	u32 ltedr;              /**< Transfer Error Disable Register */
-	u32 lteir;              /**< Transfer Error Interrupt Register */
-	u32 lteatr;             /**< Transfer Error Attributes Register */
-	u32 ltear;              /**< Transfer Error Address Register */
+	u32 ltesr;		/* Transfer Error Status Register */
+	u32 ltedr;		/* Transfer Error Disable Register */
+	u32 lteir;		/* Transfer Error Interrupt Register */
+	u32 lteatr;		/* Transfer Error Attributes Register */
+	u32 ltear;		/* Transfer Error Address Register */
 	u8 res6[0xC];
-	u32 lbcr;               /**< Configuration Register */
-#define LBCR_LDIS  0x80000000
-#define LBCR_LDIS_SHIFT    31
-#define LBCR_BCTLC 0x00C00000
-#define LBCR_BCTLC_SHIFT   22
-#define LBCR_LPBSE 0x00020000
-#define LBCR_LPBSE_SHIFT   17
-#define LBCR_EPAR  0x00010000
-#define LBCR_EPAR_SHIFT    16
-#define LBCR_BMT   0x0000FF00
-#define LBCR_BMT_SHIFT      8
-	u32 lcrr;               /**< Clock Ratio Register */
-#define LCRR_DBYP    0x80000000
-#define LCRR_DBYP_SHIFT      31
-#define LCRR_BUFCMDC 0x30000000
-#define LCRR_BUFCMDC_SHIFT   28
-#define LCRR_ECL     0x03000000
-#define LCRR_ECL_SHIFT       24
-#define LCRR_EADC    0x00030000
-#define LCRR_EADC_SHIFT      16
-#define LCRR_CLKDIV  0x0000000F
-#define LCRR_CLKDIV_SHIFT     0
-
-
+	u32 lbcr;		/* Configuration Register */
+	u32 lcrr;		/* Clock Ratio Register */
 	u8 res7[0x28];
 	u8 res8[0xF00];
-} lbus8349_t;
+} lbus83xx_t;
 
 /*
  * Serial Peripheral Interface
  */
-typedef struct spi8349
-{
-	u32 mode;     /**< mode register  */
-	u32 event;    /**< event register */
-	u32 mask;     /**< mask register  */
-	u32 com;      /**< command register */
+typedef struct spi83xx {
+	u32 mode;		/* mode register */
+	u32 event;		/* event register */
+	u32 mask;		/* mask register */
+	u32 com;		/* command register */
 	u8 res0[0x10];
-	u32 tx;       /**< transmit register */
-	u32 rx;       /**< receive register */
-	u8 res1[0xD8];
-} spi8349_t;
-
+	u32 tx;			/* transmit register */
+	u32 rx;			/* receive register */
+	u8 res1[0xFD8];
+} spi83xx_t;
 
 /*
  * DMA/Messaging Unit
  */
-typedef struct dma8349 {
-	u32 res0[0xC];	/* 0x0-0x29 reseverd */
-	u32 omisr;	/* 0x30 Outbound message interrupt status register */
-	u32 omimr;	/* 0x34 Outbound message interrupt mask register */
-	u32 res1[0x6];	/* 0x38-0x49 reserved */
-
-	u32 imr0;	/* 0x50 Inbound message register 0 */
-	u32 imr1;	/* 0x54 Inbound message register 1 */
-	u32 omr0;	/* 0x58 Outbound message register 0 */
-	u32 omr1;	/* 0x5C Outbound message register 1 */
-
-	u32 odr;	/* 0x60 Outbound doorbell register */
-	u32 res2;	/* 0x64-0x67 reserved */
-	u32 idr;	/* 0x68 Inbound doorbell register */
-	u32 res3[0x5];	/* 0x6C-0x79 reserved */
-
-	u32 imisr;	/* 0x80 Inbound message interrupt status register */
-	u32 imimr;	/* 0x84 Inbound message interrupt mask register */
-	u32 res4[0x1E];	/* 0x88-0x99 reserved */
-
-	u32 dmamr0;	/* 0x100 DMA 0 mode register */
-	u32 dmasr0;	/* 0x104 DMA 0 status register */
-	u32 dmacdar0;	/* 0x108 DMA 0 current descriptor address register */
-	u32 res5;	/* 0x10C reserved */
-	u32 dmasar0;	/* 0x110 DMA 0 source address register */
-	u32 res6;	/* 0x114 reserved */
-	u32 dmadar0;	/* 0x118 DMA 0 destination address register */
-	u32 res7;	/* 0x11C reserved */
-	u32 dmabcr0;	/* 0x120 DMA 0 byte count register */
-	u32 dmandar0;	/* 0x124 DMA 0 next descriptor address register */
-	u32 res8[0x16];	/* 0x128-0x179 reserved */
-
-	u32 dmamr1;	/* 0x180 DMA 1 mode register */
-	u32 dmasr1;	/* 0x184 DMA 1 status register */
-	u32 dmacdar1;	/* 0x188 DMA 1 current descriptor address register */
-	u32 res9;	/* 0x18C reserved */
-	u32 dmasar1;	/* 0x190 DMA 1 source address register */
-	u32 res10;	/* 0x194 reserved */
-	u32 dmadar1;	/* 0x198 DMA 1 destination address register */
-	u32 res11;	/* 0x19C reserved */
-	u32 dmabcr1;	/* 0x1A0 DMA 1 byte count register */
-	u32 dmandar1;	/* 0x1A4 DMA 1 next descriptor address register */
-	u32 res12[0x16];/* 0x1A8-0x199 reserved */
-
-	u32 dmamr2;	/* 0x200 DMA 2 mode register */
-	u32 dmasr2;	/* 0x204 DMA 2 status register */
-	u32 dmacdar2;	/* 0x208 DMA 2 current descriptor address register */
-	u32 res13;	/* 0x20C reserved */
-	u32 dmasar2;	/* 0x210 DMA 2 source address register */
-	u32 res14;	/* 0x214 reserved */
-	u32 dmadar2;	/* 0x218 DMA 2 destination address register */
-	u32 res15;	/* 0x21C reserved */
-	u32 dmabcr2;	/* 0x220 DMA 2 byte count register */
-	u32 dmandar2;	/* 0x224 DMA 2 next descriptor address register */
-	u32 res16[0x16];/* 0x228-0x279 reserved */
-
-	u32 dmamr3;	/* 0x280 DMA 3 mode register */
-	u32 dmasr3;	/* 0x284 DMA 3 status register */
-	u32 dmacdar3;	/* 0x288 DMA 3 current descriptor address register */
-	u32 res17;	/* 0x28C reserved */
-	u32 dmasar3;	/* 0x290 DMA 3 source address register */
-	u32 res18;	/* 0x294 reserved */
-	u32 dmadar3;	/* 0x298 DMA 3 destination address register */
-	u32 res19;	/* 0x29C reserved */
-	u32 dmabcr3;	/* 0x2A0 DMA 3 byte count register */
-	u32 dmandar3;	/* 0x2A4 DMA 3 next descriptor address register */
-
-	u32 dmagsr;	/* 0x2A8 DMA general status register */
-	u32 res20[0x15];/* 0x2AC-0x2FF reserved */
-} dma8349_t;
-
-/* DMAMRn bits */
-#define DMA_CHANNEL_START			(0x00000001)		/* Bit - DMAMRn CS */
-#define DMA_CHANNEL_TRANSFER_MODE_DIRECT	(0x00000004)		/* Bit - DMAMRn CTM */
-#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN	(0x00001000)		/* Bit - DMAMRn SAHE */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B	(0x00000000)		/* 2Bit- DMAMRn SAHTS 1byte */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B	(0x00004000)		/* 2Bit- DMAMRn SAHTS 2bytes */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B	(0x00008000)		/* 2Bit- DMAMRn SAHTS 4bytes */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B	(0x0000c000)		/* 2Bit- DMAMRn SAHTS 8bytes */
-#define DMA_CHANNEL_SNOOP			(0x00010000)		/* Bit - DMAMRn DMSEN */
-
-/* DMASRn bits */
-#define DMA_CHANNEL_BUSY 			(0x00000004)		/* Bit - DMASRn CB */
-#define DMA_CHANNEL_TRANSFER_ERROR		(0x00000080)		/* Bit - DMASRn TE */
+typedef struct dma83xx {
+	u32 res0[0xC];		/* 0x0-0x29 reseverd */
+	u32 omisr;		/* 0x30 Outbound message interrupt status register */
+	u32 omimr;		/* 0x34 Outbound message interrupt mask register */
+	u32 res1[0x6];		/* 0x38-0x49 reserved */
+	u32 imr0;		/* 0x50 Inbound message register 0 */
+	u32 imr1;		/* 0x54 Inbound message register 1 */
+	u32 omr0;		/* 0x58 Outbound message register 0 */
+	u32 omr1;		/* 0x5C Outbound message register 1 */
+	u32 odr;		/* 0x60 Outbound doorbell register */
+	u32 res2;		/* 0x64-0x67 reserved */
+	u32 idr;		/* 0x68 Inbound doorbell register */
+	u32 res3[0x5];		/* 0x6C-0x79 reserved */
+	u32 imisr;		/* 0x80 Inbound message interrupt status register */
+	u32 imimr;		/* 0x84 Inbound message interrupt mask register */
+	u32 res4[0x1E];		/* 0x88-0x99 reserved */
+	u32 dmamr0;		/* 0x100 DMA 0 mode register */
+	u32 dmasr0;		/* 0x104 DMA 0 status register */
+	u32 dmacdar0;		/* 0x108 DMA 0 current descriptor address register */
+	u32 res5;		/* 0x10C reserved */
+	u32 dmasar0;		/* 0x110 DMA 0 source address register */
+	u32 res6;		/* 0x114 reserved */
+	u32 dmadar0;		/* 0x118 DMA 0 destination address register */
+	u32 res7;		/* 0x11C reserved */
+	u32 dmabcr0;		/* 0x120 DMA 0 byte count register */
+	u32 dmandar0;		/* 0x124 DMA 0 next descriptor address register */
+	u32 res8[0x16];		/* 0x128-0x179 reserved */
+	u32 dmamr1;		/* 0x180 DMA 1 mode register */
+	u32 dmasr1;		/* 0x184 DMA 1 status register */
+	u32 dmacdar1;		/* 0x188 DMA 1 current descriptor address register */
+	u32 res9;		/* 0x18C reserved */
+	u32 dmasar1;		/* 0x190 DMA 1 source address register */
+	u32 res10;		/* 0x194 reserved */
+	u32 dmadar1;		/* 0x198 DMA 1 destination address register */
+	u32 res11;		/* 0x19C reserved */
+	u32 dmabcr1;		/* 0x1A0 DMA 1 byte count register */
+	u32 dmandar1;		/* 0x1A4 DMA 1 next descriptor address register */
+	u32 res12[0x16];	/* 0x1A8-0x199 reserved */
+	u32 dmamr2;		/* 0x200 DMA 2 mode register */
+	u32 dmasr2;		/* 0x204 DMA 2 status register */
+	u32 dmacdar2;		/* 0x208 DMA 2 current descriptor address register */
+	u32 res13;		/* 0x20C reserved */
+	u32 dmasar2;		/* 0x210 DMA 2 source address register */
+	u32 res14;		/* 0x214 reserved */
+	u32 dmadar2;		/* 0x218 DMA 2 destination address register */
+	u32 res15;		/* 0x21C reserved */
+	u32 dmabcr2;		/* 0x220 DMA 2 byte count register */
+	u32 dmandar2;		/* 0x224 DMA 2 next descriptor address register */
+	u32 res16[0x16];	/* 0x228-0x279 reserved */
+	u32 dmamr3;		/* 0x280 DMA 3 mode register */
+	u32 dmasr3;		/* 0x284 DMA 3 status register */
+	u32 dmacdar3;		/* 0x288 DMA 3 current descriptor address register */
+	u32 res17;		/* 0x28C reserved */
+	u32 dmasar3;		/* 0x290 DMA 3 source address register */
+	u32 res18;		/* 0x294 reserved */
+	u32 dmadar3;		/* 0x298 DMA 3 destination address register */
+	u32 res19;		/* 0x29C reserved */
+	u32 dmabcr3;		/* 0x2A0 DMA 3 byte count register */
+	u32 dmandar3;		/* 0x2A4 DMA 3 next descriptor address register */
+	u32 dmagsr;		/* 0x2A8 DMA general status register */
+	u32 res20[0x15];	/* 0x2AC-0x2FF reserved */
+} dma83xx_t;
 
 /*
  * PCI Software Configuration Registers
  */
-typedef struct pciconf8349 {
-	u32	config_address;
-#define PCI_CONFIG_ADDRESS_EN	0x80000000
-#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
-#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
-#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
-#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
-#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
-#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
-#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
-#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
+typedef struct pciconf83xx {
+	u32 config_address;
 	u32 config_data;
 	u32 int_ack;
-	u8	res[116];
-} pciconf8349_t;
+	u8 res[116];
+} pciconf83xx_t;
 
 /*
  * PCI Outbound Translation Register
  */
 typedef struct pci_outbound_window {
-	u32	potar;
-	u8	res0[4];
-	u32	pobar;
-	u8	res1[4];
-	u32	pocmr;
-	u8	res2[4];
-} pot8349_t;
+	u32 potar;
+	u8 res0[4];
+	u32 pobar;
+	u8 res1[4];
+	u32 pocmr;
+	u8 res2[4];
+} pot83xx_t;
+
 /*
  * Sequencer
  */
-typedef struct ios8349 {
-	pot8349_t	pot[6];
-#define POTAR_TA_MASK	0x000fffff
-#define	POBAR_BA_MASK	0x000fffff
-#define	POCMR_EN	0x80000000
-#define	POCMR_IO	0x40000000	/* 0--memory space 1--I/O space */
-#define	POCMR_SE	0x20000000	/* streaming enable */
-#define	POCMR_DST	0x10000000	/* 0--PCI1 1--PCI2*/
-#define	POCMR_CM_MASK	0x000fffff
-#define	POCMR_CM_4G	0x00000000
-#define	POCMR_CM_2G	0x00080000
-#define	POCMR_CM_1G	0x000C0000
-#define	POCMR_CM_512M	0x000E0000
-#define	POCMR_CM_256M	0x000F0000
-#define	POCMR_CM_128M	0x000F8000
-#define	POCMR_CM_64M	0x000FC000
-#define	POCMR_CM_32M	0x000FE000
-#define	POCMR_CM_16M	0x000FF000
-#define	POCMR_CM_8M	0x000FF800
-#define	POCMR_CM_4M	0x000FFC00
-#define	POCMR_CM_2M	0x000FFE00
-#define	POCMR_CM_1M	0x000FFF00
-#define	POCMR_CM_512K	0x000FFF80
-#define	POCMR_CM_256K	0x000FFFC0
-#define	POCMR_CM_128K	0x000FFFE0
-#define	POCMR_CM_64K	0x000FFFF0
-#define	POCMR_CM_32K	0x000FFFF8
-#define	POCMR_CM_16K	0x000FFFFC
-#define	POCMR_CM_8K	0x000FFFFE
-#define	POCMR_CM_4K	0x000FFFFF
-	u8	res0[0x60];
-	u32	pmcr;
-	u8	res1[4];
-	u32	dtcr;
-	u8	res2[4];
-} ios8349_t;
+typedef struct ios83xx {
+	pot83xx_t pot[6];
+	u8 res0[0x60];
+	u32 pmcr;
+	u8 res1[4];
+	u32 dtcr;
+	u8 res2[4];
+} ios83xx_t;
 
 /*
  * PCI Controller Control and Status Registers
  */
-typedef struct pcictrl8349 {
-	u32	esr;
-#define ESR_MERR	0x80000000
-#define ESR_APAR	0x00000400
-#define	ESR_PCISERR	0x00000200
-#define	ESR_MPERR	0x00000100
-#define	ESR_TPERR	0x00000080
-#define	ESR_NORSP	0x00000040
-#define	ESR_TABT	0x00000020
-	u32	ecdr;
-#define ECDR_APAR	0x00000400
-#define	ECDR_PCISERR	0x00000200
-#define	ECDR_MPERR	0x00000100
-#define	ECDR_TPERR	0x00000080
-#define	ECDR_NORSP	0x00000040
-#define	ECDR_TABT	0x00000020
+typedef struct pcictrl83xx {
+	u32 esr;
+	u32 ecdr;
 	u32 eer;
-#define EER_APAR	0x00000400
-#define	EER_PCISERR	0x00000200
-#define	EER_MPERR	0x00000100
-#define	EER_TPERR	0x00000080
-#define	EER_NORSP	0x00000040
-#define	EER_TABT	0x00000020
-	u32	eatcr;
-#define	EATCR_ERRTYPR_MASK	0x70000000
-#define	EATCR_ERRTYPR_APR	0x00000000	/* address parity error */
-#define	EATCR_ERRTYPR_WDPR	0x10000000	/* write data parity error */
-#define	EATCR_ERRTYPR_RDPR	0x20000000	/* read data parity error */
-#define	EATCR_ERRTYPR_MA	0x30000000	/* master abort */
-#define	EATCR_ERRTYPR_TA	0x40000000	/* target abort */
-#define	EATCR_ERRTYPR_SE	0x50000000	/* system error indication received */
-#define	EATCR_ERRTYPR_PEA	0x60000000	/* parity error indication received on a read */
-#define	EATCR_ERRTYPR_PEW	0x70000000	/* parity error indication received on a write */
-#define EATCR_BN_MASK		0x0f000000	/* beat number */
-#define	EATCR_BN_1st		0x00000000
-#define	EATCR_BN_2ed		0x01000000
-#define	EATCR_BN_3rd		0x02000000
-#define	EATCR_BN_4th		0x03000000
-#define	EATCR_BN_5th		0x0400000
-#define	EATCR_BN_6th		0x05000000
-#define	EATCR_BN_7th		0x06000000
-#define	EATCR_BN_8th		0x07000000
-#define	EATCR_BN_9th		0x08000000
-#define EATCR_TS_MASK		0x00300000	/* transaction size */
-#define	EATCR_TS_4		0x00000000
-#define	EATCR_TS_1		0x00100000
-#define	EATCR_TS_2		0x00200000
-#define	EATCR_TS_3		0x00300000
-#define	EATCR_ES_MASK		0x000f0000	/* error source */
-#define	EATCR_ES_EM		0x00000000	/* external master */
-#define	EATCR_ES_DMA		0x00050000
-#define	EATCR_CMD_MASK		0x0000f000
-#define	EATCR_HBE_MASK		0x00000f00	/* PCI high byte enable*/
-#define	EATCR_BE_MASK		0x000000f0	/* PCI byte enable */
-#define	EATCR_HPB		0x00000004	/* high parity bit */
-#define	EATCR_PB		0x00000002	/* parity bit*/
-#define	EATCR_VI		0x00000001	/* error information valid */
-	u32	eacr;
-	u32	eeacr;
-	u32	edlcr;
-	u32	edhcr;
-	u32	gcr;
-	u32	ecr;
-	u32	gsr;
-	u8	res0[12];
-	u32	pitar2;
-	u8	res1[4];
-	u32	pibar2;
-	u32	piebar2;
-	u32	piwar2;
-	u8	res2[4];
-	u32	pitar1;
-	u8	res3[4];
-	u32	pibar1;
-	u32	piebar1;
-	u32	piwar1;
-	u8	res4[4];
-	u32	pitar0;
-	u8	res5[4];
-	u32	pibar0;
-	u8	res6[4];
-	u32	piwar0;
-	u8	res7[132];
-#define PITAR_TA_MASK		0x000fffff
-#define PIBAR_MASK		0xffffffff
-#define PIEBAR_EBA_MASK		0x000fffff
-#define PIWAR_EN		0x80000000
-#define PIWAR_PF		0x20000000
-#define	PIWAR_RTT_MASK		0x000f0000
-#define	PIWAR_RTT_NO_SNOOP	0x00040000
-#define PIWAR_RTT_SNOOP		0x00050000
-#define	PIWAR_WTT_MASK		0x0000f000
-#define	PIWAR_WTT_NO_SNOOP	0x00004000
-#define PIWAR_WTT_SNOOP		0x00005000
-#define	PIWAR_IWS_MASK	0x0000003F
-#define	PIWAR_IWS_4K	0x0000000B
-#define	PIWAR_IWS_8K	0x0000000C
-#define	PIWAR_IWS_16K	0x0000000D
-#define	PIWAR_IWS_32K	0x0000000E
-#define	PIWAR_IWS_64K	0x0000000F
-#define	PIWAR_IWS_128K	0x00000010
-#define	PIWAR_IWS_256K	0x00000011
-#define	PIWAR_IWS_512K	0x00000012
-#define	PIWAR_IWS_1M	0x00000013
-#define	PIWAR_IWS_2M	0x00000014
-#define	PIWAR_IWS_4M	0x00000015
-#define	PIWAR_IWS_8M	0x00000016
-#define	PIWAR_IWS_16M	0x00000017
-#define	PIWAR_IWS_32M	0x00000018
-#define	PIWAR_IWS_64M	0x00000019
-#define	PIWAR_IWS_128M	0x0000001A
-#define	PIWAR_IWS_256M	0x0000001B
-#define	PIWAR_IWS_512M	0x0000001C
-#define	PIWAR_IWS_1G	0x0000001D
-#define	PIWAR_IWS_2G	0x0000001E
-} pcictrl8349_t;
+	u32 eatcr;
+	u32 eacr;
+	u32 eeacr;
+	u32 edlcr;
+	u32 edhcr;
+	u32 gcr;
+	u32 ecr;
+	u32 gsr;
+	u8 res0[12];
+	u32 pitar2;
+	u8 res1[4];
+	u32 pibar2;
+	u32 piebar2;
+	u32 piwar2;
+	u8 res2[4];
+	u32 pitar1;
+	u8 res3[4];
+	u32 pibar1;
+	u32 piebar1;
+	u32 piwar1;
+	u8 res4[4];
+	u32 pitar0;
+	u8 res5[4];
+	u32 pibar0;
+	u8 res6[4];
+	u32 piwar0;
+	u8 res7[132];
+} pcictrl83xx_t;
 
 /*
  * USB
  */
-typedef struct usb8349 {
+typedef struct usb83xx {
 	u8 fixme[0x2000];
-} usb8349_t;
+} usb83xx_t;
 
 /*
  * TSEC
  */
-typedef struct tsec8349 {
+typedef struct tsec83xx {
 	u8 fixme[0x1000];
-} tsec8349_t;
+} tsec83xx_t;
 
 /*
  * Security
  */
-typedef struct security8349 {
+typedef struct security83xx {
 	u8 fixme[0x10000];
-} security8349_t;
+} security83xx_t;
+
+#if defined(CONFIG_MPC834X)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[2];	/* General purpose I/O module */
+	u8			res0[0x200];
+	u8			dll_ddr[0x100];
+	u8			dll_lbc[0x100];
+	u8			res1[0xE00];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res2[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res3[0x900];
+	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	u8			res4[0x1000];
+	spi83xx_t		spi;		/* Serial Peripheral Interface */
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[2];	/* PCI Software Configuration Registers */
+	ios83xx_t		ios;		/* Sequencer */
+	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
+	u8			res5[0x19900];
+	usb83xx_t		usb;
+	tsec83xx_t		tsec[2];
+	u8			res6[0xA000];
+	security83xx_t		security;
+	u8			res7[0xC0000];
+} immap_t;
+
+#elif defined(CONFIG_MPC8360)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	u8			res0[0x200];
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
+	u8			res1[0x300];
+	u8			dll_ddr[0x100];
+	u8			dll_lbc[0x100];
+	u8			res2[0x200];
+	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
+	qesba83xx_t		qesba;		/* QE Secondary Bus Access Windows */
+	u8			res3[0x400];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res4[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res5[0x900];
+	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	u8			res6[0x2000];
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res7[128];
+	ios83xx_t		ios;		/* Sequencer (IOS) */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res8[0x4A00];
+	ddr83xx_t		ddr_secondary;	/* Secondary DDR Memory Controller Memory Map */
+	u8			res9[0x22000];
+	security83xx_t		security;
+	u8			res10[0xC0000];
+	u8			qe[0x100000];	/* QE block */
+} immap_t;
 
+#elif defined(CONFIG_MPC832X)
 typedef struct immap {
-	sysconf8349_t sysconf; /* System configuration */
-	wdt8349_t     wdt;     /* Watch Dog Timer (WDT) Registers */
-	rtclk8349_t   rtc;     /* Real Time Clock Module Registers */
-	rtclk8349_t   pit;     /* Periodic Interval Timer */
-	gtm8349_t     gtm[2];  /* Global Timers Module */
-	ipic8349_t    ipic;    /* Integrated Programmable Interrupt Controller */
-	arbiter8349_t arbiter; /* System Arbiter Registers */
-	reset8349_t   reset;   /* Reset Module */
-	clk8349_t     clk;     /* System Clock Module */
-	pmc8349_t     pmc;     /* Power Management Control Module */
-	gpio8349_t    pgio[2]; /* general purpose I/O module */
-	u8 res0[0x200];
-	u8 DDL_DDR[0x100];
-	u8 DDL_LBIU[0x100];
-	u8 res1[0xE00];
-	ddr8349_t     ddr;     /* DDR Memory Controller Memory */
-	i2c_t     i2c[2];      /* I2C1 Controller */
-	u8 res2[0x1300];
-	duart8349_t   duart[2];/* DUART */
-	u8 res3[0x900];
-	lbus8349_t    lbus;    /* Local Bus Controller Registers */
-	u8 res4[0x1000];
-	spi8349_t     spi;     /* Serial Peripheral Interface */
-	u8 res5[0xF00];
-	dma8349_t     dma;     /* DMA */
-	pciconf8349_t pci_conf[2];  /* PCI Software Configuration Registers */
-	ios8349_t     ios;     /* Sequencer */
-	pcictrl8349_t pci_ctrl[2];  /* PCI Controller Control and Status Registers */
-	u8 res6[0x19900];
-	usb8349_t     usb;
-	tsec8349_t    tsec[2];
-	u8 res7[0xA000];
-	security8349_t security;
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
+	u8			res0[0x300];
+	u8			dll_ddr[0x100];
+	u8			dll_lbc[0x100];
+	u8			res1[0x200];
+	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
+	u8			res2[0x800];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res3[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res4[0x900];
+	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	u8			res5[0x2000];
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res6[128];
+	ios83xx_t		ios;		/* Sequencer (IOS) */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res7[0x27A00];
+	security83xx_t		security;
+	u8			res8[0xC0000];
+	u8			qe[0x100000];	/* QE block */
 } immap_t;
+#endif
 
-#endif /* __IMMAP_8349__ */
+#endif				/* __IMMAP_83xx__ */
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
new file mode 100644
index 0000000..950b949
--- /dev/null
+++ b/include/asm-ppc/immap_qe.h
@@ -0,0 +1,556 @@
+/*
+ * QUICC Engine (QE) Internal Memory Map.
+ * The Internal Memory Map for devices with QE on them. This
+ * is the superset of all QE devices (8360, etc.).
+ *
+ * Copyright (c) 2006 Freescale Semiconductor, Inc.
+ * Author: Shlomi Gridih <gridish@freescale.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __IMMAP_QE_H__
+#define __IMMAP_QE_H__
+
+/* QE I-RAM
+*/
+typedef struct qe_iram {
+	u32 iadd;		/* I-RAM Address Register */
+	u32 idata;		/* I-RAM Data Register    */
+	u8 res0[0x78];
+} __attribute__ ((packed)) qe_iram_t;
+
+/* QE Interrupt Controller
+*/
+typedef struct qe_ic {
+	u32 qicr;
+	u32 qivec;
+	u32 qripnr;
+	u32 qipnr;
+	u32 qipxcc;
+	u32 qipycc;
+	u32 qipwcc;
+	u32 qipzcc;
+	u32 qimr;
+	u32 qrimr;
+	u32 qicnr;
+	u8 res0[0x4];
+	u32 qiprta;
+	u32 qiprtb;
+	u8 res1[0x4];
+	u32 qricr;
+	u8 res2[0x20];
+	u32 qhivec;
+	u8 res3[0x1C];
+} __attribute__ ((packed)) qe_ic_t;
+
+/* Communications Processor
+*/
+typedef struct cp_qe {
+	u32 cecr;		/* QE command register */
+	u32 ceccr;		/* QE controller configuration register */
+	u32 cecdr;		/* QE command data register */
+	u8 res0[0xA];
+	u16 ceter;		/* QE timer event register */
+	u8 res1[0x2];
+	u16 cetmr;		/* QE timers mask register */
+	u32 cetscr;		/* QE time-stamp timer control register */
+	u32 cetsr1;		/* QE time-stamp register 1 */
+	u32 cetsr2;		/* QE time-stamp register 2 */
+	u8 res2[0x8];
+	u32 cevter;		/* QE virtual tasks event register */
+	u32 cevtmr;		/* QE virtual tasks mask register */
+	u16 cercr;		/* QE RAM control register */
+	u8 res3[0x2];
+	u8 res4[0x24];
+	u16 ceexe1;		/* QE external request 1 event register */
+	u8 res5[0x2];
+	u16 ceexm1;		/* QE external request 1 mask register */
+	u8 res6[0x2];
+	u16 ceexe2;		/* QE external request 2 event register */
+	u8 res7[0x2];
+	u16 ceexm2;		/* QE external request 2 mask register */
+	u8 res8[0x2];
+	u16 ceexe3;		/* QE external request 3 event register */
+	u8 res9[0x2];
+	u16 ceexm3;		/* QE external request 3 mask register */
+	u8 res10[0x2];
+	u16 ceexe4;		/* QE external request 4 event register */
+	u8 res11[0x2];
+	u16 ceexm4;		/* QE external request 4 mask register */
+	u8 res12[0x2];
+	u8 res13[0x280];
+} __attribute__ ((packed)) cp_qe_t;
+
+/* QE Multiplexer
+*/
+typedef struct qe_mux {
+	u32 cmxgcr;		/* CMX general clock route register    */
+	u32 cmxsi1cr_l;		/* CMX SI1 clock route low register    */
+	u32 cmxsi1cr_h;		/* CMX SI1 clock route high register   */
+	u32 cmxsi1syr;		/* CMX SI1 SYNC route register         */
+	u32 cmxucr1;		/* CMX UCC1, UCC3 clock route register */
+	u32 cmxucr2;		/* CMX UCC5, UCC7 clock route register */
+	u32 cmxucr3;		/* CMX UCC2, UCC4 clock route register */
+	u32 cmxucr4;		/* CMX UCC6, UCC8 clock route register */
+	u32 cmxupcr;		/* CMX UPC clock route register        */
+	u8 res0[0x1C];
+} __attribute__ ((packed)) qe_mux_t;
+
+/* QE Timers
+*/
+typedef struct qe_timers {
+	u8 gtcfr1;		/* Timer 1 2 global configuration register */
+	u8 res0[0x3];
+	u8 gtcfr2;		/* Timer 3 4 global configuration register */
+	u8 res1[0xB];
+	u16 gtmdr1;		/* Timer 1 mode register */
+	u16 gtmdr2;		/* Timer 2 mode register */
+	u16 gtrfr1;		/* Timer 1 reference register */
+	u16 gtrfr2;		/* Timer 2 reference register */
+	u16 gtcpr1;		/* Timer 1 capture register */
+	u16 gtcpr2;		/* Timer 2 capture register */
+	u16 gtcnr1;		/* Timer 1 counter */
+	u16 gtcnr2;		/* Timer 2 counter */
+	u16 gtmdr3;		/* Timer 3 mode register */
+	u16 gtmdr4;		/* Timer 4 mode register */
+	u16 gtrfr3;		/* Timer 3 reference register */
+	u16 gtrfr4;		/* Timer 4 reference register */
+	u16 gtcpr3;		/* Timer 3 capture register */
+	u16 gtcpr4;		/* Timer 4 capture register */
+	u16 gtcnr3;		/* Timer 3 counter */
+	u16 gtcnr4;		/* Timer 4 counter */
+	u16 gtevr1;		/* Timer 1 event register */
+	u16 gtevr2;		/* Timer 2 event register */
+	u16 gtevr3;		/* Timer 3 event register */
+	u16 gtevr4;		/* Timer 4 event register */
+	u16 gtps;		/* Timer 1 prescale register */
+	u8 res2[0x46];
+} __attribute__ ((packed)) qe_timers_t;
+
+/* BRG
+*/
+typedef struct qe_brg {
+	u32 brgc1;		/* BRG1 configuration register  */
+	u32 brgc2;		/* BRG2 configuration register  */
+	u32 brgc3;		/* BRG3 configuration register  */
+	u32 brgc4;		/* BRG4 configuration register  */
+	u32 brgc5;		/* BRG5 configuration register  */
+	u32 brgc6;		/* BRG6 configuration register  */
+	u32 brgc7;		/* BRG7 configuration register  */
+	u32 brgc8;		/* BRG8 configuration register  */
+	u32 brgc9;		/* BRG9 configuration register  */
+	u32 brgc10;		/* BRG10 configuration register */
+	u32 brgc11;		/* BRG11 configuration register */
+	u32 brgc12;		/* BRG12 configuration register */
+	u32 brgc13;		/* BRG13 configuration register */
+	u32 brgc14;		/* BRG14 configuration register */
+	u32 brgc15;		/* BRG15 configuration register */
+	u32 brgc16;		/* BRG16 configuration register */
+	u8 res0[0x40];
+} __attribute__ ((packed)) qe_brg_t;
+
+/* SPI
+*/
+typedef struct spi {
+	u8 res0[0x20];
+	u32 spmode;		/* SPI mode register */
+	u8 res1[0x2];
+	u8 spie;		/* SPI event register */
+	u8 res2[0x1];
+	u8 res3[0x2];
+	u8 spim;		/* SPI mask register */
+	u8 res4[0x1];
+	u8 res5[0x1];
+	u8 spcom;		/* SPI command register  */
+	u8 res6[0x2];
+	u32 spitd;		/* SPI transmit data register (cpu mode) */
+	u32 spird;		/* SPI receive data register (cpu mode) */
+	u8 res7[0x8];
+} __attribute__ ((packed)) spi_t;
+
+/* SI
+*/
+typedef struct si1 {
+	u16 siamr1;		/* SI1 TDMA mode register */
+	u16 sibmr1;		/* SI1 TDMB mode register */
+	u16 sicmr1;		/* SI1 TDMC mode register */
+	u16 sidmr1;		/* SI1 TDMD mode register */
+	u8 siglmr1_h;		/* SI1 global mode register high */
+	u8 res0[0x1];
+	u8 sicmdr1_h;		/* SI1 command register high */
+	u8 res2[0x1];
+	u8 sistr1_h;		/* SI1 status register high */
+	u8 res3[0x1];
+	u16 sirsr1_h;		/* SI1 RAM shadow address register high */
+	u8 sitarc1;		/* SI1 RAM counter Tx TDMA */
+	u8 sitbrc1;		/* SI1 RAM counter Tx TDMB */
+	u8 sitcrc1;		/* SI1 RAM counter Tx TDMC */
+	u8 sitdrc1;		/* SI1 RAM counter Tx TDMD */
+	u8 sirarc1;		/* SI1 RAM counter Rx TDMA */
+	u8 sirbrc1;		/* SI1 RAM counter Rx TDMB */
+	u8 sircrc1;		/* SI1 RAM counter Rx TDMC */
+	u8 sirdrc1;		/* SI1 RAM counter Rx TDMD */
+	u8 res4[0x8];
+	u16 siemr1;		/* SI1 TDME mode register 16 bits */
+	u16 sifmr1;		/* SI1 TDMF mode register 16 bits */
+	u16 sigmr1;		/* SI1 TDMG mode register 16 bits */
+	u16 sihmr1;		/* SI1 TDMH mode register 16 bits */
+	u8 siglmg1_l;		/* SI1 global mode register low 8 bits */
+	u8 res5[0x1];
+	u8 sicmdr1_l;		/* SI1 command register low 8 bits */
+	u8 res6[0x1];
+	u8 sistr1_l;		/* SI1 status register low 8 bits */
+	u8 res7[0x1];
+	u16 sirsr1_l;		/* SI1 RAM shadow address register low 16 bits */
+	u8 siterc1;		/* SI1 RAM counter Tx TDME 8 bits */
+	u8 sitfrc1;		/* SI1 RAM counter Tx TDMF 8 bits */
+	u8 sitgrc1;		/* SI1 RAM counter Tx TDMG 8 bits */
+	u8 sithrc1;		/* SI1 RAM counter Tx TDMH 8 bits */
+	u8 sirerc1;		/* SI1 RAM counter Rx TDME 8 bits */
+	u8 sirfrc1;		/* SI1 RAM counter Rx TDMF 8 bits */
+	u8 sirgrc1;		/* SI1 RAM counter Rx TDMG 8 bits */
+	u8 sirhrc1;		/* SI1 RAM counter Rx TDMH 8 bits */
+	u8 res8[0x8];
+	u32 siml1;		/* SI1 multiframe limit register */
+	u8 siedm1;		/* SI1 extended diagnostic mode register */
+	u8 res9[0xBB];
+} __attribute__ ((packed)) si1_t;
+
+/* SI Routing Tables
+*/
+typedef struct sir {
+	u8 tx[0x400];
+	u8 rx[0x400];
+	u8 res0[0x800];
+} __attribute__ ((packed)) sir_t;
+
+/* USB Controller.
+*/
+typedef struct usb_ctlr {
+	u8 usb_usmod;
+	u8 usb_usadr;
+	u8 usb_uscom;
+	u8 res1[1];
+	u16 usb_usep1;
+	u16 usb_usep2;
+	u16 usb_usep3;
+	u16 usb_usep4;
+	u8 res2[4];
+	u16 usb_usber;
+	u8 res3[2];
+	u16 usb_usbmr;
+	u8 res4[1];
+	u8 usb_usbs;
+	u16 usb_ussft;
+	u8 res5[2];
+	u16 usb_usfrn;
+	u8 res6[0x22];
+} __attribute__ ((packed)) usb_t;
+
+/* MCC
+*/
+typedef struct mcc {
+	u32 mcce;		/* MCC event register */
+	u32 mccm;		/* MCC mask register */
+	u32 mccf;		/* MCC configuration register */
+	u32 merl;		/* MCC emergency request level register */
+	u8 res0[0xF0];
+} __attribute__ ((packed)) mcc_t;
+
+/* QE UCC Slow
+*/
+typedef struct ucc_slow {
+	u32 gumr_l;		/* UCCx general mode register (low) */
+	u32 gumr_h;		/* UCCx general mode register (high) */
+	u16 upsmr;		/* UCCx protocol-specific mode register */
+	u8 res0[0x2];
+	u16 utodr;		/* UCCx transmit on demand register */
+	u16 udsr;		/* UCCx data synchronization register */
+	u16 ucce;		/* UCCx event register */
+	u8 res1[0x2];
+	u16 uccm;		/* UCCx mask register */
+	u8 res2[0x1];
+	u8 uccs;		/* UCCx status register */
+	u8 res3[0x24];
+	u16 utpt;
+	u8 guemr;		/* UCC general extended mode register */
+	u8 res4[0x200 - 0x091];
+} __attribute__ ((packed)) ucc_slow_t;
+
+typedef struct ucc_ethernet {
+	u32 maccfg1;		/* mac configuration reg. 1            */
+	u32 maccfg2;		/* mac configuration reg. 2            */
+	u32 ipgifg;		/* interframe gap reg.                 */
+	u32 hafdup;		/* half-duplex reg.                    */
+	u8 res1[0x10];
+	u32 miimcfg;		/* MII management configuration reg    */
+	u32 miimcom;		/* MII management command reg          */
+	u32 miimadd;		/* MII management address reg          */
+	u32 miimcon;		/* MII management control reg          */
+	u32 miimstat;		/* MII management status reg           */
+	u32 miimind;		/* MII management indication reg       */
+	u32 ifctl;		/* interface control reg               */
+	u32 ifstat;		/* interface statux reg                */
+	u32 macstnaddr1;	/* mac station address part 1 reg      */
+	u32 macstnaddr2;	/* mac station address part 2 reg      */
+	u8 res2[0x8];
+	u32 uempr;		/* UCC Ethernet Mac parameter reg      */
+	u32 utbipar;		/* UCC tbi address reg                 */
+	u16 uescr;		/* UCC Ethernet statistics control reg */
+	u8 res3[0x180 - 0x15A];
+	u32 tx64;		/* Total number of frames (including bad
+				 * frames) transmitted that were exactly
+				 * of the minimal length (64 for un tagged,
+				 * 68 for tagged, or with length exactly
+				 * equal to the parameter MINLength */
+	u32 tx127;		/* Total number of frames (including bad
+				 * frames) transmitted that were between
+				 * MINLength (Including FCS length==4)
+				 * and 127 octets */
+	u32 tx255;		/* Total number of frames (including bad
+				 * frames) transmitted that were between
+				 * 128 (Including FCS length==4) and 255
+				 * octets */
+	u32 rx64;		/* Total number of frames received including
+				 * bad frames that were exactly of the
+				 * mninimal length (64 bytes) */
+	u32 rx127;		/* Total number of frames (including bad
+				 * frames) received that were between
+				 * MINLength (Including FCS length==4)
+				 * and 127 octets */
+	u32 rx255;		/* Total number of frames (including
+				 * bad frames) received that were between
+				 * 128 (Including FCS length==4) and 255
+				 * octets */
+	u32 txok;		/* Total number of octets residing in frames
+				 * that where involved in succesfull
+				 * transmission */
+	u16 txcf;		/* Total number of PAUSE control frames
+				 *  transmitted by this MAC */
+	u8 res4[0x2];
+	u32 tmca;		/* Total number of frames that were transmitted
+				 * succesfully with the group address bit set
+				 * that are not broadcast frames */
+	u32 tbca;		/* Total number of frames transmitted
+				 * succesfully that had destination address
+				 * field equal to the broadcast address */
+	u32 rxfok;		/* Total number of frames received OK */
+	u32 rxbok;		/* Total number of octets received OK */
+	u32 rbyt;		/* Total number of octets received including
+				 * octets in bad frames. Must be implemented
+				 * in HW because it includes octets in frames
+				 * that never even reach the UCC */
+	u32 rmca;		/* Total number of frames that were received
+				 * succesfully with the group address bit set
+				 * that are not broadcast frames */
+	u32 rbca;		/* Total number of frames received succesfully
+				 * that had destination address equal to the
+				 * broadcast address */
+	u32 scar;		/* Statistics carry register */
+	u32 scam;		/* Statistics caryy mask register */
+	u8 res5[0x200 - 0x1c4];
+} __attribute__ ((packed)) uec_t;
+
+/* QE UCC Fast
+*/
+typedef struct ucc_fast {
+	u32 gumr;		/* UCCx general mode register */
+	u32 upsmr;		/* UCCx protocol-specific mode register  */
+	u16 utodr;		/* UCCx transmit on demand register  */
+	u8 res0[0x2];
+	u16 udsr;		/* UCCx data synchronization register  */
+	u8 res1[0x2];
+	u32 ucce;		/* UCCx event register */
+	u32 uccm;		/* UCCx mask register.  */
+	u8 uccs;		/* UCCx status register */
+	u8 res2[0x7];
+	u32 urfb;		/* UCC receive FIFO base */
+	u16 urfs;		/* UCC receive FIFO size */
+	u8 res3[0x2];
+	u16 urfet;		/* UCC receive FIFO emergency threshold */
+	u16 urfset;		/* UCC receive FIFO special emergency
+				 * threshold */
+	u32 utfb;		/* UCC transmit FIFO base */
+	u16 utfs;		/* UCC transmit FIFO size */
+	u8 res4[0x2];
+	u16 utfet;		/* UCC transmit FIFO emergency threshold */
+	u8 res5[0x2];
+	u16 utftt;		/* UCC transmit FIFO transmit threshold */
+	u8 res6[0x2];
+	u16 utpt;		/* UCC transmit polling timer */
+	u8 res7[0x2];
+	u32 urtry;		/* UCC retry counter register */
+	u8 res8[0x4C];
+	u8 guemr;		/* UCC general extended mode register */
+	u8 res9[0x100 - 0x091];
+	uec_t ucc_eth;
+} __attribute__ ((packed)) ucc_fast_t;
+
+/* QE UCC
+*/
+typedef struct ucc_common {
+	u8 res1[0x90];
+	u8 guemr;
+	u8 res2[0x200 - 0x091];
+} __attribute__ ((packed)) ucc_common_t;
+
+typedef struct ucc {
+	union {
+		ucc_slow_t slow;
+		ucc_fast_t fast;
+		ucc_common_t common;
+	};
+} __attribute__ ((packed)) ucc_t;
+
+/* MultiPHY UTOPIA POS Controllers (UPC)
+*/
+typedef struct upc {
+	u32 upgcr;		/* UTOPIA/POS general configuration register */
+	u32 uplpa;		/* UTOPIA/POS last PHY address */
+	u32 uphec;		/* ATM HEC register */
+	u32 upuc;		/* UTOPIA/POS UCC configuration */
+	u32 updc1;		/* UTOPIA/POS device 1 configuration */
+	u32 updc2;		/* UTOPIA/POS device 2 configuration  */
+	u32 updc3;		/* UTOPIA/POS device 3 configuration */
+	u32 updc4;		/* UTOPIA/POS device 4 configuration  */
+	u32 upstpa;		/* UTOPIA/POS STPA threshold  */
+	u8 res0[0xC];
+	u32 updrs1_h;		/* UTOPIA/POS device 1 rate select  */
+	u32 updrs1_l;		/* UTOPIA/POS device 1 rate select  */
+	u32 updrs2_h;		/* UTOPIA/POS device 2 rate select  */
+	u32 updrs2_l;		/* UTOPIA/POS device 2 rate select */
+	u32 updrs3_h;		/* UTOPIA/POS device 3 rate select */
+	u32 updrs3_l;		/* UTOPIA/POS device 3 rate select */
+	u32 updrs4_h;		/* UTOPIA/POS device 4 rate select */
+	u32 updrs4_l;		/* UTOPIA/POS device 4 rate select */
+	u32 updrp1;		/* UTOPIA/POS device 1 receive priority low  */
+	u32 updrp2;		/* UTOPIA/POS device 2 receive priority low  */
+	u32 updrp3;		/* UTOPIA/POS device 3 receive priority low  */
+	u32 updrp4;		/* UTOPIA/POS device 4 receive priority low  */
+	u32 upde1;		/* UTOPIA/POS device 1 event */
+	u32 upde2;		/* UTOPIA/POS device 2 event */
+	u32 upde3;		/* UTOPIA/POS device 3 event */
+	u32 upde4;		/* UTOPIA/POS device 4 event */
+	u16 uprp1;
+	u16 uprp2;
+	u16 uprp3;
+	u16 uprp4;
+	u8 res1[0x8];
+	u16 uptirr1_0;		/* Device 1 transmit internal rate 0 */
+	u16 uptirr1_1;		/* Device 1 transmit internal rate 1 */
+	u16 uptirr1_2;		/* Device 1 transmit internal rate 2 */
+	u16 uptirr1_3;		/* Device 1 transmit internal rate 3 */
+	u16 uptirr2_0;		/* Device 2 transmit internal rate 0 */
+	u16 uptirr2_1;		/* Device 2 transmit internal rate 1 */
+	u16 uptirr2_2;		/* Device 2 transmit internal rate 2 */
+	u16 uptirr2_3;		/* Device 2 transmit internal rate 3 */
+	u16 uptirr3_0;		/* Device 3 transmit internal rate 0 */
+	u16 uptirr3_1;		/* Device 3 transmit internal rate 1 */
+	u16 uptirr3_2;		/* Device 3 transmit internal rate 2 */
+	u16 uptirr3_3;		/* Device 3 transmit internal rate 3 */
+	u16 uptirr4_0;		/* Device 4 transmit internal rate 0 */
+	u16 uptirr4_1;		/* Device 4 transmit internal rate 1 */
+	u16 uptirr4_2;		/* Device 4 transmit internal rate 2 */
+	u16 uptirr4_3;		/* Device 4 transmit internal rate 3 */
+	u32 uper1;		/* Device 1 port enable register */
+	u32 uper2;		/* Device 2 port enable register */
+	u32 uper3;		/* Device 3 port enable register */
+	u32 uper4;		/* Device 4 port enable register */
+	u8 res2[0x150];
+} __attribute__ ((packed)) upc_t;
+
+/* SDMA
+*/
+typedef struct sdma {
+	u32 sdsr;		/* Serial DMA status register */
+	u32 sdmr;		/* Serial DMA mode register */
+	u32 sdtr1;		/* SDMA system bus threshold register */
+	u32 sdtr2;		/* SDMA secondary bus threshold register */
+	u32 sdhy1;		/* SDMA system bus hysteresis register */
+	u32 sdhy2;		/* SDMA secondary bus hysteresis register */
+	u32 sdta1;		/* SDMA system bus address register */
+	u32 sdta2;		/* SDMA secondary bus address register */
+	u32 sdtm1;		/* SDMA system bus MSNUM register */
+	u32 sdtm2;		/* SDMA secondary bus MSNUM register */
+	u8 res0[0x10];
+	u32 sdaqr;		/* SDMA address bus qualify register */
+	u32 sdaqmr;		/* SDMA address bus qualify mask register */
+	u8 res1[0x4];
+	u32 sdwbcr;		/* SDMA CAM entries base register */
+	u8 res2[0x38];
+} __attribute__ ((packed)) sdma_t;
+
+/* Debug Space
+*/
+typedef struct dbg {
+	u32 bpdcr;		/* Breakpoint debug command register */
+	u32 bpdsr;		/* Breakpoint debug status register */
+	u32 bpdmr;		/* Breakpoint debug mask register */
+	u32 bprmrr0;		/* Breakpoint request mode risc register 0 */
+	u32 bprmrr1;		/* Breakpoint request mode risc register 1 */
+	u8 res0[0x8];
+	u32 bprmtr0;		/* Breakpoint request mode trb register 0 */
+	u32 bprmtr1;		/* Breakpoint request mode trb register 1 */
+	u8 res1[0x8];
+	u32 bprmir;		/* Breakpoint request mode immediate register */
+	u32 bprmsr;		/* Breakpoint request mode serial register */
+	u32 bpemr;		/* Breakpoint exit mode register */
+	u8 res2[0x48];
+} __attribute__ ((packed)) dbg_t;
+
+/* RISC Special Registers (Trap and Breakpoint)
+*/
+typedef struct rsp {
+	u8 fixme[0x100];
+} __attribute__ ((packed)) rsp_t;
+
+typedef struct qe_immap {
+	qe_iram_t iram;		/* I-RAM */
+	qe_ic_t ic;		/* Interrupt Controller */
+	cp_qe_t cp;		/* Communications Processor */
+	qe_mux_t qmx;		/* QE Multiplexer */
+	qe_timers_t qet;	/* QE Timers */
+	spi_t spi[0x2];		/* spi  */
+	mcc_t mcc;		/* mcc */
+	qe_brg_t brg;		/* brg */
+	usb_t usb;		/* USB */
+	si1_t si1;		/* SI */
+	u8 res11[0x800];
+	sir_t sir;		/* SI Routing Tables  */
+	ucc_t ucc1;		/* ucc1 */
+	ucc_t ucc3;		/* ucc3 */
+	ucc_t ucc5;		/* ucc5 */
+	ucc_t ucc7;		/* ucc7 */
+	u8 res12[0x600];
+	upc_t upc1;		/* MultiPHY UTOPIA POS Controller 1 */
+	ucc_t ucc2;		/* ucc2 */
+	ucc_t ucc4;		/* ucc4 */
+	ucc_t ucc6;		/* ucc6 */
+	ucc_t ucc8;		/* ucc8 */
+	u8 res13[0x600];
+	upc_t upc2;		/* MultiPHY UTOPIA POS Controller 2 */
+	sdma_t sdma;		/* SDMA */
+	dbg_t dbg;		/* Debug Space */
+	rsp_t rsp[0x2];		/* RISC Special Registers
+				 * (Trap and Breakpoint) */
+	u8 res14[0x300];
+	u8 res15[0x3A00];
+	u8 res16[0x8000];	/* 0x108000 -  0x110000 */
+	u8 muram[0xC000];	/* 0x110000 -  0x11C000 Multi-user RAM */
+	u8 res17[0x24000];	/* 0x11C000 -  0x140000 */
+	u8 res18[0xC0000];	/* 0x140000 -  0x200000 */
+} __attribute__ ((packed)) qe_map_t;
+
+extern qe_map_t *qe_immr;
+
+#if defined(CONFIG_MPC8360)
+#define QE_MURAM_SIZE		0xc000UL
+#elif defined(CONFIG_MPC832X)
+#define QE_MURAM_SIZE		0x4000UL
+#endif
+
+#endif				/* __IMMAP_QE_H__ */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 8e5fe11..bbc9ba0 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -95,8 +95,15 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
  * Acts as a barrier to ensure all previous I/O accesses have
  * completed before any further ones are issued.
  */
-#define eieio() __asm__ __volatile__ ("eieio" : : : "memory");
-#define sync()  __asm__ __volatile__ ("sync" : : : "memory");
+static inline void eieio(void)
+{
+	__asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+static inline void sync(void)
+{
+	__asm__ __volatile__ ("sync" : : : "memory");
+}
 
 /* Enforce in-order execution of data I/O.
  * No distinction between read/write on PPC; use eieio for all three.
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 914f28b..b226825 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -335,41 +335,6 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
  * instructions.
  */
 
-#define	TLB_LO          1
-#define	TLB_HI          0
-
-#define	TLB_DATA        TLB_LO
-#define	TLB_TAG         TLB_HI
-
-/* Tag portion */
-
-#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
-#define TLB_PAGESZ_MASK 0x00000380
-#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
-#define   PAGESZ_1K		0
-#define   PAGESZ_4K             1
-#define   PAGESZ_16K            2
-#define   PAGESZ_64K            3
-#define   PAGESZ_256K           4
-#define   PAGESZ_1M             5
-#define   PAGESZ_4M             6
-#define   PAGESZ_16M            7
-#define TLB_VALID       0x00000040      /* Entry is valid */
-
-/* Data portion */
-
-#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
-#define TLB_PERM_MASK   0x00000300
-#define TLB_EX          0x00000200      /* Instruction execution allowed */
-#define TLB_WR          0x00000100      /* Writes permitted */
-#define TLB_ZSEL_MASK   0x000000F0
-#define TLB_ZSEL(x)     (((x) & 0xF) << 4)
-#define TLB_ATTR_MASK   0x0000000F
-#define TLB_W           0x00000008      /* Caching is write-through */
-#define TLB_I           0x00000004      /* Caching is inhibited */
-#define TLB_M           0x00000002      /* Memory is coherent */
-#define TLB_G           0x00000001      /* Memory is guarded from prefetch */
-
 /*
  * e500 support
  */
@@ -482,7 +447,162 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define LAWAR_SIZE_16G		(LAWAR_SIZE_BASE+23)
 #define LAWAR_SIZE_32G		(LAWAR_SIZE_BASE+24)
 
-#ifdef CONFIG_440SPE
+#ifdef CONFIG_440
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	0x00000000
+#define SZ_4K	0x00000010
+#define SZ_16K	0x00000020
+#define SZ_64K	0x00000030
+#define SZ_256K	0x00000040
+#define SZ_1M	0x00000050
+#define SZ_16M	0x00000070
+#define SZ_256M	0x00000090
+
+/* Storage attributes */
+#define SA_W	0x00000800	/* Write-through */
+#define SA_I	0x00000400	/* Caching inhibited */
+#define SA_M	0x00000200	/* Memory coherence */
+#define SA_G	0x00000100	/* Guarded */
+#define SA_E	0x00000080	/* Endian */
+
+/* Access control */
+#define AC_X	0x00000024	/* Execute */
+#define AC_W	0x00000012	/* Write */
+#define AC_R	0x00000009	/* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	((EPN((epn)) | (sz) | TLB_VALID ))
+#define TLB1(rpn,erpn)	(((rpn) & 0xfffffc00) | (erpn))
+#define TLB2(a)		((a) & 0x00000fbf)
+
+#define tlbtab_start\
+	mflr	r1	;\
+	bl	0f	;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;\
+0:	mflr	r0	;\
+	mtlr	r1	;\
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+/*----------------------------------------------------------------------------+
+| TLB specific defines.
++----------------------------------------------------------------------------*/
+#define TLB_256MB_ALIGN_MASK 0xF0000000
+#define TLB_16MB_ALIGN_MASK  0xFF000000
+#define TLB_1MB_ALIGN_MASK   0xFFF00000
+#define TLB_256KB_ALIGN_MASK 0xFFFC0000
+#define TLB_64KB_ALIGN_MASK  0xFFFF0000
+#define TLB_16KB_ALIGN_MASK  0xFFFFC000
+#define TLB_4KB_ALIGN_MASK   0xFFFFF000
+#define TLB_1KB_ALIGN_MASK   0xFFFFFC00
+#define TLB_256MB_SIZE       0x10000000
+#define TLB_16MB_SIZE        0x01000000
+#define TLB_1MB_SIZE         0x00100000
+#define TLB_256KB_SIZE       0x00040000
+#define TLB_64KB_SIZE        0x00010000
+#define TLB_16KB_SIZE        0x00004000
+#define TLB_4KB_SIZE         0x00001000
+#define TLB_1KB_SIZE         0x00000400
+
+#define TLB_WORD0_EPN_MASK   0xFFFFFC00
+#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_V_MASK     0x00000200
+#define TLB_WORD0_V_ENABLE   0x00000200
+#define TLB_WORD0_V_DISABLE  0x00000000
+#define TLB_WORD0_TS_MASK    0x00000100
+#define TLB_WORD0_TS_1       0x00000100
+#define TLB_WORD0_TS_0       0x00000000
+#define TLB_WORD0_SIZE_MASK  0x000000F0
+#define TLB_WORD0_SIZE_1KB   0x00000000
+#define TLB_WORD0_SIZE_4KB   0x00000010
+#define TLB_WORD0_SIZE_16KB  0x00000020
+#define TLB_WORD0_SIZE_64KB  0x00000030
+#define TLB_WORD0_SIZE_256KB 0x00000040
+#define TLB_WORD0_SIZE_1MB   0x00000050
+#define TLB_WORD0_SIZE_16MB  0x00000070
+#define TLB_WORD0_SIZE_256MB 0x00000090
+#define TLB_WORD0_TPAR_MASK  0x0000000F
+#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD1_RPN_MASK   0xFFFFFC00
+#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_PAR1_MASK  0x00000300
+#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+#define TLB_WORD1_PAR1_0     0x00000000
+#define TLB_WORD1_PAR1_1     0x00000100
+#define TLB_WORD1_PAR1_2     0x00000200
+#define TLB_WORD1_PAR1_3     0x00000300
+#define TLB_WORD1_ERPN_MASK  0x0000000F
+#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD2_PAR2_MASK  0xC0000000
+#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
+#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
+#define TLB_WORD2_PAR2_0     0x00000000
+#define TLB_WORD2_PAR2_1     0x40000000
+#define TLB_WORD2_PAR2_2     0x80000000
+#define TLB_WORD2_PAR2_3     0xC0000000
+#define TLB_WORD2_U0_MASK    0x00008000
+#define TLB_WORD2_U0_ENABLE  0x00008000
+#define TLB_WORD2_U0_DISABLE 0x00000000
+#define TLB_WORD2_U1_MASK    0x00004000
+#define TLB_WORD2_U1_ENABLE  0x00004000
+#define TLB_WORD2_U1_DISABLE 0x00000000
+#define TLB_WORD2_U2_MASK    0x00002000
+#define TLB_WORD2_U2_ENABLE  0x00002000
+#define TLB_WORD2_U2_DISABLE 0x00000000
+#define TLB_WORD2_U3_MASK    0x00001000
+#define TLB_WORD2_U3_ENABLE  0x00001000
+#define TLB_WORD2_U3_DISABLE 0x00000000
+#define TLB_WORD2_W_MASK     0x00000800
+#define TLB_WORD2_W_ENABLE   0x00000800
+#define TLB_WORD2_W_DISABLE  0x00000000
+#define TLB_WORD2_I_MASK     0x00000400
+#define TLB_WORD2_I_ENABLE   0x00000400
+#define TLB_WORD2_I_DISABLE  0x00000000
+#define TLB_WORD2_M_MASK     0x00000200
+#define TLB_WORD2_M_ENABLE   0x00000200
+#define TLB_WORD2_M_DISABLE  0x00000000
+#define TLB_WORD2_G_MASK     0x00000100
+#define TLB_WORD2_G_ENABLE   0x00000100
+#define TLB_WORD2_G_DISABLE  0x00000000
+#define TLB_WORD2_E_MASK     0x00000080
+#define TLB_WORD2_E_ENABLE   0x00000080
+#define TLB_WORD2_E_DISABLE  0x00000000
+#define TLB_WORD2_UX_MASK    0x00000020
+#define TLB_WORD2_UX_ENABLE  0x00000020
+#define TLB_WORD2_UX_DISABLE 0x00000000
+#define TLB_WORD2_UW_MASK    0x00000010
+#define TLB_WORD2_UW_ENABLE  0x00000010
+#define TLB_WORD2_UW_DISABLE 0x00000000
+#define TLB_WORD2_UR_MASK    0x00000008
+#define TLB_WORD2_UR_ENABLE  0x00000008
+#define TLB_WORD2_UR_DISABLE 0x00000000
+#define TLB_WORD2_SX_MASK    0x00000004
+#define TLB_WORD2_SX_ENABLE  0x00000004
+#define TLB_WORD2_SX_DISABLE 0x00000000
+#define TLB_WORD2_SW_MASK    0x00000002
+#define TLB_WORD2_SW_ENABLE  0x00000002
+#define TLB_WORD2_SW_DISABLE 0x00000000
+#define TLB_WORD2_SR_MASK    0x00000001
+#define TLB_WORD2_SR_ENABLE  0x00000001
+#define TLB_WORD2_SR_DISABLE 0x00000000
+
 /*----------------------------------------------------------------------------+
 | Following instructions are not available in Book E mode of the GNU assembler.
 +----------------------------------------------------------------------------*/
@@ -516,11 +636,15 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define MBAR_INST 				.long 0x7c000000|\
 					(854<<1)
 
-/*----------------------------------------------------------------------------+
-| Following instruction is not available in PPC405 mode of the GNU assembler.
-+----------------------------------------------------------------------------*/
-#define TLBRE(rt,ra,ws)			.long 0x7c000000|\
-					(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
+#ifndef __ASSEMBLY__
+/* Prototypes */
+void mttlb1(unsigned long index, unsigned long value);
+void mttlb2(unsigned long index, unsigned long value);
+void mttlb3(unsigned long index, unsigned long value);
+unsigned long mftlb1(unsigned long index);
+unsigned long mftlb2(unsigned long index);
+unsigned long mftlb3(unsigned long index);
+#endif /* __ASSEMBLY__ */
 
-#endif
+#endif /* CONFIG_440 */
 #endif /* _PPC_MMU_H_ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 388dea4..0585962 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -298,6 +298,10 @@
 #define SPRN_SPRG1	0x111	/* Special Purpose Register General 1 */
 #define SPRN_SPRG2	0x112	/* Special Purpose Register General 2 */
 #define SPRN_SPRG3	0x113	/* Special Purpose Register General 3 */
+#define SPRN_SPRG4	0x114	/* Special Purpose Register General 4 */
+#define SPRN_SPRG5	0x115	/* Special Purpose Register General 5 */
+#define SPRN_SPRG6	0x116	/* Special Purpose Register General 6 */
+#define SPRN_SPRG7	0x117	/* Special Purpose Register General 7 */
 #define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
 #define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
 #define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
@@ -529,6 +533,10 @@
 #define SPRG1   SPRN_SPRG1
 #define SPRG2   SPRN_SPRG2
 #define SPRG3   SPRN_SPRG3
+#define SPRG4   SPRN_SPRG4
+#define SPRG5   SPRN_SPRG5
+#define SPRG6   SPRN_SPRG6
+#define SPRG7   SPRN_SPRG7
 #define SRR0	SPRN_SRR0	/* Save and Restore Register 0 */
 #define SRR1	SPRN_SRR1	/* Save and Restore Register 1 */
 #define SVR	SPRN_SVR	/* System Version Register */
@@ -731,6 +739,7 @@
 #define PVR_405CR_RC	0x40110145  /* same as pc405gp rev e */
 #define PVR_405EP_RA	0x51210950
 #define PVR_405GPR_RB	0x50910951
+#define PVR_405EZ_RA	0x41511460
 #define PVR_440GP_RB	0x40120440
 #define PVR_440GP_RC	0x40120481
 #define PVR_440EP_RA	0x42221850
@@ -740,17 +749,21 @@
 #define PVR_440GR_RB	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
 #define PVR_440EPX1_RA  0x216218D0 /* 440EPX rev A with Security / Kasumi */
 #define PVR_440EPX2_RA  0x216218D4 /* 440EPX rev A without Security / Kasumi */
-#define PVR_440GRX1_RA  0x216218D8 /* 440GRX rev A with Security / Kasumi */
-#define PVR_440GRX2_RA  0x216218DC /* 440GRX rev A without Security / Kasumi */
+#define PVR_440GRX1_RA  0x216218D0 /* 440GRX rev A with Security / Kasumi */
+#define PVR_440GRX2_RA  0x216218D4 /* 440GRX rev A without Security / Kasumi */
 #define PVR_440GX_RA	0x51B21850
 #define PVR_440GX_RB	0x51B21851
 #define PVR_440GX_RC	0x51B21892
 #define PVR_440GX_RF	0x51B21894
 #define PVR_405EP_RB	0x51210950
-#define PVR_440SP_RA	0x53221850
-#define PVR_440SP_RB	0x53221891
-#define PVR_440SPe_RA	0x53421890
-#define PVR_440SPe_RB	0x53421891
+#define PVR_440SP_6_RAB	0x53221850 /* 440SP rev A&B with RAID 6 support enabled	*/
+#define PVR_440SP_RAB	0x53321850 /* 440SP rev A&B without RAID 6 support	*/
+#define PVR_440SP_6_RC	0x53221891 /* 440SP rev C with RAID 6 support enabled	*/
+#define PVR_440SP_RC	0x53321891 /* 440SP rev C without RAID 6 support	*/
+#define PVR_440SPe_6_RA	0x53421890 /* 440SPe rev A with RAID 6 support enabled	*/
+#define PVR_440SPe_RA	0x53521890 /* 440SPe rev A without RAID 6 support	*/
+#define PVR_440SPe_6_RB	0x53421891 /* 440SPe rev B with RAID 6 support enabled	*/
+#define PVR_440SPe_RB	0x53521891 /* 440SPe rev B without RAID 6 support	*/
 #define PVR_601		0x00010000
 #define PVR_602		0x00050000
 #define PVR_603		0x00030000
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 30b44e3..464f6b5 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -83,6 +83,7 @@ typedef struct bd_info {
     defined(CONFIG_405GP) || \
     defined(CONFIG_405CR) || \
     defined(CONFIG_405EP) || \
+    defined(CONFIG_405EZ) || \
     defined(CONFIG_440)
 	unsigned char	bi_s_version[4];	/* Version of this structure */
 	unsigned char	bi_r_version[32];	/* Version of the ROM (AMCC) */
@@ -107,7 +108,8 @@ typedef struct bd_info {
 	unsigned char   bi_enet3addr[6];
 #endif
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+    defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
diff --git a/include/common.h b/include/common.h
index ac78d1c..b162dbd 100644
--- a/include/common.h
+++ b/include/common.h
@@ -187,6 +187,7 @@ void	hang		(void) __attribute__ ((noreturn));
 long int initdram (int);
 int	display_options (void);
 void	print_size (ulong, const char *);
+int	print_buffer (ulong addr, void* data, uint width, uint count, uint linelen);
 
 /* common/main.c */
 void	main_loop	(void);
@@ -402,6 +403,11 @@ void		ppcSync(void);
 void		ppcDcbz(unsigned long value);
 #endif
 
+#if defined (CONFIG_MPC83XX)
+void		ppcDWload(unsigned int *addr, unsigned int *ret);
+void		ppcDWstore(unsigned int *addr, unsigned int *value);
+#endif
+
 /* $(CPU)/cpu.c */
 int	checkcpu      (void);
 int	checkicache   (void);
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 8753b9f..c380c54 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -179,6 +179,19 @@
 #undef CFG_IPBSPEED_133   	/* define for 133MHz speed */
 #endif
 #endif /* CONFIG_MPC5200 */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+
 /*
  * I2C configuration
  */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
new file mode 100644
index 0000000..cecb225
--- /dev/null
+++ b/include/configs/MPC832XEMDS.h
@@ -0,0 +1,631 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+#define CONFIG_QE		1	/* Has QE */
+#define CONFIG_MPC83XX		1	/* MPC83xx family */
+#define CONFIG_MPC832X		1	/* MPC832x CPU specific */
+#define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK	66000000	/* in HZ */
+#else
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66000000
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CSB_TO_CLKIN_2X1 |\
+	HRCWL_CORE_TO_CSB_2X1 |\
+	HRCWL_CE_PLL_VCO_DIV_2 |\
+	HRCWL_CE_PLL_DIV_1X1 |\
+	HRCWL_CE_TO_PLL_1X3)
+
+#ifdef CONFIG_PCISLAVE
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_AGENT |\
+	HRCWH_PCI1_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+#endif
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRL		0x00000000
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CFG_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory */
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */
+
+#undef CONFIG_SPD_EEPROM
+#if defined(CONFIG_SPD_EEPROM)
+/* Determine DDR configuration from I2C interface
+ */
+#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
+#else
+/* Manually set up DDR parameters
+ */
+#define CFG_DDR_SIZE		128	/* MB */
+#define CFG_DDR_CS0_CONFIG	0x80840102
+#define CFG_DDR_TIMING_0	0x00220802
+#define CFG_DDR_TIMING_1	0x3935d322
+#define CFG_DDR_TIMING_2	0x0f9048ca
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_CLK_CNTL	0x02000000
+#define CFG_DDR_MODE		0x44400232
+#define CFG_DDR_MODE2		0x8000c000
+#define CFG_DDR_INTERVAL	0x03200064
+#define CFG_DDR_CS0_BNDS	0x00000007
+#define CFG_DDR_SDRAM_CFG	0x43080000
+#define CFG_DDR_SDRAM_CFG2	0x00401000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CFG_DRAM_TEST		/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00000000	/* memtest region */
+#define CFG_MEMTEST_END		0x00100000
+
+/*
+ * The reserved memory
+ */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xE6000000	/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_2)
+#define CFG_LBC_LBCR		0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000	/* FLASH base address */
+#define CFG_FLASH_SIZE		16	/* FLASH size is 16M */
+
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32MB window size */
+
+#define CFG_BR0_PRELIM	(CFG_FLASH_BASE |	/* Flash Base address */ \
+			(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
+			BR_V)			/* valid */
+#define CFG_OR0_PRELIM		0xfe006ff7	/* 16MB Flash size */
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CFG_BCSR		0xF8000000
+#define CFG_LBLAWBAR1_PRELIM	CFG_BCSR	/* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* Access window size 32K */
+
+#define CFG_BR1_PRELIM		(CFG_BCSR|0x00000801)	/* Port size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM		0xFFFFE9f7	/* length 32K */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#undef CFG_LB_SDRAM		/* The board has not SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+#define CFG_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CFG_LBLAWBAR2_PRELIM	CFG_LBC_SDRAM_BASE
+#define CFG_LBLAWAR2_PRELIM	0x80000019	/* 64MB */
+
+/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM	0xf0001861	/*Port size=32bit, MSEL=SDRAM */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *                 XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM	0xfc006901
+
+#define CFG_LBC_LSRT	0x32000000	/* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON	0x0063b723
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_NORMAL)
+
+#endif
+
+/*
+ * Windows to access PIB via local bus
+ */
+#define CFG_LBLAWBAR3_PRELIM	0xf8008000	/* windows base 0xf8008000 */
+#define CFG_LBLAWAR3_PRELIM	0x8000000f	/* windows size 64KB */
+
+/*
+ * CS2 on Local Bus, to PIB
+ */
+#define CFG_BR2_PRELIM	0xf8008801	/* CS2 base address at 0xf8008000 */
+#define CFG_OR2_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
+
+/*
+ * CS3 on Local Bus, to PIB
+ */
+#define CFG_BR3_PRELIM	0xf8010801	/* CS3 base address at 0xf8010000 */
+#define CFG_OR3_PRELIM	0xffffe9f7	/* size 32KB, port size 8bit, GPCM */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8323@0"
+#define OF_SOC			"soc8323@e0000000"
+#define OF_QE			"qe@e0100000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc8323@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE	0x7F
+#define CFG_I2C_NOPROBES	{0x51}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET	0x3000
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI_MEM_BASE	0x80000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI_MMIO_BASE	0x90000000
+#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_PHYS		0xE0300000
+#define CFG_PCI_IO_SIZE		0x100000	/* 1M */
+
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
+#define CFG_PCI_SLV_MEM_BUS	0x00000000
+#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+
+
+#ifdef CONFIG_PCI
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"Freescale GETH"
+
+#define CONFIG_UEC_ETH1		/* ETH3 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM	2	/* UCC3 */
+#define CFG_UEC1_RX_CLK		QE_CLK9
+#define CFG_UEC1_TX_CLK		QE_CLK10
+#define CFG_UEC1_ETH_TYPE	FAST_ETH
+#define CFG_UEC1_PHY_ADDR	3
+#define CFG_UEC1_INTERFACE_MODE	ENET_100_MII
+#endif
+
+#define CONFIG_UEC_ETH2		/* ETH4 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM	3	/* UCC4 */
+#define CFG_UEC2_RX_CLK		QE_CLK7
+#define CFG_UEC2_TX_CLK		QE_CLK8
+#define CFG_UEC2_ETH_TYPE	FAST_ETH
+#define CFG_UEC2_PHY_ADDR	4
+#define CFG_UEC2_INTERFACE_MODE	ENET_100_MII
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_PCI \
+				| CFG_CMD_I2C) \
+				& \
+				~(CFG_CMD_ENV \
+				| CFG_CMD_LOADS))
+#else
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_I2C) \
+				& \
+				~(CFG_CMD_ENV \
+				| CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PCI \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_I2C)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_I2C  )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_LOAD_ADDR		0x2000000	/* default load address */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	#define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CFG_HID0_INIT		0x000000000
+#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2		HID2_HBE
+
+/*
+ * Cache Config
+ */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value */
+#endif
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+
+/* BCSR: cache-inhibit and guarded */
+#define CFG_IBAT2L	(CFG_BCSR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CFG_IBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT3U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U	CFG_IBAT3U
+
+#define CFG_IBAT4L	(0)
+#define CFG_IBAT4U	(0)
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
+#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#else
+#define CFG_IBAT6L	(0)
+#define CFG_IBAT6U	(0)
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_ETHADDR	00:04:9f:ef:03:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	00:04:9f:ef:03:02
+#endif
+
+#define CONFIG_BAUDRATE	115200
+
+#define CONFIG_LOADADDR	200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+   "netdev=eth0\0"							\
+   "consoledev=ttyS0\0"							\
+   "ramdiskaddr=1000000\0"						\
+   "ramdiskfile=ramfs.83xx\0"						\
+   "fdtaddr=400000\0"							\
+   "fdtfile=mpc832xemds.dtb\0"						\
+   ""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 66f1646..0460be9 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -36,6 +36,7 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC834X		1	/* MPC834X family */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
 
@@ -61,7 +62,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
 
-#define CFG_IMMRBAR		0xE0000000
+#define CFG_IMMR		0xE0000000
 
 #undef CFG_DRAM_TEST				/* memory test, takes time */
 #define CFG_MEMTEST_START	0x00000000      /* memtest region */
@@ -70,7 +71,7 @@
 /*
  * DDR Setup
  */
-#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_ECC			/* support DDR ECC function */
 #define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 
@@ -89,8 +90,15 @@
 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_BASE
 #define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING
 
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CFG_DDRCDR_VALUE	0x80080001
+
 #if defined(CONFIG_SPD_EEPROM)
 /*
  * Determine DDR configuration from I2C interface.
@@ -101,6 +109,21 @@
  * Manually set up DDR parameters
  */
 #define CFG_DDR_SIZE		256		/* MB */
+#if defined(CONFIG_DDR_II)
+#define CFG_DDRCDR		0x80080001
+#define CFG_DDR_CS2_BNDS	0x0000000f
+#define CFG_DDR_CS2_CONFIG	0x80330102
+#define CFG_DDR_TIMING_0	0x00220802
+#define CFG_DDR_TIMING_1	0x38357322
+#define CFG_DDR_TIMING_2	0x2f9048c8
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_CLK_CNTL	0x02000000
+#define CFG_DDR_MODE		0x47d00432
+#define CFG_DDR_MODE2		0x8000c000
+#define CFG_DDR_INTERVAL	0x03cf0080
+#define CFG_DDR_SDRAM_CFG	0x43000000
+#define CFG_DDR_SDRAM_CFG2	0x00401000
+#else
 #define CFG_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 #define CFG_DDR_TIMING_1	0x36332321
 #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
@@ -115,6 +138,7 @@
 #define CFG_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
 #endif
 #endif
+#endif
 
 /*
  * SDRAM on the Local Bus
@@ -128,19 +152,20 @@
 #define CFG_FLASH_CFI				/* use the Common Flash Interface */
 #define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		8		/* flash size in MB */
+#define CFG_FLASH_SIZE		32		/* max flash size in MB */
 /* #define CFG_FLASH_USE_BUFFER_WRITE */
 
 #define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
-				(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
+				(2 << BR_PS_SHIFT) |	/* 16 bit port size */	 \
 				BR_V)			/* valid */
-
-#define CFG_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */
+#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
+#define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32 MB window size */
 
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+#define CFG_MAX_FLASH_SECT	256		/* max sectors per device */
 
 #undef CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
@@ -185,7 +210,11 @@
 #define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
 #define CFG_LBC_LBCR	0x00000000
 
-#define CFG_LB_SDRAM	/* if board has SRDAM on local bus */
+/*
+ * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
+ * if board has SRDAM on local bus, you can define CFG_LB_SDRAM
+ */
+#undef CFG_LB_SDRAM
 
 #ifdef CFG_LB_SDRAM
 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
@@ -299,29 +328,45 @@
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1        (CFG_IMMRBAR+0x4500)
-#define CFG_NS16550_COM2        (CFG_IMMRBAR+0x4600)
+#define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
 
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
 #ifdef  CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8349@0"
+#define OF_SOC			"soc8349@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc8349@e0000000/serial@4500"
+
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
 #undef CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
-#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
 #define CFG_I2C_OFFSET		0x3000
 #define CFG_I2C2_OFFSET		0x3100
 
 /* TSEC */
 #define CFG_TSEC1_OFFSET 0x24000
-#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
 #define CFG_TSEC2_OFFSET 0x25000
-#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
 
 /* USB */
 #define CFG_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */
@@ -615,8 +660,8 @@
 #endif
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CFG_IBAT5L	(CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 #define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
@@ -666,11 +711,11 @@
 #define CONFIG_ETH1ADDR		00:E0:0C:00:7E:21
 #endif
 
-#define CONFIG_IPADDR		192.168.205.5
+#define CONFIG_IPADDR		192.168.1.253
 
 #define CONFIG_HOSTNAME		mpc8349emds
-#define CONFIG_ROOTPATH		/opt/eldk/ppc_6xx
-#define CONFIG_BOOTFILE		/tftpboot/tqm83xx/uImage
+#define CONFIG_ROOTPATH		/nfsroot/rootfs
+#define CONFIG_BOOTFILE		uImage
 
 #define CONFIG_SERVERIP		192.168.1.1
 #define CONFIG_GATEWAYIP	192.168.1.1
@@ -703,14 +748,31 @@
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
 		"bootm\0"						\
-	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/mpc8349emds/uImage\0"			\
 	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
 	"update=protect off fe000000 fe03ffff; "			\
 		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"	\
 	"upd=run load;run update\0"					\
+	"fdtaddr=400000\0"						\
+	"fdtfile=mpc8349emds.dtb\0"					\
 	""
 
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
new file mode 100644
index 0000000..37bbfb3
--- /dev/null
+++ b/include/configs/MPC8349ITX.h
@@ -0,0 +1,703 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
+
+ Memory map:
+
+ 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
+ 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
+ 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
+ 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
+ 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
+ 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
+ 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
+ 0xF001_0000-0xF001_FFFF Local bus expansion slot
+ 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
+ 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
+ 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
+
+ I2C address list:
+						Align.	Board
+ Bus	Addr	Part No.	Description	Length	Location
+ ----------------------------------------------------------------
+ I2C0	0x50	M24256-BWMN6P	Board EEPROM	2	U64
+
+ I2C1	0x20	PCF8574		I2C Expander	0	U8
+ I2C1	0x21	PCF8574		I2C Expander	0	U10
+ I2C1	0x38	PCF8574A	I2C Expander	0	U8
+ I2C1	0x39	PCF8574A	I2C Expander	0	U10
+ I2C1	0x51	(DDR)		DDR EEPROM	1	U1
+ I2C1	0x68	DS1339		RTC		1	U68
+
+ Note that a given board has *either* a pair of 8574s or a pair of 8574As.
+*/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if (TEXT_BASE == 0xFE000000)
+#define CFG_LOWBOOT
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC834X		/* MPC834x family (8343, 8347, 8349) */
+#define CONFIG_MPC8349		/* MPC8349 specific */
+
+#define CFG_IMMR		0xE0000000	/* The IMMR is relocated to here */
+
+
+/* On-board devices */
+
+#ifdef CONFIG_MPC8349ITX
+#define CONFIG_COMPACT_FLASH	/* The CF card interface on the back of the board */
+#define CONFIG_VSC7385		/* The Vitesse 7385 5-port switch */
+#endif
+
+#define CONFIG_PCI
+#define CONFIG_RTC_DS1337
+#define CONFIG_HARD_I2C
+#define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
+
+/*
+ * Device configurations
+ */
+
+/* I2C */
+#ifdef CONFIG_HARD_I2C
+
+#define CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+#define CFG_SPD_BUS_NUM		1	/* The I2C bus for SPD */
+
+#define CFG_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
+#define CFG_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
+#define CFG_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
+#define CFG_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
+#define CFG_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
+#define CFG_I2C_RTC_ADDR	0x68	/* I2C1, DS1339 RTC*/
+#define SPD_EEPROM_ADDRESS	0x51	/* I2C1, DDR */
+
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+/* Don't probe these addresses: */
+#define CFG_I2C_NOPROBES	{{1, CFG_I2C_8574_ADDR1}, \
+				 {1, CFG_I2C_8574_ADDR2}, \
+				 {1, CFG_I2C_8574A_ADDR1}, \
+				 {1, CFG_I2C_8574A_ADDR2}}
+/* Bit definitions for the 8574[A] I2C expander */
+#define I2C_8574_REVISION	0x03	/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
+#define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
+#define I2C_8574_MPCICLKRN	0x10	/* MiniPCI Clk Run */
+#define I2C_8574_PCI66		0x20	/* 0=33MHz PCI, 1=66MHz PCI */
+#define I2C_8574_FLASHSIDE	0x40	/* 0=Reset vector from U4, 1=from U7*/
+
+#undef CONFIG_SOFT_I2C
+
+#endif
+
+/* Compact Flash */
+#ifdef CONFIG_COMPACT_FLASH
+
+#define CFG_IDE_MAXBUS		1
+#define CFG_IDE_MAXDEVICE	1
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	CFG_CF_BASE
+#define CFG_ATA_DATA_OFFSET	0x0000
+#define CFG_ATA_REG_OFFSET	0
+#define CFG_ATA_ALT_OFFSET	0x0200
+#define CFG_ATA_STRIDE		2
+
+#define ATA_RESET_TIME	1	/* If a CF card is not inserted, time out quickly */
+
+#define CONFIG_DOS_PARTITION
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE 		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE 	CFG_DDR_BASE
+#define CFG_83XX_DDR_USES_CS0
+#define CFG_MEMTEST_START	0x1000		/* memtest region */
+#define CFG_MEMTEST_END		0x2000
+
+#ifdef CONFIG_HARD_I2C
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+#endif
+
+#ifndef CONFIG_SPD_EEPROM	/* No SPD? Then manually set up DDR parameters */
+    #define CFG_DDR_SIZE	256		/* Mb */
+    #define CFG_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+
+    #define CFG_DDR_TIMING_1	0x26242321
+    #define CFG_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
+#endif
+
+/*
+ *Flash on the Local Bus
+ */
+
+#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_MAX_FLASH_SECT	135	/* 127 64KB sectors + 8 8KB sectors per device */
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+/* The ITX has two flash chips, but the ITX-GP has only one.  To support both
+boards, we say we have two, but don't display a message if we find only one. */
+#define CFG_FLASH_QUIET_TEST
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_FLASH_BANKS_LIST 	{CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
+#define CFG_FLASH_SIZE		16		/* FLASH size in MB */
+#define CFG_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
+
+/*
+ * BRx, ORx, LBLAWBARx, and LBLAWARx
+ */
+
+/* Flash */
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_16 | BR_V)
+#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE
+#define CFG_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385
+
+#define CFG_VSC7385_BASE	0xF8000000
+
+#define CFG_BR1_PRELIM		(CFG_VSC7385_BASE | BR_PS_8 | BR_V)
+#define CFG_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
+				OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CFG_LBLAWBAR1_PRELIM	CFG_VSC7385_BASE
+#define CFG_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
+
+#endif
+
+/* LED */
+
+#define CFG_LED_BASE		0xF9000000
+#define CFG_BR2_PRELIM		(CFG_LED_BASE | BR_PS_8 | BR_V)
+#define CFG_OR2_PRELIM		(OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+				OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
+				OR_GPCM_EHTR | OR_GPCM_EAD)
+
+/* Compact Flash */
+
+#ifdef CONFIG_COMPACT_FLASH
+
+#define CFG_CF_BASE		0xF0000000
+
+#define CFG_BR3_PRELIM		(CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
+#define CFG_OR3_PRELIM		(OR_UPM_AM | OR_UPM_BI)
+
+#define CFG_LBLAWBAR3_PRELIM	CFG_CF_BASE
+#define CFG_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
+
+#endif
+
+/*
+ * U-Boot memory configuration
+ */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef	CFG_RAMBOOT
+#endif
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR	0x00000000
+
+#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_NS16550_COM1	(CFG_IMMR + 0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR + 0x4600)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE
+#define CONFIG_OF_BOARD_SETUP
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8349@0"
+#define OF_SOC			"soc8349@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc8349@e0000000/serial@4500"
+
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+
+#define CONFIG_MPC83XX_PCI2
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_MMIO_BASE	(CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE)
+#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xE2000000
+#define CFG_PCI1_IO_SIZE	0x01000000	/* 16M */
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CFG_PCI2_MEM_BASE	(CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE)
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI2_MMIO_BASE	(CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE)
+#define CFG_PCI2_MMIO_PHYS	CFG_PCI2_MMIO_BASE
+#define CFG_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	(CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE)
+#define CFG_PCI2_IO_SIZE	0x01000000	/* 16M */
+#endif
+
+#define _IO_BASE		0x00000000	/* points to PCI I/O space */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)	    (x)
+#endif
+
+#ifndef CONFIG_PCI_PNP
+    #define PCI_ENET0_IOADDR	0x00000000
+    #define PCI_ENET0_MEMADDR	CFG_PCI2_MEM_BASE
+    #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN	66666666	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
+#endif
+
+/* TSEC */
+
+#ifdef CONFIG_TSEC_ENET
+
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE		/* In case CFG_CMD_MII is specified */
+
+#define CONFIG_MPC83XX_TSEC1
+
+#ifdef CONFIG_MPC83XX_TSEC1
+#define CONFIG_MPC83XX_TSEC1_NAME  "TSEC0"
+#define CFG_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
+#define TSEC1_PHYIDX		0
+#endif
+
+#ifdef CONFIG_MPC83XX_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_MPC83XX_TSEC2_NAME  "TSEC1"
+#define CFG_TSEC2_OFFSET	0x25000
+#define CONFIG_UNKNOWN_TSEC	/* TSEC2 is proprietary */
+#define TSEC2_PHY_ADDR		4
+#define TSEC2_PHYIDX		0
+#endif
+
+#define CONFIG_ETHPRIME		"Freescale TSEC"
+
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef CFG_RAMBOOT
+  #define CFG_ENV_IS_IN_FLASH
+  #define CFG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE))
+  #define CFG_ENV_SIZE		0x2000
+#else
+  #define CFG_NO_FLASH		/* Flash is not usable now */
+  #define CFG_ENV_IS_NOWHERE	/* Store ENV in memory only */
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/* CONFIG_COMMANDS */
+
+#ifdef CONFIG_COMPACT_FLASH
+#define CONFIG_COMMANDS_CF	(CFG_CMD_IDE | CFG_CMD_FAT)
+#else
+#define CONFIG_COMMANDS_CF	0
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_COMMANDS_PCI	CFG_CMD_PCI
+#else
+#define CONFIG_COMMANDS_PCI	0
+#endif
+
+#ifdef CONFIG_HARD_I2C
+#define CONFIG_COMMANDS_I2C	CFG_CMD_I2C
+#else
+#define CONFIG_COMMANDS_I2C	0
+#endif
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				CONFIG_COMMANDS_CF	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_PING	| \
+				CONFIG_COMMANDS_I2C	| \
+				CONFIG_COMMANDS_PCI	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_CACHE	| \
+				CFG_CMD_IRQ)
+#include <cmd_confdefs.h>
+
+/* Watchdog */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CFG_HUSH_PARSER			/* Use the HUSH parser */
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_LOADADDR	200000	/* default location for tftp and bootm */
+
+#ifdef CONFIG_MPC8349ITX
+#define CFG_PROMPT	"MPC8349E-mITX> "	/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT	"MPC8349E-mITX-GP> "	/* Monitor Command Prompt */
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log2 of the above value */
+#endif
+
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#ifdef CFG_LOWBOOT
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#endif
+
+/*
+ * System performance
+ */
+#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+#define CFG_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
+#define CFG_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
+#define CFG_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
+#define CFG_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRH SICRH_TSOBI1	/* Needed for gigabit to work on TSEC 1 */
+#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1)
+
+#define CFG_HID0_INIT	0x000000000
+#define CFG_HID0_FINAL	CFG_HID0_INIT
+
+#define CFG_HID2	HID2_HBE
+
+/* DDR  */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI  */
+#ifdef CONFIG_PCI
+#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT1L	0
+#define CFG_IBAT1U	0
+#define CFG_IBAT2L	0
+#define CFG_IBAT2U	0
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CFG_IBAT3L	(CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT3U	(CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L	(CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4U	(CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT3L	0
+#define CFG_IBAT3U	0
+#define CFG_IBAT4L	0
+#define CFG_IBAT4U	0
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT7L	0
+#define CFG_IBAT7U	0
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_MPC83XX_TSEC1
+#define CONFIG_ETHADDR		00:E0:0C:00:8C:01
+#endif
+
+#ifdef CONFIG_MPC83XX_TSEC2
+#define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
+#endif
+
+#define CONFIG_IPADDR		192.168.1.253
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.252.0
+#define CONFIG_NETDEV		eth0
+
+#ifdef CONFIG_MPC8349ITX
+#define CONFIG_HOSTNAME		mpc8349emitx
+#else
+#define CONFIG_HOSTNAME		mpc8349emitxgp
+#endif
+
+/* Default path and filenames */
+#define CONFIG_ROOTPATH		/nfsroot/rootfs
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#ifdef CONFIG_MPC8349ITX
+#define CONFIG_FDTFILE		mpc8349emitx.dtb
+#else
+#define CONFIG_FDTFILE		mpc8349emitxgp.dtb
+#endif
+
+#define CONFIG_BOOTDELAY	0
+
+#define XMK_STR(x)	#x
+#define MK_STR(x)	XMK_STR(x)
+
+#define CONFIG_BOOTARGS \
+	"root=/dev/nfs rw" \
+	" nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
+	" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" 	\
+		MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
+		MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
+	" console=ttyS0," MK_STR(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" MK_STR(CONFIG_NETDEV) "\0" 				\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" 				\
+	"tftpflash=tftpboot $loadaddr $uboot; " 			\
+		"protect off " MK_STR(TEXT_BASE) " +$filesize; " 	\
+		"erase " MK_STR(TEXT_BASE) " +$filesize; " 		\
+		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " 	\
+		"protect on " MK_STR(TEXT_BASE) " +$filesize; " 	\
+		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" 	\
+	"fdtaddr=400000\0"						\
+	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"	\
+	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	" console=$console,$baudrate $othbootargs; "			\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw"				\
+	" console=$console,$baudrate $othbootargs; "			\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
new file mode 100644
index 0000000..d2af0e1
--- /dev/null
+++ b/include/configs/MPC8360EMDS.h
@@ -0,0 +1,662 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_QE		1 /* Has QE */
+#define CONFIG_MPC83XX		1 /* MPC83XX family */
+#define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
+#define CONFIG_MPC8360EMDS	1 /* MPC8360EMDS board specific */
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK	66000000 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN	66000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66000000
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CE_PLL_VCO_DIV_4 |\
+	HRCWL_CE_PLL_DIV_1X1 |\
+	HRCWL_CE_TO_PLL_1X6 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#ifdef CONFIG_PCISLAVE
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_AGENT |\
+	HRCWH_PCI1_ARBITER_DISABLE |\
+	HRCWH_PCICKDRV_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT)
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCICKDRV_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT)
+#endif
+
+/*
+ * System IO Config
+ */
+#define CFG_SICRH		0x00000000
+#define CFG_SICRL		0x40000000
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CFG_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CFG_83XX_DDR_USES_CS0
+
+#define CONFIG_DDR_ECC		/* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CFG_DDRCDR_VALUE	0x80080001
+
+#define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS	0x52 /* DDR SODIMM */
+#else
+/*
+ * Manually set up DDR parameters
+ */
+#define CFG_DDR_SIZE		256 /* MB */
+#if defined(CONFIG_DDR_II)
+#define CFG_DDRCDR		0x80080001
+#define CFG_DDR_CS0_BNDS	0x0000000f
+#define CFG_DDR_CS0_CONFIG	0x80330102
+#define CFG_DDR_TIMING_0	0x00220802
+#define CFG_DDR_TIMING_1	0x38357322
+#define CFG_DDR_TIMING_2	0x2f9048c8
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_CLK_CNTL	0x02000000
+#define CFG_DDR_MODE		0x47d00432
+#define CFG_DDR_MODE2		0x8000c000
+#define CFG_DDR_INTERVAL	0x03cf0080
+#define CFG_DDR_SDRAM_CFG	0x43000000
+#define CFG_DDR_SDRAM_CFG2	0x00401000
+#else
+#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+#define CFG_DDR_TIMING_1	0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
+#define CFG_DDR_TIMING_2	0x00000800 /* may need tuning */
+#define CFG_DDR_CONTROL		0x42008000 /* Self refresh,2T timing */
+#define CFG_DDR_MODE		0x20000162 /* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL	0x045b0100 /* page mode */
+#endif
+#endif
+
+/*
+ * Memory test
+ */
+#undef CFG_DRAM_TEST		/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00000000 /* memtest region */
+#define CFG_MEMTEST_END		0x00100000
+
+/*
+ * The reserved memory
+ */
+
+#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef	CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR		0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI		/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CFG_FLASH_SIZE		32 /* max FLASH size is 32M */
+
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
+
+#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | /* Flash Base address */ \
+			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+			BR_V)	/* valid */
+#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
+#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */
+
+#undef	CFG_FLASH_CHECKSUM
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CFG_BCSR		0xF8000000
+#define CFG_LBLAWBAR1_PRELIM	CFG_BCSR /* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM	0x8000000F /* Access window size 64K */
+
+#define CFG_BR1_PRELIM		(CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM		0xFFFFE9f7 /* length 32K */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CFG_LB_SDRAM		/* if board has SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+#define CFG_LBLAWBAR2_PRELIM	CFG_LBC_SDRAM_BASE
+#define CFG_LBLAWAR2_PRELIM	0x80000019 /* 64MB */
+
+/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM	0xf0001861 /*Port size=32bit, MSEL=SDRAM */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows	OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM	0xfc006901
+
+#define CFG_LBC_LSRT	0x32000000 /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR	0x20000000 /* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON	0x0063b723
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_NORMAL)
+
+#endif
+
+/*
+ * Windows to access PIB via local bus
+ */
+#define CFG_LBLAWBAR3_PRELIM	0xf8010000 /* windows base 0xf8010000 */
+#define CFG_LBLAWAR3_PRELIM	0x8000000e /* windows size 32KB */
+
+/*
+ * CS4 on Local Bus, to PIB
+ */
+#define CFG_BR4_PRELIM	0xf8008801 /* CS4 base address at 0xf8008000 */
+#define CFG_OR4_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
+
+/*
+ * CS5 on Local Bus, to PIB
+ */
+#define CFG_BR5_PRELIM	0xf8010801 /* CS5 base address at 0xf8010000 */
+#define CFG_OR5_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8360@0"
+#define OF_SOC			"soc8360@e0000000"
+#define OF_QE			"qe@e0100000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc8360@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE	0x7F
+#define CFG_I2C_NOPROBES	{0x52} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET	0x3000
+#define CFG_I2C2_OFFSET 0x3100
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
+#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI_MEM_BASE	0x80000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
+#define CFG_PCI_MMIO_BASE	0x90000000
+#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CFG_PCI_IO_BASE		0xE0300000
+#define CFG_PCI_IO_PHYS		0xE0300000
+#define CFG_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
+#define CFG_PCI_SLV_MEM_BUS	0x00000000
+#define CFG_PCI_SLV_MEM_SIZE	0x80000000
+
+
+#ifdef CONFIG_PCI
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"Freescale GETH"
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1		/* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM	0	/* UCC1 */
+#define CFG_UEC1_RX_CLK		QE_CLK_NONE
+#define CFG_UEC1_TX_CLK		QE_CLK9
+#define CFG_UEC1_ETH_TYPE	GIGA_ETH
+#define CFG_UEC1_PHY_ADDR	0
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#endif
+
+#define CONFIG_UEC_ETH2		/* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM	1	/* UCC2 */
+#define CFG_UEC2_RX_CLK		QE_CLK_NONE
+#define CFG_UEC2_TX_CLK		QE_CLK4
+#define CFG_UEC2_ETH_TYPE	GIGA_ETH
+#define CFG_UEC2_PHY_ADDR	1
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#endif
+
+/*
+ * Environment
+ */
+
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x40000 /* 256K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define	 CONFIG_COMMANDS	((CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_PCI \
+				| CFG_CMD_I2C) \
+				& \
+				~(CFG_CMD_ENV \
+				| CFG_CMD_LOADS))
+#else
+#define	 CONFIG_COMMANDS	((CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_I2C) \
+				& \
+				~(CFG_CMD_ENV \
+				| CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define	 CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PCI \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_I2C)
+#else
+#define	 CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_ASKENV \
+				| CFG_CMD_I2C  )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_LOAD_ADDR		0x2000000 /* default load address */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CFG_HID0_INIT		0x000000000
+#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
+#define CFG_HID2		HID2_HBE
+
+/*
+ * Cache Config
+ */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5 /*log base 2 of the above value */
+#endif
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+
+/* BCSR: cache-inhibit and guarded */
+#define CFG_IBAT2L	(CFG_BCSR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CFG_IBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT3U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/* Local bus SDRAM: cacheable */
+#define CFG_IBAT4L	(CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT4U	(CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
+#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#else
+#define CFG_IBAT6L	(0)
+#define CFG_IBAT6U	(0)
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_ETHADDR	00:04:9f:ef:01:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+   "netdev=eth0\0"							\
+   "consoledev=ttyS0\0"							\
+   "ramdiskaddr=1000000\0"						\
+   "ramdiskfile=ramfs.83xx\0"						\
+   "fdtaddr=400000\0"							\
+   "fdtfile=mpc8360emds.dtb\0"						\
+   ""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 9d5c4f4..027dd22 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -1,6 +1,9 @@
 /*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
  * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -32,8 +35,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_IDENT_STRING     " $Name: esd_PCI405_05_07_28 $"
-
 #define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
 #define CONFIG_PCI405		1	/* ...on a PCI405 board		*/
@@ -53,9 +54,9 @@
 	"mem_linux=14336k\0"					        \
 	"optargs=panic=0\0"					        \
 	"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"	\
-	"addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
+	"addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
 	""
-#define	CONFIG_BOOTCOMMAND      "run ramargs;run addcon;loadpci"
+#define	CONFIG_BOOTCOMMAND      "run ramargs;run addcons;loadpci"
 
 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index dd5d831..d02c39b 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -51,17 +51,13 @@
 
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#if 0 /* test-only */
 #define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_PHY1_ADDR	1	/* PHY address			*/
-#else
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#endif
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
 
 #define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 2c34ce0..5b011e8 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -238,6 +238,17 @@
 		"protect on FC000000 +${filesize}\0"
 #endif
 
+#ifndef CONFIG_CAM5200
+#define CUSTOM_ENV_SETTINGS						\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
+#else
+#define CUSTOM_ENV_SETTINGS 						\
+	"bootfile=cam5200/uImage\0"					\
+	"u-boot=cam5200/u-boot.bin\0"					\
+	"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"
+#endif
+
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
@@ -255,8 +266,7 @@
 		"bootm ${kernel_addr}\0"				\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
 		"bootm\0"						\
-	"bootfile=/tftpboot/tqm5200/uImage\0"				\
-	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
+	CUSTOM_ENV_SETTINGS						\
 	"load=tftp 200000 ${u-boot}\0"					\
 	ENV_UPDT							\
 	""
@@ -332,15 +342,7 @@
  */
 #define CFG_FLASH_BASE		0xFC000000
 
-#ifndef CONFIG_CAM5200
-/* use CFI flash driver */
-#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
-					   (= chip selects) */
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#else /* CONFIG_CAM5200 */
+#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
 #define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks
 					   (= chip selects) */
 #define CFG_FLASH_WORD_SIZE	unsigned int /* main flash device with */
@@ -351,7 +353,15 @@
 #define CFG_FLASH_ADDR1		0x2AA
 #define CFG_FLASH_2ND_16BIT_DEV	1	/* NIOS flash is a 16bit device */
 #define CFG_MAX_FLASH_SECT	128
-#endif /* ifndef CONFIG_CAM5200 */
+#else
+/* use CFI flash driver */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#endif
 
 #define CFG_FLASH_EMPTY_INFO
 #define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
new file mode 100644
index 0000000..925bf34
--- /dev/null
+++ b/include/configs/TQM8272.h
@@ -0,0 +1,754 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
+#define CONFIG_MPC8272_FAMILY   1
+#define CONFIG_TQM8272		1
+
+#define	CONFIG_GET_CPU_STR_F	1	/* Get the CPU ID STR */
+#define CONFIG_BOARD_GET_CPU_CLK_F	1 /* Get the CLKIN from board fct */
+
+#define	STK82xx_150		1	/* on a STK82xx.150 */
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1		*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_EARLY_INIT_R	1
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		115200
+#endif
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consdev=ttyCPM0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"hostname=tqm8272\0"						\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=$(consdev),$(baudrate)\0"			\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 300000 ${bootfile};"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/tqm8272/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	"load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0"		\
+	"update=protect off 40000000 4003ffff;era 40000000 4003ffff;"	\
+		"cp.b 300000 40000000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"cphwib=cp.b 4003fc00 33fc00 400\0"				\
+	"upd=run load;run cphwib;run update\0"				\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_I2C	1
+
+#if CONFIG_I2C
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define ADD_CMD_I2C		CFG_CMD_I2C	| \
+				CFG_CMD_DATE	|\
+				CFG_CMD_DTT	|\
+				CFG_CMD_EEPROM
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_I2C_X
+
+/* EEPROM */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* necessary for the LM75 chip */
+#define CFG_I2C_MULTI_EEPROMS		1	/* more than one eeprom */
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
+#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
+#else
+#undef CONFIG_HARD_I2C
+#undef CONFIG_SOFT_I2C
+#define ADD_CMD_I2C		0
+#endif
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#ifdef CONFIG_82xx_CONS_SMC1
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+#endif
+#ifdef CONFIG_82xx_CONS_SMC2
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+#endif
+
+#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
+#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
+ * X.29 connector, and FCC2 is hardwired to the X.1 connector)
+ */
+#define CFG_FCC_ETHERNET
+
+#if defined(CFG_FCC_ETHERNET)
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
+#else
+#define	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */
+#endif
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ *  - RX clk is CLK11
+ *  - TX clk is CLK12
+ */
+# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT	2		/* Port C */
+
+#if STK82xx_150
+#define CFG_MDIO_PIN	0x00008000	/* PC16 */
+#define CFG_MDC_PIN	0x00004000	/* PC17 */
+#endif
+
+#if STK82xx_100
+#define CFG_MDIO_PIN	0x00000002	/* PC30 */
+#define CFG_MDC_PIN	0x00000001	/* PC31 */
+#endif
+
+#if 1
+#define MDIO_ACTIVE	(iop->pdir |=  CFG_MDIO_PIN)
+#define MDIO_TRISTATE	(iop->pdir &= ~CFG_MDIO_PIN)
+#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  CFG_MDIO_PIN; \
+			else	iop->pdat &= ~CFG_MDIO_PIN
+
+#define MDC(bit)	if(bit) iop->pdat |=  CFG_MDC_PIN; \
+			else	iop->pdat &= ~CFG_MDC_PIN
+#else
+#define MDIO_ACTIVE	({unsigned long tmp; tmp = iop->pdir; tmp |=  CFG_MDIO_PIN; iop->pdir = tmp;})
+#define MDIO_TRISTATE	({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;})
+#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)
+
+#define MDIO(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CFG_MDIO_PIN; iop->pdat = tmp;}\
+			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;}
+
+#define MDC(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CFG_MDC_PIN; iop->pdat = tmp;}\
+			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;}
+#endif
+
+#define MIIDELAY	udelay(1)
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PING	| \
+				ADD_CMD_I2C	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#if 0
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR	0x300000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0x40000104	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * CAN stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_CAN_BASE	0x51000000
+#define	CFG_CAN_SIZE	1
+#define CFG_CAN_BR	((CFG_CAN_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_UPMC			|\
+			 BRx_V)
+
+#define CFG_CAN_OR	(MEG_TO_AM(CFG_CAN_SIZE)	|\
+			 ORxU_BI)
+
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CFG_FLASH0_BASE 0x40000000
+#define CFG_FLASH0_SIZE 32	/* 32 MB */
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_CFI				/* flash is CFI compat.	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#define CFG_UPDATE_FLASH_SIZE
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
+#define CFG_ENV_SIZE		0x20000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	0x20000
+
+/* Where is the Hardwareinformation Block (from Monitor Sources) */
+#define MON_RES_LENGTH		(0x0003FC00)
+#define HWIB_INFO_START_ADDR    (CFG_FLASH_BASE + MON_RES_LENGTH)
+#define HWIB_INFO_LEN           512
+#define CIB_INFO_START_ADDR     (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
+#define CIB_INFO_LEN            512
+
+#define CFG_HWINFO_OFFSET	0x3fc00	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000060	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND_CS_DIST		0x80
+#define CFG_NAND_UPM_WRITE_CMD_OFS	0x20
+#define CFG_NAND_UPM_WRITE_ADDR_OFS	0x40
+
+#define CFG_NAND_BR	((CFG_NAND0_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_UPMB			|\
+			 BRx_V)
+
+#define CFG_NAND_OR	(MEG_TO_AM(CFG_NAND_SIZE)	|\
+			 ORxU_BI			|\
+			 ORxU_EHTR_8IDLE)
+
+#define CFG_NAND_SIZE	1
+#define CFG_NAND0_BASE 0x50000000
+#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
+#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
+#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
+
+#define CFG_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
+			     CFG_NAND1_BASE, \
+			     CFG_NAND2_BASE, \
+			     CFG_NAND3_BASE, \
+			   }
+
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
+#define WRITE_NAND_UPM(d, adr, off) do \
+{ \
+	volatile unsigned char *addr = (unsigned char *) (adr + off); \
+	WRITE_NAND(d, addr); \
+} while(0)
+
+#endif /* CFG_CMD_NAND */
+
+#define	CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+#define CONFIG_PCI_PNP
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#if 0
+#define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
+
+#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+#else
+#define CFG_HRCW_MASTER	(HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)	/* 60x mode  */
+#define BCR_APD01	0x10000000
+#define CFG_BCR_SINGLE		(BCR_APD01|BCR_ETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+#define CFG_SIUMCR_LOW		(SIUMCR_DPPC00)
+#define CFG_SIUMCR_HIGH		(SIUMCR_DPPC00 | SIUMCR_ABE)
+#else
+#define CFG_SIUMCR		(SIUMCR_DPPC00)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR        SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    32 bit  FLASH
+ *  1   60x     SDRAM   64 bit  SDRAM
+ *  2   60x	UPMB	 8 bit	NAND
+ *  3   60x	UPMC	 8 bit	CAN
+ *
+ */
+
+/* Initialize SDRAM
+	 */
+#undef CFG_INIT_LOCAL_SDRAM		/* No SDRAM on Local Bus */
+
+#define SDRAM_MAX_SIZE	0x20000000	/* max. 512 MB		*/
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CFG_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
+
+#define CFG_MPTPR       0x4000
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ * In fact, the address is rather configuration data presented to the SDRAM on
+ * its address lines. Because the address lines may be mux'ed externally either
+ * for 8 column or 9 column devices, some bits appear twice in the 8260's
+ * address:
+ *
+ * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
+ * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
+ *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
+ *-----------------------------------------------------------------------------
+ */
+#define CFG_MRS_OFFS	0x00000110
+
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_32                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV4                  |\
+			 ORxG_SCY_8_CLK                 |\
+			 ORxG_TRLX)
+
+/* SDRAM on TQM8272 can have either 8 or 9 columns.
+ * The number affects configuration values.
+ */
+
+/* Bank 1 - 60x bus SDRAM
+ */
+#define CFG_PSRT        0x20	/* Low Value */
+/* #define CFG_PSRT        0x10	 Fast Value */
+#define CFG_LSRT        0x20	/* Local Bus */
+#ifndef CFG_RAMBOOT
+#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM	CFG_OR1_8COL
+
+/* SDRAM initialization values for 8-column chips
+ */
+#define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A7             |\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_BUFCMD			|\
+			 PSDMR_CL_2)
+
+
+/* SDRAM initialization values for 9-column chips
+ */
+#define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A5             |\
+			 ORxS_NUMR_13)
+
+#define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A7            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_BUFCMD			|\
+			 PSDMR_CL_2)
+
+#define CFG_OR1_10COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A4             |\
+			 ORxS_NUMR_13)
+
+#define CFG_PSDMR_10COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A17_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A4            |\
+			 PSDMR_RFRC_6_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_BUFCMD			|\
+			 PSDMR_CL_2)
+
+#define PSDMR_RFRC_66MHZ_SINGLE         0x00028000  /* PSDMR[RFRC] at 66 MHz single mode */
+#define PSDMR_RFRC_100MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 100 MHz single mode */
+#define PSDMR_RFRC_133MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 133 MHz single mode */
+#define PSDMR_RFRC_66MHZ_60X            0x00030000  /* PSDMR[RFRC] at 66 MHz 60x mode */
+#define PSDMR_RFRC_100MHZ_60X           0x00028000  /* PSDMR[RFRC] at 100 MHz 60x mode */
+#define PSDMR_RFRC_DEFAULT              PSDMR_RFRC_133MHZ_SINGLE  /* PSDMR[RFRC] default value */
+
+#define PSDMR_PRETOACT_66MHZ_SINGLE     0x00002000  /* PSDMR[PRETOACT] at 66 MHz single mode */
+#define PSDMR_PRETOACT_100MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 100 MHz single mode */
+#define PSDMR_PRETOACT_133MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 133 MHz single mode */
+#define PSDMR_PRETOACT_66MHZ_60X        0x00001000  /* PSDMR[PRETOACT] at 66 MHz 60x mode */
+#define PSDMR_PRETOACT_100MHZ_60X       0x00001000  /* PSDMR[PRETOACT] at 100 MHz 60x mode */
+#define PSDMR_PRETOACT_DEFAULT          PSDMR_PRETOACT_133MHZ_SINGLE  /* PSDMR[PRETOACT] default value */
+
+#define PSDMR_WRC_66MHZ_SINGLE          0x00000020  /* PSDMR[WRC] at 66 MHz single mode */
+#define PSDMR_WRC_100MHZ_SINGLE         0x00000020  /* PSDMR[WRC] at 100 MHz single mode */
+#define PSDMR_WRC_133MHZ_SINGLE         0x00000010  /* PSDMR[WRC] at 133 MHz single mode */
+#define PSDMR_WRC_66MHZ_60X             0x00000010  /* PSDMR[WRC] at 66 MHz 60x mode */
+#define PSDMR_WRC_100MHZ_60X            0x00000010  /* PSDMR[WRC] at 100 MHz 60x mode */
+#define PSDMR_WRC_DEFAULT               PSDMR_WRC_133MHZ_SINGLE  /* PSDMR[WRC] default value */
+
+#define PSDMR_BUFCMD_66MHZ_SINGLE       0x00000000  /* PSDMR[BUFCMD] at 66 MHz single mode */
+#define PSDMR_BUFCMD_100MHZ_SINGLE      0x00000000  /* PSDMR[BUFCMD] at 100 MHz single mode */
+#define PSDMR_BUFCMD_133MHZ_SINGLE      0x00000004  /* PSDMR[BUFCMD] at 133 MHz single mode */
+#define PSDMR_BUFCMD_66MHZ_60X          0x00000000  /* PSDMR[BUFCMD] at 66 MHz 60x mode */
+#define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
+#define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
+
+#endif /* CFG_RAMBOOT */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 4bbee97..ed03577 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -37,10 +37,11 @@
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC83XX		1	/* MPC83XX family */
 #define CONFIG_MPC834X		1	/* MPC834X specific */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_TQM834X		1	/* TQM834X board specific */
 
 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */
-#define CFG_IMMRBAR		0xff400000
+#define CFG_IMMR		0xff400000
 
 /* System clock. Primary input clock when in PCI host mode */
 #define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */
@@ -83,6 +84,7 @@
 #define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #undef CFG_FLASH_CHECKSUM
 #define CFG_FLASH_BASE		0x80000000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		8		/* FLASH size in MB */
 
 /* buffered writes in the AMD chip set is not supported yet */
 #undef CFG_FLASH_USE_BUFFER_WRITE
@@ -197,14 +199,15 @@ extern int tqm834x_num_flash_banks;
 #define CFG_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_IMMRBAR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMRBAR + 0x4600)
+#define CFG_NS16550_COM1	(CFG_IMMR + 0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR + 0x4600)
 
 /*
  * I2C
  */
 #define CONFIG_HARD_I2C				/* I2C with hardware support	*/
 #undef CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CONFIG_FSL_I2C
 #define CFG_I2C_SPEED			400000	/* I2C speed: 400KHz		*/
 #define CFG_I2C_SLAVE			0x7F	/* slave address		*/
 #define CFG_I2C_OFFSET			0x3000
@@ -235,9 +238,9 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_MII
 
 #define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+#define CFG_TSEC1		(CFG_IMMR + CFG_TSEC1_OFFSET)
 #define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMRBAR + CFG_TSEC2_OFFSET)
+#define CFG_TSEC2		(CFG_IMMR + CFG_TSEC2_OFFSET)
 
 #if defined(CONFIG_TSEC_ENET)
 
@@ -460,8 +463,8 @@ extern int tqm834x_num_flash_banks;
 #endif
 
 /* IMMRBAR */
-#define CFG_IBAT6L	(CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT6U	(CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CFG_IBAT6L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U	(CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
 
 /* FLASH */
 #define CFG_IBAT7L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
new file mode 100644
index 0000000..9e02ca3
--- /dev/null
+++ b/include/configs/acadia.h
@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * acadia.h - configuration for AMCC Acadia (405EZ)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ACADIA			1	/* Board is Acadia	*/
+#define CONFIG_4xx			1	/* ... PPC4xx family	*/
+#define CONFIG_405EZ			1	/* Specifc 405EZ support*/
+#undef	CFG_DRAM_TEST				/* Disable-takes long time */
+#define CONFIG_SYS_CLK_FREQ	66666666	/* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+
+#define CONFIG_NO_SERIAL_EEPROM
+/*#undef CONFIG_NO_SERIAL_EEPROM*/
+
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*----------------------------------------------------------------------------
+ * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+ * assuming a 66MHz input clock to the 405EZ.
+ *---------------------------------------------------------------------------*/
+/* #define PLLMR0_100_100_12 */
+#define PLLMR0_200_133_66
+/* #define PLLMR0_266_160_80 */
+/* #define PLLMR0_333_166_83 */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_MONITOR_LEN		(256 * 1024)/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(384 * 1024)/* Reserve 128 kB for malloc()	*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_USB_HOST		0xef603000	/* USB OHCI 1.1 controller	*/
+
+/*
+ * Define here the location of the environment variables (FLASH).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ *       supported for backward compatibility.
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+   #define CFG_ENV_IS_IN_FLASH	1 		/* use FLASH for environment vars	*/
+#else
+   #define CFG_ENV_IS_IN_NAND	1		/* use NAND for environment vars	*/
+#endif
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=acadia\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"				\
+	"bootfile=acadia/uImage\0"					\
+	"kernel_addr=fff10000\0"					\
+	"ramdisk_addr=fff20000\0"					\
+	"initrd_high=30000000\0"					\
+	"load=tftp 200000 acadia/u-boot.bin\0"				\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b ${fileaddr} fffc0000 ${filesize};"		\
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	"kozio=bootm ffc60000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_NET_MULTI	1
+#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+#if 0 /* test-only */
+#define TEST_ONLY_NAND
+#endif
+
+#ifdef TEST_ONLY_NAND
+#define CMD_NAND		CFG_CMD_NAND
+#else
+#define CMD_NAND		0
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#define CONFIG_COMMANDS       (CONFIG_CMD_DFL	|	\
+			       CFG_CMD_ASKENV	|	\
+			       CFG_CMD_DHCP	|	\
+			       CFG_CMD_DTT	|	\
+			       CFG_CMD_DIAG	|	\
+			       CFG_CMD_EEPROM	|	\
+			       CFG_CMD_ELF	|	\
+			       CFG_CMD_FAT	|	\
+			       CFG_CMD_I2C	|	\
+			       CFG_CMD_IRQ	|	\
+			       CFG_CMD_MII	|	\
+			       CMD_NAND		|	\
+			       CFG_CMD_NET	|	\
+			       CFG_CMD_NFS	|	\
+			       CFG_CMD_PCI	|	\
+			       CFG_CMD_PING	|	\
+			       CFG_CMD_REGINFO	|	\
+			       CFG_CMD_SDRAM	|	\
+			       CFG_CMD_USB)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG					/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command		*/
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands	*/
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CFG_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CFG_BASE_BAUD		691200
+#define CONFIG_BAUDRATE		115200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
+#if 0 /* test-only... */
+/*-----------------------------------------------------------------------
+ * SPI stuff - Define to include SPI control
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SPI
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
+#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS     1		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	1024		    /* sectors per device   */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif
+
+#ifdef TEST_ONLY_NAND
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CFG_NAND_BASE		(CFG_NAND + CFG_NAND_CS)
+#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384		/* For AMCC 405EZ CPU		*/
+#define CFG_CACHELINE_SIZE	32		/* ...				*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5		/* log base 2 of the above value*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x4000			/* 16K of onchip SRAM		*/
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR	/* inside of SRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE	128			/* size for initial data	*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define CFG_NAND		0xd0000000
+#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
+
+/* Memory Bank 0 (Flash) initialization */
+#define CFG_EBC_PB0AP		0x03337200
+#define CFG_EBC_PB0CR		0xfe0bc000 	/* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit	*/
+
+/* Memory Bank 1 (CRAM) initialization */
+#define CFG_EBC_PB1AP		0x030400c0
+#define CFG_EBC_PB1CR		0x000bc000
+
+/* Memory Bank 2 (CRAM) initialization */
+#define CFG_EBC_PB2AP		0x030400c0
+#define CFG_EBC_PB2CR		0x020bc000
+
+/* Memory Bank 3 (NAND-FLASH) initialization					*/
+#define CFG_EBC_PB3AP		0x018003c0
+#define CFG_EBC_PB3CR		(CFG_NAND | 0x1c000)
+
+/* Memory Bank 4 (CPLD) initialization */
+#define CFG_EBC_PB4AP		0x04006000
+#define CFG_EBC_PB4CR		0x80018000 	/* BAS=0x000,BS=16MB,BU=R/W,BW=32bit	*/
+
+#define CFG_EBC_CFG		0xf8400000
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO_0 setup (PPC405EZ specific)
+ *
+ * GPIO0[0-3]	- External Bus Controller CS_4 - CS_7 Outputs
+ * GPIO0[4]	- External Bus Controller Hold Input
+ * GPIO0[5]	- External Bus Controller Priority Input
+ * GPIO0[6]	- External Bus Controller HLDA Output
+ * GPIO0[7]	- External Bus Controller Bus Request Output
+ * GPIO0[8]	- CRAM Clk Output
+ * GPIO0[9]	- External Bus Controller Ready Input
+ * GPIO0[10]	- CRAM Adv Output
+ * GPIO0[11-24]	- NAND Flash Control Data -> Bypasses GPIO when enabled
+ * GPIO0[25]	- External DMA Request Input
+ * GPIO0[26]	- External DMA EOT I/O
+ * GPIO0[25]	- External DMA Ack_n Output
+ * GPIO0[17-23]	- External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[28-30]	- Trace Outputs / PWM Inputs
+ * GPIO0[31]	- PWM_8 I/O
+ */
+#define CFG_GPIO0_TCR		0xC0000000
+#define CFG_GPIO0_OSRL		0x50000000
+#define CFG_GPIO0_OSRH		0x00000055
+#define CFG_GPIO0_ISR1L		0x00000000
+#define CFG_GPIO0_ISR1H		0x00000055
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TSRH		0x00000055
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO_1 setup (PPC405EZ specific)
+ *
+ * GPIO1[0-6]	- PWM_9 to PWM_15 I/O
+ * GPIO1[7]	- PWM_DIV_CLK (Out) / IRQ4 Input
+ * GPIO1[8]	- TS5 Output / DAC_IP_TRIG Input
+ * GPIO1[9]	- TS6 Output / ADC_IP_TRIG Input
+ * GPIO1[10-12]	- UART0 Control Inputs
+ * GPIO1[13]	- UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
+ * GPIO1[14]	- UART0_RTS_N Output/SPI_SS_2_N Output
+ * GPIO1[15]	- SPI_SS_3_N Output/UART0_RI_N Input
+ * GPIO1[16]	- SPI_SS_1_N Output
+ * GPIO1[17-20]	- Trace Output/External Interrupts IRQ0 - IRQ3 inputs
+ */
+#define CFG_GPIO1_OSRH		0x55455555
+#define CFG_GPIO1_OSRL		0x40000110
+#define CFG_GPIO1_ISR1H		0x00000000
+#define CFG_GPIO1_ISR1L		0x15555445
+#define CFG_GPIO1_TSRH		0x00000000
+#define CFG_GPIO1_TSRL		0x00000000
+#define CFG_GPIO1_TCR		0xFFFF8014
+
+/*-----------------------------------------------------------------------
+ * EPLD Regs.
+ */
+#define	EPLD_BASE	0x80000000
+#define	EPLD_ETHRSTBOOT	0x10
+#define	EPLD_CTRL	0x14
+#define	EPLD_MUXOE	0x16
+
+/*
+ * State definations
+ */
+#define	LOAK_INIT	0x494e4954	/* ASCII "INIT" */
+#define	LOAK_NONE	0x4e4f4e45	/* ASCII "NONE" */
+#define	LOAK_CRAM	0x4352414d	/* ASCII "CRAM" */
+#define	LOAK_PSRAM	0x50535241	/* ASCII "PSRA" - PSRAM */
+#define	LOAK_OCM	0x4f434d20	/* ASCII "OCM " */
+#define	LOAK_ZERO	0x5a45524f	/* ASCII "ZERO" */
+#define	LOAK_SPL	0x53504c20	/* ASCII "SPL" */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+  #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
new file mode 100644
index 0000000..67f62d3
--- /dev/null
+++ b/include/configs/alpr.h
@@ -0,0 +1,365 @@
+/*
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ALPR		1	    /* Board is ebony		*/
+#define CONFIG_440GX		1	    /* Specifc GX support	*/
+#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
+#define CONFIG_LAST_STAGE_INIT	1	    /* call last_stage_init()	*/
+#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0			*/
+#define CFG_FLASH_BASE		0xffe00000	/* start of FLASH		*/
+#define CFG_MONITOR_BASE	0xfffc0000	/* start of monitor		*/
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory		*/
+#define	CFG_PCI_MEMSIZE		0x40000000	/* size of mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE	0xe0000000	/* internal peripherals		*/
+#define CFG_ISRAM_BASE		0xc0000000	/* internal SRAM		*/
+#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs		*/
+#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
+
+
+#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM  1
+#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CFG_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE		115200
+#define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI		1	/* The flash is CFI compatible		*/
+#define CFG_FLASH_CFI_DRIVER	1	/* Use common CFI driver		*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
+#undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
+#define CFG_SDRAM_TABLE	{ \
+		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
+		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs	*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (PCF8594C)
+ *----------------------------------------------------------------------*/
+#define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
+					/* 8 byte page write mode using */
+					/* last 3 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run kernelx\" to boot the system;"			\
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth3\0"							\
+	"hostname=alpr\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath} ${init}\0"		\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
+		"mem=193M\0"						\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/projects/alpr/nfs_root\0"			\
+	"bootfile=/alpr/uImage\0"					\
+	"kernel_addr=fff00000\0"					\
+	"ramdisk_addr=fff10000\0"					\
+	"load=tftp 100000 /alpr/u-boot/u-boot.bin\0"			\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	"ethprime=ppc_4xx_eth3\0"					\
+	"ethact=ppc_4xx_eth3\0"						\
+	"autoload=no\0"							\
+	"ipconfig=dhcp;setenv serverip 11.0.0.152\0"			\
+	"load_fpga=fpga load 0 ffe00000 10dd9a\0"			\
+	"mtdargs=setenv bootargs root=/dev/mtdblock6 rw "		\
+		"rootfstype=jffs2 init=/sbin/init\0"			\
+	"kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
+		";bootm 200000\0"					\
+	"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip "	\
+		"addtty;bootm 200000\0"					\
+	"kernel1=setenv actkernel 'kernel1';run load_fpga "		\
+		"kernel1_mtd\0"						\
+	"kernel2=setenv actkernel 'kernel2';run load_fpga "		\
+		"kernel2_mtd\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run kernel2"
+
+#define CONFIG_BOOTDELAY	2	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI	1
+#define CONFIG_PHY_ADDR		0x02	/* dummy setting, no EMAC0 used	*/
+#define CONFIG_PHY1_ADDR	0x03	/* dummy setting, no EMAC1 used	*/
+#define CONFIG_PHY2_ADDR	0x01	/* PHY address for EMAC2	*/
+#define CONFIG_PHY3_ADDR	0x02	/* PHY address for EMAC3	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#define CONFIG_M88E1111_PHY	1	/* needed for PHY specific setup*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_FPGA	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_REGINFO)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_ALT_MEMTEST		1	/* Enable more extensive memtest*/
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC     	1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
+
+#define CFG_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CONFIG_PCI_BOOTDELAY	1       /* enable pci bootdelay variable*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ *-----------------------------------------------------------------------*/
+#define CONFIG_FPGA             CFG_ALTERA_CYCLON2
+#define CFG_FPGA_CHECK_CTRLC
+#define CFG_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_COUNT       1		/* Ich habe 2 ... aber in
+					Reihe geschaltet -> sollte gehen,
+					aufpassen mit Datasize ist jetzt
+					halt doppelt so gross ... Seite 306
+					ist das mit den multiple Device in PS
+					Mode erklaert ...*/
+
+/* FPGA program pin configuration */
+#define CFG_GPIO_CLK		18	/* FPGA clk pin (cpu output)		*/
+#define CFG_GPIO_DATA		19	/* FPGA data pin (cpu output)		*/
+#define CFG_GPIO_STATUS		20	/* FPGA status pin (cpu input)		*/
+#define CFG_GPIO_CONFIG		21	/* FPGA CONFIG pin (cpu output)		*/
+#define CFG_GPIO_CON_DON	22	/* FPGA CONFIG_DONE pin (cpu input)	*/
+
+#define CFG_GPIO_SEL_DPR	14	/* cpu output */
+#define CFG_GPIO_SEL_AVR	15	/* cpu output */
+#define CFG_GPIO_PROG_EN	23	/* cpu output */
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup
+ *-----------------------------------------------------------------------*/
+#define CFG_GPIO_SHUTDOWN	(0x80000000 >> 6)
+#define CFG_GPIO_SSD_EMPTY	(0x80000000 >> 9)
+#define CFG_GPIO_EREADY		(0x80000000 >> 26)
+#define CFG_GPIO_REV0		(0x80000000 >> 14)
+#define CFG_GPIO_REV1		(0x80000000 >> 15)
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE	4
+#define NAND_MAX_CHIPS		CFG_MAX_NAND_DEVICE
+#define CFG_NAND_BASE		0xF0000000	/* NAND FLASH Base Address	*/
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE + 0, CFG_NAND_BASE + 2,	\
+				  CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 }
+#define CFG_NAND_QUIET_TEST	1	/* don't warn upon unknown NAND flash	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH		CFG_FLASH_BASE
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NAND-FLASH) initialization					*/
+#define CFG_EBC_PB1AP		0x01840380	/* TWT=3			*/
+#define CFG_EBC_PB1CR		(CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		32768	/* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 4961011..bcc736c 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -257,6 +257,7 @@
 	"bootfile=/tftpboot/bamboo/uImage\0"				\
 	"kernel_addr=fff00000\0"					\
 	"ramdisk_addr=fff10000\0"					\
+	"initrd_high=30000000\0"					\
 	"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0"		\
 	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
 		"cp.b 100000 fffa0000 60000;"			        \
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
new file mode 100644
index 0000000..65dfc81
--- /dev/null
+++ b/include/configs/bf533-ezkit.h
@@ -0,0 +1,228 @@
+/*
+ * U-boot - Configuration file for BF533 EZKIT board
+ */
+
+#ifndef __CONFIG_EZKIT533_H__
+#define __CONFIG_EZKIT533_H__
+
+#define CONFIG_BAUDRATE		57600
+#define CONFIG_STAMP		1
+
+#define CONFIG_BOOTDELAY	5
+#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
+
+#define CFG_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_LOADADDR		0x01000000	/* default load address */
+#define CONFIG_BOOTCOMMAND	"tftp $(loadaddr) linux"
+/* #define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw" */
+
+#define CONFIG_DRIVER_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20310300
+
+#if 0
+#define	CONFIG_MII
+#define CFG_DISCOVER_PHY
+#endif
+
+#define CONFIG_RTC_BFIN		1
+#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
+
+/*
+ * Boot Mode Set
+ * Blackfin can support several boot modes
+ */
+#define BF533_BYPASS_BOOT	0x0001	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
+#define BF533_PARA_BOOT		0x0002	/* Bootmode 1: Boot from 8-bit or 16-bit flash */
+#define BF533_SPI_BOOT		0x0004	/* Bootmode 3: Boot from SPI flash */
+/* Define the boot mode */
+#define BFIN_BOOT_MODE		BF533_BYPASS_BOOT
+/* #define BFIN_BOOT_MODE	BF533_SPI_BOOT */
+
+#define CONFIG_PANIC_HANG 1
+
+#define ADSP_BF531		0x31
+#define ADSP_BF532		0x32
+#define ADSP_BF533		0x33
+#define BFIN_CPU		ADSP_BF533
+
+/* This sets the default state of the cache on U-Boot's boot */
+#define CONFIG_ICACHE_ON
+#define CONFIG_DCACHE_ON
+
+/* Define where the uboot will be loaded by on-chip boot rom */
+#define APP_ENTRY 0x00001000
+
+/* CONFIG_CLKIN_HZ is any value in Hz				*/
+#define CONFIG_CLKIN_HZ		27000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
+/*						    1=CLKIN/2	*/
+#define CONFIG_CLKIN_HALF	0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
+/*						 1=bypass PLL	*/
+#define CONFIG_PLL_BYPASS	0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
+/* Values can range from 1-64					*/
+#define CONFIG_VCO_MULT		22
+/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
+/* Values can be 1, 2, 4, or 8 ONLY				*/
+#define CONFIG_CCLK_DIV		1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15					*/
+#define CONFIG_SCLK_DIV		5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
+/* Values can range from 2-65535				*/
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
+#define CONFIG_SPI_BAUD		2
+#define CONFIG_SPI_BAUD_INITBLOCK	4
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
+#endif
+
+#define CONFIG_MEM_SIZE		32	/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH	9	/* 8, 9, 10, 11    */
+#define CONFIG_MEM_MT48LC16M16A2TG_75	1
+
+#define CONFIG_LOADS_ECHO	1
+
+
+#define CONFIG_COMMANDS			(CONFIG_CMD_DFL	| \
+					 CFG_CMD_PING	| \
+					 CFG_CMD_ELF	| \
+					 CFG_CMD_I2C	| \
+					 CFG_CMD_JFFS2	| \
+					 CFG_CMD_DATE)
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CFG_PROMPT		"ezkit> "	/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
+#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024 * 1024)	/* 1 ... 31 MB in DRAM */
+#define	CFG_LOAD_ADDR		0x01000000	/* default load address */
+#define	CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 * 1024)
+#define CFG_FLASH_BASE		0x20000000
+
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_SIZE	0x4000
+#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
+
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CFG_FLASH0_BASE		0x20000000
+#define CFG_FLASH1_BASE		0x20200000
+#define CFG_FLASH2_BASE		0x20280000
+#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	40	/* max number of sectors on one chip */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x20020000
+#define	CFG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
+
+/* JFFS Partition offset set  */
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR	11
+
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+
+#define POLL_MODE		1
+#define FLASH_TOT_SECT		40
+#define FLASH_SIZE		0x220000
+#define CFG_FLASH_SIZE		0x220000
+
+/*
+ * Initialize PSD4256 registers for using I2C
+ */
+#define	CONFIG_MISC_INIT_R
+
+/*
+ * I2C settings
+ * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
+ */
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged */
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL			PF0
+#define PF_SDA			PF1
+
+#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
+#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit)	if(bit) { \
+				*pFIO_FLAG_S = PF_SDA; \
+				asm("ssync;"); \
+				} \
+			else    { \
+				*pFIO_FLAG_C = PF_SDA; \
+				asm("ssync;"); \
+				}
+#define I2C_SCL(bit)	if(bit) { \
+				*pFIO_FLAG_S = PF_SCL; \
+				asm("ssync;"); \
+				} \
+			else    { \
+				*pFIO_FLAG_C = PF_SCL; \
+				asm("ssync;"); \
+				}
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED		50000
+#define CFG_I2C_SLAVE		0xFE
+
+#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
+
+/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
+/* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
+				~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
+#define AMBCTL1VAL		(B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
+				B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
+*/
+#define AMGCTLVAL		0xFF
+#define AMBCTL0VAL		0x7BB07BB0
+#define AMBCTL1VAL		0xFFC27BB0
+
+#define CONFIG_VDSP		1
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP		0x8
+#define SHT_STRTAB_VDSP		0x1
+#define ELFSHDRSIZE_VDSP	0x2C
+#define VDSP_ENTRY_ADDR		0xFFA00000
+#endif
+
+#endif
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
new file mode 100644
index 0000000..79a1404
--- /dev/null
+++ b/include/configs/bf533-stamp.h
@@ -0,0 +1,467 @@
+/*
+ * U-boot - Configuration file for BF533 STAMP board
+ */
+
+#ifndef __CONFIG_STAMP_H__
+#define __CONFIG_STAMP_H__
+
+#define CONFIG_STAMP			1
+#define CONFIG_RTC_BFIN			1
+#define CONFIG_BF533			1
+/*
+ * Boot Mode Set
+ * Blackfin can support several boot modes
+ */
+#define BF533_BYPASS_BOOT	0x0001	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
+#define BF533_PARA_BOOT		0x0002	/* Bootmode 1: Boot from 8-bit or 16-bit flash */
+#define BF533_SPI_BOOT		0x0004	/* Bootmode 3: Boot from SPI flash */
+/* Define the boot mode */
+#define BFIN_BOOT_MODE		BF533_BYPASS_BOOT
+/* #define BFIN_BOOT_MODE	BF533_SPI_BOOT */
+
+#define CONFIG_PANIC_HANG 1
+
+#define ADSP_BF531		0x31
+#define ADSP_BF532		0x32
+#define ADSP_BF533		0x33
+#define BFIN_CPU		ADSP_BF533
+
+/* This sets the default state of the cache on U-Boot's boot */
+#define CONFIG_ICACHE_ON
+#define CONFIG_DCACHE_ON
+
+/* Define where the uboot will be loaded by on-chip boot rom */
+#define APP_ENTRY 0x00001000
+
+/*
+ * Stringize definitions - needed for environmental settings
+ */
+#define STRINGIZE2(x) #x
+#define STRINGIZE(x) STRINGIZE2(x)
+
+/*
+ * Board settings
+ */
+#define CONFIG_DRIVER_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20300300
+
+/* FLASH/ETHERNET uses the same address range */
+#define SHARED_RESOURCES 	1
+
+/* Is I2C bit-banged? */
+#define CONFIG_SOFT_I2C		1
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL			PF3
+#define PF_SDA			PF2
+
+/*
+ * Video splash screen support
+ */
+#define  CONFIG_VIDEO		0
+
+#define CONFIG_VDSP		1
+
+/*
+ * Clock settings
+ */
+
+/* CONFIG_CLKIN_HZ is any value in Hz				*/
+#define CONFIG_CLKIN_HZ		11059200
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
+/*						    1=CLKIN/2	*/
+#define CONFIG_CLKIN_HALF	0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
+/*						 1=bypass PLL	*/
+#define CONFIG_PLL_BYPASS	0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
+/* Values can range from 1-64					*/
+#define CONFIG_VCO_MULT		36
+/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
+/* Values can be 1, 2, 4, or 8 ONLY				*/
+#define CONFIG_CCLK_DIV		1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
+/* Values can range from 1-15					*/
+#define CONFIG_SCLK_DIV		5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
+/* Values can range from 2-65535				*/
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
+#define CONFIG_SPI_BAUD		2
+
+#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CONFIG_SPI_BAUD_INITBLOCK	4
+#endif
+
+/*
+ * Network settings
+ */
+
+#if (CONFIG_DRIVER_SMC91111)
+#if 0
+#define	CONFIG_MII
+#endif
+
+/* network support */
+#define CONFIG_IPADDR		192.168.0.15
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_HOSTNAME		STAMP
+#define CONFIG_ROOTPATH		/checkout/uClinux-dist/romfs
+
+/* To remove hardcoding and enable MAC storage in EEPROM  */
+/* #define CONFIG_ETHADDR		02:80:ad:20:31:b8 */
+#endif /* CONFIG_DRIVER_SMC91111 */
+
+/*
+ * Flash settings
+ */
+
+#define CFG_FLASH_CFI		/* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver	*/
+#define	CFG_FLASH_CFI_AMD_RESET
+
+#define CFG_FLASH_BASE		0x20000000
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x20004000
+#define	CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
+#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_HEADER		(CFG_ENV_OFFSET + 0x12A)	/* 0x12A is the length of LDR file header */
+#endif
+
+#define	CFG_ENV_SIZE		0x2000
+#define CFG_ENV_SECT_SIZE 	0x2000	/* Total Size of Environment Sector */
+#define	ENV_IS_EMBEDDED
+
+#define CFG_FLASH_ERASE_TOUT	30000	/* Timeout for Chip Erase (in ms) */
+#define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms) */
+
+/* JFFS Partition offset set  */
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_NUM_BANKS  1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR 	11
+
+/*
+ * following timeouts shall be used once the
+ * Flash real protection is enabled
+ */
+#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+
+/*
+ * SDRAM settings & memory map
+ */
+
+#define CONFIG_MEM_SIZE		128	/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH     11	/* 8, 9, 10, 11    */
+#define CONFIG_MEM_MT48LC64M4A2FB_7E	1
+
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
+#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#endif
+
+#define	CFG_SDRAM_BASE		0x00000000
+
+#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 *1024)
+#define CFG_MEMTEST_END		(CFG_MAX_RAM_SIZE - 0x80000 - 1)
+#define CONFIG_LOADADDR		0x01000000
+
+#define CFG_LOAD_ADDR 		CONFIG_LOADADDR
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)     /* Reserve 128 kB for malloc()	*/
+#define CFG_GBL_DATA_SIZE	0x4000		/* Reserve 16k for Global Data  */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+
+#define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - 0x40000)
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
+
+/* Check to make sure everything fits in SDRAM */
+#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
+	#error Memory Map does not fit into configuration
+#endif
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
+#endif
+
+#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
+#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
+#else
+#undef CONFIG_SPI_FLASH_FAST_READ
+#endif
+#endif
+
+/*
+ * Command settings
+ */
+
+#define CFG_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
+#endif
+
+/* configuration lookup from the BOOTP/DHCP server, */
+/* but not try to load any image using TFTP	    */
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CONFIG_BOOTCOMMAND 	"eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
+#endif
+
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw console=ttyBF0,57600"
+
+#if (CONFIG_DRIVER_SMC91111)
+#define CONFIG_COMMANDS1	(CONFIG_CMD_DFL | \
+				 CFG_CMD_PING   | \
+				 CFG_CMD_ELF    | \
+				 CFG_CMD_CACHE  | \
+				 CFG_CMD_JFFS2  | \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_DATE)
+
+#else
+#define CONFIG_COMMANDS1	(CONFIG_CMD_DFL | \
+				 CFG_CMD_ELF    | \
+				 CFG_CMD_CACHE  | \
+				 CFG_CMD_JFFS2  | \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_DATE)
+#endif
+
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#if (CONFIG_DRIVER_SMC91111)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
+		"$(rootpath) console=ttyBF0,57600\0" \
+	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
+		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
+	"ramboot=tftpboot $(loadaddr) linux; " \
+		"run ramargs;run addip;bootelf\0" \
+	"nfsboot=tftpboot $(loadaddr) linux; " \
+		"run nfsargs;run addip;bootelf\0" \
+	"flashboot=bootm 0x20100000\0" \
+	"update=tftpboot $(loadaddr) u-boot.bin; " \
+		"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
+		"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
+	""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+	"flashboot=bootm 0x20100000\0" \
+	"
+#endif
+
+#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
+		"$(rootpath) console=ttyBF0,57600\0"	\
+	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
+		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
+	"ramboot=tftpboot $(loadaddr) linux; " \
+		"run ramargs;run addip;bootelf\0" \
+	"nfsboot=tftpboot $(loadaddr) linux; "	\
+		"run nfsargs;run addip;bootelf\0" \
+	"flashboot=bootm 0x20100000\0" \
+	"update=tftpboot $(loadaddr) u-boot.ldr;"	\
+		"eeprom write $(loadaddr) 0x0 $(filesize);\0"\
+	""
+#endif
+
+#ifdef CONFIG_SOFT_I2C
+#if (!CONFIG_SOFT_I2C)
+#undef CONFIG_SOFT_I2C
+#endif
+#endif
+
+#if (CONFIG_SOFT_I2C)
+#define CONFIG_COMMANDS2   CFG_CMD_I2C
+#else
+#define CONFIG_COMMANDS2 0
+#endif /* CONFIG_SOFT_I2C */
+
+#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
+#define CONFIG_COMMANDS  ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 | CFG_CMD_DHCP)
+#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#define CONFIG_COMMANDS  ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2)
+#endif
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Console settings
+ */
+
+#define CONFIG_BAUDRATE		57600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
+#if (BFIN_CPU == ADSP_BF531)
+#define	CFG_PROMPT	"serial_bf531> "	/* Monitor Command Prompt */
+#elif (BFIN_CPU == ADSP_BF532)
+#define	CFG_PROMPT	"serial_bf532> "	/* Monitor Command Prompt */
+#else
+#define	CFG_PROMPT	"serial_bf533> "	/* Monitor Command Prompt */
+#endif
+#else
+#if (BFIN_CPU == ADSP_BF531)
+#define	CFG_PROMPT	"bf531> "	/* Monitor Command Prompt */
+#elif (BFIN_CPU == ADSP_BF532)
+#define	CFG_PROMPT	"bf532> "	/* Monitor Command Prompt */
+#else
+#define	CFG_PROMPT	"bf533> "	/* Monitor Command Prompt */
+#endif
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_LOADS_ECHO	1
+
+/*
+ * I2C settings
+ * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
+ */
+#if (CONFIG_SOFT_I2C)
+
+#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
+#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit)	if(bit) { \
+				*pFIO_FLAG_S = PF_SDA; \
+				asm("ssync;"); \
+				} \
+			else	{ \
+				*pFIO_FLAG_C = PF_SDA; \
+				asm("ssync;"); \
+				}
+#define I2C_SCL(bit)	if(bit) { \
+				*pFIO_FLAG_S = PF_SCL; \
+				asm("ssync;"); \
+				} \
+			else	{ \
+				*pFIO_FLAG_C = PF_SCL; \
+				asm("ssync;"); \
+				}
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED		50000
+#define CFG_I2C_SLAVE		0xFE
+#endif /* CONFIG_SOFT_I2C */
+
+/*
+ * Compact Flash settings
+ */
+
+/* Enabled below option for CF support */
+/* #define CONFIG_STAMP_CF	1 */
+
+#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
+
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_DOS_PARTITION	1
+/*
+ * IDE/ATA stuff
+ */
+#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef  CONFIG_IDE_LED			/* no led for ide supported */
+#undef  CONFIG_IDE_RESET		/* no reset for ide supported */
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0x20200000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET	0x0007	/* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE		2
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define	CFG_HZ			1000	/* 1ms time tick */
+
+#define CFG_BOOTM_LEN		0x4000000/* Large Image Length, set to 64 Meg */
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs */
+
+#define CONFIG_SPI
+
+#ifdef  CONFIG_VIDEO
+#if (CONFIG_VIDEO)
+#define CONFIG_SPLASH_SCREEN	1
+#define CONFIG_SILENT_CONSOLE	1
+#else
+#undef CONFIG_VIDEO
+#endif
+#endif
+
+/*
+ * FLASH organization and environment definitions
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)/* Initial Memory map for Linux */
+
+/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
+/*#define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL		(B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
+				B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
+#define AMBCTL1VAL   		(B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
+				B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
+*/
+#define AMGCTLVAL		0xFF
+#define AMBCTL0VAL		0xBBC3BBC3
+#define AMBCTL1VAL		0x99B39983
+#define CF_AMBCTL1VAL		0x99B3ffc2
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP		0x8
+#define SHT_STRTAB_VDSP		0x1
+#define ELFSHDRSIZE_VDSP	0x2C
+#define VDSP_ENTRY_ADDR		0xFFA00000
+#endif
+
+#endif
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
new file mode 100644
index 0000000..f6755ac
--- /dev/null
+++ b/include/configs/bf537-stamp.h
@@ -0,0 +1,502 @@
+/*
+ * U-boot - Configuration file for BF537 STAMP board
+ */
+
+#ifndef __CONFIG_BF537_H__
+#define __CONFIG_BF537_H__
+
+#define CFG_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_BAUDRATE		57600
+/* Set default serial console for bf537 */
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BF537		1
+#define CONFIG_BOOTDELAY	5
+/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
+/*#define CONFIG_BF537_STAMP_LEDCMD	1*/
+
+/*
+ * Boot Mode Set
+ * Blackfin can support several boot modes
+ */
+#define BF537_BYPASS_BOOT	0x0011	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM)  */
+#define BF537_PARA_BOOT		0x0012	/* Bootmode 1: Boot from 8-bit or 16-bit flash                          */
+#define BF537_SPI_MASTER_BOOT	0x0014	/* Bootmode 3: SPI master mode boot from SPI flash                      */
+#define BF537_SPI_SLAVE_BOOT	0x0015	/* Bootmode 4: SPI slave mode boot from SPI flash                       */
+#define BF537_TWI_MASTER_BOOT	0x0016	/* Bootmode 5: TWI master mode boot from EEPROM                         */
+#define BF537_TWI_SLAVE_BOOT	0x0017	/* Bootmode 6: TWI slave mode boot from EEPROM                          */
+#define BF537_UART_BOOT		0x0018	/* Bootmode 7: UART slave mdoe boot via UART host                       */
+/* Define the boot mode */
+#define BFIN_BOOT_MODE		BF537_BYPASS_BOOT
+
+#define CONFIG_PANIC_HANG 1
+
+#define ADSP_BF534		0x34
+#define ADSP_BF536		0x36
+#define ADSP_BF537		0x37
+#define BFIN_CPU		ADSP_BF537
+
+/* This sets the default state of the cache on U-Boot's boot */
+#define CONFIG_ICACHE_ON
+#define CONFIG_DCACHE_ON
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST_TEST
+
+/* Define where the uboot will be loaded by on-chip boot rom */
+#define APP_ENTRY 0x00001000
+
+#define CONFIG_RTC_BFIN		1
+#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
+
+/* CONFIG_CLKIN_HZ is any value in Hz				*/
+#define CONFIG_CLKIN_HZ		25000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
+/*						    1=CLKIN/2	*/
+#define CONFIG_CLKIN_HALF	0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
+/*						    1=bypass PLL*/
+#define CONFIG_PLL_BYPASS	0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
+/* Values can range from 1-64					*/
+#define CONFIG_VCO_MULT			20
+/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
+/* Values can be 1, 2, 4, or 8 ONLY				*/
+#define CONFIG_CCLK_DIV			1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
+/* Values can range from 1-15					*/
+#define CONFIG_SCLK_DIV			5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
+/* Values can range from 2-65535				*/
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
+#define CONFIG_SPI_BAUD			2
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#define CONFIG_SPI_BAUD_INITBLOCK	4
+#endif
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
+#endif
+
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
+#define CONFIG_SPI_FLASH_FAST_READ 1	/* Needed if SPI_CLK > 20 MHz */
+#else
+#undef CONFIG_SPI_FLASH_FAST_READ
+#endif
+#endif
+
+#define CONFIG_MEM_SIZE			64	/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH		10	/* 8, 9, 10, 11 */
+#define CONFIG_MEM_MT48LC32M8A2_75	1
+
+#define CONFIG_LOADS_ECHO		1
+
+/*
+ * rarpb, bootp or dhcp commands will perform only a
+ * configuration lookup from the BOOTP/DHCP server
+ * but not try to load any image using TFTP
+ */
+#define CFG_AUTOLOAD			"no"
+
+/*
+ * Network Settings
+ */
+/* network support */
+#if (BFIN_CPU != ADSP_BF534)
+#define CONFIG_IPADDR		192.168.0.15
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_HOSTNAME		BF537
+#endif
+
+#define CONFIG_ROOTPATH		/romfs
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
+
+#define CFG_LONGHELP		1
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
+#define CONFIG_BOOTCOMMAND 	"run ramboot"
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST)
+/* POST support */
+#define CONFIG_POST 		( CFG_POST_MEMORY | \
+				  CFG_POST_UART	  | \
+				  CFG_POST_FLASH  | \
+				  CFG_POST_ETHER  | \
+				  CFG_POST_LED	  | \
+				  CFG_POST_BUTTON)
+#else
+#undef CONFIG_POST
+#endif
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG	CFG_CMD_DIAG
+#define FLASH_START_POST_BLOCK	11	/* Should > = 11 */
+#define FLASH_END_POST_BLOCK	71	/* Should < = 71 */
+#else
+#define CFG_CMD_POST_DIAG	0
+#endif
+
+/* CF-CARD IDE-HDD Support */
+
+/* #define CONFIG_BFIN_TRUE_IDE */	/* Add CF flash card support */
+/* #define CONFIG_BFIN_CF_IDE */	/* Add CF flash card support */
+/* #define CONFIG_BFIN_HDD_IDE */	/* Add IDE Disk Drive (HDD) support */
+
+#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
+# define CONFIG_BFIN_IDE	1
+# define ADD_IDE_CMD		CFG_CMD_IDE
+#else
+# define ADD_IDE_CMD		0
+#endif
+
+/*#define CONFIG_BF537_NAND */		/* Add nand flash support */
+
+#ifdef CONFIG_BF537_NAND
+# define ADD_NAND_CMD		CFG_CMD_NAND
+#else
+# define ADD_NAND_CMD		0
+#endif
+
+#define CONFIG_NETCONSOLE	1
+#define CONFIG_NET_MULTI	1
+
+#if (BFIN_CPU == ADSP_BF534)
+#define CONFIG_BFIN_CMD		(CONFIG_CMD_DFL & ~CFG_CMD_NET)
+#else
+#define CONFIG_BFIN_CMD		(CONFIG_CMD_DFL | CFG_CMD_PING)
+#endif
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+#define CONFIG_COMMANDS		(CONFIG_BFIN_CMD| \
+				 CFG_CMD_ELF	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_CACHE  | \
+				 CFG_CMD_JFFS2	| \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_DHCP   | \
+				 ADD_IDE_CMD	| \
+				 ADD_NAND_CMD	| \
+				 CFG_CMD_POST_DIAG | \
+				 CFG_CMD_DATE)
+#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#define CONFIG_COMMANDS		(CONFIG_BFIN_CMD| \
+				 CFG_CMD_ELF	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_CACHE  | \
+				 CFG_CMD_JFFS2	| \
+				 CFG_CMD_EEPROM | \
+				 ADD_IDE_CMD	| \
+				 CFG_CMD_DATE)
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
+#define CONFIG_LOADADDR	0x1000000
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
+#if (BFIN_CPU != ADSP_BF534)
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
+	"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
+	"addip=setenv bootargs $(bootargs) "			\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+	":$(hostname):eth0:off\0"				\
+	"ramboot=tftpboot $(loadaddr) linux;"			\
+	"run ramargs;run addip;bootelf\0"			\
+	"nfsboot=tftpboot $(loadaddr) linux;"			\
+	"run nfsargs;run addip;bootelf\0"			\
+	"flashboot=bootm 0x20100000\0"				\
+	"update=tftpboot $(loadaddr) u-boot.bin;"		\
+	"protect off 0x20000000 0x2007FFFF;"			\
+	"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0"	\
+	""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
+	"flashboot=bootm 0x20100000\0"				\
+	""
+#endif
+#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#if (BFIN_CPU != ADSP_BF534)
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
+	"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
+	"addip=setenv bootargs $(bootargs) "			\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+	":$(hostname):eth0:off\0"				\
+	"ramboot=tftpboot $(loadaddr) linux;"			\
+	"run ramargs;run addip;bootelf\0"			\
+	"nfsboot=tftpboot $(loadaddr) linux;"			\
+	"run nfsargs;run addip;bootelf\0"			\
+	"flashboot=bootm 0x20100000\0"				\
+	"update=tftpboot $(loadaddr) u-boot.ldr;"		\
+	"eeprom write $(loadaddr) 0x0 $(filesize);\0"		\
+	""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"	\
+	"flashboot=bootm 0x20100000\0"				\
+	""
+#endif
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#if (BFIN_CPU == ADSP_BF534)
+#define	CFG_PROMPT		"serial_bf534> "	/* Monitor Command Prompt */
+#elif (BFIN_CPU == ADSP_BF536)
+#define	CFG_PROMPT		"serial_bf536> "	/* Monitor Command Prompt */
+#else
+#define	CFG_PROMPT		"serial_bf537> "	/* Monitor Command Prompt */
+#endif
+#else
+#if (BFIN_CPU == ADSP_BF534)
+#define	CFG_PROMPT		"bf534> "	/* Monitor Command Prompt */
+#elif (BFIN_CPU == ADSP_BF536)
+#define	CFG_PROMPT		"bf536> "	/* Monitor Command Prompt */
+#else
+#define	CFG_PROMPT		"bf537> "	/* Monitor Command Prompt */
+#endif
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CFG_MAX_RAM_SIZE       	(CONFIG_MEM_SIZE * 1024*1024)
+#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START	0x0	/* memtest works on */
+#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */
+#define	CFG_LOAD_ADDR		CONFIG_LOADADDR	/* default load address */
+#define	CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define	CFG_SDRAM_BASE		0x00000000
+
+#define CFG_FLASH_BASE		0x20000000
+
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_SIZE	0x4000
+#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
+
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT)
+/* for bf537-stamp, usrt boot mode still store env in flash */
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x20004000
+#define CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
+#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_HEADER		(CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
+#endif
+#define CFG_ENV_SIZE		0x2000
+#define	CFG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
+/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */
+#define ENV_IS_EMBEDDED
+/* #endif */
+
+/* JFFS Partition offset set  */
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR	15
+
+#define CONFIG_SPI
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+
+#define POLL_MODE		1
+#define FLASH_TOT_SECT		71
+#define FLASH_SIZE		0x400000
+#define CFG_FLASH_SIZE		0x400000
+
+/*
+ * Board NAND Infomation
+ */
+
+#define CFG_NAND_ADDR		0x20212000
+#define CFG_NAND_BASE		CFG_NAND_ADDR
+#define CFG_MAX_NAND_DEVICE	1
+#define SECTORSIZE		512
+#define ADDR_COLUMN		1
+#define ADDR_PAGE		2
+#define ADDR_COLUMN_PAGE	3
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS		1
+#define NAND_MAX_CHIPS		1
+#define BFIN_NAND_READY		PF3
+
+#define NAND_WAIT_READY(nand)  			\
+	do { 					\
+		int timeout = 0; 		\
+		while(!(*pPORTFIO & PF3)) 	\
+			if (timeout++ > 100000)	\
+				break;		\
+	} while (0)
+
+#define BFIN_NAND_CLE		(1<<2)	/* A2 -> Command Enable */
+#define BFIN_NAND_ALE		(1<<1)	/* A1 -> Address Enable */
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+/*
+ * Initialize PSD4256 registers for using I2C
+ */
+#define CONFIG_MISC_INIT_R
+
+#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
+
+/*
+ * I2C settings
+ * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
+ */
+/* #define CONFIG_SOFT_I2C	1*/	/* I2C bit-banged */
+#define CONFIG_HARD_I2C		1	/* I2C TWI */
+#if defined CONFIG_HARD_I2C
+#define CONFIG_TWICLK_KHZ	50
+#endif
+
+#if defined CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PF_SCL			PF0
+#define PF_SDA			PF1
+
+#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
+#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit)		if(bit) { \
+					*pFIO_FLAG_S = PF_SDA; \
+					asm("ssync;"); \
+					} \
+				else    { \
+					*pFIO_FLAG_C = PF_SDA; \
+					asm("ssync;"); \
+					}
+#define I2C_SCL(bit)		if(bit) { \
+					*pFIO_FLAG_S = PF_SCL; \
+					asm("ssync;"); \
+					} \
+				else    { \
+					*pFIO_FLAG_C = PF_SCL; \
+					asm("ssync;"); \
+					}
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#endif
+
+#define CFG_I2C_SPEED		50000
+#define CFG_I2C_SLAVE		0xFE
+
+/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
+/* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
+				~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
+#define AMBCTL1VAL		(B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
+				B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
+*/
+
+#define AMGCTLVAL		0xFF
+#define AMBCTL0VAL		0x7BB07BB0
+#define AMBCTL1VAL		0xFFC27BB0
+
+#define CONFIG_VDSP		1
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP		0x8
+#define SHT_STRTAB_VDSP		0x1
+#define ELFSHDRSIZE_VDSP	0x2C
+#define VDSP_ENTRY_ADDR		0xFFA00000
+#endif
+
+#if defined(CONFIG_BFIN_IDE)
+
+#define CONFIG_DOS_PARTITION	1
+/*
+ * IDE/ATA stuff
+ */
+#undef  CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
+#undef  CONFIG_IDE_LED		/* no led for ide supported */
+#undef  CONFIG_IDE_RESET	/* no reset for ide supported */
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1)	/* max. 1 drives per IDE bus */
+
+#undef  AMBCTL1VAL
+#define AMBCTL1VAL		0xFFC3FFC3
+
+#define CONFIG_CF_ATASEL_DIS	0x20311800
+#define CONFIG_CF_ATASEL_ENA	0x20311802
+
+#if defined(CONFIG_BFIN_TRUE_IDE)
+/*
+ * Note that these settings aren't for the most part used in include/ata.h
+ * when all of the ATA registers are setup
+ */
+#define CFG_ATA_BASE_ADDR	0x2031C000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET	0x001C	/* Offset for alternate registers */
+#define CFG_ATA_STRIDE		2	/* CF.A0 --> Blackfin.Ax */
+#endif				/* CONFIG_BFIN_TRUE_IDE */
+
+#if defined(CONFIG_BFIN_CF_IDE)	/* USE CompactFlash Storage Card in the common memory space */
+#define CFG_ATA_BASE_ADDR	0x20211800
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET	0x000E	/* Offset for alternate registers */
+#define CFG_ATA_STRIDE		1	/* CF.A0 --> Blackfin.Ax */
+#endif				/* CONFIG_BFIN_CF_IDE */
+
+#if defined(CONFIG_BFIN_HDD_IDE)	/* USE TRUE IDE */
+#define CFG_ATA_BASE_ADDR	0x20314000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET	0x001C	/* Offset for alternate registers */
+#define CFG_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */
+
+#undef  CONFIG_SCLK_DIV
+#define CONFIG_SCLK_DIV		8
+#endif				/* CONFIG_BFIN_HDD_IDE */
+
+#endif				/*CONFIG_BFIN_IDE */
+
+#endif
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
new file mode 100644
index 0000000..8d826fa
--- /dev/null
+++ b/include/configs/bf561-ezkit.h
@@ -0,0 +1,244 @@
+/*
+ * U-boot - Configuration file for BF561 EZKIT board
+ */
+
+#ifndef __CONFIG_EZKIT561_H__
+#define __CONFIG_EZKIT561_H__
+
+#define CONFIG_VDSP		1
+#define CONFIG_BF561		1
+
+#define CFG_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_BAUDRATE		57600
+/* Set default serial console for bf537 */
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_EZKIT561		1
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_PANIC_HANG 1
+
+/*
+* Boot Mode Set
+* Blackfin can support several boot modes
+*/
+#define BF561_BYPASS_BOOT	0x21
+#define BF561_PARA_BOOT		0x22
+#define BF561_SPI_BOOT		0x24
+/* Define the boot mode */
+#define BFIN_BOOT_MODE	BF561_BYPASS_BOOT
+
+/* This sets the default state of the cache on U-Boot's boot */
+#define CONFIG_ICACHE_ON
+#define CONFIG_DCACHE_ON
+
+/* Define where the uboot will be loaded by on-chip boot rom */
+#define APP_ENTRY 0x00001000
+
+/*
+ * Stringize definitions - needed for environmental settings
+ */
+#define STRINGIZE2(x) #x
+#define STRINGIZE(x) STRINGIZE2(x)
+
+/*
+ * Board settings
+ */
+#define CONFIG_DRIVER_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x2C010300
+#define CONFIG_ASYNC_EBIU_BASE	CONFIG_SMC91111_BASE & ~(4*1024*1024)
+#define CONFIG_SMC_USE_32_BIT	1
+#define CONFIG_MISC_INIT_R	1
+
+/*
+ * Clock settings
+ */
+
+/* CONFIG_CLKIN_HZ is any value in Hz				*/
+#define CONFIG_CLKIN_HZ		30000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
+/*						    1=CLKIN/2	*/
+#define CONFIG_CLKIN_HALF	0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
+/*						 1=bypass PLL	*/
+#define CONFIG_PLL_BYPASS	0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is	*/
+/* Values can range from 1-64					*/
+#define CONFIG_VCO_MULT		20
+/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
+/* Values can be 1, 2, 4, or 8 ONLY				*/
+#define CONFIG_CCLK_DIV		1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
+/* Values can range from 1-15					*/
+#define CONFIG_SCLK_DIV		5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
+/* Values can range from 2-65535				*/
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
+#define CONFIG_SPI_BAUD		2
+#define CONFIG_SPI_BAUD_INITBLOCK	4
+
+/*
+ * Network settings
+ */
+#if (CONFIG_DRIVER_SMC91111)
+#define CONFIG_IPADDR		192.168.0.15
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_HOSTNAME		ezkit561
+#define CONFIG_ROOTPATH		/arm-cross-build/BF561/uClinux-dist/romfs
+#endif				/* CONFIG_DRIVER_SMC91111 */
+
+/*
+ * Flash settings
+ */
+
+#define CFG_FLASH_CFI		/* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver */
+#define CFG_FLASH_CFI_AMD_RESET
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_FLASH_BASE		0x20000000
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	135	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR		0x20020000
+#define	CFG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
+/* JFFS Partition offset set  */
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	1
+/* 512k reserved for u-boot */
+#define CFG_JFFS2_FIRST_SECTOR	8
+
+/*
+ * SDRAM settings & memory map
+ */
+
+#define CONFIG_MEM_SIZE			64	/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH		9	/* 8, 9, 10, 11    */
+#define CONFIG_MEM_MT48LC16M16A2TG_75	1
+
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 * 1024)
+
+#define CFG_MEMTEST_START	0x0	/* memtest works on */
+#define CFG_MEMTEST_END		( (CONFIG_MEM_SIZE - 1) * 1024*1024)	/* 1 ... 63 MB in DRAM */
+
+#define	CONFIG_LOADADDR		0x01000000	/* default load address */
+#define CFG_LOAD_ADDR		CONFIG_LOADADDR
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
+#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
+
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+
+#define CFG_GBL_DATA_SIZE	0x4000
+#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+
+#if ( CONFIG_CLKIN_HALF == 0 )
+#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#else
+#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#endif
+
+#if (CONFIG_PLL_BYPASS == 0)
+#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#else
+#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
+#endif
+
+/*
+ * Command settings
+ */
+
+#define CFG_AUTOLOAD	"no"	/* rarpb, bootp, dhcp commands will	*/
+				/* only perform a configuration		*/
+				/* lookup from the BOOTP/DHCP server	*/
+				/* but not try to load any image	*/
+				/* using TFTP				*/
+#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, */
+					/* currently its disabled */
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw console=ttyBF0,57600"
+
+#if (CONFIG_DRIVER_SMC91111)
+#define CONFIG_COMMANDS1	(CONFIG_CMD_DFL	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_ELF	| \
+				 CFG_CMD_CACHE	| \
+				 CFG_CMD_JFFS2	| \
+				 CFG_CMD_DHCP)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" 		\
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):"	\
+		"$(rootpath) console=ttyBF0,57600\0"						\
+	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):"	\
+		"$(gatewayip):$(netmask):$(hostname):eth0:off\0"	\
+	"ramboot=tftpboot $(loadaddr) linux; "		\
+		"run ramargs; run addip; bootelf\0"			\
+	"nfsboot=tftpboot $(loadaddr) linux; "		\
+		"run nfsargs; run addip; bootelf\0"			\
+	"update=tftpboot $(loadaddr) u-boot.bin; "	\
+		"protect off 0x20000000 0x2003FFFF; "			\
+		"erase 0x20000000 0x2003FFFF; "				\
+		"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
+	""
+#else
+#define CONFIG_COMMANDS1	(CONFIG_CMD_DFL	| \
+				 CFG_CMD_ELF	| \
+				 CFG_CMD_CACHE	| \
+				 CFG_CMD_JFFS2)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0"		\
+	"flashboot=bootm 0x20100000\0"					\
+	""
+#endif
+
+#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Console settings
+ */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_PROMPT		"ezkit> "	/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size */
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#endif
+#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_LOADS_ECHO	1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_HZ			1000		/* decrementer freq: 10 ms ticks */
+#define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
+
+/*
+ * FLASH organization and environment definitions
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define AMGCTLVAL		0x3F
+#define AMBCTL0VAL		0x7BB07BB0
+#define AMBCTL1VAL		0xFFC27BB0
+
+#ifdef CONFIG_VDSP
+#define ET_EXEC_VDSP		0x8
+#define SHT_STRTAB_VDSP		0x1
+#define ELFSHDRSIZE_VDSP	0x2C
+#define VDSP_ENTRY_ADDR		0xFFA00000
+#endif
+
+#endif				/* __CONFIG_EZKIT561_H__ */
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index a66cdc3..10c4814 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -106,6 +106,7 @@
 	"bootfile=/tftpboot/bubinga/uImage\0"				\
 	"kernel_addr=fff80000\0"					\
 	"ramdisk_addr=fff90000\0"					\
+	"initrd_high=30000000\0"					\
 	"load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0"		\
 	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
 		"cp.b 100000 fffc0000 40000;"			        \
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index d8882ea..a42319b 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -133,8 +133,9 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
-#define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS {0x53,0x52}	/* SPD i2c spd addresses	*/
+#define CONFIG_PROG_SDRAM_TLB	1	/* setup SDRAM TLB's dynamically*/
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -177,6 +178,7 @@
 	"bootfile=/tftpboot/ebony/uImage\0"				\
 	"kernel_addr=ff800000\0"					\
 	"ramdisk_addr=ff810000\0"					\
+	"initrd_high=30000000\0"					\
 	"load=tftp 100000 /tftpboot/ebony/u-boot.bin\0"		        \
 	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
 		"cp.b 100000 fffc0000 40000;"			        \
diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h
deleted file mode 100644
index 5eda673..0000000
--- a/include/configs/ezkit533.h
+++ /dev/null
@@ -1,188 +0,0 @@
-#ifndef __CONFIG_EZKIT533_H__
-#define __CONFIG_EZKIT533_H__
-
-#define CFG_LONGHELP		1
-#define CONFIG_BAUDRATE		57600
-#define CONFIG_STAMP		1
-#define CONFIG_BOOTDELAY	5
-
-#define CONFIG_DRIVER_SMC91111	1
-#define CONFIG_SMC91111_BASE	0x20310300
-#if 0
-#define CONFIG_MII
-#define CFG_DISCOVER_PHY
-#endif
-
-#define CONFIG_RTC_BF533	1
-#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
-
-/* CONFIG_CLKIN_HZ is any value in Hz				 */
-#define CONFIG_CLKIN_HZ		 27000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	 */
-/*						    1=CLKIN/2	 */
-#define CONFIG_CLKIN_HALF		0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	 */
-/*						 1=bypass PLL	 */
-#define CONFIG_PLL_BYPASS		0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	 */
-/* Values can range from 1-64					 */
-#define CONFIG_VCO_MULT			22
-/* CONFIG_CCLK_DIV controls what the core clock divider is	 */
-/* Values can be 1, 2, 4, or 8 ONLY				 */
-#define CONFIG_CCLK_DIV			1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15					 */
-#define CONFIG_SCLK_DIV			5
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
-#endif
-
-#define CONFIG_MEM_SIZE			32	       /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH		 9	       /* 8, 9, 10, 11	  */
-#define CONFIG_MEM_MT48LC16M16A2TG_75	 1
-
-#define CONFIG_LOADS_ECHO	1
-
-
-#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | \
-					 CFG_CMD_PING	| \
-					 CFG_CMD_ELF	| \
-					 CFG_CMD_I2C	| \
-					 CFG_CMD_JFFS2	| \
-					 CFG_CMD_DATE)
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off"
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_PROMPT		"ezkit> "	/* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x01F00000	/* 1 ... 31 MB in DRAM */
-#define CFG_LOAD_ADDR		0x01000000	/* default load address */
-#define CFG_HZ			1000	/* decrementer freq: 10 ms ticks */
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_MAX_RAM_SIZE	0x02000000
-#define CFG_FLASH_BASE		0x20000000
-
-#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE	(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_SIZE	0x4000
-#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
-
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-#define CFG_FLASH0_BASE		0x20000000
-#define CFG_FLASH1_BASE		0x20200000
-#define CFG_FLASH2_BASE		0x20280000
-#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT	40	/* max number of sectors on one chip */
-
-#define CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_ADDR		0x20020000
-#define CFG_ENV_SECT_SIZE	0x10000 /* Total Size of Environment Sector */
-
-/* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS  1
-/* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR		       11
-
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-
-#define POLL_MODE		1
-#define FLASH_TOT_SECT		40
-#define FLASH_SIZE		0x220000
-#define CFG_FLASH_SIZE		0x220000
-
-/*
- * Initialize PSD4256 registers for using I2C
- */
-#define CONFIG_MISC_INIT_R
-
-/*
- * I2C settings
- * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
- */
-#define CONFIG_SOFT_I2C			1	/* I2C bit-banged		*/
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PF_SCL				PF0
-#define PF_SDA				PF1
-
-#define I2C_INIT			(*pFIO_DIR |=  PF_SCL); asm("ssync;")
-#define I2C_ACTIVE			(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE			(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ			((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit)			if(bit) { \
-							*pFIO_FLAG_S = PF_SDA; \
-							asm("ssync;"); \
-						} \
-					else	{ \
-							*pFIO_FLAG_C = PF_SDA; \
-							asm("ssync;"); \
-						}
-#define I2C_SCL(bit)			if(bit) { \
-							*pFIO_FLAG_S = PF_SCL; \
-							asm("ssync;"); \
-						} \
-					else	{ \
-							*pFIO_FLAG_C = PF_SCL; \
-							asm("ssync;"); \
-						}
-#define I2C_DELAY			udelay(5)	/* 1/4 I2C clock duration */
-
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xFE
-
-
-#define __ADSPLPBLACKFIN__	1
-#define __ADSPBF533__		1
-
-/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL |	\
-				~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL		(B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN |	\
-				B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
-*/
-#define AMGCTLVAL		0xFF
-#define AMBCTL0VAL		0x7BB07BB0
-#define AMBCTL1VAL		0xFFC27BB0
-
-#define CONFIG_VDSP		1
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP		0x8
-#define SHT_STRTAB_VDSP		0x1
-#define ELFSHDRSIZE_VDSP	0x2C
-#define VDSP_ENTRY_ADDR		0xFFA00000
-#endif
-
-#endif
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
index cfaf153..095b5f6 100644
--- a/include/configs/hmi1001.h
+++ b/include/configs/hmi1001.h
@@ -210,6 +210,7 @@
  */
 #define CONFIG_MPC5xxx_FEC	1
 #define CONFIG_PHY_ADDR		0x00
+#define CONFIG_MII		1		/* MII PHY management		*/
 
 /*
  * GPIO configuration
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
new file mode 100644
index 0000000..b1dbe2c
--- /dev/null
+++ b/include/configs/idmr.h
@@ -0,0 +1,213 @@
+/*
+ * Configuration settings for the iDMR board
+ *
+ * Based on MC5272C3, r5200  and M5271EVB board configs
+ * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IDMR_H
+#define _IDMR_H
+
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_MCF52x2		/* define processor family */
+#define CONFIG_M5271		/* define processor type */
+#define CONFIG_IDMR		/* define board type */
+
+#undef CONFIG_WATCHDOG		/* disable watchdog */
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BAUDRATE		19200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_ETHADDR		00:06:3b:01:41:55
+#define CONFIG_ETHPRIME
+#define CONFIG_IPADDR		192.168.30.1
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_ROOTPATH
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.0.0
+#define CONFIG_HOSTNAME		idmr
+#define CONFIG_BOOTFILE		/tftpboot/idmr/uImage
+#define CONFIG_PREBOOT		"echo;echo Type \"run flash_nfs\" to mount root " \
+				"filesystem over NFS; echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
+		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
+	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
+	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
+		"$(ramdisk_addr)\0"					\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ethact=FEC ETHERNET\0"						\
+	"update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; "	\
+		"cp.b 200000 ff800000 $(filesize);"			\
+		"prot on ff800000 ff81ffff\0"				\
+	"load=tftp 200000 $(u-boot)\0"					\
+	"u-boot=/tftpboot/idmr/u-boot.bin\0"				\
+	""
+
+/*
+ * Commands' definition
+ */
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL		| \
+					CFG_CMD_PING		| \
+					CFG_CMD_JFFS2		| \
+					CFG_CMD_NET)		& \
+					~(CFG_CMD_LOADS		| \
+						CFG_CMD_LOADB))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*
+ * Configuration for environment, which occupies third sector in flash.
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_ADDR		0xff820000
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CFG_ENV_SIZE		0x2000
+#define CFG_ENV_IS_IN_FLASH
+#else /* CONFIG_MONITOR_IS_IN_RAM */
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH
+#endif /* !CONFIG_MONITOR_IS_IN_RAM */
+
+#define CFG_PROMPT		"=> "
+#define CFG_LONGHELP				/* undef to save memory */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
+#else /* !(CONFIG_COMMANDS & CFG_CMD_KGDB) */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#endif /* (CONFIG_COMMANDS & CFG_CMD_KGDB) */
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR		0x00100000
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+#define CFG_HZ			(50000000 / 64)
+#define CFG_CLK			100000000
+
+#define CFG_MBAR		0x40000000	/* Register Base Addrs */
+
+/*
+ * Ethernet
+ */
+#define FEC_ENET
+#define CONFIG_NET_RETRY_COUNT	5
+#define CFG_ENET_BD_BASE	0x480000
+#define CFG_DISCOVER_PHY	1
+#define CONFIG_MII		1
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x20000000
+#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CFG_FLASH_BASE		0xff800000
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_MONITOR_BASE	0x20000
+#else /* !CONFIG_MONITOR_IS_IN_RAM */
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#endif /* CONFIG_MONITOR_IS_IN_RAM */
+
+#define CFG_MONITOR_LEN		0x20000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	(64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/* FLASH organization */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT	1000
+
+#define CFG_FLASH_SIZE		0x800000
+/*
+ * #define CFG_FLASH_USE_BUFFER_WRITE	1
+ */
+
+/* Cache Configuration */
+#define CFG_CACHELINE_SIZE	16
+
+/* Port configuration */
+#define CFG_FECI2C		0xF0
+
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=idmr-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=idmr-0:128k(u-boot),"	\
+						"64k(env),"	\
+						"640k(kernel),"	\
+						"2m(rootfs),"	\
+						"-(user)";
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#error MII commands don't work on iDMR board and sholud not be enabled.
+#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+#endif /* _IDMR_H */
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
new file mode 100644
index 0000000..5b97526
--- /dev/null
+++ b/include/configs/jupiter.h
@@ -0,0 +1,291 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* especially an MPC5200 */
+#define CONFIG_JUPITER		1	/* ... on Jupiter board */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_BOARD_EARLY_INIT_R	1
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+/*#define CONFIG_PCI		*/
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+#define ADD_PCI_CMD 		CFG_CMD_PCI
+#endif
+
+#define CFG_XLB_PIPELINING	1
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MII		1
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"addcons=setenv bootargs ${bootargs} console=${contyp},"	\
+		"${baudrate}\0"						\
+	"contyp=ttyS0\0"						\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=/tftpboot/jupiter/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   	/* define for 133MHz speed */
+
+#if 0
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+#endif
+
+#if 0
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xFF000000
+#define CFG_FLASH_SIZE		0x01000000
+
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_ENV_ADDR		(TEXT_BASE + 0x40000) /* third sector */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CFG_UPDATE_FLASH_SIZE	1
+#define CFG_FLASH_USE_BUFFER_WRITE	1
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x20000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OVERWRITE	1
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x10000004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CFG_ALT_MEMTEST		1
+
+#define CFG_LOAD_ADDR		0x200000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00047801
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
new file mode 100644
index 0000000..1606d0d
--- /dev/null
+++ b/include/configs/katmai.h
@@ -0,0 +1,429 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * katmai.h - configuration for AMCC Katmai (440SPe)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_KATMAI			1	/* Board is Katmai	*/
+#define CONFIG_4xx			1	/* ... PPC4xx family	*/
+#define CONFIG_440			1	/* ... PPC440 family	*/
+#define CONFIG_440SPE			1	/* Specifc SPe support	*/
+#undef	CFG_DRAM_TEST				/* Disable-takes long time */
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc */
+
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH	*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
+#define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
+
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
+#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CFG_PCI_TARGBASE	CFG_PCI_MEMBASE
+
+#define CFG_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
+#define CFG_PCIE_MEMSIZE	0x01000000
+#define CFG_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
+
+#define CFG_PCIE0_CFGBASE	0xc0000000
+#define CFG_PCIE0_XCFGBASE	0xc0000400
+#define CFG_PCIE1_CFGBASE	0xc0001000
+#define CFG_PCIE1_XCFGBASE	0xc0001400
+#define CFG_PCIE2_CFGBASE	0xc0002000
+#define CFG_PCIE2_XCFGBASE	0xc0002400
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#define CFG_ACE_BASE		0xe0000000	/* Xilinx ACE controller - Compact Flash */
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM	1
+#define CFG_OCM_DATA_ADDR	CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_SERIAL_MULTI	1
+#undef CONFIG_UART1_CONSOLE
+#undef CFG_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS	{0x51, 0x52}	/* SPD i2c spd addresses*/
+#define CONFIG_DDR_ECC		1	/* with ECC support		*/
+#undef  CONFIG_STRESS
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_SPD_BUS_NUM		0	/* The I2C bus for SPD		*/
+
+#define IIC0_BOOTPROM_ADDR	0x50
+#define IIC0_ALT_BOOTPROM_ADDR	0x54
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0x50)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11	1
+#define CFG_RTC_BUS_NUM		1	/* The I2C bus for RTC		*/
+#define CFG_I2C_RTC_ADDR	0x68
+#define CFG_M41T11_BASE_YEAR	1900	/* play along with linux	*/
+
+/* I2C DTT */
+#define CONFIG_DTT_ADM1021	1	/* ADM1021 temp sensor support	*/
+#define CFG_DTT_BUS_NUM		1	/* The I2C bus for DTT		*/
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the ADM1021, the rest determines index into
+ * CFG_DTT_ADM1021 array below.
+ */
+#define CONFIG_DTT_SENSORS	{ 0, 1 }
+
+/*
+ * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
+ * there will be one entry in this array for each two (dummy) sensors in
+ * CONFIG_DTT_SENSORS.
+ *
+ * For Katmai board:
+ * - only one ADM1021
+ * - i2c addr 0x18
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
+ */
+#define CFG_DTT_ADM1021		{ { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define	CFG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=katmai\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"				\
+	"bootfile=katmai/uImage\0"					\
+	"kernel_addr=fff10000\0"					\
+	"ramdisk_addr=fff20000\0"					\
+	"initrd_high=30000000\0"					\
+	"load=tftp 200000 katmai/u-boot.bin\0"				\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b ${fileaddr} fffc0000 ${filesize};"		\
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	"kozio=bootm ffc60000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_DTT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_EXT2	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_IBM_EMAC4_V4	1	/* 440SPe has this EMAC version	*/
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
+#define CONFIG_PHY_RESET_DELAY	1000
+#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
+#define CFG_EXTBDINFO		1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
+#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS     1		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	1024		    /* sectors per device   */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_ENV_SECT_SIZE	0x20000 /* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
+#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT	1	/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
+#undef	CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
+/* #define CFG_PCI_SUBSYS_ID	CFG_PCI_SUBSYS_DEVICEID */
+
+/*
+ *  NETWORK Support (PCI):
+ */
+/* Support for Intel 82557/82559/82559ER chips. */
+#define CONFIG_EEPRO100
+
+/*-----------------------------------------------------------------------
+ * Xilinx System ACE support
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYSTEMACE	1	/* Enable SystemACE support	*/
+#define CFG_SYSTEMACE_WIDTH	16	/* Data bus width is 16		*/
+#define CFG_SYSTEMACE_BASE	CFG_ACE_BASE
+#define CONFIG_DOS_PARTITION	1
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/* Memory Bank 0 (Flash) initialization					*/
+#define CFG_EBC_PB0AP		(EBC_BXAP_BME_DISABLED      |		\
+				 EBC_BXAP_TWT_ENCODE(7)     |		\
+				 EBC_BXAP_BCE_DISABLE       |		\
+				 EBC_BXAP_BCT_2TRANS        |		\
+				 EBC_BXAP_CSN_ENCODE(0)     |		\
+				 EBC_BXAP_OEN_ENCODE(0)     |		\
+				 EBC_BXAP_WBN_ENCODE(0)     |		\
+				 EBC_BXAP_WBF_ENCODE(0)     |		\
+				 EBC_BXAP_TH_ENCODE(0)      |		\
+				 EBC_BXAP_RE_DISABLED       |		\
+				 EBC_BXAP_SOR_DELAYED       |		\
+				 EBC_BXAP_BEM_WRITEONLY     |		\
+				 EBC_BXAP_PEN_DISABLED)
+#define CFG_EBC_PB0CR		(EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |	\
+				 EBC_BXCR_BS_16MB                    |	\
+				 EBC_BXCR_BU_RW                      |	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (Xilinx System ACE controller) initialization		*/
+#define CFG_EBC_PB1AP		0x7F8FFE80
+#define CFG_EBC_PB1CR		(EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE)  |	\
+				 EBC_BXCR_BS_1MB                    |	\
+				 EBC_BXCR_BU_RW                     |	\
+				 EBC_BXCR_BW_16BIT)
+
+/*-------------------------------------------------------------------------
+ * Initialize EBC CONFIG -
+ * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+ * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+ *-------------------------------------------------------------------------*/
+#define CFG_EBC_CFG		(EBC_CFG_LE_UNLOCK    |	\
+				 EBC_CFG_PTD_ENABLE   |	\
+				 EBC_CFG_RTC_16PERCLK | \
+				 EBC_CFG_ATC_PREVIOUS | \
+				 EBC_CFG_DTC_PREVIOUS | \
+				 EBC_CFG_CTC_PREVIOUS | \
+				 EBC_CFG_OEO_PREVIOUS | \
+				 EBC_CFG_EMC_DEFAULT  |	\
+				 EBC_CFG_PME_DISABLE  |	\
+				 EBC_CFG_PR_16)
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CFG_GPIO_PCIE_PRESENT0	17
+#define CFG_GPIO_PCIE_PRESENT1	21
+#define CFG_GPIO_PCIE_PRESENT2	23
+#define CFG_GPIO_RS232_FORCEOFF	30
+
+#define CFG_PFC0		(GPIO_VAL(CFG_GPIO_PCIE_PRESENT0) | \
+				 GPIO_VAL(CFG_GPIO_PCIE_PRESENT1) | \
+				 GPIO_VAL(CFG_GPIO_PCIE_PRESENT2) | \
+				 GPIO_VAL(CFG_GPIO_RS232_FORCEOFF))
+#define CFG_GPIO_OR		GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
+#define CFG_GPIO_TCR		GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
+#define CFG_GPIO_ODR		0
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/*Initial Memory map for Linux*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs		*/
+#define CFG_CACHELINE_SIZE	32	/* ...				*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h
new file mode 100644
index 0000000..7e51523
--- /dev/null
+++ b/include/configs/lpc2292sodimm.h
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the EP7312 board.
+ *
+ * Modified to work on Armadillo HT1070 ARM720T board
+ * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#undef CONFIG_INIT_CRITICAL		/* undef for developing */
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
+#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
+#define CONFIG_LPC2292
+#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+
+#undef CONFIG_USE_IRQ			/* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_MMC	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_PING)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"LPC2292SODIMM # " /* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x40000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x40000000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x00040000	/* default load address	for armadillo: kernel img is here*/
+
+#define CFG_SYS_CLK_FREQ        58982400        /* Hz */
+#define	CFG_HZ			2048		/* decrementer freq in Hz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x81000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB SDRAM */
+
+#define PHYS_FLASH_1		0x80000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x00200000 /* 2 MB */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	1024	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(0x0 + 0x3C000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x2000 /* Total Size of Environment Sector	*/
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_MMC 1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 0350e91..9c8769b 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -37,8 +37,9 @@
 #define CONFIG_440		1
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
 
-#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
@@ -132,10 +133,9 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#undef  CONFIG_SPD_EEPROM		/* SPD EEPROM init doesn't support DDR2 */
-#define SPD_EEPROM_ADDRESS {0x52,0x53}	/* I2C SPD addresses */
-#define IIC0_DIMM0_ADDR         0x52
-#define IIC0_DIMM1_ADDR         0x53
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS	{0x53, 0x52}	/* SPD i2c spd addresses*/
+#undef CONFIG_DDR_ECC			/* no ECC support for now	*/
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -178,6 +178,7 @@
 	"bootfile=/tftpboot/luan/uImage\0"				\
 	"kernel_addr=fc000000\0"					\
 	"ramdisk_addr=fc100000\0"					\
+	"initrd_high=30000000\0"					\
 	"load=tftp 100000 /tftpboot/luan/u-boot.bin\0"			\
 	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
 		"cp.b 100000 fffc0000 40000;"			        \
@@ -205,11 +206,6 @@
 #define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 #define CONFIG_NET_MULTI		/* needed for NetConsole	*/
 
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
 #ifdef DEBUG
 #define CONFIG_PANIC_HANG
 #else
@@ -218,9 +214,7 @@
 
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL		|	\
 				CFG_CMD_ASKENV		|	\
-			        CFG_CMD_CACHE		|	\
 				CFG_CMD_DHCP		|	\
-				CFG_CMD_DIAG		|	\
 				CFG_CMD_ELF		|	\
 				CFG_CMD_EEPROM		|	\
 				CFG_CMD_I2C		|	\
@@ -231,7 +225,6 @@
 				CFG_CMD_PCI		|	\
 				CFG_CMD_PING		|	\
 				CFG_CMD_REGINFO		|	\
-				CFG_CMD_SETGETDCR	|	\
 				CFG_CMD_SDRAM		|	\
 				0)
 
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
index 0c935bf..621a81c 100644
--- a/include/configs/mcc200.h
+++ b/include/configs/mcc200.h
@@ -94,6 +94,8 @@
 #define CONFIG_USB_OHCI
 #define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
 #define CONFIG_USB_STORAGE
+/* automatic software updates (see board/mcc200/auto_update.c) */
+#define CONFIG_AUTO_UPDATE 1
 
 /*
  * Supported commands
@@ -173,7 +175,7 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
 
 #define CFG_I2C_SPEED		100000 /* 100 kHz */
 #define CFG_I2C_SLAVE		0x7F
@@ -263,6 +265,7 @@
  */
 #if !defined(CONFIG_PRS200)
 #define CONFIG_LCD		1
+#define CONFIG_PROGRESSBAR 1
 #endif
 
 #if defined(CONFIG_LCD)
diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
new file mode 100644
index 0000000..0c10294
--- /dev/null
+++ b/include/configs/mecp5200.h
@@ -0,0 +1,345 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*************************************************************************
+ * (c) 2005 esd gmbh Hannover
+ *
+ *
+ * from IceCube.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+ *************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board */
+#define CONFIG_MECP5200		1	/* ... on MECP5200  board */
+#define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM      */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#if 0 /* test-only */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#else
+#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
+#endif
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
+
+#define CONFIG_MII
+#if 0 /* test-only !!! */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+#endif
+
+#else	/* MPC5100 */
+
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 0
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD		0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_EXT2	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_IDE	| \
+				 CFG_CMD_BSP	| \
+				 CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+#endif
+#if (TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT08	1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to CBX-CPU5200 (mecp5200);" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=eth0\0" \
+	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+	"net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
+	"vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
+	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
+	"loadaddr=01000000\0" \
+	"serverip=192.168.2.99\0" \
+	"gatewayip=10.0.0.79\0" \
+	"user=mu\0" \
+	"target=mecp5200.esd\0" \
+	"script=mecp5200.bat\0" \
+	"image=/tftpboot/vxWorks_mecp5200\0" \
+	"ipaddr=10.0.13.196\0" \
+	"netmask=255.255.0.0\0" \
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		86000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CFG_I2C_MULTI_EEPROMS		1
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xFFC00000
+#define CFG_FLASH_SIZE		0x00400000
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x003E0000)
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	512
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+/*
+ * Environment settings
+ */
+#if 1 /* test-only */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars*/
+				   /* total size of a CAT24WC32 is 8192 bytes */
+#define CONFIG_ENV_OVERWRITE	1
+#endif
+
+#define CFG_FLASH_CFI_DRIVER	1	   /* Flash is CFI conformant		*/
+#define CFG_FLASH_CFI		1	   /* Flash is CFI conformant		*/
+#define CFG_FLASH_PROTECTION	1	   /* use hardware protection		*/
+#if 0
+#define CFG_FLASH_USE_BUFFER_WRITE 1       /* use buffered writes (20x faster)  */
+#endif
+#define CFG_FLASH_INCREMENT	0x00400000 /* size of  flash bank		*/
+#define CFG_FLASH_BANKS_LIST  { CFG_FLASH_BASE }
+#define CFG_FLASH_EMPTY_INFO	1	   /* show if bank is empty		*/
+
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_UDP_CHECKSUM     1
+
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x01052444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00085d00
+
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS1_START		0xfd000000
+#define CFG_CS1_SIZE		0x00010000
+#define CFG_CS1_CFG		0x10101410
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers		*/
+#define CFG_ATA_STRIDE		4
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
new file mode 100644
index 0000000..5328e8d
--- /dev/null
+++ b/include/configs/motionpro.h
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Based on PRO Motion board config file by Andy Joseph, andy@promessdev.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * High Level Configuration Options
+ */
+
+
+/* CPU and board */
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
+#define CONFIG_MOTIONPRO	1	/* ... on Promess Motion-PRO board */
+
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_PING)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_NETCONSOLE	1	/* network console */
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_PHY_ADDR		0x2
+#define CONFIG_PHY_TYPE		0x79c874
+
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR	"\x1b\x1b"
+#define DEBUG_BOOTKEYS		0
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#undef CONFIG_BOOTARGS
+#define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, "		\
+					"press \"<Esc><Esc>\" to stop\n"
+
+#define CONFIG_ETHADDR		00:50:C2:40:10:00
+#define CONFIG_OVERWRITE_ETHADDR_ONCE	1
+#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
+
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"sdram_test=0\0"						\
+	"netdev=eth0\0"							\
+	"hostname=motionpro\0"						\
+	"netmask=255.255.0.0\0"						\
+	"ipaddr=192.168.160.22\0"					\
+	"serverip=192.168.1.1\0"					\
+	"gatewayip=192.168.1.1\0"					\
+	"kernel_addr=200000\0"						\
+	"u-boot_addr=100000\0"						\
+	"kernel_sector=20\0"						\
+	"kernel_size=1000\0"						\
+	"console=ttyS0,115200\0"					\
+	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
+	"bootfile=/tftpboot/motionpro/uImage\0"				\
+	"u-boot=/tftpboot/motionpro/u-boot.bin\0"			\
+	"load=tftp $(u-boot_addr) $(u-boot)\0"				\
+	"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; "	\
+		"cp.b $(u-boot_addr) fff00000 $(filesize);"		\
+		"prot on fff00000 fff3ffff\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) console=$(console) "		\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
+		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
+	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
+	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
+		"$(ramdisk_addr)\0"					\
+	"net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; "	\
+		"bootm $(kernel_addr)\0"				\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"fstype=ext3\0"							\
+	"fatargs=setenv bootargs init=/linuxrc rw\0"			\
+	""
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+
+/*
+ * do board-specific init
+ */
+#define CONFIG_BOARD_EARLY_INIT_R	1
+
+
+/*
+ * Low level configuration
+ */
+
+
+/*
+ * Clock configuration: SYS_XTALIN = 25MHz
+ */
+#define CFG_MPC5XXX_CLKIN	25000000
+
+
+/*
+ * Memory map
+ */
+/*
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000.
+ * Setting MBAR to otherwise will cause system hang when using SmartDMA such
+ * as network commands.
+ */
+#define CFG_MBAR		0xf0000000
+#define CFG_SDRAM_BASE		0x00000000
+
+/*
+ * If building for running out of SDRAM, then MBAR has been set up beforehand
+ * (e.g., by the BDI). Otherwise we must specify the default boot-up value of
+ * MBAR, as given in the doccumentation.
+ */
+#if TEXT_BASE == 0x00100000
+#define CFG_DEFAULT_MBAR	0xf0000000
+#else /* TEXT_BASE != 0x00100000 */
+#define CFG_DEFAULT_MBAR	0x80000000
+#define CFG_LOWBOOT		1
+#endif /* TEXT_BASE == 0x00100000 */
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* 128 kB for malloc() */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
+
+
+/*
+ * Chip selects configuration
+ */
+/* Boot Chipselect */
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x03035D00
+
+/* Flash memory addressing */
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CFG_CS0_CFG		CFG_BOOTCS_CFG
+
+/* Dual Port SRAM -- Kollmorgen Drive memory addressing */
+#define CFG_CS1_START		0x50000000
+#define CFG_CS1_SIZE		0x10000
+#define CFG_CS1_CFG		0x05055800
+
+/* Local register access */
+#define CFG_CS2_START		0x50010000
+#define CFG_CS2_SIZE		0x10000
+#define CFG_CS2_CFG		0x05055800
+
+/* Anybus CompactCom Module memory addressing */
+#define CFG_CS3_START		0x50020000
+#define CFG_CS3_SIZE		0x10000
+#define CFG_CS3_CFG		0x05055800
+
+/* No burst and dead cycle = 2 for all CSs */
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x22222222
+
+
+/*
+ * SDRAM configuration
+ */
+/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 2, 32 bit data bus */
+#define SDRAM_CONFIG1		0x52222600
+#define SDRAM_CONFIG2		0x88b70000
+#define SDRAM_CONTROL		0x50570000
+#define SDRAM_MODE		0x008d0000
+
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1
+#define CFG_FLASH_BASE		0xff000000
+#define CFG_FLASH_SIZE		0x01000000
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_FLASH_16BIT		/* Flash is 16-bit */
+
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+/* This has to be a multiple of the Flash sector size */
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_ENV_SIZE		0x1000
+#define CFG_ENV_SECT_SIZE	0x10000
+
+
+/*
+ * Pin multiplexing configuration
+ */
+
+/* PSC1: UART1
+ * PSC2: GPIO (default)
+ * PSC3: GPIO (default)
+ * USB: 2xUART4/5
+ * Ethernet: Ethernet 100Mbit with MD
+ * Timer: CAN2/GPIO
+ * PSC6/IRDA: GPIO (default)
+ */
+#define CFG_GPS_PORT_CONFIG	0x1105a004
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x03f00000	/* 1 ... 64 MiB in DRAM */
+
+#define CFG_LOAD_ADDR		0x200000	/* default kernel load addr */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+
+
+/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
+#define CFG_RESET_ADDRESS	0xfff00100
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
index 89e9164..fe4e638 100644
--- a/include/configs/ocotea.h
+++ b/include/configs/ocotea.h
@@ -148,8 +148,9 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM	1	 /* Use SPD EEPROM for setup	 */
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
 #define SPD_EEPROM_ADDRESS {0x53,0x52}	/* SPD i2c spd addresses	*/
+#define CONFIG_PROG_SDRAM_TLB	1	/* setup SDRAM TLB's dynamically*/
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -192,6 +193,7 @@
 	"bootfile=/tftpboot/ocotea/uImage\0"				\
 	"kernel_addr=fff00000\0"					\
 	"ramdisk_addr=fff10000\0"					\
+	"initrd_high=30000000\0"					\
 	"load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0"		\
 	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
 		"cp.b 100000 fffc0000 40000;"			        \
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
new file mode 100644
index 0000000..54462f0
--- /dev/null
+++ b/include/configs/p3mx.h
@@ -0,0 +1,451 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Based on original work by
+ *      Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
+ *
+ * The defines:
+ * CONFIG_P3M750 or
+ * CONFIG_P3M7448
+ * are written into include/config.h by the "make xxx_config" command
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_P3Mx			/* used for both board versions	*/
+
+#if defined (CONFIG_P3M750)
+#define CONFIG_750FX			/* 750GL/GX/FX			*/
+#define CFG_BOARD_NAME		"P3M750"
+#define CFG_BUS_HZ		100000000
+#define CFG_BUS_CLK		CFG_BUS_HZ
+#define CFG_TCLK		100000000
+#elif defined (CONFIG_P3M7448)
+#define CONFIG_74xx
+#define CFG_BOARD_NAME		"P3M7448"
+#define CFG_BUS_HZ		133333333
+#define CFG_BUS_CLK		CFG_BUS_HZ
+#define CFG_TCLK		133333333
+#endif
+#define CFG_GT_DUAL_CPU			/* also for JTAG even with one cpu */
+
+/* which initialization functions to call for this board */
+#define CFG_BOARD_ASM_INIT	1
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+#define CONFIG_BOARD_EARLY_INIT_R 1     /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R      1	/* Call misc_init_r()		*/
+#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE		0x00000000
+#ifdef CONFIG_P3M750
+#define CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte	*/
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#if defined (CONFIG_P3M750)
+#define CFG_FLASH_BASE		0xff800000	/* start of flash banks	*/
+#define CFG_BOOT_SIZE		_8M		/* boot flash		*/
+#elif defined (CONFIG_P3M7448)
+#define CFG_FLASH_BASE		0xff000000	/* start of flash banks	*/
+#define CFG_BOOT_SIZE		_16M		/* boot flash		*/
+#endif
+#define CFG_BOOT_SPACE		CFG_FLASH_BASE	/* BOOT_CS0 flash 0    */
+#define CFG_MONITOR_BASE	0xfff00000
+#define CFG_RESET_ADDRESS	0xfff00100
+#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define CFG_MISC_REGION_BASE	0xf0000000
+
+#define CFG_DFL_GT_REGS		0xf1000000	/* boot time GT_REGS */
+#define CFG_GT_REGS		0xf1000000	/* GT Registers are mapped here */
+#define CFG_INT_SRAM_BASE	0x42000000	/* GT offers 256k internal SRAM */
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+ /*
+ * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+*/
+#undef	CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR	0x42000000
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_MPSC			/* MV64460 Serial		*/
+#define CONFIG_MPSC_PORT	0
+#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+/* Change the default ethernet port, use this define (options: 0, 1, 2) */
+#define CFG_ETH_PORT		ETH_0
+#define CONFIG_NET_MULTI
+#define MV_ETH_DEVS		2
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI			/* The flash is CFI compatible		*/
+#define CFG_FLASH_CFI_DRIVER		/* Use common CFI driver		*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#if defined (CONFIG_P3M750)
+#define CFG_ENV_SECT_SIZE	0x20000 	/* one sector (1 device)*/
+#elif defined (CONFIG_P3M7448)
+#define CFG_ENV_SECT_SIZE	0x40000 	/* two sectors (2 devices parallel */
+#endif
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_MV64460_ECC
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CFG_I2C_SPEED		100000		/* I2C speed default	*/
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11	1
+#define CFG_I2C_RTC_ADDR	0x68
+#define CFG_M41T11_BASE_YEAR	1900	/* play along with linux	*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#undef CONFIG_PCI			/* include pci support		*/
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/
+#endif /* CONFIG_PCI */
+
+/* PCI MEMORY MAP section */
+#define CFG_PCI0_MEM_BASE	0x80000000
+#define CFG_PCI0_MEM_SIZE	_128M
+#define CFG_PCI1_MEM_BASE	0x88000000
+#define CFG_PCI1_MEM_SIZE	_128M
+
+#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CFG_PCI0_IO_BASE	0xfa000000
+#define CFG_PCI0_IO_SIZE	_16M
+#define CFG_PCI1_IO_BASE	0xfb000000
+#define CFG_PCI1_IO_SIZE	_16M
+
+#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
+#define CFG_PCI0_IO_SPACE_PCI	0x00000000
+#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
+#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+
+#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
+#define CFG_PCI_IDSEL 0x30
+
+#undef	CONFIG_BOOTARGS
+#define	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"u-boot=p3mx/u-boot/u-boot.bin\0"				\
+	"load=tftp 100000 ${u-boot}\0"					\
+	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
+		"cp.b 100000 fff00000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	"serverip=11.0.0.152\0"
+
+#if defined (CONFIG_P3M750)
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
+	"hostname=p3m750\0"						\
+	"bootfile=/tftpboot/p3mx/vxWorks.st\0"				\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc180000\0"					\
+	"vxfile=p3m750/vxWorks\0"					\
+	"vxuser=ddg\0"							\
+	"vxpass=ddg\0"							\
+	"vxtarget=target\0"						\
+	"vxflags=0x8\0"							\
+	"vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} "	\
+		"e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} "	\
+		"f=${vxflags}\0"
+#elif defined (CONFIG_P3M7448)
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
+	"hostname=p3m7448\0"
+#endif
+
+#if defined (CONFIG_P3M750)
+#define CONFIG_BOOTCOMMAND	"tftp;run vxargs;bootvx"
+#elif defined (CONFIG_P3M7448)
+#define CONFIG_BOOTCOMMAND	" "
+#endif
+
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_CACHE   | \
+				CFG_CMD_SDRAM)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x08000000	/* default load address */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * Marvell MV64460 config settings
+ *----------------------------------------------------------------------*/
+/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
+#if defined (CONFIG_P3M750)
+#define CFG_BOOT_PAR		0x8FDFF87F	/* 16 bit flash, disable burst*/
+#elif defined (CONFIG_P3M7448)
+#define CFG_BOOT_PAR		0x8FEFFFFF	/* 32 bit flash, burst enabled */
+#endif
+
+/*
+ * MPP[0]	Serial Port 0 TxD	TxD	OUT	Connected to P14 (buffered)
+ * MPP[1]	Serial Port 0 RxD	RxD	IN	Connected to P14 (buffered)
+ * MPP[2]	NC
+ * MPP[3]	Serial Port 1 TxD	TxD	OUT	Connected to P14 (buffered)
+ * MPP[4]	PCI Monarch#		GPIO	IN	Connected to P12
+ * MPP[5]	Serial Port 1 RxD	RxD	IN	Connected to P14 (buffered)
+ * MPP[6]	PMC Carrier Interrupt 0	Int	IN	Connected to P14
+ * MPP[7]	PMC Carrier Interrupt 1	Int	IN	Connected to P14
+ * MPP[8]	Reserved				Do not use
+ * MPP[9]	Reserved				Do not use
+ * MPP[10]	Reserved				Do not use
+ * MPP[11]	Reserved				Do not use
+ * MPP[12]	Phy 0 Interrupt		Int	IN
+ * MPP[13]	Phy 1 Interrupt		Int	IN
+ * MPP[14]	NC
+ * MPP[15]	NC
+ * MPP[16]	PCI Interrupt C		Int	IN	Connected to P11
+ * MPP[17]	PCI Interrupt D		Int	IN	Connected to P11
+ * MPP[18]	Watchdog NMI#		GPIO	IN	Connected to MPP[24]
+ * MPP[19]	Watchdog Expired#	WDE	OUT	Connected to rst logic
+ * MPP[20]	Watchdog Status		WD_STS	IN	Read back of rst by watchdog
+ * MPP[21]	NC
+ * MPP[22]	GP LED Green		GPIO	OUT
+ * MPP[23]	GP LED Red		GPIO	OUT
+ * MPP[24]	Watchdog NMI#		Int	OUT
+ * MPP[25]	NC
+ * MPP[26]	NC
+ * MPP[27]	PCI Interrupt A		Int	IN	Connected to P11
+ * MPP[28]	NC
+ * MPP[29]	PCI Interrupt B		Int	IN	Connected to P11
+ * MPP[30]	Module reset		GPIO	OUT	Board reset
+ * MPP[31]	PCI EReady		GPIO	IN	Connected to P12
+ */
+#define CFG_MPP_CONTROL_0	0x00303022
+#define CFG_MPP_CONTROL_1	0x00000000
+#define CFG_MPP_CONTROL_2	0x00004000
+#define CFG_MPP_CONTROL_3	0x00000004
+#define CFG_GPP_LEVEL_CONTROL	0x280730D0
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* init ram */
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CFG_IBAT2L BATL_NO_ACCESS
+#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U CFG_IBAT3U
+
+#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U CFG_IBAT4U
+
+/* set rest out of range for Linux !!!!!!!!!!! */
+
+/* IBAT5 and DBAT5 */
+#define CFG_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT5U CFG_IBAT5U
+
+/* IBAT6 and DBAT6 */
+#define CFG_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U CFG_IBAT6U
+
+/* IBAT7 and DBAT7 */
+#define CFG_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT7U CFG_IBAT7U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+#define CFG_VXWORKS_MAC_PTR	0x42010000 /* use some memory in SRAM that's not used!!! */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+#define CFG_L2
+
+#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
+#define L2_INIT 0
+#else
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		    */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index ba6b113..06c6652 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * Configuation settings for the PDNB3 board.
@@ -71,12 +71,18 @@
 #define CONFIG_BAUDRATE         115200
 #define CFG_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
 
+#if defined(CONFIG_SCPU)
+#define CMD_NAND_ADD		0
+#else
+#define CMD_NAND_ADD		CFG_CMD_NAND
+#endif
+
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DATE	| \
 				CFG_CMD_NET	| \
 				CFG_CMD_MII	| \
-				CFG_CMD_NAND	| \
+				CMD_NAND_ADD	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_PING)
@@ -176,12 +182,20 @@
 
 #define CFG_FLASH_BASE          0x50000000
 #define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#if defined(CONFIG_SCPU)
+#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 512 kB for Monitor	*/
+#else
 #define CFG_MONITOR_LEN		(504 << 10)	/* Reserve 512 kB for Monitor	*/
+#endif
 
 /*
  * Expansion bus settings
  */
+#if defined(CONFIG_SCPU)
+#define CFG_EXP_CS0		0x94d23C42	/* 8bit, max size		*/
+#else
 #define CFG_EXP_CS0		0x94913C43	/* 8bit, max size		*/
+#endif
 #define CFG_EXP_CS1		0x85000043	/* 8bit, 512bytes		*/
 
 /*
@@ -194,6 +208,12 @@
 /*
  * FLASH and environment organization
  */
+#if defined(CONFIG_SCPU)
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
+#endif
+
 #define FLASH_BASE0_PRELIM	CFG_FLASH_BASE		/* FLASH bank #0	*/
 
 #define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
@@ -217,20 +237,28 @@
 
 #define	CFG_ENV_IS_IN_FLASH	1
 
-#define CFG_ENV_SECT_SIZE	0x1000 	/* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#if defined(CONFIG_SCPU)
+/* no redundant environment on SCPU */
+#define CFG_ENV_SECT_SIZE	0x20000 /* size of one complete sector		*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#else
+#define CFG_ENV_SECT_SIZE	0x1000 	/* size of one complete sector		*/
 #define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif
 
+#if !defined(CONFIG_SCPU)
 /*
  * NAND-FLASH stuff
  */
 #define CFG_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS		1
 #define CFG_NAND_BASE		0x51000000	/* NAND FLASH Base Address	*/
+#endif
 
 /*
  * GPIO settings
@@ -284,9 +312,15 @@
 /*
  * I2C RTC
  */
+#if 0 /* test-only */
+#define CONFIG_RTC_DS1340	1
+#define CFG_I2C_RTC_ADDR	0x68
+#else
+/* M41T11 Serial Access Timekeeper(R) SRAM */
 #define CONFIG_RTC_M41T11	1
 #define CFG_I2C_RTC_ADDR	0x68
 #define CFG_M41T11_BASE_YEAR	1900	/* play along with the linux driver */
+#endif
 
 /*
  * Spartan3 FPGA configuration support
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
new file mode 100644
index 0000000..65aac5c
--- /dev/null
+++ b/include/configs/sbc8349.h
@@ -0,0 +1,734 @@
+/*
+ * WindRiver SBC8349 U-Boot configuration file.
+ * Copyright (c) 2006, 2007 Wind River Systems, Inc.
+ *
+ * Paul Gortmaker <paul.gortmaker@windriver.com>
+ * Based on the MPC8349EMDS config.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * sbc8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC834X		1	/* MPC834X family */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
+#define CONFIG_SBC8349		1	/* WRS SBC8349 board specific */
+
+#undef CONFIG_PCI
+/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ	66000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
+#else
+#define CONFIG_SYS_CLK_FREQ	33000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
+#endif
+#endif
+
+#undef CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
+
+#define CFG_IMMR		0xE0000000
+
+#undef CFG_DRAM_TEST				/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00000000	/* memtest region */
+#define CFG_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+#undef CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+#define CFG_83XX_DDR_USES_CS0		/* WRS; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS	0x52		/* DDR DIMM */
+
+#else
+/*
+ * Manually set up DDR parameters
+ * NB: manual DDR setup untested on sbc834x
+ */
+#define CFG_DDR_SIZE		256		/* MB */
+#define CFG_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CFG_DDR_TIMING_1	0x36332321
+#define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CFG_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CFG_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+#define CFG_DDR_MODE		0x00000023	/* DLL,normal,seq,4/2.5, 8 burst len */
+#else
+/* the default burst length is 4 - for 64-bit data path */
+#define CFG_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0x10000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFF800000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		8		/* flash size in MB */
+/* #define CFG_FLASH_USE_BUFFER_WRITE */
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
+				(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
+				BR_V)			/* valid */
+
+#define CFG_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
+#define CFG_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MID_FLASH_JUMP	0x7F000000
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xFD000000		/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000			/* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE	0x100			/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)		/* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR	0x00000000
+
+#undef CFG_LB_SDRAM	/* if board has SDRAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM		0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+#define CFG_LBLAWBAR2_PRELIM	0xF0000000
+#define CFG_LBLAWAR2_PRELIM	0x80000019 /* 64M */
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *                 XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
+ */
+
+#define CFG_OR2_PRELIM	0xFC006901
+
+#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32 */
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR8	(5 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC3	(3 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
+				| CFG_LBC_LSDMR_BSMA1516	\
+				| CFG_LBC_LSDMR_RFCR8		\
+				| CFG_LBC_LSDMR_PRETOACT6	\
+				| CFG_LBC_LSDMR_ACTTORW3	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC3		\
+				| CFG_LBC_LSDMR_CL3		\
+				)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_NORMAL)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2        (CFG_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8349@0"
+#define OF_SOC			"soc8349@e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc8349@e0000000/serial@4500"
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#define CFG_I2C1_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+#define CFG_I2C_OFFSET		CFG_I2C2_OFFSET
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_MMIO_BASE	0x90000000
+#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xE2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CFG_PCI2_MEM_BASE	0xA0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI2_MMIO_BASE	0xB0000000
+#define CFG_PCI2_MMIO_PHYS	CFG_PCI2_MMIO_BASE
+#define CFG_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xE2100000
+#define CFG_PCI2_IO_SIZE	0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_64BIT
+#define PCI_ONE_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0xFIXME
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+#define CONFIG_MPC83XX_TSEC1	1
+#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC83XX_TSEC2	1
+#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define CONFIG_PHY_BCM5421S	1
+#define TSEC1_PHY_ADDR		0x19
+#define TSEC2_PHY_ADDR		0x1a
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+#else
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C		\
+				)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C		\
+				| CFG_CMD_MII		\
+				)
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory */
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#if 1 /*528/264*/
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*396/132*/
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_3X1)
+#elif 0 /*264/132*/
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*132/132*/
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_1X1)
+#elif 0 /*264/264 */
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_1X1)
+#endif
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#endif
+
+/* System IO Config */
+#define CFG_SICRH SICRH_TSOBI1
+#define CFG_SICRL SICRL_LDP_A
+
+#define CFG_HID0_INIT	0x000000000
+#define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+
+/* #define CFG_HID0_FINAL		(\
+	HID0_ENABLE_INSTRUCTION_CACHE |\
+	HID0_ENABLE_M_BIT |\
+	HID0_ENABLE_ADDRESS_BROADCAST ) */
+
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT1L	(0)
+#define CFG_IBAT1U	(0)
+#define CFG_IBAT2L	(0)
+#define CFG_IBAT2U	(0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CFG_IBAT3L	(CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT3U	(CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L	(CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4U	(CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT3L	(0)
+#define CFG_IBAT3U	(0)
+#define CFG_IBAT4L	(0)
+#define CFG_IBAT4U	(0)
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
+#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR		00:a0:1e:a0:13:8d
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:a0:1e:a0:13:8e
+#endif
+
+#define CONFIG_IPADDR		192.168.1.234
+
+#define CONFIG_HOSTNAME		SBC8349
+#define CONFIG_ROOTPATH		/tftpboot/rootfs
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	 115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=sbc8349\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"		\
+	"update=protect off fff00000 fff3ffff; "			\
+		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0"	\
+	"upd=run load;run update\0"					\
+	"fdtaddr=400000\0"						\
+	"fdtfile=sbc8349.dtb\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
new file mode 100644
index 0000000..8298084
--- /dev/null
+++ b/include/configs/sc3.h
@@ -0,0 +1,588 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
+ *
+ * From:
+ * (C) Copyright 2003
+ * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef USE_VGA_GRAPHICS
+
+/* Memory Map
+ * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
+ * 0x74000000 .... 0x740FFFFF -> CS#6
+ * 0x74100000 .... 0x741FFFFF -> CS#7
+ * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
+ * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
+ * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
+ * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
+ * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
+ * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
+ * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
+ * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
+ *
+ * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
+ * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
+ * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
+ * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
+ * 0xEED00000 .... 0xEED00003 -> PCI-Bus
+ * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
+ * 0xEF40003F .... 0xEF5FFFFF -> reserved
+ * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
+ * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
+ * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
+ * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
+ * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
+ * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
+ */
+
+#define CONFIG_SOLIDCARD3	1
+#define CONFIG_4xx	1
+#define CONFIG_405GP	1
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+/*
+ * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
+ * If undefined, IDE access uses a seperat emulation with higher access speed.
+ * Consider to inform your Linux IDE driver about the different addresses!
+ * IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes
+ * the CFG_CMD_IDE macro!
+ */
+#define IDE_USES_ISA_EMULATION
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_SERIAL_MULTI
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+/*
+ * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input
+ * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature
+ */
+#if CONFIG_SERIAL_SOFTWARE_FIFO
+ #define CONFIG_POWER_DOWN
+#endif
+
+/*
+ * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
+ */
+#define CONFIG_SYS_CLK_FREQ	33333333
+
+/*
+ * define CONFIG_BAUDRATE to the baudrate value you want to use as default
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3 /* autoboot after 3 seconds	      */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nand_args=setenv bootargs root=/dev/mtdblock5 rw"		\
+		"rootfstype=jffs2\0"					\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate}\0"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0"	\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/sc3/uImage\0"				\
+	"u-boot=/tftpboot/sc3/u-boot.bin\0"				\
+	"setup=tftp 200000 /tftpboot/sc3/setup.img;autoscr 200000\0"	\
+	"kernel_addr=FFE08000\0"					\
+	""
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_SILENT_CONSOLE	1	/* enable silent startup */
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#if 1	/* feel free to disable for development */
+#define CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
+#define CONFIG_AUTOBOOT_PROMPT		"\nSC3 - booting... stop with S\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"S"	/* 1st "password"	*/
+#endif
+
+/*
+ * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
+ * the CONFIG_BOOTDELAY delay to boot your machine
+ */
+#define CONFIG_BOOTCOMMAND	"bootp;dcache on;bootm"
+
+/*
+ * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
+ * set different values at the u-boot prompt
+ */
+#ifdef USE_VGA_GRAPHICS
+ #define CONFIG_BOOTARGS	"root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
+#else
+ #define CONFIG_BOOTARGS	"console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
+#endif
+/*
+ * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
+ * This reserves memory bank #4 for this purpose
+ */
+#undef CONFIG_ISP1161_PRESENT
+
+#undef CONFIG_LOADS_ECHO   /* no echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_NET_MULTI
+/* #define CONFIG_EEPRO100_SROM_WRITE */
+/* #define CONFIG_SHOW_MAC */
+#define CONFIG_EEPRO100
+#define CONFIG_MII 1			/* add 405GP MII PHY management		*/
+#define CONFIG_PHY_ADDR 1	/* the connected Phy defaults to address 1 */
+
+#define CONFIG_COMMANDS	  \
+	   (CONFIG_CMD_DFL	| \
+			CFG_CMD_AUTOSCRIPT	| \
+			CFG_CMD_PCI		| \
+			CFG_CMD_IRQ		| \
+			CFG_CMD_NET		| \
+			CFG_CMD_MII		| \
+			CFG_CMD_PING		| \
+			CFG_CMD_NAND		| \
+			CFG_CMD_JFFS2		| \
+			CFG_CMD_I2C		| \
+			CFG_CMD_IDE		| \
+			CFG_CMD_DATE		| \
+			CFG_CMD_DHCP		| \
+			CFG_CMD_CACHE		| \
+			CFG_CMD_ELF	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	1		/* undef to save memory		*/
+#define CFG_PROMPT	"SC3> "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ *
+ * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
+ * (see 405GP datasheet for descritpion)
+ */
+#undef	CFG_EXT_SERIAL_CLOCK		/* external serial clock */
+#undef	CFG_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD		921600	/* internal clock */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR		0x1000000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+/*-----------------------------------------------------------------------
+ * IIC stuff
+ *-----------------------------------------------------------------------
+ */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+
+#define I2C_INIT
+#define I2C_ACTIVE 0
+#define I2C_TRISTATE 0
+
+#define CFG_I2C_SPEED		100000	/* use the standard 100kHz speed */
+#define CFG_I2C_SLAVE		0x7F		/* mask valid bits */
+
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR 0x68
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+/* If you want to see, whats connected to your PCI bus */
+/* #define CONFIG_PCI_SCAN_SHOW */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#if !(CONFIG_COMMANDS & CFG_CMD_IDE)
+
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
+#define CONFIG_START_IDE	1	/* check, if use IDE */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
+
+#define	CONFIG_ATAPI
+#define	CONFIG_DOS_PARTITION
+#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#ifndef IDE_USES_ISA_EMULATION
+
+/* New and faster access */
+#define	CFG_ATA_BASE_ADDR		0x7A000000	/* start of ISA IO emulation */
+
+/* How many IDE busses are available */
+#define	CFG_IDE_MAXBUS		1
+
+/* What IDE ports are available */
+#define	CFG_ATA_IDE0_OFFSET	0x000		/* first is available */
+#undef	CFG_ATA_IDE1_OFFSET			/* second not available */
+
+/* access to the data port is calculated:
+   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+
+/* access to the registers is calculated:
+   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
+#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+
+/* access to the alternate register is calculated:
+   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
+#define CFG_ATA_ALT_OFFSET	0x008		/* Offset for alternate registers	*/
+
+#else /* IDE_USES_ISA_EMULATION */
+
+#define	CFG_ATA_BASE_ADDR		0x79000000	/* start of ISA IO emulation */
+
+/* How many IDE busses are available */
+#define	CFG_IDE_MAXBUS		1
+
+/* What IDE ports are available */
+#define	CFG_ATA_IDE0_OFFSET	0x01F0	/* first is available */
+#undef	CFG_ATA_IDE1_OFFSET				/* second not available */
+
+/* access to the data port is calculated:
+   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+
+/* access to the registers is calculated:
+   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
+#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+
+/* access to the alternate register is calculated:
+   CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
+#define CFG_ATA_ALT_OFFSET	0x03F0		/* Offset for alternate registers	*/
+
+#endif /* IDE_USES_ISA_EMULATION */
+
+#endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */
+
+/*
+#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
+#define	CFG_IR_REG_BASE_ADDR	0xF0200000
+#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000
+*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * CFG_FLASH_BASE   -> start address of internal flash
+ * CFG_MONITOR_BASE -> start of u-boot
+ */
+#ifndef __ASSEMBLER__
+extern unsigned long offsetOfBigFlash;
+extern unsigned long offsetOfEnvironment;
+#endif
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFE00000
+#define CFG_MONITOR_BASE	0xFFFC0000     /* placed last 256k */
+#define CFG_MONITOR_LEN		(224 * 1024)	/* Reserve 224 KiB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 KiB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MiB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization ## FIXME: lookup in datasheet
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_CFI			/* flash is CFI compat.	*/
+#define CFG_FLASH_CFI_DRIVER		/* Use common CFI driver*/
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CFG_WRITE_SWAPPED_DATA		/* swap Databytes between reading/writing */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#if CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_OFFSET		0x00000000  /* Offset of Environment Sector in bottom type */
+#define CFG_ENV_SIZE		0x4000	    /* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x4000	    /* see README - env sector total size	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+#endif
+/* let us changing anything in our environment */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND-FLASH stuff
+ */
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CFG_NAND_BASE		0x77D00000
+
+
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
+
+/* No command line, one static partition Partition 3 contains jffs2 rootfs */
+#undef	CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_SIZE		0x00400000
+#define CONFIG_JFFS2_PART_OFFSET	0x00c00000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *
+ * CFG_DCACHE_SIZE -> size of data cache:
+ * - 405GP 8k
+ * - 405GPr 16k
+ * How to handle the difference in chache size?
+ * CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes
+ * (used in cpu/ppc4xx/start.S)
+*/
+#define CFG_DCACHE_SIZE    16384
+
+#define CFG_CACHELINE_SIZE 32
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE
+#define FLASH_BASE1_PRELIM	0
+
+/*-----------------------------------------------------------------------
+ * Some informations about the internal SRAM (OCM=On Chip Memory)
+ *
+ * CFG_OCM_DATA_ADDR -> location
+ * CFG_OCM_DATA_SIZE -> size
+*/
+
+#define CFG_TEMP_STACK_OCM	1
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM):
+ * - we are using the internal 4k SRAM, so we don't need data cache mapping
+ * - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
+ * - Stackpointer will be located to
+ *   (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
+ *   in cpu/ppc4xx/start.S
+ */
+
+#undef CFG_INIT_DCACHE_CS
+/* Where the internal SRAM starts */
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR
+/* Where the internal SRAM ends (only offset) */
+#define CFG_INIT_RAM_END	0x0F00
+
+/*
+
+ CFG_INIT_RAM_ADDR ------> ------------ lower address
+			   |	      |
+			   |  ^       |
+			   |  |       |
+			   |  | Stack |
+ CFG_GBL_DATA_OFFSET ----> ------------
+			   |	      |
+			   | 64 Bytes |
+			   |	      |
+ CFG_INIT_RAM_END  ------> ------------ higher address
+  (offset only)
+
+*/
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE     64
+#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+/* Initial value of the stack pointern in internal SRAM */
+#define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/* ################################################################################### */
+/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects  */
+/* They are currently undefined cause they are initiaized in board/solidcard3/init.S   */
+
+/* This chip select accesses the boot device */
+/* It depends on boot select switch if this device is 16 or 8 bit */
+
+#undef CFG_EBC_PB0AP
+#undef CFG_EBC_PB0CR
+
+#undef CFG_EBC_PB1AP
+#undef CFG_EBC_PB1CR
+
+#undef CFG_EBC_PB2AP
+#undef CFG_EBC_PB2CR
+
+#undef CFG_EBC_PB3AP
+#undef CFG_EBC_PB3CR
+
+#undef CFG_EBC_PB4AP
+#undef CFG_EBC_PB4CR
+
+#undef CFG_EBC_PB5AP
+#undef CFG_EBC_PB5CR
+
+#undef CFG_EBC_PB6AP
+#undef CFG_EBC_PB6CR
+
+#undef CFG_EBC_PB7AP
+#undef CFG_EBC_PB7CR
+
+#define CFG_EBC_CFG    0xb84ef000
+
+#define CONFIG_SDRAM_BANK0	/* use the standard SDRAM initialization */
+#undef CONFIG_SPD_EEPROM
+
+/*
+ * Define this to get more information about system configuration
+ */
+/* #define SC3_DEBUGOUT */
+#undef SC3_DEBUGOUT
+
+/***********************************************************************
+ * External peripheral base address
+ ***********************************************************************/
+
+#define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
+/*
+ Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
+ Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
+ das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
+ auf ISA- und PCI-Zyklen)
+ */
+#define CFG_ISA_IO_BASE_ADDRESS  0xE8000000
+/*#define CFG_ISA_IO_BASE_ADDRESS  0x79000000 */
+
+/************************************************************
+ * Video support
+ ************************************************************/
+
+#ifdef USE_VGA_GRAPHICS
+#define CONFIG_VIDEO		/* To enable video controller support */
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+/* #define CONFIG_VIDEO_LOGO */
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+/* #define CONFIG_VIDEO_HW_CURSOR */
+#define CONFIG_VIDEO_ONBOARD	/* Video controller is on-board */
+
+#define VIDEO_HW_RECTFILL
+#define VIDEO_HW_BITBLT
+
+#endif
+
+/************************************************************
+ * Ident
+ ************************************************************/
+#define CONFIG_SC3_VERSION "r1.4"
+
+#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 1a460cd..29f3b40 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2006
@@ -23,7 +23,7 @@
  */
 
 /************************************************************************
- * sequoia.h - configuration for Sequoia board (PowerPC440EPx)
+ * sequoia.h - configuration for Sequoia & Rainier boards
  ***********************************************************************/
 #ifndef __CONFIG_H
 #define __CONFIG_H
@@ -31,7 +31,7 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
+/* This config file is used for Sequoia (440EPx) and Rainier (440GRx)	*/
 #ifndef CONFIG_RAINIER
 #define CONFIG_SEQUOIA		1		/* Board is Sequoia	*/
 #define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
@@ -39,7 +39,7 @@
 #define CONFIG_440GRX		1		/* Specific PPC440GRx	*/
 #endif
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
-#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+#define CONFIG_SYS_CLK_FREQ	33000000	/* external freq to pll	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
@@ -102,6 +102,7 @@
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
 #else
 #define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
+#define CFG_ENV_IS_EMBEDDED	1	/* use embedded environment */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -187,7 +188,10 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM        (256)    /* 256MB			*/
+#define CFG_MBYTES_SDRAM        (256)		/* 256MB			*/
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_DDR_DATA_EYE			/* use DDR2 optimization	*/
+#endif
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -218,9 +222,21 @@
 
 #undef	CONFIG_BOOTARGS
 
+/* Setup some board specific values for the default environment variables */
+#ifndef CONFIG_RAINIER
+#define CONFIG_HOSTNAME		sequoia
+#define CFG_BOOTFILE		"bootfile=/tftpboot/sequoia/uImage\0"
+#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xxFP\0"
+#else
+#define CONFIG_HOSTNAME		rainier
+#define CFG_BOOTFILE		"bootfile=/tftpboot/rainier/uImage\0"
+#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xx\0"
+#endif
+
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CFG_BOOTFILE							\
+	CFG_ROOTPATH							\
 	"netdev=eth0\0"							\
-	"hostname=sequoia\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
@@ -234,13 +250,11 @@
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xxFP\0"					\
-	"bootfile=/tftpboot/sequoia/uImage\0"				\
 	"kernel_addr=FC000000\0"					\
 	"ramdisk_addr=FC180000\0"					\
-	"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0"		\
+	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
 	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
-		"cp.b 100000 FFFA0000 60000\0"			        \
+		"cp.b 200000 FFFA0000 60000\0"			        \
 	"upd=run load;run update\0"					\
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
@@ -345,7 +359,7 @@
  *----------------------------------------------------------------------*/
 /* General PCI */
 #define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#undef CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
@@ -377,7 +391,7 @@
 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CFG_NAND_CS		3		/* NAND chip connected to CSx	*/
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
-#define CFG_EBC_PB0AP		0x03017300
+#define CFG_EBC_PB0AP		0x03017200
 #define CFG_EBC_PB0CR		(CFG_FLASH | 0xda000)
 
 /* Memory Bank 3 (NAND-FLASH) initialization					*/
@@ -386,7 +400,7 @@
 #else
 #define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
 /* Memory Bank 3 (NOR-FLASH) initialization					*/
-#define CFG_EBC_PB3AP		0x03017300
+#define CFG_EBC_PB3AP		0x03017200
 #define CFG_EBC_PB3CR		(CFG_FLASH | 0xda000)
 
 /* Memory Bank 0 (NAND-FLASH) initialization					*/
diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h
index 9d3609a..09bbebd 100644
--- a/include/configs/spc1920.h
+++ b/include/configs/spc1920.h
@@ -44,19 +44,19 @@
 #define CONFIG_BAUDRATE		19200
 
 /* use PLD CLK4 instead of brg */
-#undef CFG_SPC1920_SMC1_CLK4
+#define CFG_SPC1920_SMC1_CLK4
 
 #define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK  */
 #define CONFIG_8xx_CPUCLK_DEFAULT	50000000
 #define CFG_8xx_CPUCLK_MIN		40000000
 #define CFG_8xx_CPUCLK_MAX		133000000
 
-#define CFG_RESET_ADDRESS		0xf8000000
+#define CFG_RESET_ADDRESS		0xC0000000
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_LAST_STAGE_INIT
 
-
-#if 1
+#if 0
 #define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
 #else
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
@@ -83,12 +83,13 @@
 #ifndef CONFIG_COMMANDS
 #define CONFIG_COMMANDS	(CONFIG_CMD_DFL   \
 			 | CFG_CMD_ASKENV \
+			 | CFG_CMD_DATE \
 			 | CFG_CMD_ECHO   \
 			 | CFG_CMD_IMMAP  \
 			 | CFG_CMD_JFFS2 \
 			 | CFG_CMD_PING \
 			 | CFG_CMD_DHCP \
-			 | CFG_CMD_IMMAP \
+			 | CFG_CMD_I2C \
 			 | CFG_CMD_MII)
 			/* & ~( CFG_CMD_NET)) */
 
@@ -193,13 +194,39 @@
 #define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
 #define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 
+#ifdef CFG_CMD_DATE
+# define CONFIG_RTC_DS3231
+# define CFG_I2C_RTC_ADDR      0x68
+#endif
+
 /*-----------------------------------------------------------------------
  * I2C configuration
  */
 #if (CONFIG_COMMANDS & CFG_CMD_I2C)
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address defaults */
-#define CFG_I2C_SLAVE		0x7F
+/* enable I2C and select the hardware/software driver */
+#undef CONFIG_HARD_I2C                 /* I2C with hardware support    */
+#define CONFIG_SOFT_I2C                1       /* I2C bit-banged               */
+
+#define CFG_I2C_SPEED          93000   /* 93 kHz is supposed to work   */
+#define CFG_I2C_SLAVE          0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL         0x00000020      /* PB 26 */
+#define PB_SDA         0x00000010      /* PB 27 */
+
+#define I2C_INIT       (immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE     (immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE   (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ       ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+		       else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+		       else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY      udelay(2)       /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -220,7 +247,7 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CFG_SIUMCR      (SIUMCR_FRC)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
@@ -283,7 +310,7 @@
  * FLASH timing:
  */
 #define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
-				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+				 OR_SCY_6_CLK | OR_EHTR | OR_BI)
 
 #define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 #define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
@@ -330,7 +357,56 @@
 			MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
 
 
-/* PLD CS5 */
+/*
+ * DSP Host Port Interface CS3
+ */
+#define CFG_SPC1920_HPI_BASE   0x90000000
+#define CFG_PRELIM_OR3_AM      0xF8000000
+
+#define CFG_OR3         (CFG_PRELIM_OR3_AM | \
+				       OR_G5LS | \
+				       OR_SCY_0_CLK | \
+				       OR_BI)
+
+#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
+					       BR_MS_UPMA | \
+					       BR_PS_16 | \
+					       BR_V);
+
+#define CFG_MAMR (MAMR_GPL_A4DIS | \
+		MAMR_RLFA_5X | \
+		MAMR_WLFA_5X)
+
+#define CONFIG_SPC1920_HPI_TEST
+
+#ifdef CONFIG_SPC1920_HPI_TEST
+#define HPI_REG(x)             (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x)))
+#define HPI_HPIC_1             HPI_REG(0)
+#define HPI_HPIC_2             HPI_REG(2)
+#define HPI_HPIA_1             HPI_REG(0x2000008)
+#define HPI_HPIA_2             HPI_REG(0x2000008 + 2)
+#define HPI_HPID_INC_1         HPI_REG(0x1000004)
+#define HPI_HPID_INC_2         HPI_REG(0x1000004 + 2)
+#define HPI_HPID_NOINC_1       HPI_REG(0x300000c)
+#define HPI_HPID_NOINC_2       HPI_REG(0x300000c + 2)
+#endif /* CONFIG_SPC1920_HPI_TEST */
+
+/*
+ * Ramtron FM18L08 FRAM 32KB on CS4
+ */
+#define CFG_SPC1920_FRAM_BASE	0x80100000
+#define CFG_PRELIM_OR4_AM	0xffff8000
+#define CFG_OR4		(CFG_PRELIM_OR4_AM | \
+					OR_ACS_DIV2 | \
+					OR_BI | \
+					OR_SCY_4_CLK | \
+					OR_TRLX)
+
+#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+/*
+ * PLD CS5
+ */
 #define CFG_SPC1920_PLD_BASE	0x80000000
 #define CFG_PRELIM_OR5_AM	0xffff8000
 
@@ -343,10 +419,6 @@
 
 #define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 
-/* #define CFG_PLD_BASE   0x30000000 */
-/* #define CFG_OR5_PRELIM 0xffff1110 */
-/* #define CFG_BR5_PRELIM 0x30000401 */
-
 /*
  * Internal Definitions
  *
diff --git a/include/configs/stamp.h b/include/configs/stamp.h
deleted file mode 100644
index 248ca70..0000000
--- a/include/configs/stamp.h
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * U-boot - stamp.h  Configuration file for STAMP board
- *			having BF533 processor
- *
- * Copyright (c) 2005 blackfin.uclinux.org
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_STAMP_H__
-#define __CONFIG_STAMP_H__
-
-/*
- * Board settings
- *
- */
-
-#define __ADSPLPBLACKFIN__		1
-#define __ADSPBF533__			1
-#define CONFIG_STAMP			1
-#define CONFIG_RTC_BF533		1
-
-/* FLASH/ETHERNET uses the same address range */
-#define SHARED_RESOURCES		1
-
-#define CONFIG_VDSP			1
-
-/*
- * Clock settings
- *
- */
-
-/* CONFIG_CLKIN_HZ is any value in Hz				 */
-#define CONFIG_CLKIN_HZ			11059200
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	 */
-/*						    1=CLKIN/2	 */
-#define CONFIG_CLKIN_HALF		0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	 */
-/*						 1=bypass PLL	 */
-#define CONFIG_PLL_BYPASS		0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	 */
-/* Values can range from 1-64					 */
-#define CONFIG_VCO_MULT			45
-/* CONFIG_CCLK_DIV controls what the core clock divider is	 */
-/* Values can be 1, 2, 4, or 8 ONLY				 */
-#define CONFIG_CCLK_DIV			1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15					 */
-#define CONFIG_SCLK_DIV			6
-
-/*
- * Network Settings
- */
-/* network support */
-#define CONFIG_IPADDR		192.168.0.15
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_GATEWAYIP	192.168.0.1
-#define CONFIG_SERVERIP		192.168.0.2
-#define CONFIG_HOSTNAME		STAMP
-#define CONFIG_ROOTPATH			/checkout/uClinux-dist/romfs
-
-/* To remove hardcoding and enable MAC storage in EEPROM  */
-/* #define CONFIG_ETHADDR		02:80:ad:20:31:b8 */
-
-/*
- * Command settings
- *
- */
-
-#define CFG_LONGHELP			1
-
-#define CONFIG_BOOTDELAY		5
-#define CONFIG_BOOT_RETRY_TIME		-1	/* Enable this if bootretry required, currently its disabled */
-#define CONFIG_BOOTCOMMAND		"run ramboot"
-#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n"
-
-#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | \
-					 CFG_CMD_PING	| \
-					 CFG_CMD_ELF	| \
-					 CFG_CMD_I2C	| \
-					 CFG_CMD_CACHE	| \
-					 CFG_CMD_JFFS2	| \
-					 CFG_CMD_DATE)
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
-
-#define CONFIG_EXTRA_ENV_SETTINGS												\
-	"ramargs=setenv bootargs root=/dev/mtdblock0 rw\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "									\
-	"nfsroot=$(serverip):$(rootpath)\0"											\
-	"addip=setenv bootargs $(bootargs) "										\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"							\
-	":$(hostname):eth0:off\0"													\
-    "ramboot=tftpboot 0x1000000 linux;"											\
-	"run ramargs;run addip;bootelf\0"											\
-	"nfsboot=tftpboot 0x1000000 linux;"											\
-	"run nfsargs;run addip;bootelf\0"											\
-	"flashboot=bootm 0x20100000\0"												\
-	""
-
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-/*
- * Console settings
- *
- */
-
-#define CONFIG_BAUDRATE			57600
-#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CFG_PROMPT			"stamp>"	/* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE			1024	/* Console I/O Buffer Size */
-#else
-#define CFG_CBSIZE			256	/* Console I/O Buffer Size */
-#endif
-#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS			16	/* max number of command args */
-#define CFG_BARGSIZE			CFG_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_LOADS_ECHO		1
-
-/*
- * Network settings
- *
- */
-
-#define CONFIG_DRIVER_SMC91111		1
-#define CONFIG_SMC91111_BASE		0x20300300
-/* To remove hardcoding and enable MAC storage in EEPROM */
-/* #define HARDCODE_MAC			1 */
-
-/*
- * Flash settings
- *
- */
-
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
-#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-#define CFG_FLASH_CFI_AMD_RESET
-
-#define CFG_ENV_IS_IN_FLASH		1
-
-#define CFG_FLASH_BASE			0x20000000
-#define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT		67		/* max number of sectors on one chip */
-
-#define CFG_ENV_ADDR			0x20020000
-#define CFG_ENV_SIZE			0x10000
-#define CFG_ENV_SECT_SIZE		0x10000 /* Total Size of Environment Sector */
-
-#define CFG_FLASH_ERASE_TOUT		30000	/* Timeout for Chip Erase (in ms) */
-#define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT		1	/* Timeout for Flash Write (in ms) */
-
-/* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS  1
-/* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR		11
-
-/*
- * following timeouts shall be used once the
- * Flash real protection is enabled
- */
-#define CFG_FLASH_LOCK_TOUT		5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT		10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-
-/*
- * I2C settings
- * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
- */
-#define CONFIG_SOFT_I2C			1	/* I2C bit-banged		*/
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PF_SCL				PF3
-#define PF_SDA				PF2
-
-#define I2C_INIT			(*pFIO_DIR |=  PF_SCL); asm("ssync;")
-#define I2C_ACTIVE			(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE			(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ			((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit)			if(bit) { \
-							*pFIO_FLAG_S = PF_SDA; \
-							asm("ssync;"); \
-						} \
-					else	{ \
-							*pFIO_FLAG_C = PF_SDA; \
-							asm("ssync;"); \
-						}
-#define I2C_SCL(bit)			if(bit) { \
-							*pFIO_FLAG_S = PF_SCL; \
-							asm("ssync;"); \
-						} \
-					else	{ \
-							*pFIO_FLAG_C = PF_SCL; \
-							asm("ssync;"); \
-						}
-#define I2C_DELAY			udelay(5)	/* 1/4 I2C clock duration */
-
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xFE
-
-/*
- * Compact Flash settings
- */
-
-/* Enabled below option for CF support */
-/* #define CONFIG_STAMP_CF		1 */
-
-#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
-
-#define CONFIG_MISC_INIT_R		1
-#define CONFIG_DOS_PARTITION		1
-
-/*
- * IDE/ATA stuff
- */
-#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
-#undef	CONFIG_IDE_LED			/* no led for ide supported */
-#undef	CONFIG_IDE_RESET		/* no reset for ide supported */
-
-#define CFG_IDE_MAXBUS	1		/* max. 1 IDE busses */
-#define CFG_IDE_MAXDEVICE		(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
-
-#define CFG_ATA_BASE_ADDR		0x20200000
-#define CFG_ATA_IDE0_OFFSET		0x0000
-
-#define CFG_ATA_DATA_OFFSET		0x0020	/* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET		0x0020	/* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET		0x0007	/* Offset for alternate registers */
-
-#define CFG_ATA_STRIDE			2
-#endif
-
-/*
- * SDRAM settings
- *
- */
-
-#define CONFIG_MEM_SIZE			128		/* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH		11	       /* 8, 9, 10, 11	  */
-#define CONFIG_MEM_MT48LC64M4A2FB_7E	1
-
-#define CFG_MEMTEST_START		0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END			0x07EFFFFF	/* 1 ... 127 MB in DRAM */
-#define CFG_LOAD_ADDR			0x01000000	/* default load address */
-
-#define CFG_SDRAM_BASE			0x00000000
-#define CFG_MAX_RAM_SIZE		0x08000000
-
-#define CFG_MONITOR_LEN			(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
-
-#if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ			( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
-#else
-#define CONFIG_VCO_HZ			(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
-#endif
-
-#if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ			( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ			( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
-#else
-#define CONFIG_CCLK_HZ			CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ			CONFIG_CLKIN_HZ
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_HZ				1000		/* 1ms time tick */
-
-#define CFG_MALLOC_LEN			(128 << 10)	/* Reserve 128 kB for malloc()	*/
-#define CFG_MALLOC_BASE			(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_SIZE		0x4000
-#define CFG_GBL_DATA_ADDR		(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE		(CFG_GBL_DATA_ADDR  - 4)
-
-#define CFG_LARGE_IMAGE_LEN	0x4000000	/* Large Image Length, set to 64 Meg */
-
-#define CONFIG_SHOW_BOOT_PROGRESS	1	/* Show boot progress on LEDs */
-
-/*
- * Stack sizes
- */
-#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-
-/*
- * FLASH organization and environment definitions
- */
-#define CFG_BOOTMAPSZ			(8 << 20)	/* Initial Memory map for Linux */
-
-/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
-/*#define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL		(B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL |	\
-				B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
-#define AMBCTL1VAL		(B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL |	\
-				B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
-*/
-#define AMGCTLVAL		0xFF
-#define AMBCTL0VAL		0xBBC3BBC3
-#define AMBCTL1VAL		0x99B39983
-#define CF_AMBCTL1VAL		0x99B3ffc2
-
-#ifdef CONFIG_VDSP
-#define ET_EXEC_VDSP		0x8
-#define SHT_STRTAB_VDSP		0x1
-#define ELFSHDRSIZE_VDSP	0x2C
-#define VDSP_ENTRY_ADDR		0xFFA00000
-#endif
-
-#endif
diff --git a/include/configs/yellowstone.h b/include/configs/taishan.h
index ba27f37..2b28f93 100644
--- a/include/configs/yellowstone.h
+++ b/include/configs/taishan.h
@@ -1,10 +1,7 @@
 /*
- * (C) Copyright 2005-2006
+ * (C) Copyright 2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ -12,7 +9,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -22,64 +19,66 @@
  */
 
 /************************************************************************
- * yellowstone.h - configuration for YELLOWSTONE board
+ * TAISHAN.h - configuration for AMCC 440GX Ref
  ***********************************************************************/
+
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-#define CONFIG_YOLLOWSTONE	1	/* Board is Yellowstone         */
-#define CONFIG_440GR		1	/* Specific PPC440EP support    */
-#define CONFIG_4xx		1	/* ... PPC4xx family	        */
-#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
+#define CONFIG_TAISHAN		1	/* Board is taishan		*/
+#define CONFIG_440GX		1	/* Specifc GX support		*/
+#define CONFIG_4xx		1	/* ... PPC4xx family		*/
+#undef	CFG_DRAM_TEST			/* Disable-takes long time!	*/
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
 
-#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
-#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
-#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
-#define CFG_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
-#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
-#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
-#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
-
-/*Don't change either of these*/
-#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
-#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
-/*Don't change either of these*/
-
-#define CFG_USB_DEVICE          0x50000000
-#define CFG_NVRAM_BASE_ADDR     0x80000000
-#define CFG_BCSR_BASE	        (CFG_NVRAM_BASE_ADDR | 0x2000)
-#define CFG_BOOT_BASE_ADDR      0xf0000000
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CFG_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CFG_MONITOR_BASE	0xfffc0000	/* start of monitor	*/
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE	0xe0000000	/* internal peripherals	*/
+#define CFG_ISRAM_BASE		0xc0000000	/* internal SRAM	*/
+#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+
+#define CFG_EBC0_FLASH_BASE	CFG_FLASH_BASE
+#define CFG_EBC1_FPGA_BASE	(CFG_PERIPHERAL_BASE + 0x01000000)
+#define CFG_EBC2_LCM_BASE	(CFG_PERIPHERAL_BASE + 0x02000000)
+#define CFG_EBC3_CONN_BASE	(CFG_PERIPHERAL_BASE + 0x08000000)
+
+#define CFG_GPIO_BASE		(CFG_PERIPHERAL_BASE + 0x00000700)
 
 /*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in SDRAM)
+ * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
-#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CFG_INIT_RAM_END	(8 << 10)
-#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
+#define CFG_TEMP_STACK_OCM	1
+#define CFG_OCM_DATA_ADDR	CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM*/
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data*/
+
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
+#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc*/
 
 /*-----------------------------------------------------------------------
  * Serial Port
  *----------------------------------------------------------------------*/
-#define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
+#define CONFIG_UART1_CONSOLE	1	/* use of UART1 as console	*/
+#define CONFIG_SERIAL_MULTI     1	/* enable serial multi support	*/
+#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_SERIAL_MULTI     1
-/*define this if you want console on UART1*/
-#undef CONFIG_UART1_CONSOLE
 
 #define CFG_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@@ -87,70 +86,81 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-/*
- * Define here the location of the environment variables (FLASH or EEPROM).
- * Note: DENX encourages to use redundant environment in FLASH.
- */
-#if 1
 #define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
-#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
-#define CFG_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 
-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS     1		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	1024		    /* sectors per device   */
 
+#undef	CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
-
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#ifdef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
 
 /* Address and size of Redundant Environment Sector	*/
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
-#endif /* CFG_ENV_IS_IN_FLASH */
 
 /*-----------------------------------------------------------------------
- * DDR SDRAM
+ * E2PROM bootstrap configure value
  *----------------------------------------------------------------------*/
-#undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
-#define CFG_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
-#define CFG_SDRAM_BANKS	        (2)
 
+/*
+ * 800/133/66
+ * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
+ */
+
+/*
+ * 800/160/80
+ * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
+ */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
+#define	CFG_SDRAM0_TR0		0xC10A401A
+#undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
 #define CFG_I2C_SLAVE		0x7F
 
-#define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#undef CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	0x50
 #define CFG_I2C_EEPROM_ADDR_LEN 1
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 
-#ifdef CFG_ENV_IS_IN_EEPROM
-#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
-#define CFG_ENV_OFFSET		0x0
-#endif /* CFG_ENV_IS_IN_EEPROM */
+#define CFG_BOOTSTRAP_IIC_ADDR	0x50
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
@@ -160,14 +170,14 @@
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
-	"hostname=yellowstone\0"					\
+	"hostname=taishan\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
 	"flash_nfs=run nfsargs addip addtty;"				\
 		"bootm ${kernel_addr}\0"				\
 	"flash_self=run ramargs addip addtty;"				\
@@ -175,14 +185,19 @@
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 	        "bootm\0"						\
 	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/yellowstone/uImage\0"			\
+	"bootfile=/tftpboot/taishan/uImage\0"				\
 	"kernel_addr=fc000000\0"					\
 	"ramdisk_addr=fc180000\0"					\
-	"load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0"		\
-	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
-		"cp.b 100000 fff80000 80000;"			        \
+	"initrd_high=30000000\0"					\
+	"load=tftp 100000 /tftpboot/taishan/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
 		"setenv filesize;saveenv\0"				\
 	"upd=run load;run update\0"					\
+	"fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
+	"$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0"	\
+	"dhcp=setenv bootargs $(bootargs) ip=dhcp\0"			\
+	"kozio=bootm 0xffe00000\0"					\
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
@@ -193,44 +208,39 @@
 #endif
 
 #define CONFIG_BAUDRATE		115200
-
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_EMAC_NR_START	2	/* start with EMAC 2 (skip 0&1)	*/
 #define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_NET_MULTI        1	/* required for netconsole      */
-#define CONFIG_PHY1_ADDR        3
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
-#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
-
+#define CONFIG_NET_MULTI	1
+#define CONFIG_PHY_ADDR	      	0xff	     /* no phy on EMAC0		*/
+#define CONFIG_PHY1_ADDR      	0xff	     /* no phy on EMAC1		*/
+#define CONFIG_PHY2_ADDR	0x1
+#define CONFIG_PHY3_ADDR	0x3
+#define CONFIG_ET1011C_PHY	1
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
+#define CONFIG_PHY_RESET_DELAY	1000
 #define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 
 #define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-#ifdef CONFIG_440EP
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/*Comment this out to enable USB 1.1 device*/
-#define USB_2_0_DEVICE
-#endif /*CONFIG_440EP*/
-
-#ifdef DEBUG
-#define CONFIG_PANIC_HANG
-#else
-#define CONFIG_HW_WATCHDOG			/* watchdog */
-#endif
-
+/*-----------------------------------------------------------------------
+ * Console/Commands/Parser
+ *----------------------------------------------------------------------*/
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_DIAG	| \
+				CFG_CMD_DTT	| \
 				CFG_CMD_ELF	| \
 				CFG_CMD_EEPROM	| \
 				CFG_CMD_I2C	| \
@@ -240,15 +250,16 @@
 				CFG_CMD_NFS	| \
 				CFG_CMD_PCI	| \
 				CFG_CMD_PING	| \
-				CFG_CMD_REGINFO	| \
-				CFG_CMD_SDRAM)
+				CFG_CMD_REGINFO)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
-/*
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
  * Miscellaneous configurable options
- */
+ *----------------------------------------------------------------------*/
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
@@ -260,14 +271,13 @@
 #define CFG_MAXARGS	        16	/* max number of command args	*/
 #define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
 #define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
 #define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI          1       /* support kdi files            */
 
-#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
@@ -280,18 +290,18 @@
  *-----------------------------------------------------------------------
  */
 /* General PCI */
-#define CONFIG_PCI			/* include pci support	        */
-#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
-#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_EEPRO100       1		/* include PCI EEPRO100		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
 
 /* Board-specific PCI */
-#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
-#define CFG_PCI_TARGET_INIT
-#define CFG_PCI_MASTER_INIT
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
 
 #define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
-#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
 
 /*
  * For booting Linux, the board info and command line data
@@ -302,8 +312,8 @@
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE		32768	/* For AMCC 440 CPUs			*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -321,5 +331,4 @@
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
 #endif
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/uc101.h b/include/configs/uc101.h
new file mode 100644
index 0000000..8cd8e9b
--- /dev/null
+++ b/include/configs/uc101.h
@@ -0,0 +1,353 @@
+/*
+ * (C) Copyright 2003-2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
+#define CONFIG_UC101		1	/* UC101 board			*/
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DISPLAY	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DTT	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+
+#if (TEXT_BASE == 0xFFF00000) /* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addwdt=setenv bootargs ${bootargs} wdt=off"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#define CONFIG_MISC_INIT_R	1
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x58
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+/* for LM81 */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR		0x51
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM81			1	/* ON Semi's LM75		*/
+#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
+#define CFG_DTT_MAX_TEMP		70
+#define CFG_DTT_LOW_TEMP		-30
+#define CFG_DTT_HYSTERESIS		3
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xFF800000
+
+#define CFG_FLASH_SIZE		0x00800000 /* 8 MByte */
+#define CFG_MAX_FLASH_SECT	140	/* max num of sects on one chip */
+
+#define CFG_ENV_ADDR		(TEXT_BASE+0x40000) /* second sector */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_CFI_AMD_RESET
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x4000
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SRAM_BASE		0x80100000	/* CS 1 */
+#define CFG_DISPLAY_BASE	0x80600000	/* CS 3 */
+#define	CFG_IB_MASTER		0xc0510000	/* CS 6 */
+#define CFG_IB_EPLD		0xc0500000	/* CS 7 */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_DDR	 1
+#define SDRAM_MODE      0x018D0000
+#define SDRAM_EMODE     0x40090000
+#define SDRAM_CONTROL   0x714f0f00
+#define SDRAM_CONFIG1   0x73722930
+#define SDRAM_CONFIG2   0x47770000
+#define SDRAM_TAPDELAY  0x10000000
+
+/* SRAM */
+#define SRAM_BASE		CFG_SRAM_BASE	/* SRAM base address	*/
+#define SRAM_LEN		0x1fffff
+#define SRAM_END		(SRAM_BASE + SRAM_LEN)
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_MII		1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x4d558044
+
+/*use  Hardware WDT */
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START	0x00300000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 3 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x300000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00045D00
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+/* 8Mbit SRAM @0x80100000 */
+#define CFG_CS1_START		CFG_SRAM_BASE
+#define CFG_CS1_SIZE		0x00100000
+#define CFG_CS1_CFG		0x21D00
+
+/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
+#define CFG_CS3_START		CFG_DISPLAY_BASE
+#define CFG_CS3_SIZE		0x00000100
+#define CFG_CS3_CFG		0x00081802
+
+/* Interbus Master 16 Bit */
+#define CFG_CS6_START		CFG_IB_MASTER
+#define CFG_CS6_SIZE		0x00010000
+#define CFG_CS6_CFG		0x00FF3500
+
+/* Interbus EPLD 8 Bit */
+#define CFG_CS7_START		CFG_IB_EPLD
+#define CFG_CS7_SIZE		0x00010000
+#define CFG_CS7_CFG		0x00081800
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+
+#define CONFIG_IDE_PREINIT	1
+/* #define CONFIG_IDE_RESET	1 beispile siehe tqm5200.c */
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CFG_ATA_STRIDE          4
+
+#define CONFIG_ATAPI            1
+
+/*---------------------------------------------------------------------*/
+/* Display addresses						       */
+/*---------------------------------------------------------------------*/
+#define CFG_DISP_CHR_RAM	(CFG_DISPLAY_BASE + 0x38)
+#define CFG_DISP_CWORD		(CFG_DISPLAY_BASE + 0x30)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 554a7a4..e19591d 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -39,6 +39,7 @@
 #define CONFIG_NETCONSOLE		1
 
 #define CONFIG_BOARD_EARLY_INIT_R	1	/* do board-specific init */
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* do board-specific init */
 
 #define CFG_XLB_PIPELINING		1	/* gives better performance */
 
@@ -101,7 +102,7 @@
 				 CFG_CMD_IRQ	| \
 				 CFG_CMD_JFFS2	| \
 				 CFG_CMD_MII	| \
-				 CFG_CMD_SDRAMi	| \
+				 CFG_CMD_SDRAM	| \
 				 CFG_CMD_DATE	| \
 				 CFG_CMD_USB	| \
 				 CFG_CMD_FAT)
@@ -135,7 +136,7 @@
 	"preboot=echo;echo Type \"run flash_nfs\" to mount root "	\
 		"filesystem over NFS; echo\0"				\
 	"netdev=eth0\0"							\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"		\
 	"addip=setenv bootargs $(bootargs) "				\
 		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
 		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
@@ -144,7 +145,7 @@
 		"$(ramdisk_addr)\0"					\
 	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
+		"nfsroot=$(serverip):$(rootpath) wdt=off\0"		\
 	"hostname=v38b\0"						\
 	"ethact=FEC ETHERNET\0"						\
 	"rootpath=/opt/eldk-3.1.1/ppc_6xx\0"				\
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
index 28abd6e..b34dc71 100644
--- a/include/configs/walnut.h
+++ b/include/configs/walnut.h
@@ -68,6 +68,7 @@
 	"bootfile=/tftpboot/walnut/uImage\0"				\
 	"kernel_addr=fff80000\0"					\
 	"ramdisk_addr=fff80000\0"					\
+	"initrd_high=30000000\0"					\
 	"load=tftp 100000 /tftpboot/walnut/u-boot.bin\0"		\
 	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
 		"cp.b 100000 fffc0000 40000;"				\
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 9f98500..b59f75b 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005-2006
+ * (C) Copyright 2005-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -22,7 +22,7 @@
  */
 
 /************************************************************************
- * yosemite.h - configuration for YOSEMITE board
+ * yosemite.h - configuration for Yosemite & Yellowstone boards
  ***********************************************************************/
 #ifndef __CONFIG_H
 #define __CONFIG_H
@@ -30,13 +30,21 @@
 /*-----------------------------------------------------------------------
  * High Level Configuration Options
  *----------------------------------------------------------------------*/
-#define CONFIG_YOSEMITE		1	/* Board is Yosemite            */
-#define CONFIG_440EP		1	/* Specific PPC440EP support    */
-#define CONFIG_4xx		1	/* ... PPC4xx family	        */
+/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
+#ifndef CONFIG_YELLOWSTONE
+#define CONFIG_YOSEMITE		1	/* Board is Yosemite		*/
+#define CONFIG_440EP		1	/* Specific PPC440EP support	*/
+#define CONFIG_HOSTNAME		yosemite
+#else
+#define CONFIG_440GR		1	/* Specific PPC440GR support	*/
+#define CONFIG_HOSTNAME		yellowstone
+#endif
+#define CONFIG_4xx		1	/* ... PPC4xx family		*/
 #define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+#define CONFIG_BOARD_RESET	1	/* call board_reset()		*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
@@ -158,9 +166,21 @@
 
 #undef	CONFIG_BOOTARGS
 
+/* Setup some board specific values for the default environment variables */
+#ifndef CONFIG_YELLOWSTONE
+#define CONFIG_HOSTNAME		yosemite
+#define CFG_BOOTFILE		"bootfile=/tftpboot/yosemite/uImage\0"
+#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xxFP\0"
+#else
+#define CONFIG_HOSTNAME		yellowstone
+#define CFG_BOOTFILE		"bootfile=/tftpboot/yellowstone/uImage\0"
+#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xx\0"
+#endif
+
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CFG_BOOTFILE							\
+	CFG_ROOTPATH							\
 	"netdev=eth0\0"							\
-	"hostname=yosemite\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
@@ -174,13 +194,12 @@
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 	        "bootm\0"						\
-	"rootpath=/opt/eldk/ppc_4xx\0"					\
-	"bootfile=/tftpboot/yosemite/uImage\0"				\
+	"bootfile=/tftpboot/${hostname}/uImage\0"			\
 	"kernel_addr=fc000000\0"					\
 	"ramdisk_addr=fc180000\0"					\
-	"load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0"		\
+	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
 	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
-		"cp.b 100000 fff80000 80000;"			        \
+		"cp.b 200000 fff80000 80000;"			        \
 		"setenv filesize;saveenv\0"				\
 	"upd=run load;run update\0"					\
 	""
@@ -223,9 +242,15 @@
 #define CFG_USB_OHCI_SLOT_NAME	"ppc440"
 #define CFG_USB_OHCI_MAX_ROOT_PORTS	15
 
-/*Comment this out to enable USB 1.1 device*/
+/* Comment this out to enable USB 1.1 device */
 #define USB_2_0_DEVICE
-#endif /*CONFIG_440EP*/
+
+#define CMD_USB			(CFG_CMD_USB | CFG_CMD_FAT | CFG_CMD_EXT2)
+
+#define CONFIG_SUPPORT_VFAT
+#else
+#define CMD_USB			0	/* no USB on 440GR		*/
+#endif /* CONFIG_440EP */
 
 #ifdef DEBUG
 #define CONFIG_PANIC_HANG
@@ -248,11 +273,7 @@
 				CFG_CMD_PING	| \
 				CFG_CMD_REGINFO	| \
 				CFG_CMD_SDRAM	| \
-				CFG_CMD_FAT	| \
-				CFG_CMD_EXT2	| \
-				CFG_CMD_USB	)
-
-#define CONFIG_SUPPORT_VFAT
+				CMD_USB)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -312,6 +333,20 @@
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH		CFG_FLASH_BASE
+#define CFG_CPLD		0x80000000
+
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x03017300
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0xda000)
+
+/* Memory Bank 2 (CPLD) initialization						*/
+#define CFG_EBC_PB2AP		0x04814500
+#define CFG_EBC_PB2CR		(CFG_CPLD | 0x18000)
+
+/*-----------------------------------------------------------------------
  * Cache Configuration
  */
 #define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index a6532b5..eb4859c 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -45,11 +45,11 @@
 #define EXTCLK_50		50000000
 #define EXTCLK_83		83333333
 
-#define	CONFIG_IBM_EMAC4_V4		1
-#define	CONFIG_MISC_INIT_F		1	/* Use misc_init_f()	*/
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 #undef  CONFIG_STRESS
-#undef  ENABLE_ECC
+
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
@@ -118,10 +118,9 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
-#define SPD_EEPROM_ADDRESS {0x53, 0x52}	/* SPD i2c spd addresses	*/
-#define IIC0_DIMM0_ADDR		0x53
-#define IIC0_DIMM1_ADDR		0x52
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS	{0x53, 0x52}	/* SPD i2c spd addresses*/
+#undef CONFIG_DDR_ECC			/* no ECC support for now	*/
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -178,6 +177,7 @@
 	"bootfile=yucca/uImage\0"					\
 	"kernel_addr=E7F10000\0"					\
 	"ramdisk_addr=E7F20000\0"					\
+	"initrd_high=30000000\0"					\
 	"load=tftp 100000 yuca/u-boot.bin\0"				\
 	"update=protect off 2:4-7;era 2:4-7;"				\
 		"cp.b ${fileaddr} FFFB0000 ${filesize};"		\
@@ -210,6 +210,7 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define	CONFIG_IBM_EMAC4_V4	1
 #define CONFIG_MII		1	/* MII PHY management		*/
 #undef CONFIG_NET_MULTI
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
diff --git a/include/dtt.h b/include/dtt.h
index a17aa67..842a761 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -29,6 +29,7 @@
 
 #if defined(CONFIG_DTT_LM75) || \
     defined(CONFIG_DTT_DS1621) || \
+    defined(CONFIG_DTT_LM81) || \
     defined(CONFIG_DTT_ADM1021)
 
 #define CONFIG_DTT				/* We have a DTT */
@@ -58,6 +59,14 @@ extern int dtt_get_temp(int sensor);
 #define DTT_TEMP_SET		0x3
 #endif
 
+#if defined(CONFIG_DTT_LM81)
+#define DTT_READ_TEMP		0x27
+#define DTT_CONFIG_TEMP		0x4b
+#define DTT_TEMP_MAX		0x39
+#define DTT_TEMP_HYST		0x3a
+#define DTT_CONFIG		0x40
+#endif
+
 #if defined(CONFIG_DTT_DS1621)
 #define DTT_READ_TEMP		0xAA
 #define DTT_READ_COUNTER	0xA8
diff --git a/include/environment.h b/include/environment.h
index 26b0712..af605ab 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -79,8 +79,7 @@
 # ifdef CFG_ENV_OFFSET_REDUND
 #  define CFG_REDUNDAND_ENVIRONMENT
 # endif
-# if defined(CONFIG_NAND_U_BOOT)
-/* Use embedded environment in NAND boot versions */
+# ifdef CFG_ENV_IS_EMBEDDED
 #  define ENV_IS_EMBEDDED	1
 # endif
 #endif /* CFG_ENV_IS_IN_NAND */
diff --git a/include/flash.h b/include/flash.h
index 9c57cbc..43b9c6b 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -51,6 +51,7 @@ typedef struct {
 	ushort	device_id2;		/* extended device id			*/
 	ushort	ext_addr;		/* extended query table address		*/
 	ushort	cfi_version;		/* cfi version				*/
+	ushort	cfi_offset;		/* offset for cfi query 		*/
 #endif
 } flash_info_t;
 
@@ -251,6 +252,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define STM_ID_x800AB	0x005B005B	/* M29W800AB ID (8M = 512K x 16 )	*/
 #define STM_ID_29W320DT 0x22CA22CA	/* M29W320DT ID (32 M, top boot sector) */
 #define STM_ID_29W320DB 0x22CB22CB	/* M29W320DB ID (32 M, bottom boot sect)	*/
+#define STM_ID_29W320ET 0x22562256	/* M29W320ET ID (32 M, top boot sector) */
+#define STM_ID_29W320EB 0x22572257	/* M29W320EB ID (32 M, bottom boot sect)*/
 #define STM_ID_29W040B	0x00E300E3	/* M29W040B ID (4M = 512K x 8)	*/
 #define FLASH_PSD4256GV 0x00E9		/* PSD4256 Flash and CPLD combination	*/
 
@@ -303,6 +306,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 
 #define TOSH_ID_FVT160	0xC2		/* TC58FVT160 ID (16 M, top )		*/
 #define TOSH_ID_FVB160	0x43		/* TC58FVT160 ID (16 M, bottom )	*/
+#define PHILIPS_LPC2292 0x0401FF13  /* LPC2292 internal FLASH			*/
 
 /*-----------------------------------------------------------------------
  * Internal FLASH identification codes
diff --git a/include/i2c.h b/include/i2c.h
index 6d39080..6e6c845 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -46,6 +46,27 @@
  */
 #define I2C_RXTX_LEN	128	/* maximum tx/rx buffer length */
 
+#if defined(CONFIG_I2C_MULTI_BUS)
+#define CFG_MAX_I2C_BUS		2
+#define I2C_GET_BUS()		i2c_get_bus_num()
+#define I2C_SET_BUS(a)		i2c_set_bus_num(a)
+#else
+#define CFG_MAX_I2C_BUS		1
+#define I2C_GET_BUS()		0
+#define I2C_SET_BUS(a)
+#endif
+
+/* define the I2C bus number for RTC and DTT if not already done */
+#if !defined(CFG_RTC_BUS_NUM)
+#define CFG_RTC_BUS_NUM		0
+#endif
+#if !defined(CFG_DTT_BUS_NUM)
+#define CFG_DTT_BUS_NUM		0
+#endif
+#if !defined(CFG_SPD_BUS_NUM)
+#define CFG_SPD_BUS_NUM		0
+#endif
+
 /*
  * Initialization, must be called once on start up, may be called
  * repeatedly to change the speed and slave addresses.
@@ -82,4 +103,49 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
 uchar i2c_reg_read (uchar chip, uchar reg);
 void  i2c_reg_write(uchar chip, uchar reg, uchar val);
 
+/*
+ * Functions for setting the current I2C bus and its speed
+ */
+
+/*
+ * i2c_set_bus_num:
+ *
+ *  Change the active I2C bus.  Subsequent read/write calls will
+ *  go to this one.
+ *
+ * 	bus - bus index, zero based
+ *
+ * 	Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_num(unsigned int bus);
+
+/*
+ * i2c_get_bus_num:
+ *
+ *  Returns index of currently active I2C bus.  Zero-based.
+ */
+
+unsigned int i2c_get_bus_num(void);
+
+/*
+ * i2c_set_bus_speed:
+ *
+ *  Change the speed of the active I2C bus
+ *
+ * 	speed - bus speed in Hz
+ *
+ * 	Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_speed(unsigned int);
+
+/*
+ * i2c_get_bus_speed:
+ *
+ *  Returns speed of currently active I2C bus in Hz
+ */
+
+unsigned int i2c_get_bus_speed(void);
+
 #endif	/* _I2C_H_ */
diff --git a/include/ide.h b/include/ide.h
index dfef32f..6976a6c 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -48,8 +48,8 @@ typedef ulong lbaint_t;
  * Function Prototypes
  */
 
-void  ide_init  (void);
-ulong ide_read	(int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
-ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
+void ide_init(void);
+ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer);
+ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, void *buffer);
 
 #endif /* _IDE_H */
diff --git a/include/ioports.h b/include/ioports.h
index d7e19e1..cfba667 100644
--- a/include/ioports.h
+++ b/include/ioports.h
@@ -53,3 +53,13 @@ typedef struct {
  * like the table in the 8260UM (and in the hymod manuals).
  */
 extern const iop_conf_t iop_conf_tab[4][32];
+
+typedef struct {
+	unsigned char	port;
+	unsigned char	pin;
+	int		dir;
+	int		open_drain;
+	int		assign;
+} qe_iop_conf_t;
+
+#define QE_IOP_TAB_END	(-1)
diff --git a/include/linux/stat.h b/include/linux/stat.h
index f9422cb..4d05aa9 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -67,7 +67,7 @@ struct stat {
 
 #endif	/* __PPC__ */
 
-#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__)
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__)
 
 struct stat {
 	unsigned short st_dev;
diff --git a/include/mpc8260.h b/include/mpc8260.h
index ff52a7b..d9dd92d 100644
--- a/include/mpc8260.h
+++ b/include/mpc8260.h
@@ -35,7 +35,15 @@
 #endif
 #ifndef CPU_ID_STR
 #if defined(CONFIG_MPC8272_FAMILY)
+#ifdef CONFIG_MPC8247
+#define CPU_ID_STR	"MPC8247"
+#elif defined CONFIG_MPC8248
+#define CPU_ID_STR	"MPC8248"
+#elif defined CONFIG_MPC8271
+#define CPU_ID_STR	"MPC8271"
+#else
 #define CPU_ID_STR	"MPC8272"
+#endif
 #else
 #define CPU_ID_STR	"MPC8260"
 #endif
@@ -66,6 +74,7 @@
 #define BCR_EXDD	0x00000400	/* External Master Delay Disable*/
 #define BCR_ISPS	0x00000010	/* Internal Space Port Size	*/
 
+
 /*-----------------------------------------------------------------------
  * PPC_ACR - 60x Bus Arbiter Configuration Register			 4-28
  */
@@ -168,6 +177,7 @@
 #define SIUMCR_MMR10	0x00008000	/* - " -			*/
 #define SIUMCR_MMR11	0x0000c000	/* - " -			*/
 #define SIUMCR_LPBSE	0x00002000	/* LocalBus Parity Byte Select Enable*/
+#define SIUMCR_ABE	0x00000400	/* Address output buffer impedance*/
 
 /*-----------------------------------------------------------------------
  * IMMR - Internal Memory Map Register					 4-34
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index ea40bad..c2a4ff5 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -8,306 +8,1015 @@
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * mpc83xx.h
- *
- * MPC83xx specific definitions
  */
 
 #ifndef __MPC83XX_H__
 #define __MPC83XX_H__
 
+#include <config.h>
 #if defined(CONFIG_E300)
 #include <asm/e300.h>
 #endif
 
-/*
- * MPC83xx cpu provide RCR register to do reset thing specially. easier
- * to implement
+/* MPC83xx cpu provide RCR register to do reset thing specially
  */
-
 #define MPC83xx_RESET
 
-/*
- * System reset offset (PowerPC standard)
+/* System reset offset (PowerPC standard)
  */
-#define EXC_OFF_SYS_RESET	0x0100
+#define EXC_OFF_SYS_RESET		0x0100
 
-/*
- * Default Internal Memory Register Space (Freescale recomandation)
+/* IMMRBAR - Internal Memory Register Base Address
  */
-#define CONFIG_DEFAULT_IMMR 0xFF400000
+#define CONFIG_DEFAULT_IMMR		0xFF400000	/* Default IMMR base address */
+#define IMMRBAR				0x0000		/* Register offset to immr */
+#define IMMRBAR_BASE_ADDR		0xFFF00000	/* Base address mask */
+#define IMMRBAR_RES			~(IMMRBAR_BASE_ADDR)
 
-/*
- * Watchdog
+/* LAWBAR - Local Access Window Base Address Register
+ */
+#define LBLAWBAR0			0x0020		/* Register offset to immr */
+#define LBLAWAR0			0x0024
+#define LBLAWBAR1			0x0028
+#define LBLAWAR1			0x002C
+#define LBLAWBAR2			0x0030
+#define LBLAWAR2			0x0034
+#define LBLAWBAR3			0x0038
+#define LBLAWAR3			0x003C
+#define LAWBAR_BAR			0xFFFFF000	/* Base address mask */
+
+/* SPRIDR - System Part and Revision ID Register
+ */
+#define SPRIDR_PARTID			0xFFFF0000	/* Part Identification */
+#define SPRIDR_REVID			0x0000FFFF	/* Revision Identification */
+
+#define SPR_8349E_REV10			0x80300100
+#define SPR_8349_REV10			0x80310100
+#define SPR_8347E_REV10_TBGA		0x80320100
+#define SPR_8347_REV10_TBGA		0x80330100
+#define SPR_8347E_REV10_PBGA		0x80340100
+#define SPR_8347_REV10_PBGA		0x80350100
+#define SPR_8343E_REV10			0x80360100
+#define SPR_8343_REV10			0x80370100
+
+#define SPR_8349E_REV11			0x80300101
+#define SPR_8349_REV11			0x80310101
+#define SPR_8347E_REV11_TBGA		0x80320101
+#define SPR_8347_REV11_TBGA		0x80330101
+#define SPR_8347E_REV11_PBGA		0x80340101
+#define SPR_8347_REV11_PBGA		0x80350101
+#define SPR_8343E_REV11			0x80360101
+#define SPR_8343_REV11			0x80370101
+
+#define SPR_8349E_REV31			0x80300300
+#define SPR_8349_REV31			0x80310300
+#define SPR_8347E_REV31_TBGA		0x80320300
+#define SPR_8347_REV31_TBGA		0x80330300
+#define SPR_8347E_REV31_PBGA		0x80340300
+#define SPR_8347_REV31_PBGA		0x80350300
+#define SPR_8343E_REV31			0x80360300
+#define SPR_8343_REV31			0x80370300
+
+#define SPR_8360E_REV10			0x80480010
+#define SPR_8360_REV10			0x80490010
+#define SPR_8360E_REV11			0x80480011
+#define SPR_8360_REV11			0x80490011
+#define SPR_8360E_REV12			0x80480012
+#define SPR_8360_REV12			0x80490012
+#define SPR_8360E_REV20			0x80480020
+#define SPR_8360_REV20			0x80490020
+
+#define SPR_8323E_REV10			0x80620010
+#define SPR_8323_REV10			0x80630010
+#define SPR_8321E_REV10			0x80660010
+#define SPR_8321_REV10			0x80670010
+#define SPR_8323E_REV11			0x80620011
+#define SPR_8323_REV11			0x80630011
+#define SPR_8321E_REV11			0x80660011
+#define SPR_8321_REV11			0x80670011
+
+/* SPCR - System Priority Configuration Register
  */
-#define SWCRR      0x0204
-#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
-#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
-#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */
-#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
-#define SWCRR_RES  ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+#define SPCR_PCIHPE			0x10000000	/* PCI Highest Priority Enable */
+#define SPCR_PCIHPE_SHIFT		(31-3)
+#define SPCR_PCIPR			0x03000000	/* PCI bridge system bus request priority */
+#define SPCR_PCIPR_SHIFT		(31-7)
+#define SPCR_OPT			0x00800000	/* Optimize */
+#define SPCR_TBEN			0x00400000	/* E300 PowerPC core time base unit enable */
+#define SPCR_TBEN_SHIFT			(31-9)
+#define SPCR_COREPR			0x00300000	/* E300 PowerPC Core system bus request priority */
+#define SPCR_COREPR_SHIFT		(31-11)
+
+#if defined(CONFIG_MPC834X)
+/* SPCR bits - MPC8349 specific */
+#define SPCR_TSEC1DP			0x00003000	/* TSEC1 data priority */
+#define SPCR_TSEC1DP_SHIFT		(31-19)
+#define SPCR_TSEC1BDP			0x00000C00	/* TSEC1 buffer descriptor priority */
+#define SPCR_TSEC1BDP_SHIFT		(31-21)
+#define SPCR_TSEC1EP			0x00000300	/* TSEC1 emergency priority */
+#define SPCR_TSEC1EP_SHIFT		(31-23)
+#define SPCR_TSEC2DP			0x00000030	/* TSEC2 data priority */
+#define SPCR_TSEC2DP_SHIFT		(31-27)
+#define SPCR_TSEC2BDP			0x0000000C	/* TSEC2 buffer descriptor priority */
+#define SPCR_TSEC2BDP_SHIFT		(31-29)
+#define SPCR_TSEC2EP			0x00000003	/* TSEC2 emergency priority */
+#define SPCR_TSEC2EP_SHIFT		(31-31)
+#endif
 
-#define SWCNR      0x0208
-#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
-#define SWCNR_RES  ~(SWCNR_SWCN)
+/* SICRL/H - System I/O Configuration Register Low/High
+ */
+#if defined(CONFIG_MPC834X)
+/* SICRL bits - MPC8349 specific */
+#define SICRL_LDP_A			0x80000000
+#define SICRL_USB1			0x40000000
+#define SICRL_USB0			0x20000000
+#define SICRL_UART			0x0C000000
+#define SICRL_GPIO1_A			0x02000000
+#define SICRL_GPIO1_B			0x01000000
+#define SICRL_GPIO1_C			0x00800000
+#define SICRL_GPIO1_D			0x00400000
+#define SICRL_GPIO1_E			0x00200000
+#define SICRL_GPIO1_F			0x00180000
+#define SICRL_GPIO1_G			0x00040000
+#define SICRL_GPIO1_H			0x00020000
+#define SICRL_GPIO1_I			0x00010000
+#define SICRL_GPIO1_J			0x00008000
+#define SICRL_GPIO1_K			0x00004000
+#define SICRL_GPIO1_L			0x00003000
+
+/* SICRH bits - MPC8349 specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_TSEC1_A			0x10000000
+#define SICRH_TSEC1_B			0x08000000
+#define SICRH_TSEC1_C			0x04000000
+#define SICRH_TSEC1_D			0x02000000
+#define SICRH_TSEC1_E			0x01000000
+#define SICRH_TSEC1_F			0x00800000
+#define SICRH_TSEC2_A			0x00400000
+#define SICRH_TSEC2_B			0x00200000
+#define SICRH_TSEC2_C			0x00100000
+#define SICRH_TSEC2_D			0x00080000
+#define SICRH_TSEC2_E			0x00040000
+#define SICRH_TSEC2_F			0x00020000
+#define SICRH_TSEC2_G			0x00010000
+#define SICRH_TSEC2_H			0x00008000
+#define SICRH_GPIO2_A			0x00004000
+#define SICRH_GPIO2_B			0x00002000
+#define SICRH_GPIO2_C			0x00001000
+#define SICRH_GPIO2_D			0x00000800
+#define SICRH_GPIO2_E			0x00000400
+#define SICRH_GPIO2_F			0x00000200
+#define SICRH_GPIO2_G			0x00000180
+#define SICRH_GPIO2_H			0x00000060
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
+#elif defined(CONFIG_MPC8360)
+/* SICRL bits - MPC8360 specific */
+#define SICRL_LDP_A			0xC0000000
+#define SICRL_LCLK_1			0x10000000
+#define SICRL_LCLK_2			0x08000000
+#define SICRL_SRCID_A			0x03000000
+#define SICRL_IRQ_CKSTP_A		0x00C00000
+
+/* SICRH bits - MPC8360 specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_SECONDARY_DDR		0x40000000
+#define SICRH_SDDROE			0x20000000
+#define SICRH_IRQ3			0x10000000
+#define SICRH_UC1EOBI			0x00000004
+#define SICRH_UC2E1OBI			0x00000002
+#define SICRH_UC2E2OBI			0x00000001
+
+#elif defined(CONFIG_MPC832X)
+/* SICRL bits - MPC832X specific */
+#define SICRL_LDP_LCS_A			0x80000000
+#define SICRL_IRQ_CKS			0x20000000
+#define SICRL_PCI_MSRC			0x10000000
+#define SICRL_URT_CTPR			0x06000000
+#define SICRL_IRQ_CTPR			0x00C00000
+#endif
 
-#define SWSRR      0x020E
+/* SWCRR - System Watchdog Control Register
+ */
+#define SWCRR				0x0204		/* Register offset to immr */
+#define SWCRR_SWTC			0xFFFF0000	/* Software Watchdog Time Count */
+#define SWCRR_SWEN			0x00000004	/* Watchdog Enable bit */
+#define SWCRR_SWRI			0x00000002	/* Software Watchdog Reset/Interrupt Select bit */
+#define SWCRR_SWPR			0x00000001	/* Software Watchdog Counter Prescale bit */
+#define SWCRR_RES			~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+
+/* SWCNR - System Watchdog Counter Register
+ */
+#define SWCNR				0x0208		/* Register offset to immr */
+#define SWCNR_SWCN			0x0000FFFF	/* Software Watchdog Count mask */
+#define SWCNR_RES			~(SWCNR_SWCN)
 
-/*
- * Default Internal Memory Register Space (Freescale recomandation)
+/* SWSRR - System Watchdog Service Register
  */
-#define IMMRBAR 0x0000
-#define IMMRBAR_BASE_ADDR     0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */
-#define IMMRBAR_RES           ~(IMMRBAR_BASE_ADDR)
+#define SWSRR				0x020E		/* Register offset to immr */
 
-/*
- * Default Internal Memory Register Space (Freescale recomandation)
+/* ACR - Arbiter Configuration Register
+ */
+#define ACR_COREDIS			0x10000000	/* Core disable */
+#define ACR_COREDIS_SHIFT		(31-7)
+#define ACR_PIPE_DEP			0x00070000	/* Pipeline depth */
+#define ACR_PIPE_DEP_SHIFT		(31-15)
+#define ACR_PCI_RPTCNT			0x00007000	/* PCI repeat count */
+#define ACR_PCI_RPTCNT_SHIFT		(31-19)
+#define ACR_RPTCNT			0x00000700	/* Repeat count */
+#define ACR_RPTCNT_SHIFT		(31-23)
+#define ACR_APARK			0x00000030	/* Address parking */
+#define ACR_APARK_SHIFT			(31-27)
+#define ACR_PARKM			0x0000000F	/* Parking master */
+#define ACR_PARKM_SHIFT			(31-31)
+
+/* ATR - Arbiter Timers Register
  */
-#define LBLAWBAR0 0x0020
-#define LBLAWAR0  0x0024
-#define LBLAWBAR1 0x0028
-#define LBLAWAR1  0x002C
-#define LBLAWBAR2 0x0030
-#define LBLAWAR2  0x0034
-#define LBLAWBAR3 0x0038
-#define LBLAWAR3  0x003C
+#define ATR_DTO				0x00FF0000	/* Data time out */
+#define ATR_ATO				0x000000FF	/* Address time out */
 
+/* AER - Arbiter Event Register
+ */
+#define AER_ETEA			0x00000020	/* Transfer error */
+#define AER_RES				0x00000010	/* Reserved transfer type */
+#define AER_ECW				0x00000008	/* External control word transfer type */
+#define AER_AO				0x00000004	/* Address Only transfer type */
+#define AER_DTO				0x00000002	/* Data time out */
+#define AER_ATO				0x00000001	/* Address time out */
+
+/* AEATR - Arbiter Event Address Register
+ */
+#define AEATR_EVENT			0x07000000	/* Event type */
+#define AEATR_MSTR_ID			0x001F0000	/* Master Id */
+#define AEATR_TBST			0x00000800	/* Transfer burst */
+#define AEATR_TSIZE			0x00000700	/* Transfer Size */
+#define AEATR_TTYPE			0x0000001F	/* Transfer Type */
 
-/*
- * Base Registers & Option Registers
- */
-#define BR0 0x5000
-#define BR1 0x5008
-#define BR2 0x5010
-#define BR3 0x5018
-#define BR4 0x5020
-#define BR5 0x5028
-#define BR6 0x5030
-#define BR7 0x5038
-
-#define BR_BA		0xFFFF8000
-#define BR_BA_SHIFT		15
-#define BR_PS		0x00001800
-#define BR_PS_SHIFT		11
-#define BR_PS_8		0x00000800  /* Port Size 8 bit */
-#define BR_PS_16	0x00001000  /* Port Size 16 bit */
-#define BR_PS_32	0x00001800  /* Port Size 32 bit */
-#define BR_DECC		0x00000600
-#define BR_DECC_SHIFT		 9
-#define BR_WP		0x00000100
-#define BR_WP_SHIFT		 8
-#define BR_MSEL		0x000000E0
-#define BR_MSEL_SHIFT		 5
-#define BR_MS_GPCM	0x00000000  /* GPCM */
-#define BR_MS_SDRAM	0x00000060  /* SDRAM */
-#define BR_MS_UPMA	0x00000080  /* UPMA */
-#define BR_MS_UPMB	0x000000A0  /* UPMB */
-#define BR_MS_UPMC	0x000000C0  /* UPMC */
-#define BR_V		0x00000001
-#define BR_V_SHIFT		 0
-#define BR_RES		~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
-
-#define OR0 0x5004
-#define OR1 0x500C
-#define OR2 0x5014
-#define OR3 0x501C
-#define OR4 0x5024
-#define OR5 0x502C
-#define OR6 0x5034
-#define OR7 0x503C
-
-#define OR_GPCM_AM		0xFFFF8000
-#define OR_GPCM_AM_SHIFT		15
-#define OR_GPCM_BCTLD		0x00001000
-#define OR_GPCM_BCTLD_SHIFT		12
-#define OR_GPCM_CSNT		0x00000800
-#define OR_GPCM_CSNT_SHIFT		11
-#define OR_GPCM_ACS		0x00000600
-#define OR_GPCM_ACS_SHIFT		 9
-#define OR_GPCM_ACS_0b10	0x00000400
-#define OR_GPCM_ACS_0b11	0x00000600
-#define OR_GPCM_XACS		0x00000100
-#define OR_GPCM_XACS_SHIFT		 8
-#define OR_GPCM_SCY		0x000000F0
-#define OR_GPCM_SCY_SHIFT		 4
-#define OR_GPCM_SCY_1		0x00000010
-#define OR_GPCM_SCY_2		0x00000020
-#define OR_GPCM_SCY_3		0x00000030
-#define OR_GPCM_SCY_4		0x00000040
-#define OR_GPCM_SCY_5		0x00000050
-#define OR_GPCM_SCY_6		0x00000060
-#define OR_GPCM_SCY_7		0x00000070
-#define OR_GPCM_SCY_8		0x00000080
-#define OR_GPCM_SCY_9		0x00000090
-#define OR_GPCM_SCY_10		0x000000a0
-#define OR_GPCM_SCY_11		0x000000b0
-#define OR_GPCM_SCY_12		0x000000c0
-#define OR_GPCM_SCY_13		0x000000d0
-#define OR_GPCM_SCY_14		0x000000e0
-#define OR_GPCM_SCY_15		0x000000f0
-#define OR_GPCM_SETA		0x00000008
-#define OR_GPCM_SETA_SHIFT		 3
-#define OR_GPCM_TRLX		0x00000004
-#define OR_GPCM_TRLX_SHIFT		 2
-#define OR_GPCM_EHTR		0x00000002
-#define OR_GPCM_EHTR_SHIFT		 1
-#define OR_GPCM_EAD		0x00000001
-#define OR_GPCM_EAD_SHIFT		 0
-
-#define OR_UPM_AM    0xFFFF8000
-#define OR_UPM_AM_SHIFT      15
-#define OR_UPM_XAM   0x00006000
-#define OR_UPM_XAM_SHIFT     13
-#define OR_UPM_BCTLD 0x00001000
-#define OR_UPM_BCTLD_SHIFT   12
-#define OR_UPM_BI    0x00000100
-#define OR_UPM_BI_SHIFT       8
-#define OR_UPM_TRLX  0x00000004
-#define OR_UPM_TRLX_SHIFT     2
-#define OR_UPM_EHTR  0x00000002
-#define OR_UPM_EHTR_SHIFT     1
-#define OR_UPM_EAD   0x00000001
-#define OR_UPM_EAD_SHIFT      0
-
-#define OR_SDRAM_AM    0xFFFF8000
-#define OR_SDRAM_AM_SHIFT      15
-#define OR_SDRAM_XAM   0x00006000
-#define OR_SDRAM_XAM_SHIFT     13
-#define OR_SDRAM_COLS  0x00001C00
-#define OR_SDRAM_COLS_SHIFT    10
-#define OR_SDRAM_ROWS  0x000001C0
-#define OR_SDRAM_ROWS_SHIFT     6
-#define OR_SDRAM_PMSEL 0x00000020
-#define OR_SDRAM_PMSEL_SHIFT    5
-#define OR_SDRAM_EAD   0x00000001
-#define OR_SDRAM_EAD_SHIFT      0
+/* HRCWL - Hard Reset Configuration Word Low
+ */
+#define HRCWL_LBIUCM			0x80000000
+#define HRCWL_LBIUCM_SHIFT		31
+#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1	0x00000000
+#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1	0x80000000
+
+#define HRCWL_DDRCM			0x40000000
+#define HRCWL_DDRCM_SHIFT		30
+#define HRCWL_DDR_TO_SCB_CLK_1X1	0x00000000
+#define HRCWL_DDR_TO_SCB_CLK_2X1	0x40000000
+
+#define HRCWL_SPMF			0x0f000000
+#define HRCWL_SPMF_SHIFT		24
+#define HRCWL_CSB_TO_CLKIN_16X1		0x00000000
+#define HRCWL_CSB_TO_CLKIN_1X1		0x01000000
+#define HRCWL_CSB_TO_CLKIN_2X1		0x02000000
+#define HRCWL_CSB_TO_CLKIN_3X1		0x03000000
+#define HRCWL_CSB_TO_CLKIN_4X1		0x04000000
+#define HRCWL_CSB_TO_CLKIN_5X1		0x05000000
+#define HRCWL_CSB_TO_CLKIN_6X1		0x06000000
+#define HRCWL_CSB_TO_CLKIN_7X1		0x07000000
+#define HRCWL_CSB_TO_CLKIN_8X1		0x08000000
+#define HRCWL_CSB_TO_CLKIN_9X1		0x09000000
+#define HRCWL_CSB_TO_CLKIN_10X1		0x0A000000
+#define HRCWL_CSB_TO_CLKIN_11X1		0x0B000000
+#define HRCWL_CSB_TO_CLKIN_12X1		0x0C000000
+#define HRCWL_CSB_TO_CLKIN_13X1		0x0D000000
+#define HRCWL_CSB_TO_CLKIN_14X1		0x0E000000
+#define HRCWL_CSB_TO_CLKIN_15X1		0x0F000000
+
+#define HRCWL_VCO_BYPASS		0x00000000
+#define HRCWL_VCO_1X2			0x00000000
+#define HRCWL_VCO_1X4			0x00200000
+#define HRCWL_VCO_1X8			0x00400000
+
+#define HRCWL_COREPLL			0x007F0000
+#define HRCWL_COREPLL_SHIFT		16
+#define HRCWL_CORE_TO_CSB_BYPASS	0x00000000
+#define HRCWL_CORE_TO_CSB_1X1		0x00020000
+#define HRCWL_CORE_TO_CSB_1_5X1		0x00030000
+#define HRCWL_CORE_TO_CSB_2X1		0x00040000
+#define HRCWL_CORE_TO_CSB_2_5X1		0x00050000
+#define HRCWL_CORE_TO_CSB_3X1		0x00060000
+
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#define HRCWL_CEVCOD			0x000000C0
+#define HRCWL_CEVCOD_SHIFT		6
+#define HRCWL_CE_PLL_VCO_DIV_4		0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_8		0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_2		0x00000080
+
+#define HRCWL_CEPDF			0x00000020
+#define HRCWL_CEPDF_SHIFT		5
+#define HRCWL_CE_PLL_DIV_1X1		0x00000000
+#define HRCWL_CE_PLL_DIV_2X1		0x00000020
+
+#define HRCWL_CEPMF			0x0000001F
+#define HRCWL_CEPMF_SHIFT		0
+#define HRCWL_CE_TO_PLL_1X16_		0x00000000
+#define HRCWL_CE_TO_PLL_1X2		0x00000002
+#define HRCWL_CE_TO_PLL_1X3		0x00000003
+#define HRCWL_CE_TO_PLL_1X4		0x00000004
+#define HRCWL_CE_TO_PLL_1X5		0x00000005
+#define HRCWL_CE_TO_PLL_1X6		0x00000006
+#define HRCWL_CE_TO_PLL_1X7		0x00000007
+#define HRCWL_CE_TO_PLL_1X8		0x00000008
+#define HRCWL_CE_TO_PLL_1X9		0x00000009
+#define HRCWL_CE_TO_PLL_1X10		0x0000000A
+#define HRCWL_CE_TO_PLL_1X11		0x0000000B
+#define HRCWL_CE_TO_PLL_1X12		0x0000000C
+#define HRCWL_CE_TO_PLL_1X13		0x0000000D
+#define HRCWL_CE_TO_PLL_1X14		0x0000000E
+#define HRCWL_CE_TO_PLL_1X15		0x0000000F
+#define HRCWL_CE_TO_PLL_1X16		0x00000010
+#define HRCWL_CE_TO_PLL_1X17		0x00000011
+#define HRCWL_CE_TO_PLL_1X18		0x00000012
+#define HRCWL_CE_TO_PLL_1X19		0x00000013
+#define HRCWL_CE_TO_PLL_1X20		0x00000014
+#define HRCWL_CE_TO_PLL_1X21		0x00000015
+#define HRCWL_CE_TO_PLL_1X22		0x00000016
+#define HRCWL_CE_TO_PLL_1X23		0x00000017
+#define HRCWL_CE_TO_PLL_1X24		0x00000018
+#define HRCWL_CE_TO_PLL_1X25		0x00000019
+#define HRCWL_CE_TO_PLL_1X26		0x0000001A
+#define HRCWL_CE_TO_PLL_1X27		0x0000001B
+#define HRCWL_CE_TO_PLL_1X28		0x0000001C
+#define HRCWL_CE_TO_PLL_1X29		0x0000001D
+#define HRCWL_CE_TO_PLL_1X30		0x0000001E
+#define HRCWL_CE_TO_PLL_1X31		0x0000001F
+#endif
 
-/*
- * Hard Reset Configration Word - High
+/* HRCWH - Hardware Reset Configuration Word High
  */
-#define HRCWH_PCI_AGENT              0x00000000
-#define HRCWH_PCI_HOST               0x80000000
+#define HRCWH_PCI_HOST			0x80000000
+#define HRCWH_PCI_HOST_SHIFT		31
+#define HRCWH_PCI_AGENT			0x00000000
 
-#define HRCWH_32_BIT_PCI             0x00000000
-#define HRCWH_64_BIT_PCI             0x40000000
+#if defined(CONFIG_MPC834X)
+#define HRCWH_32_BIT_PCI		0x00000000
+#define HRCWH_64_BIT_PCI		0x40000000
+#endif
 
-#define HRCWH_PCI1_ARBITER_DISABLE   0x00000000
-#define HRCWH_PCI1_ARBITER_ENABLE    0x20000000
+#define HRCWH_PCI1_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI1_ARBITER_ENABLE	0x20000000
 
-#define HRCWH_PCI2_ARBITER_DISABLE   0x00000000
-#define HRCWH_PCI2_ARBITER_ENABLE    0x10000000
+#define HRCWH_PCI_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI_ARBITER_ENABLE	0x20000000
 
-#define HRCWH_CORE_DISABLE           0x08000000
-#define HRCWH_CORE_ENABLE            0x00000000
+#if defined(CONFIG_MPC834X)
+#define HRCWH_PCI2_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI2_ARBITER_ENABLE	0x10000000
 
-#define HRCWH_FROM_0X00000100        0x00000000
-#define HRCWH_FROM_0XFFF00100        0x04000000
+#elif defined(CONFIG_MPC8360)
+#define HRCWH_PCICKDRV_DISABLE		0x00000000
+#define HRCWH_PCICKDRV_ENABLE		0x10000000
+#endif
 
-#define HRCWH_BOOTSEQ_DISABLE        0x00000000
-#define HRCWH_BOOTSEQ_NORMAL         0x01000000
-#define HRCWH_BOOTSEQ_EXTENDED       0x02000000
+#define HRCWH_CORE_DISABLE		0x08000000
+#define HRCWH_CORE_ENABLE		0x00000000
 
-#define HRCWH_SW_WATCHDOG_DISABLE    0x00000000
-#define HRCWH_SW_WATCHDOG_ENABLE     0x00800000
+#define HRCWH_FROM_0X00000100		0x00000000
+#define HRCWH_FROM_0XFFF00100		0x04000000
 
-#define HRCWH_ROM_LOC_DDR_SDRAM      0x00000000
-#define HRCWH_ROM_LOC_PCI1           0x00100000
-#define HRCWH_ROM_LOC_PCI2           0x00200000
-#define HRCWH_ROM_LOC_LOCAL_8BIT     0x00500000
-#define HRCWH_ROM_LOC_LOCAL_16BIT    0x00600000
-#define HRCWH_ROM_LOC_LOCAL_32BIT    0x00700000
+#define HRCWH_BOOTSEQ_DISABLE		0x00000000
+#define HRCWH_BOOTSEQ_NORMAL		0x01000000
+#define HRCWH_BOOTSEQ_EXTENDED		0x02000000
 
-#define HRCWH_TSEC1M_IN_RGMII        0x00000000
-#define HRCWH_TSEC1M_IN_RTBI         0x00004000
-#define HRCWH_TSEC1M_IN_GMII         0x00008000
-#define HRCWH_TSEC1M_IN_TBI          0x0000C000
+#define HRCWH_SW_WATCHDOG_DISABLE	0x00000000
+#define HRCWH_SW_WATCHDOG_ENABLE	0x00800000
 
-#define HRCWH_TSEC2M_IN_RGMII        0x00000000
-#define HRCWH_TSEC2M_IN_RTBI         0x00001000
-#define HRCWH_TSEC2M_IN_GMII         0x00002000
-#define HRCWH_TSEC2M_IN_TBI          0x00003000
+#define HRCWH_ROM_LOC_DDR_SDRAM		0x00000000
+#define HRCWH_ROM_LOC_PCI1		0x00100000
+#if defined(CONFIG_MPC834X)
+#define HRCWH_ROM_LOC_PCI2		0x00200000
+#endif
+#define HRCWH_ROM_LOC_LOCAL_8BIT	0x00500000
+#define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
+#define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
+
+#if defined(CONFIG_MPC834X)
+#define HRCWH_TSEC1M_IN_RGMII		0x00000000
+#define HRCWH_TSEC1M_IN_RTBI		0x00004000
+#define HRCWH_TSEC1M_IN_GMII		0x00008000
+#define HRCWH_TSEC1M_IN_TBI		0x0000C000
+#define HRCWH_TSEC2M_IN_RGMII		0x00000000
+#define HRCWH_TSEC2M_IN_RTBI		0x00001000
+#define HRCWH_TSEC2M_IN_GMII		0x00002000
+#define HRCWH_TSEC2M_IN_TBI		0x00003000
+#endif
+
+#if defined(CONFIG_MPC8360)
+#define HRCWH_SECONDARY_DDR_DISABLE	0x00000000
+#define HRCWH_SECONDARY_DDR_ENABLE	0x00000010
+#endif
 
-#define HRCWH_BIG_ENDIAN             0x00000000
-#define HRCWH_LITTLE_ENDIAN          0x00000008
+#define HRCWH_BIG_ENDIAN		0x00000000
+#define HRCWH_LITTLE_ENDIAN		0x00000008
 
-/*
- * Hard Reset Configration Word - Low
- */
-#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
-#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
-
-#define HRCWL_DDR_TO_SCB_CLK_1X1     0x00000000
-#define HRCWL_DDR_TO_SCB_CLK_2X1     0x40000000
-
-#define HRCWL_CSB_TO_CLKIN_16X1      0x00000000
-#define HRCWL_CSB_TO_CLKIN_1X1       0x01000000
-#define HRCWL_CSB_TO_CLKIN_2X1       0x02000000
-#define HRCWL_CSB_TO_CLKIN_3X1       0x03000000
-#define HRCWL_CSB_TO_CLKIN_4X1       0x04000000
-#define HRCWL_CSB_TO_CLKIN_5X1       0x05000000
-#define HRCWL_CSB_TO_CLKIN_6X1       0x06000000
-#define HRCWL_CSB_TO_CLKIN_7X1       0x07000000
-#define HRCWL_CSB_TO_CLKIN_8X1       0x08000000
-#define HRCWL_CSB_TO_CLKIN_9X1       0x09000000
-#define HRCWL_CSB_TO_CLKIN_10X1      0x0A000000
-#define HRCWL_CSB_TO_CLKIN_11X1      0x0B000000
-#define HRCWL_CSB_TO_CLKIN_12X1      0x0C000000
-#define HRCWL_CSB_TO_CLKIN_13X1      0x0D000000
-#define HRCWL_CSB_TO_CLKIN_14X1      0x0E000000
-#define HRCWL_CSB_TO_CLKIN_15X1      0x0F000000
-
-#define HRCWL_VCO_BYPASS             0x00000000
-#define HRCWL_VCO_1X2                0x00000000
-#define HRCWL_VCO_1X4                0x00200000
-#define HRCWL_VCO_1X8                0x00400000
-
-#define HRCWL_CORE_TO_CSB_BYPASS     0x00000000
-#define HRCWL_CORE_TO_CSB_1X1        0x00020000
-#define HRCWL_CORE_TO_CSB_1_5X1      0x00030000
-#define HRCWL_CORE_TO_CSB_2X1        0x00040000
-#define HRCWL_CORE_TO_CSB_2_5X1      0x00050000
-#define HRCWL_CORE_TO_CSB_3X1        0x00060000
+#define HRCWH_LALE_NORMAL		0x00000000
+#define HRCWH_LALE_EARLY		0x00000004
 
-/*
- * LCRR - Clock Ratio Register (10.3.1.16)
- */
-#define LCRR_DBYP      0x80000000
-#define LCRR_DBYP_SHIFT        31
-#define LCRR_BUFCMDC   0x30000000
-#define LCRR_BUFCMDC_1 0x10000000
-#define LCRR_BUFCMDC_2 0x20000000
-#define LCRR_BUFCMDC_3 0x30000000
-#define LCRR_BUFCMDC_4 0x00000000
-#define LCRR_BUFCMDC_SHIFT     28
-#define LCRR_ECL       0x03000000
-#define LCRR_ECL_4     0x00000000
-#define LCRR_ECL_5     0x01000000
-#define LCRR_ECL_6     0x02000000
-#define LCRR_ECL_7     0x03000000
-#define LCRR_ECL_SHIFT         24
-#define LCRR_EADC      0x00030000
-#define LCRR_EADC_1    0x00010000
-#define LCRR_EADC_2    0x00020000
-#define LCRR_EADC_3    0x00030000
-#define LCRR_EADC_4    0x00000000
-#define LCRR_EADC_SHIFT        16
-#define LCRR_CLKDIV    0x0000000F
-#define LCRR_CLKDIV_2  0x00000002
-#define LCRR_CLKDIV_4  0x00000004
-#define LCRR_CLKDIV_8  0x00000008
-#define LCRR_CLKDIV_SHIFT       0
+#define HRCWH_LDP_SET			0x00000000
+#define HRCWH_LDP_CLEAR			0x00000002
+
+/* RSR - Reset Status Register
+ */
+#define RSR_RSTSRC			0xE0000000	/* Reset source */
+#define RSR_RSTSRC_SHIFT		29
+#define RSR_BSF				0x00010000	/* Boot seq. fail */
+#define RSR_BSF_SHIFT			16
+#define RSR_SWSR			0x00002000	/* software soft reset */
+#define RSR_SWSR_SHIFT			13
+#define RSR_SWHR			0x00001000	/* software hard reset */
+#define RSR_SWHR_SHIFT			12
+#define RSR_JHRS			0x00000200	/* jtag hreset */
+#define RSR_JHRS_SHIFT			9
+#define RSR_JSRS			0x00000100	/* jtag sreset status */
+#define RSR_JSRS_SHIFT			8
+#define RSR_CSHR			0x00000010	/* checkstop reset status */
+#define RSR_CSHR_SHIFT			4
+#define RSR_SWRS			0x00000008	/* software watchdog reset status */
+#define RSR_SWRS_SHIFT			3
+#define RSR_BMRS			0x00000004	/* bus monitop reset status */
+#define RSR_BMRS_SHIFT			2
+#define RSR_SRS				0x00000002	/* soft reset status */
+#define RSR_SRS_SHIFT			1
+#define RSR_HRS				0x00000001	/* hard reset status */
+#define RSR_HRS_SHIFT			0
+#define RSR_RES				~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
+					 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
+					 RSR_BMRS | RSR_SRS | RSR_HRS)
+/* RMR - Reset Mode Register
+ */
+#define RMR_CSRE			0x00000001	/* checkstop reset enable */
+#define RMR_CSRE_SHIFT			0
+#define RMR_RES				~(RMR_CSRE)
+
+/* RCR - Reset Control Register
+ */
+#define RCR_SWHR			0x00000002	/* software hard reset */
+#define RCR_SWSR			0x00000001	/* software soft reset */
+#define RCR_RES				~(RCR_SWHR | RCR_SWSR)
+
+/* RCER - Reset Control Enable Register
+ */
+#define RCER_CRE			0x00000001	/* software hard reset */
+#define RCER_RES			~(RCER_CRE)
+
+/* SPMR - System PLL Mode Register
+ */
+#define SPMR_LBIUCM			0x80000000
+#define SPMR_DDRCM			0x40000000
+#define SPMR_SPMF			0x0F000000
+#define SPMR_CKID			0x00800000
+#define SPMR_CKID_SHIFT			23
+#define SPMR_COREPLL			0x007F0000
+#define SPMR_CEVCOD			0x000000C0
+#define SPMR_CEPDF			0x00000020
+#define SPMR_CEPMF			0x0000001F
+
+/* OCCR - Output Clock Control Register
+ */
+#define OCCR_PCICOE0			0x80000000
+#define OCCR_PCICOE1			0x40000000
+#define OCCR_PCICOE2			0x20000000
+#define OCCR_PCICOE3			0x10000000
+#define OCCR_PCICOE4			0x08000000
+#define OCCR_PCICOE5			0x04000000
+#define OCCR_PCICOE6			0x02000000
+#define OCCR_PCICOE7			0x01000000
+#define OCCR_PCICD0			0x00800000
+#define OCCR_PCICD1			0x00400000
+#define OCCR_PCICD2			0x00200000
+#define OCCR_PCICD3			0x00100000
+#define OCCR_PCICD4			0x00080000
+#define OCCR_PCICD5			0x00040000
+#define OCCR_PCICD6			0x00020000
+#define OCCR_PCICD7			0x00010000
+#define OCCR_PCI1CR			0x00000002
+#define OCCR_PCI2CR			0x00000001
+#define OCCR_PCICR			OCCR_PCI1CR
+
+/* SCCR - System Clock Control Register
+ */
+#define SCCR_ENCCM			0x03000000
+#define SCCR_ENCCM_SHIFT		24
+#define SCCR_ENCCM_0			0x00000000
+#define SCCR_ENCCM_1			0x01000000
+#define SCCR_ENCCM_2			0x02000000
+#define SCCR_ENCCM_3			0x03000000
+
+#define SCCR_PCICM			0x00010000
+#define SCCR_PCICM_SHIFT		16
+
+/* SCCR bits - MPC8349 specific */
+#ifdef CONFIG_MPC834X
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+#endif
+
+#define SCCR_USBMPHCM			0x00c00000
+#define SCCR_USBMPHCM_SHIFT		22
+#define SCCR_USBDRCM			0x00300000
+#define SCCR_USBDRCM_SHIFT		20
+
+#define SCCR_USBCM_0			0x00000000
+#define SCCR_USBCM_1			0x00500000
+#define SCCR_USBCM_2			0x00A00000
+#define SCCR_USBCM_3			0x00F00000
+
+/* CSn_BDNS - Chip Select memory Bounds Register
+ */
+#define CSBNDS_SA			0x00FF0000
+#define CSBNDS_SA_SHIFT			8
+#define CSBNDS_EA			0x000000FF
+#define CSBNDS_EA_SHIFT			24
+
+/* CSn_CONFIG - Chip Select Configuration Register
+ */
+#define CSCONFIG_EN			0x80000000
+#define CSCONFIG_AP			0x00800000
+#define CSCONFIG_ROW_BIT		0x00000700
+#define CSCONFIG_ROW_BIT_12		0x00000000
+#define CSCONFIG_ROW_BIT_13		0x00000100
+#define CSCONFIG_ROW_BIT_14		0x00000200
+#define CSCONFIG_COL_BIT		0x00000007
+#define CSCONFIG_COL_BIT_8		0x00000000
+#define CSCONFIG_COL_BIT_9		0x00000001
+#define CSCONFIG_COL_BIT_10		0x00000002
+#define CSCONFIG_COL_BIT_11		0x00000003
+
+/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
+ */
+#define TIMING_CFG1_PRETOACT		0x70000000
+#define TIMING_CFG1_PRETOACT_SHIFT	28
+#define TIMING_CFG1_ACTTOPRE		0x0F000000
+#define TIMING_CFG1_ACTTOPRE_SHIFT	24
+#define TIMING_CFG1_ACTTORW		0x00700000
+#define TIMING_CFG1_ACTTORW_SHIFT	20
+#define TIMING_CFG1_CASLAT		0x00070000
+#define TIMING_CFG1_CASLAT_SHIFT	16
+#define TIMING_CFG1_REFREC		0x0000F000
+#define TIMING_CFG1_REFREC_SHIFT	12
+#define TIMING_CFG1_WRREC		0x00000700
+#define TIMING_CFG1_WRREC_SHIFT		8
+#define TIMING_CFG1_ACTTOACT		0x00000070
+#define TIMING_CFG1_ACTTOACT_SHIFT	4
+#define TIMING_CFG1_WRTORD		0x00000007
+#define TIMING_CFG1_WRTORD_SHIFT	0
+#define TIMING_CFG1_CASLAT_20		0x00030000	/* CAS latency = 2.0 */
+#define TIMING_CFG1_CASLAT_25		0x00040000	/* CAS latency = 2.5 */
+
+/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
+ */
+#define TIMING_CFG2_CPO			0x0F800000
+#define TIMING_CFG2_CPO_SHIFT		23
+#define TIMING_CFG2_ACSM		0x00080000
+#define TIMING_CFG2_WR_DATA_DELAY	0x00001C00
+#define TIMING_CFG2_WR_DATA_DELAY_SHIFT	10
+#define TIMING_CFG2_CPO_DEF		0x00000000	/* default (= CASLAT + 1) */
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG_SREN			0x40000000
+#define SDRAM_CFG_ECC_EN		0x20000000
+#define SDRAM_CFG_RD_EN			0x10000000
+#define SDRAM_CFG_SDRAM_TYPE		0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
+#define SDRAM_CFG_DYN_PWR		0x00200000
+#define SDRAM_CFG_32_BE			0x00080000
+#define SDRAM_CFG_8_BE			0x00040000
+#define SDRAM_CFG_NCAP			0x00020000
+#define SDRAM_CFG_2T_EN			0x00008000
+#define SDRAM_CFG_SDRAM_TYPE_DDR	0x02000000
+
+/* DDR_SDRAM_MODE - DDR SDRAM Mode Register
+ */
+#define SDRAM_MODE_ESD			0xFFFF0000
+#define SDRAM_MODE_ESD_SHIFT		16
+#define SDRAM_MODE_SD			0x0000FFFF
+#define SDRAM_MODE_SD_SHIFT		0
+#define DDR_MODE_EXT_MODEREG		0x4000		/* select extended mode reg */
+#define DDR_MODE_EXT_OPMODE		0x3FF8		/* operating mode, mask */
+#define DDR_MODE_EXT_OP_NORMAL		0x0000		/* normal operation */
+#define DDR_MODE_QFC			0x0004		/* QFC / compatibility, mask */
+#define DDR_MODE_QFC_COMP		0x0000		/* compatible to older SDRAMs */
+#define DDR_MODE_WEAK			0x0002		/* weak drivers */
+#define DDR_MODE_DLL_DIS		0x0001		/* disable DLL */
+#define DDR_MODE_CASLAT			0x0070		/* CAS latency, mask */
+#define DDR_MODE_CASLAT_15		0x0010		/* CAS latency 1.5 */
+#define DDR_MODE_CASLAT_20		0x0020		/* CAS latency 2 */
+#define DDR_MODE_CASLAT_25		0x0060		/* CAS latency 2.5 */
+#define DDR_MODE_CASLAT_30		0x0030		/* CAS latency 3 */
+#define DDR_MODE_BTYPE_SEQ		0x0000		/* sequential burst */
+#define DDR_MODE_BTYPE_ILVD		0x0008		/* interleaved burst */
+#define DDR_MODE_BLEN_2			0x0001		/* burst length 2 */
+#define DDR_MODE_BLEN_4			0x0002		/* burst length 4 */
+#define DDR_REFINT_166MHZ_7US		1302		/* exact value for 7.8125us */
+#define DDR_BSTOPRE			256		/* use 256 cycles as a starting point */
+#define DDR_MODE_MODEREG		0x0000		/* select mode register */
+
+/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
+ */
+#define SDRAM_INTERVAL_REFINT		0x3FFF0000
+#define SDRAM_INTERVAL_REFINT_SHIFT	16
+#define SDRAM_INTERVAL_BSTOPRE		0x00003FFF
+#define SDRAM_INTERVAL_BSTOPRE_SHIFT	0
+
+/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
+ */
+#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025	0x01000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075	0x03000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1		0x04000000
+
+/* ECC_ERR_INJECT - Memory data path error injection mask ECC
+ */
+#define ECC_ERR_INJECT_EMB		(0x80000000>>22)	/* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EIEN		(0x80000000>>23)	/* Error Injection Enable */
+#define ECC_ERR_INJECT_EEIM		(0xff000000>>24)	/* ECC Erroe Injection Enable */
+#define ECC_ERR_INJECT_EEIM_SHIFT	0
+
+/* CAPTURE_ECC - Memory data path read capture ECC
+ */
+#define CAPTURE_ECC_ECE			(0xff000000>>24)
+#define CAPTURE_ECC_ECE_SHIFT		0
+
+/* ERR_DETECT - Memory error detect
+ */
+#define ECC_ERROR_DETECT_MME		(0x80000000>>0)		/* Multiple Memory Errors */
+#define ECC_ERROR_DETECT_MBE		(0x80000000>>28)	/* Multiple-Bit Error */
+#define ECC_ERROR_DETECT_SBE		(0x80000000>>29)	/* Single-Bit ECC Error Pickup */
+#define ECC_ERROR_DETECT_MSE		(0x80000000>>31)	/* Memory Select Error */
+
+/* ERR_DISABLE - Memory error disable
+ */
+#define ECC_ERROR_DISABLE_MBED		(0x80000000>>28)	/* Multiple-Bit ECC Error Disable */
+#define ECC_ERROR_DISABLE_SBED		(0x80000000>>29)	/* Sinle-Bit ECC Error disable */
+#define ECC_ERROR_DISABLE_MSED		(0x80000000>>31)	/* Memory Select Error Disable */
+#define ECC_ERROR_ENABLE		~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
+					 ECC_ERROR_DISABLE_MBED)
+/* ERR_INT_EN - Memory error interrupt enable
+ */
+#define ECC_ERR_INT_EN_MBEE		(0x80000000>>28)	/* Multiple-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_SBEE		(0x80000000>>29)	/* Single-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MSEE		(0x80000000>>31)	/* Memory Select Error Interrupt Enable */
+#define ECC_ERR_INT_DISABLE		~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
+					 ECC_ERR_INT_EN_MSEE)
+/* CAPTURE_ATTRIBUTES - Memory error attributes capture
+ */
+#define ECC_CAPT_ATTR_BNUM		(0xe0000000>>1)		/* Data Beat Num */
+#define ECC_CAPT_ATTR_BNUM_SHIFT	28
+#define ECC_CAPT_ATTR_TSIZ		(0xc0000000>>6)		/* Transaction Size */
+#define ECC_CAPT_ATTR_TSIZ_FOUR_DW	0
+#define ECC_CAPT_ATTR_TSIZ_ONE_DW	1
+#define ECC_CAPT_ATTR_TSIZ_TWO_DW	2
+#define ECC_CAPT_ATTR_TSIZ_THREE_DW	3
+#define ECC_CAPT_ATTR_TSIZ_SHIFT	24
+#define ECC_CAPT_ATTR_TSRC		(0xf8000000>>11)	/* Transaction Source */
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT	0x0
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF	0x2
+#define ECC_CAPT_ATTR_TSRC_TSEC1	0x4
+#define ECC_CAPT_ATTR_TSRC_TSEC2	0x5
+#define ECC_CAPT_ATTR_TSRC_USB		(0x06|0x07)
+#define ECC_CAPT_ATTR_TSRC_ENCRYPT	0x8
+#define ECC_CAPT_ATTR_TSRC_I2C		0x9
+#define ECC_CAPT_ATTR_TSRC_JTAG		0xA
+#define ECC_CAPT_ATTR_TSRC_PCI1		0xD
+#define ECC_CAPT_ATTR_TSRC_PCI2		0xE
+#define ECC_CAPT_ATTR_TSRC_DMA		0xF
+#define ECC_CAPT_ATTR_TSRC_SHIFT	16
+#define ECC_CAPT_ATTR_TTYP		(0xe0000000>>18)	/* Transaction Type */
+#define ECC_CAPT_ATTR_TTYP_WRITE	0x1
+#define ECC_CAPT_ATTR_TTYP_READ		0x2
+#define ECC_CAPT_ATTR_TTYP_R_M_W	0x3
+#define ECC_CAPT_ATTR_TTYP_SHIFT	12
+#define ECC_CAPT_ATTR_VLD		(0x80000000>>31)	/* Valid */
+
+/* ERR_SBE - Single bit ECC memory error management
+ */
+#define ECC_ERROR_MAN_SBET		(0xff000000>>8)		/* Single-Bit Error Threshold 0..255 */
+#define ECC_ERROR_MAN_SBET_SHIFT	16
+#define ECC_ERROR_MAN_SBEC		(0xff000000>>24)	/* Single Bit Error Counter 0..255 */
+#define ECC_ERROR_MAN_SBEC_SHIFT	0
+
+/* BR - Base Registers
+ */
+#define BR0				0x5000		/* Register offset to immr */
+#define BR1				0x5008
+#define BR2				0x5010
+#define BR3				0x5018
+#define BR4				0x5020
+#define BR5				0x5028
+#define BR6				0x5030
+#define BR7				0x5038
+
+#define BR_BA				0xFFFF8000
+#define BR_BA_SHIFT			15
+#define BR_PS				0x00001800
+#define BR_PS_SHIFT			11
+#define BR_PS_8				0x00000800	/* Port Size 8 bit */
+#define BR_PS_16			0x00001000	/* Port Size 16 bit */
+#define BR_PS_32			0x00001800	/* Port Size 32 bit */
+#define BR_DECC				0x00000600
+#define BR_DECC_SHIFT			9
+#define BR_WP				0x00000100
+#define BR_WP_SHIFT			8
+#define BR_MSEL				0x000000E0
+#define BR_MSEL_SHIFT			5
+#define BR_MS_GPCM			0x00000000	/* GPCM */
+#define BR_MS_SDRAM			0x00000060	/* SDRAM */
+#define BR_MS_UPMA			0x00000080	/* UPMA */
+#define BR_MS_UPMB			0x000000A0	/* UPMB */
+#define BR_MS_UPMC			0x000000C0	/* UPMC */
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#define BR_ATOM				0x0000000C
+#define BR_ATOM_SHIFT			2
+#endif
+#define BR_V				0x00000001
+#define BR_V_SHIFT			0
+
+#if defined(CONFIG_MPC834X)
+#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
+#elif defined(CONFIG_MPC8360)
+#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
+#endif
+
+/* OR - Option Registers
+ */
+#define OR0				0x5004		/* Register offset to immr */
+#define OR1				0x500C
+#define OR2				0x5014
+#define OR3				0x501C
+#define OR4				0x5024
+#define OR5				0x502C
+#define OR6				0x5034
+#define OR7				0x503C
+
+#define OR_GPCM_AM			0xFFFF8000
+#define OR_GPCM_AM_SHIFT		15
+#define OR_GPCM_BCTLD			0x00001000
+#define OR_GPCM_BCTLD_SHIFT		12
+#define OR_GPCM_CSNT			0x00000800
+#define OR_GPCM_CSNT_SHIFT		11
+#define OR_GPCM_ACS			0x00000600
+#define OR_GPCM_ACS_SHIFT		9
+#define OR_GPCM_ACS_0b10		0x00000400
+#define OR_GPCM_ACS_0b11		0x00000600
+#define OR_GPCM_XACS			0x00000100
+#define OR_GPCM_XACS_SHIFT		8
+#define OR_GPCM_SCY			0x000000F0
+#define OR_GPCM_SCY_SHIFT		4
+#define OR_GPCM_SCY_1			0x00000010
+#define OR_GPCM_SCY_2			0x00000020
+#define OR_GPCM_SCY_3			0x00000030
+#define OR_GPCM_SCY_4			0x00000040
+#define OR_GPCM_SCY_5			0x00000050
+#define OR_GPCM_SCY_6			0x00000060
+#define OR_GPCM_SCY_7			0x00000070
+#define OR_GPCM_SCY_8			0x00000080
+#define OR_GPCM_SCY_9			0x00000090
+#define OR_GPCM_SCY_10			0x000000a0
+#define OR_GPCM_SCY_11			0x000000b0
+#define OR_GPCM_SCY_12			0x000000c0
+#define OR_GPCM_SCY_13			0x000000d0
+#define OR_GPCM_SCY_14			0x000000e0
+#define OR_GPCM_SCY_15			0x000000f0
+#define OR_GPCM_SETA			0x00000008
+#define OR_GPCM_SETA_SHIFT		3
+#define OR_GPCM_TRLX			0x00000004
+#define OR_GPCM_TRLX_SHIFT		2
+#define OR_GPCM_EHTR			0x00000002
+#define OR_GPCM_EHTR_SHIFT		1
+#define OR_GPCM_EAD			0x00000001
+#define OR_GPCM_EAD_SHIFT		0
+
+#define OR_UPM_AM			0xFFFF8000
+#define OR_UPM_AM_SHIFT			15
+#define OR_UPM_XAM			0x00006000
+#define OR_UPM_XAM_SHIFT		13
+#define OR_UPM_BCTLD			0x00001000
+#define OR_UPM_BCTLD_SHIFT		12
+#define OR_UPM_BI			0x00000100
+#define OR_UPM_BI_SHIFT			8
+#define OR_UPM_TRLX			0x00000004
+#define OR_UPM_TRLX_SHIFT		2
+#define OR_UPM_EHTR			0x00000002
+#define OR_UPM_EHTR_SHIFT		1
+#define OR_UPM_EAD			0x00000001
+#define OR_UPM_EAD_SHIFT		0
+
+#define OR_SDRAM_AM			0xFFFF8000
+#define OR_SDRAM_AM_SHIFT		15
+#define OR_SDRAM_XAM			0x00006000
+#define OR_SDRAM_XAM_SHIFT		13
+#define OR_SDRAM_COLS			0x00001C00
+#define OR_SDRAM_COLS_SHIFT		10
+#define OR_SDRAM_ROWS			0x000001C0
+#define OR_SDRAM_ROWS_SHIFT		6
+#define OR_SDRAM_PMSEL			0x00000020
+#define OR_SDRAM_PMSEL_SHIFT		5
+#define OR_SDRAM_EAD			0x00000001
+#define OR_SDRAM_EAD_SHIFT		0
+
+#define OR_AM_32KB			0xFFFF8000
+#define OR_AM_64KB			0xFFFF0000
+#define OR_AM_128KB			0xFFFE0000
+#define OR_AM_256KB			0xFFFC0000
+#define OR_AM_512KB			0xFFF80000
+#define OR_AM_1MB			0xFFF00000
+#define OR_AM_2MB			0xFFE00000
+#define OR_AM_4MB			0xFFC00000
+#define OR_AM_8MB			0xFF800000
+#define OR_AM_16MB			0xFF000000
+#define OR_AM_32MB			0xFE000000
+#define OR_AM_64MB			0xFC000000
+#define OR_AM_128MB			0xF8000000
+#define OR_AM_256MB			0xF0000000
+#define OR_AM_512MB			0xE0000000
+#define OR_AM_1GB			0xC0000000
+#define OR_AM_2GB			0x80000000
+#define OR_AM_4GB			0x00000000
+
+#define LBLAWAR_EN			0x80000000
+#define LBLAWAR_4KB			0x0000000B
+#define LBLAWAR_8KB			0x0000000C
+#define LBLAWAR_16KB			0x0000000D
+#define LBLAWAR_32KB			0x0000000E
+#define LBLAWAR_64KB			0x0000000F
+#define LBLAWAR_128KB			0x00000010
+#define LBLAWAR_256KB			0x00000011
+#define LBLAWAR_512KB			0x00000012
+#define LBLAWAR_1MB			0x00000013
+#define LBLAWAR_2MB			0x00000014
+#define LBLAWAR_4MB			0x00000015
+#define LBLAWAR_8MB			0x00000016
+#define LBLAWAR_16MB			0x00000017
+#define LBLAWAR_32MB			0x00000018
+#define LBLAWAR_64MB			0x00000019
+#define LBLAWAR_128MB			0x0000001A
+#define LBLAWAR_256MB			0x0000001B
+#define LBLAWAR_512MB			0x0000001C
+#define LBLAWAR_1GB			0x0000001D
+#define LBLAWAR_2GB			0x0000001E
+
+/* LBCR - Local Bus Configuration Register
+ */
+#define LBCR_LDIS			0x80000000
+#define LBCR_LDIS_SHIFT			31
+#define LBCR_BCTLC			0x00C00000
+#define LBCR_BCTLC_SHIFT		22
+#define LBCR_LPBSE			0x00020000
+#define LBCR_LPBSE_SHIFT		17
+#define LBCR_EPAR			0x00010000
+#define LBCR_EPAR_SHIFT			16
+#define LBCR_BMT			0x0000FF00
+#define LBCR_BMT_SHIFT			8
+
+/* LCRR - Clock Ratio Register
+ */
+#define LCRR_DBYP			0x80000000
+#define LCRR_DBYP_SHIFT			31
+#define LCRR_BUFCMDC			0x30000000
+#define LCRR_BUFCMDC_SHIFT		28
+#define LCRR_BUFCMDC_1			0x10000000
+#define LCRR_BUFCMDC_2			0x20000000
+#define LCRR_BUFCMDC_3			0x30000000
+#define LCRR_BUFCMDC_4			0x00000000
+#define LCRR_ECL			0x03000000
+#define LCRR_ECL_SHIFT			24
+#define LCRR_ECL_4			0x00000000
+#define LCRR_ECL_5			0x01000000
+#define LCRR_ECL_6			0x02000000
+#define LCRR_ECL_7			0x03000000
+#define LCRR_EADC			0x00030000
+#define LCRR_EADC_SHIFT			16
+#define LCRR_EADC_1			0x00010000
+#define LCRR_EADC_2			0x00020000
+#define LCRR_EADC_3			0x00030000
+#define LCRR_EADC_4			0x00000000
+#define LCRR_CLKDIV			0x0000000F
+#define LCRR_CLKDIV_SHIFT		0
+#define LCRR_CLKDIV_2			0x00000002
+#define LCRR_CLKDIV_4			0x00000004
+#define LCRR_CLKDIV_8			0x00000008
+
+/* DMAMR - DMA Mode Register
+ */
+#define DMA_CHANNEL_START			0x00000001	/* Bit - DMAMRn CS */
+#define DMA_CHANNEL_TRANSFER_MODE_DIRECT	0x00000004	/* Bit - DMAMRn CTM */
+#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN	0x00001000	/* Bit - DMAMRn SAHE */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B	0x00000000	/* 2Bit- DMAMRn SAHTS 1byte */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B	0x00004000	/* 2Bit- DMAMRn SAHTS 2bytes */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B	0x00008000	/* 2Bit- DMAMRn SAHTS 4bytes */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B	0x0000c000	/* 2Bit- DMAMRn SAHTS 8bytes */
+#define DMA_CHANNEL_SNOOP			0x00010000	/* Bit - DMAMRn DMSEN */
+
+/* DMASR - DMA Status Register
+ */
+#define DMA_CHANNEL_BUSY			0x00000004	/* Bit - DMASRn CB */
+#define DMA_CHANNEL_TRANSFER_ERROR		0x00000080	/* Bit - DMASRn TE */
+
+/* CONFIG_ADDRESS - PCI Config Address Register
+ */
+#define PCI_CONFIG_ADDRESS_EN		0x80000000
+#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
+#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
+#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
+#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
+#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
+#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
+#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
+#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
+
+/* POTAR - PCI Outbound Translation Address Register
+ */
+#define POTAR_TA_MASK			0x000fffff
+
+/* POBAR - PCI Outbound Base Address Register
+ */
+#define POBAR_BA_MASK			0x000fffff
+
+/* POCMR - PCI Outbound Comparision Mask Register
+ */
+#define POCMR_EN			0x80000000
+#define POCMR_IO			0x40000000	/* 0-memory space 1-I/O space */
+#define POCMR_SE			0x20000000	/* streaming enable */
+#define POCMR_DST			0x10000000	/* 0-PCI1 1-PCI2 */
+#define POCMR_CM_MASK			0x000fffff
+#define POCMR_CM_4G			0x00000000
+#define POCMR_CM_2G			0x00080000
+#define POCMR_CM_1G			0x000C0000
+#define POCMR_CM_512M			0x000E0000
+#define POCMR_CM_256M			0x000F0000
+#define POCMR_CM_128M			0x000F8000
+#define POCMR_CM_64M			0x000FC000
+#define POCMR_CM_32M			0x000FE000
+#define POCMR_CM_16M			0x000FF000
+#define POCMR_CM_8M			0x000FF800
+#define POCMR_CM_4M			0x000FFC00
+#define POCMR_CM_2M			0x000FFE00
+#define POCMR_CM_1M			0x000FFF00
+#define POCMR_CM_512K			0x000FFF80
+#define POCMR_CM_256K			0x000FFFC0
+#define POCMR_CM_128K			0x000FFFE0
+#define POCMR_CM_64K			0x000FFFF0
+#define POCMR_CM_32K			0x000FFFF8
+#define POCMR_CM_16K			0x000FFFFC
+#define POCMR_CM_8K			0x000FFFFE
+#define POCMR_CM_4K			0x000FFFFF
+
+/* PITAR - PCI Inbound Translation Address Register
+ */
+#define PITAR_TA_MASK			0x000fffff
+
+/* PIBAR - PCI Inbound Base/Extended Address Register
+ */
+#define PIBAR_MASK			0xffffffff
+#define PIEBAR_EBA_MASK			0x000fffff
+
+/* PIWAR - PCI Inbound Windows Attributes Register
+ */
+#define PIWAR_EN			0x80000000
+#define PIWAR_PF			0x20000000
+#define PIWAR_RTT_MASK			0x000f0000
+#define PIWAR_RTT_NO_SNOOP		0x00040000
+#define PIWAR_RTT_SNOOP			0x00050000
+#define PIWAR_WTT_MASK			0x0000f000
+#define PIWAR_WTT_NO_SNOOP		0x00004000
+#define PIWAR_WTT_SNOOP			0x00005000
+#define PIWAR_IWS_MASK			0x0000003F
+#define PIWAR_IWS_4K			0x0000000B
+#define PIWAR_IWS_8K			0x0000000C
+#define PIWAR_IWS_16K			0x0000000D
+#define PIWAR_IWS_32K			0x0000000E
+#define PIWAR_IWS_64K			0x0000000F
+#define PIWAR_IWS_128K			0x00000010
+#define PIWAR_IWS_256K			0x00000011
+#define PIWAR_IWS_512K			0x00000012
+#define PIWAR_IWS_1M			0x00000013
+#define PIWAR_IWS_2M			0x00000014
+#define PIWAR_IWS_4M			0x00000015
+#define PIWAR_IWS_8M			0x00000016
+#define PIWAR_IWS_16M			0x00000017
+#define PIWAR_IWS_32M			0x00000018
+#define PIWAR_IWS_64M			0x00000019
+#define PIWAR_IWS_128M			0x0000001A
+#define PIWAR_IWS_256M			0x0000001B
+#define PIWAR_IWS_512M			0x0000001C
+#define PIWAR_IWS_1G			0x0000001D
+#define PIWAR_IWS_2G			0x0000001E
 
 #endif	/* __MPC83XX_H__ */
diff --git a/include/part.h b/include/part.h
index 318aa3c..29c0320 100644
--- a/include/part.h
+++ b/include/part.h
@@ -22,6 +22,7 @@
  */
 #ifndef _PART_H
 #define _PART_H
+
 #include <ide.h>
 
 typedef struct block_dev_desc {
@@ -43,7 +44,11 @@ typedef struct block_dev_desc {
 	unsigned long	(*block_read)(int dev,
 				      unsigned long start,
 				      lbaint_t blkcnt,
-				      unsigned long *buffer);
+				      void *buffer);
+	unsigned long	(*block_write)(int dev,
+				       unsigned long start,
+				       lbaint_t blkcnt,
+				       const void *buffer);
 }block_dev_desc_t;
 
 /* Interface types: */
@@ -83,6 +88,14 @@ typedef struct disk_partition {
 	uchar	type[32];	/* string type description		*/
 } disk_partition_t;
 
+/* Misc _get_dev functions */
+block_dev_desc_t* get_dev(char* ifname, int dev);
+block_dev_desc_t* ide_get_dev(int dev);
+block_dev_desc_t* scsi_get_dev(int dev);
+block_dev_desc_t* usb_stor_get_dev(int dev);
+block_dev_desc_t* mmc_get_dev(int dev);
+block_dev_desc_t* systemace_get_dev(int dev);
+
 /* disk/part.c */
 int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
 void print_part (block_dev_desc_t *dev_desc);
diff --git a/include/ppc405.h b/include/ppc405.h
index 4470240..08f10d2 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -117,6 +117,48 @@
 /*-----------------------------------------------------------------------------+
 |  Universal interrupt controller interrupts
 +-----------------------------------------------------------------------------*/
+#if defined(CONFIG_405EZ)
+#define UIC_DMA0	0x80000000	/* DMA chan. 0			*/
+#define UIC_DMA1	0x40000000	/* DMA chan. 1			*/
+#define UIC_DMA2	0x20000000	/* DMA chan. 2			*/
+#define UIC_DMA3	0x10000000	/* DMA chan. 3			*/
+#define UIC_1588	0x08000000	/* IEEE 1588 network synchronization */
+#define UIC_UART0	0x04000000	/* UART 0			*/
+#define UIC_UART1	0x02000000	/* UART 1			*/
+#define UIC_CAN0	0x01000000	/* CAN 0			*/
+#define UIC_CAN1	0x00800000	/* CAN 1			*/
+#define UIC_SPI		0x00400000	/* SPI				*/
+#define UIC_IIC		0x00200000	/* IIC				*/
+#define UIC_CHT0	0x00100000	/* Chameleon timer high pri interrupt */
+#define UIC_CHT1	0x00080000	/* Chameleon timer high pri interrupt */
+#define UIC_USBH1	0x00040000	/* USB Host 1			*/
+#define UIC_USBH2	0x00020000	/* USB Host 2			*/
+#define UIC_USBDEV	0x00010000	/* USB Device			*/
+#define UIC_ENET	0x00008000	/* Ethernet interrupt status 	*/
+#define UIC_ENET1	0x00008000	/* dummy define              	*/
+#define UIC_EMAC_WAKE	0x00004000	/* EMAC wake up			*/
+
+#define UIC_MADMAL	0x00002000	/* Logical OR of following MadMAL int */
+#define UIC_MAL_SERR 	0x00002000	/*   MAL SERR			*/
+#define UIC_MAL_TXDE	0x00002000	/*   MAL TXDE			*/
+#define UIC_MAL_RXDE	0x00002000	/*   MAL RXDE			*/
+
+#define UIC_MAL_TXEOB	0x00001000	/* MAL TXEOB			*/
+#define UIC_MAL_TXEOB1	0x00000800	/* MAL TXEOB1			*/
+#define UIC_MAL_RXEOB	0x00000400	/* MAL RXEOB			*/
+#define UIC_NAND	0x00000200	/* NAND Flash controller	*/
+#define UIC_ADC		0x00000100	/* ADC				*/
+#define UIC_DAC		0x00000080	/* DAC				*/
+#define UIC_OPB2PLB	0x00000040	/* OPB to PLB bridge interrupt	*/
+#define UIC_RESERVED0	0x00000020	/* Reserved			*/
+#define UIC_EXT0	0x00000010	/* External  interrupt 0	*/
+#define UIC_EXT1	0x00000008	/* External  interrupt 1	*/
+#define UIC_EXT2	0x00000004	/* External  interrupt 2	*/
+#define UIC_EXT3	0x00000002	/* External  interrupt 3	*/
+#define UIC_EXT4	0x00000001	/* External  interrupt 4	*/
+
+#else	/* !defined(CONFIG_405EZ) */
+
 #define UIC_UART0     0x80000000      /* UART 0                             */
 #define UIC_UART1     0x40000000      /* UART 1                             */
 #define UIC_IIC       0x20000000      /* IIC                                */
@@ -144,6 +186,7 @@
 #define UIC_EXT4      0x00000004      /* External  interrupt 4              */
 #define UIC_EXT5      0x00000002      /* External  interrupt 5              */
 #define UIC_EXT6      0x00000001      /* External  interrupt 6              */
+#endif	/* defined(CONFIG_405EZ) */
 
 /******************************************************************************
  * SDRAM Controller
@@ -160,6 +203,7 @@
   #define mem_bear    0x10    /* bus error address reg		     */
 #endif
   #define mem_mcopt1  0x20    /* memory controller options 1	     */
+  #define mem_status  0x24    /* memory status			     */
   #define mem_rtr     0x30    /* refresh timer reg		     */
   #define mem_pmit    0x34    /* power management idle timer	     */
   #define mem_mb0cf   0x40    /* memory bank 0 configuration	     */
@@ -239,6 +283,7 @@
   #define pbesr0      0x21    /* periph bus error status reg 0       */
   #define pbesr1      0x22    /* periph bus error status reg 1       */
   #define epcr        0x23    /* external periph control reg         */
+#define EBC0_CFG	0x23	/* external bus configuration reg	*/
 
 #ifdef CONFIG_405EP
 /******************************************************************************
@@ -494,6 +539,325 @@
  */
 #define VCO_MIN     500
 #define VCO_MAX     1000
+#elif defined(CONFIG_405EZ)
+/******************************************************************************
+ * SDR Registers
+ ******************************************************************************/
+#define SDR_DCR_BASE 0x0E
+#define sdrcfga (SDR_DCR_BASE+0x0)	/* ADDR */
+#define sdrcfgd (SDR_DCR_BASE+0x1)	/* Data */
+
+#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
+#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
+
+#define sdrnand0	0x4000
+#define sdrultra0	0x4040
+#define sdrultra1	0x4050
+#define sdricintstat	0x4510
+
+#define SDR_NAND0_NDEN		0x80000000
+
+#define SDR_ULTRA0_NDGPIOBP	0x80000000
+#define SDR_ULTRA0_CSN_MASK	0x78000000
+#define SDR_ULTRA0_CSNSEL0	0x40000000
+#define SDR_ULTRA0_CSNSEL1	0x20000000
+#define SDR_ULTRA0_CSNSEL2	0x10000000
+#define SDR_ULTRA0_CSNSEL3	0x08000000
+
+#define SDR_ULTRA1_LEDNENABLE	0x40000000
+
+#define SDR_ICRX_STAT	0x80000000
+#define SDR_ICTX0_STAT	0x40000000
+#define SDR_ICTX1_STAT	0x20000000
+
+/******************************************************************************
+ * Control
+ ******************************************************************************/
+#define CNTRL_DCR_BASE 0x0C
+#define cprcfga (CNTRL_DCR_BASE+0x0)   /* CPR addr reg     */
+#define cprcfgd (CNTRL_DCR_BASE+0x1)   /* CPR data reg     */
+
+/* CPR Registers */
+#define cprclkupd       0x020		/* CPR_CLKUPD */
+#define cprpllc         0x040		/* CPR_PLLC */
+#define cprplld         0x060		/* CPR_PLLD */
+#define cprprimad       0x080		/* CPR_PRIMAD */
+#define cprperd0        0x0e0		/* CPR_PERD0 */
+#define cprperd1        0x0e1		/* CPR_PERD1 */
+#define cprperc0        0x180		/* CPR_PERC0 */
+#define cprmisc0        0x181		/* CPR_MISC0 */
+#define cprmisc1        0x182		/* CPR_MISC1 */
+
+/*
+ * Macro for accessing the indirect CPR register
+ */
+#define mtcpr(reg, data)  mtdcr(cprcfga,reg);mtdcr(cprcfgd,data)
+#define mfcpr(reg, data)  mtdcr(cprcfga,reg);data = mfdcr(cprcfgd)
+
+#define CPR_CLKUPD_ENPLLCH_EN  0x40000000     /* Enable CPR PLL Changes */
+#define CPR_CLKUPD_ENDVCH_EN   0x20000000     /* Enable CPR Sys. Div. Changes */
+#define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */
+
+#define PLLD_FBDV_MASK         0x1F000000     /* PLL feedback divider value */
+#define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */
+#define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */
+
+#define PRIMAD_CPUDV_MASK      0x0F000000     /* CPU Clock Divisor Mask */
+#define PRIMAD_PLBDV_MASK      0x000F0000     /* PLB Clock Divisor Mask */
+#define PRIMAD_OPBDV_MASK      0x00000F00     /* OPB Clock Divisor Mask */
+#define PRIMAD_EBCDV_MASK      0x0000000F     /* EBC Clock Divisor Mask */
+
+#define PERD0_PWMDV_MASK       0xFF000000     /* PWM Divider Mask */
+#define PERD0_SPIDV_MASK       0x000F0000     /* SPI Divider Mask */
+#define PERD0_U0DV_MASK        0x0000FF00     /* UART 0 Divider Mask */
+#define PERD0_U1DV_MASK        0x000000FF     /* UART 1 Divider Mask */
+
+#if 0 /* Deprecated */
+#define CNTRL_DCR_BASE 0x0f0
+#define cpc0_pllmr0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0                */
+#define cpc0_boot     (CNTRL_DCR_BASE+0x1)  /* Clock status register               */
+#define cpc0_epctl    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register        */
+#define cpc0_pllmr1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1                */
+#define cpc0_ucr      (CNTRL_DCR_BASE+0x5)  /* UART control register               */
+#define cpc0_pci      (CNTRL_DCR_BASE+0x9)  /* PCI control register                */
+
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register          */
+#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register      */
+#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register          */
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register        */
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register          */
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register             */
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                    */
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register         */
+
+/* Bit definitions */
+#define PLLMR0_CPU_DIV_MASK      0x00300000     /* CPU clock divider */
+#define PLLMR0_CPU_DIV_BYPASS    0x00000000
+#define PLLMR0_CPU_DIV_2         0x00100000
+#define PLLMR0_CPU_DIV_3         0x00200000
+#define PLLMR0_CPU_DIV_4         0x00300000
+
+#define PLLMR0_CPU_TO_PLB_MASK   0x00030000     /* CPU:PLB Frequency Divisor */
+#define PLLMR0_CPU_PLB_DIV_1     0x00000000
+#define PLLMR0_CPU_PLB_DIV_2     0x00010000
+#define PLLMR0_CPU_PLB_DIV_3     0x00020000
+#define PLLMR0_CPU_PLB_DIV_4     0x00030000
+
+#define PLLMR0_OPB_TO_PLB_MASK   0x00003000     /* OPB:PLB Frequency Divisor */
+#define PLLMR0_OPB_PLB_DIV_1     0x00000000
+#define PLLMR0_OPB_PLB_DIV_2     0x00001000
+#define PLLMR0_OPB_PLB_DIV_3     0x00002000
+#define PLLMR0_OPB_PLB_DIV_4     0x00003000
+
+#define PLLMR0_EXB_TO_PLB_MASK   0x00000300     /* External Bus:PLB Divisor  */
+#define PLLMR0_EXB_PLB_DIV_2     0x00000000
+#define PLLMR0_EXB_PLB_DIV_3     0x00000100
+#define PLLMR0_EXB_PLB_DIV_4     0x00000200
+#define PLLMR0_EXB_PLB_DIV_5     0x00000300
+
+#define PLLMR0_MAL_TO_PLB_MASK   0x00000030     /* MAL:PLB Divisor  */
+#define PLLMR0_MAL_PLB_DIV_1     0x00000000
+#define PLLMR0_MAL_PLB_DIV_2     0x00000010
+#define PLLMR0_MAL_PLB_DIV_3     0x00000020
+#define PLLMR0_MAL_PLB_DIV_4     0x00000030
+
+#define PLLMR0_PCI_TO_PLB_MASK   0x00000003     /* PCI:PLB Frequency Divisor */
+#define PLLMR0_PCI_PLB_DIV_1     0x00000000
+#define PLLMR0_PCI_PLB_DIV_2     0x00000001
+#define PLLMR0_PCI_PLB_DIV_3     0x00000002
+#define PLLMR0_PCI_PLB_DIV_4     0x00000003
+
+#define PLLMR1_SSCS_MASK         0x80000000     /* Select system clock source */
+#define PLLMR1_PLLR_MASK         0x40000000     /* PLL reset */
+#define PLLMR1_FBMUL_MASK        0x00F00000     /* PLL feedback multiplier value */
+#define PLLMR1_FBMUL_DIV_16      0x00000000
+#define PLLMR1_FBMUL_DIV_1       0x00100000
+#define PLLMR1_FBMUL_DIV_2       0x00200000
+#define PLLMR1_FBMUL_DIV_3       0x00300000
+#define PLLMR1_FBMUL_DIV_4       0x00400000
+#define PLLMR1_FBMUL_DIV_5       0x00500000
+#define PLLMR1_FBMUL_DIV_6       0x00600000
+#define PLLMR1_FBMUL_DIV_7       0x00700000
+#define PLLMR1_FBMUL_DIV_8       0x00800000
+#define PLLMR1_FBMUL_DIV_9       0x00900000
+#define PLLMR1_FBMUL_DIV_10      0x00A00000
+#define PLLMR1_FBMUL_DIV_11      0x00B00000
+#define PLLMR1_FBMUL_DIV_12      0x00C00000
+#define PLLMR1_FBMUL_DIV_13      0x00D00000
+#define PLLMR1_FBMUL_DIV_14      0x00E00000
+#define PLLMR1_FBMUL_DIV_15      0x00F00000
+
+#define PLLMR1_FWDVA_MASK        0x00070000     /* PLL forward divider A value */
+#define PLLMR1_FWDVA_DIV_8       0x00000000
+#define PLLMR1_FWDVA_DIV_7       0x00010000
+#define PLLMR1_FWDVA_DIV_6       0x00020000
+#define PLLMR1_FWDVA_DIV_5       0x00030000
+#define PLLMR1_FWDVA_DIV_4       0x00040000
+#define PLLMR1_FWDVA_DIV_3       0x00050000
+#define PLLMR1_FWDVA_DIV_2       0x00060000
+#define PLLMR1_FWDVA_DIV_1       0x00070000
+#define PLLMR1_FWDVB_MASK        0x00007000     /* PLL forward divider B value */
+#define PLLMR1_TUNING_MASK       0x000003FF     /* PLL tune bits */
+
+/* Defines for CPC0_EPRCSR register */
+#define CPC0_EPRCSR_E0NFE          0x80000000
+#define CPC0_EPRCSR_E1NFE          0x40000000
+#define CPC0_EPRCSR_E1RPP          0x00000080
+#define CPC0_EPRCSR_E0RPP          0x00000040
+#define CPC0_EPRCSR_E1ERP          0x00000020
+#define CPC0_EPRCSR_E0ERP          0x00000010
+#define CPC0_EPRCSR_E1PCI          0x00000002
+#define CPC0_EPRCSR_E0PCI          0x00000001
+
+/* Defines for CPC0_BOOR Register */
+#define CPC0_BOOT_SEP                      0x00000002 /* serial EEPROM present  */
+
+/* Defines for CPC0_PLLMR1 Register fields */
+#define PLL_ACTIVE                 0x80000000
+#define CPC0_PLLMR1_SSCS           0x80000000
+#define PLL_RESET                  0x40000000
+#define CPC0_PLLMR1_PLLR           0x40000000
+    /* Feedback multiplier */
+#define PLL_FBKDIV                 0x00F00000
+#define CPC0_PLLMR1_FBDV           0x00F00000
+#define PLL_FBKDIV_16              0x00000000
+#define PLL_FBKDIV_1               0x00100000
+#define PLL_FBKDIV_2               0x00200000
+#define PLL_FBKDIV_3               0x00300000
+#define PLL_FBKDIV_4               0x00400000
+#define PLL_FBKDIV_5               0x00500000
+#define PLL_FBKDIV_6               0x00600000
+#define PLL_FBKDIV_7               0x00700000
+#define PLL_FBKDIV_8               0x00800000
+#define PLL_FBKDIV_9               0x00900000
+#define PLL_FBKDIV_10              0x00A00000
+#define PLL_FBKDIV_11              0x00B00000
+#define PLL_FBKDIV_12              0x00C00000
+#define PLL_FBKDIV_13              0x00D00000
+#define PLL_FBKDIV_14              0x00E00000
+#define PLL_FBKDIV_15              0x00F00000
+    /* Forward A divisor */
+#define PLL_FWDDIVA                0x00070000
+#define CPC0_PLLMR1_FWDVA          0x00070000
+#define PLL_FWDDIVA_8              0x00000000
+#define PLL_FWDDIVA_7              0x00010000
+#define PLL_FWDDIVA_6              0x00020000
+#define PLL_FWDDIVA_5              0x00030000
+#define PLL_FWDDIVA_4              0x00040000
+#define PLL_FWDDIVA_3              0x00050000
+#define PLL_FWDDIVA_2              0x00060000
+#define PLL_FWDDIVA_1              0x00070000
+    /* Forward B divisor */
+#define PLL_FWDDIVB                0x00007000
+#define CPC0_PLLMR1_FWDVB          0x00007000
+#define PLL_FWDDIVB_8              0x00000000
+#define PLL_FWDDIVB_7              0x00001000
+#define PLL_FWDDIVB_6              0x00002000
+#define PLL_FWDDIVB_5              0x00003000
+#define PLL_FWDDIVB_4              0x00004000
+#define PLL_FWDDIVB_3              0x00005000
+#define PLL_FWDDIVB_2              0x00006000
+#define PLL_FWDDIVB_1              0x00007000
+    /* PLL tune bits */
+#define PLL_TUNE_MASK            0x000003FF
+#define PLL_TUNE_2_M_3           0x00000133     /*  2 <= M <= 3               */
+#define PLL_TUNE_4_M_6           0x00000134     /*  3 <  M <= 6               */
+#define PLL_TUNE_7_M_10          0x00000138     /*  6 <  M <= 10              */
+#define PLL_TUNE_11_M_14         0x0000013C     /* 10 <  M <= 14              */
+#define PLL_TUNE_15_M_40         0x0000023E     /* 14 <  M <= 40              */
+#define PLL_TUNE_VCO_LOW         0x00000000     /* 500MHz <= VCO <=  800MHz   */
+#define PLL_TUNE_VCO_HI          0x00000080     /* 800MHz <  VCO <= 1000MHz   */
+
+/* Defines for CPC0_PLLMR0 Register fields */
+    /* CPU divisor */
+#define PLL_CPUDIV                 0x00300000
+#define CPC0_PLLMR0_CCDV           0x00300000
+#define PLL_CPUDIV_1               0x00000000
+#define PLL_CPUDIV_2               0x00100000
+#define PLL_CPUDIV_3               0x00200000
+#define PLL_CPUDIV_4               0x00300000
+    /* PLB divisor */
+#define PLL_PLBDIV                 0x00030000
+#define CPC0_PLLMR0_CBDV           0x00030000
+#define PLL_PLBDIV_1               0x00000000
+#define PLL_PLBDIV_2               0x00010000
+#define PLL_PLBDIV_3               0x00020000
+#define PLL_PLBDIV_4               0x00030000
+    /* OPB divisor */
+#define PLL_OPBDIV                 0x00003000
+#define CPC0_PLLMR0_OPDV           0x00003000
+#define PLL_OPBDIV_1               0x00000000
+#define PLL_OPBDIV_2               0x00001000
+#define PLL_OPBDIV_3               0x00002000
+#define PLL_OPBDIV_4               0x00003000
+    /* EBC divisor */
+#define PLL_EXTBUSDIV              0x00000300
+#define CPC0_PLLMR0_EPDV           0x00000300
+#define PLL_EXTBUSDIV_2            0x00000000
+#define PLL_EXTBUSDIV_3            0x00000100
+#define PLL_EXTBUSDIV_4            0x00000200
+#define PLL_EXTBUSDIV_5            0x00000300
+    /* MAL divisor */
+#define PLL_MALDIV                 0x00000030
+#define CPC0_PLLMR0_MPDV           0x00000030
+#define PLL_MALDIV_1               0x00000000
+#define PLL_MALDIV_2               0x00000010
+#define PLL_MALDIV_3               0x00000020
+#define PLL_MALDIV_4               0x00000030
+    /* PCI divisor */
+#define PLL_PCIDIV                 0x00000003
+#define CPC0_PLLMR0_PPFD           0x00000003
+#define PLL_PCIDIV_1               0x00000000
+#define PLL_PCIDIV_2               0x00000001
+#define PLL_PCIDIV_3               0x00000002
+#define PLL_PCIDIV_4               0x00000003
+
+/*
+ *-------------------------------------------------------------------------------
+ * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+ * assuming a 33.3MHz input clock to the 405EP.
+ *-------------------------------------------------------------------------------
+ */
+#define PLLMR0_266_133_66  (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+			    PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+			    PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_66  (PLL_FBKDIV_8  |  \
+			    PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+			    PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_133_66_66_33  (PLL_FBKDIV_4  |  \
+			      PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
+			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+/*
+ * PLL Voltage Controlled Oscillator (VCO) definitions
+ * Maximum and minimum values (in MHz) for correct PLL operation.
+ */
+#define VCO_MIN     500
+#define VCO_MAX     1000
+#endif /* #if 0 */
 #else /* #ifdef CONFIG_405EP */
 /******************************************************************************
  * Control
@@ -576,6 +940,121 @@
 /******************************************************************************
  * Memory Access Layer
  ******************************************************************************/
+#if defined(CONFIG_405EZ)
+#define	MAL_DCR_BASE	0x380
+#define	malmcr		(MAL_DCR_BASE+0x00)	/* MAL Config reg	      */
+#define	malesr		(MAL_DCR_BASE+0x01)	/* Err Status reg (Read/Clear)*/
+#define	malier		(MAL_DCR_BASE+0x02)	/* Interrupt enable reg	      */
+#define	maldbr		(MAL_DCR_BASE+0x03)	/* Mal Debug reg (Read only)  */
+#define	maltxcasr	(MAL_DCR_BASE+0x04)	/* TX Channel active reg (set)*/
+#define	maltxcarr	(MAL_DCR_BASE+0x05)	/* TX Channel active reg (Reset)     */
+#define	maltxeobisr	(MAL_DCR_BASE+0x06)	/* TX End of buffer int status reg   */
+#define	maltxdeir	(MAL_DCR_BASE+0x07)	/* TX Descr. Error Int reg    */
+/*				      0x08-0x0F	   Reserved		      */
+#define	malrxcasr	(MAL_DCR_BASE+0x10)	/* RX Channel active reg (set)*/
+#define	malrxcarr	(MAL_DCR_BASE+0x11)	/* RX Channel active reg (Reset)     */
+#define	malrxeobisr	(MAL_DCR_BASE+0x12)	/* RX End of buffer int status reg   */
+#define	malrxdeir	(MAL_DCR_BASE+0x13)	/* RX Descr. Error Int reg  */
+/*				      0x14-0x1F	   Reserved		    */
+#define	maltxctp0r	(MAL_DCR_BASE+0x20)  /* TX 0 Channel table ptr reg  */
+#define	maltxctp1r	(MAL_DCR_BASE+0x21)  /* TX 1 Channel table ptr reg  */
+#define	maltxctp2r	(MAL_DCR_BASE+0x22)  /* TX 2 Channel table ptr reg  */
+#define	maltxctp3r	(MAL_DCR_BASE+0x23)  /* TX 3 Channel table ptr reg  */
+#define	maltxctp4r	(MAL_DCR_BASE+0x24)  /* TX 4 Channel table ptr reg  */
+#define	maltxctp5r	(MAL_DCR_BASE+0x25)  /* TX 5 Channel table ptr reg  */
+#define	maltxctp6r	(MAL_DCR_BASE+0x26)  /* TX 6 Channel table ptr reg  */
+#define	maltxctp7r	(MAL_DCR_BASE+0x27)  /* TX 7 Channel table ptr reg  */
+#define	maltxctp8r	(MAL_DCR_BASE+0x28)  /* TX 8 Channel table ptr reg  */
+#define	maltxctp9r	(MAL_DCR_BASE+0x29)  /* TX 9 Channel table ptr reg  */
+#define	maltxctp10r	(MAL_DCR_BASE+0x2A)  /* TX 10 Channel table ptr reg */
+#define	maltxctp11r	(MAL_DCR_BASE+0x2B)  /* TX 11 Channel table ptr reg */
+#define	maltxctp12r	(MAL_DCR_BASE+0x2C)  /* TX 12 Channel table ptr reg */
+#define	maltxctp13r	(MAL_DCR_BASE+0x2D)  /* TX 13 Channel table ptr reg */
+#define	maltxctp14r	(MAL_DCR_BASE+0x2E)  /* TX 14 Channel table ptr reg */
+#define	maltxctp15r	(MAL_DCR_BASE+0x2F)  /* TX 15 Channel table ptr reg */
+#define	maltxctp16r	(MAL_DCR_BASE+0x30)  /* TX 16 Channel table ptr reg */
+#define	maltxctp17r	(MAL_DCR_BASE+0x31)  /* TX 17 Channel table ptr reg */
+#define	maltxctp18r	(MAL_DCR_BASE+0x32)  /* TX 18 Channel table ptr reg */
+#define	maltxctp19r	(MAL_DCR_BASE+0x33)  /* TX 19 Channel table ptr reg */
+#define	maltxctp20r	(MAL_DCR_BASE+0x34)  /* TX 20 Channel table ptr reg */
+#define	maltxctp21r	(MAL_DCR_BASE+0x35)  /* TX 21 Channel table ptr reg */
+#define	maltxctp22r	(MAL_DCR_BASE+0x36)  /* TX 22 Channel table ptr reg */
+#define	maltxctp23r	(MAL_DCR_BASE+0x37)  /* TX 23 Channel table ptr reg */
+#define	maltxctp24r	(MAL_DCR_BASE+0x38)  /* TX 24 Channel table ptr reg */
+#define	maltxctp25r	(MAL_DCR_BASE+0x39)  /* TX 25 Channel table ptr reg */
+#define	maltxctp26r	(MAL_DCR_BASE+0x3A)  /* TX 26 Channel table ptr reg */
+#define	maltxctp27r	(MAL_DCR_BASE+0x3B)  /* TX 27 Channel table ptr reg */
+#define	maltxctp28r	(MAL_DCR_BASE+0x3C)  /* TX 28 Channel table ptr reg */
+#define	maltxctp29r	(MAL_DCR_BASE+0x3D)  /* TX 29 Channel table ptr reg */
+#define	maltxctp30r	(MAL_DCR_BASE+0x3E)  /* TX 30 Channel table ptr reg */
+#define	maltxctp31r	(MAL_DCR_BASE+0x3F)  /* TX 31 Channel table ptr reg */
+#define	malrxctp0r	(MAL_DCR_BASE+0x40)  /* RX 0 Channel table ptr reg  */
+#define	malrxctp1r	(MAL_DCR_BASE+0x41)  /* RX 1 Channel table ptr reg  */
+#define	malrxctp2r	(MAL_DCR_BASE+0x42)  /* RX 2 Channel table ptr reg  */
+#define	malrxctp3r	(MAL_DCR_BASE+0x43)  /* RX 3 Channel table ptr reg  */
+#define	malrxctp4r	(MAL_DCR_BASE+0x44)  /* RX 4 Channel table ptr reg  */
+#define	malrxctp5r	(MAL_DCR_BASE+0x45)  /* RX 5 Channel table ptr reg  */
+#define	malrxctp6r	(MAL_DCR_BASE+0x46)  /* RX 6 Channel table ptr reg  */
+#define	malrxctp7r	(MAL_DCR_BASE+0x47)  /* RX 7 Channel table ptr reg  */
+#define	malrxctp8r	(MAL_DCR_BASE+0x48)  /* RX 8 Channel table ptr reg  */
+#define	malrxctp9r	(MAL_DCR_BASE+0x49)  /* RX 9 Channel table ptr reg  */
+#define	malrxctp10r	(MAL_DCR_BASE+0x4A)  /* RX 10 Channel table ptr reg */
+#define	malrxctp11r	(MAL_DCR_BASE+0x4B)  /* RX 11 Channel table ptr reg */
+#define	malrxctp12r	(MAL_DCR_BASE+0x4C)  /* RX 12 Channel table ptr reg */
+#define	malrxctp13r	(MAL_DCR_BASE+0x4D)  /* RX 13 Channel table ptr reg */
+#define	malrxctp14r	(MAL_DCR_BASE+0x4E)  /* RX 14 Channel table ptr reg */
+#define	malrxctp15r	(MAL_DCR_BASE+0x4F)  /* RX 15 Channel table ptr reg */
+#define	malrxctp16r	(MAL_DCR_BASE+0x50)  /* RX 16 Channel table ptr reg */
+#define	malrxctp17r	(MAL_DCR_BASE+0x51)  /* RX 17 Channel table ptr reg */
+#define	malrxctp18r	(MAL_DCR_BASE+0x52)  /* RX 18 Channel table ptr reg */
+#define	malrxctp19r	(MAL_DCR_BASE+0x53)  /* RX 19 Channel table ptr reg */
+#define	malrxctp20r	(MAL_DCR_BASE+0x54)  /* RX 20 Channel table ptr reg */
+#define	malrxctp21r	(MAL_DCR_BASE+0x55)  /* RX 21 Channel table ptr reg */
+#define	malrxctp22r	(MAL_DCR_BASE+0x56)  /* RX 22 Channel table ptr reg */
+#define	malrxctp23r	(MAL_DCR_BASE+0x57)  /* RX 23 Channel table ptr reg */
+#define	malrxctp24r	(MAL_DCR_BASE+0x58)  /* RX 24 Channel table ptr reg */
+#define	malrxctp25r	(MAL_DCR_BASE+0x59)  /* RX 25 Channel table ptr reg */
+#define	malrxctp26r	(MAL_DCR_BASE+0x5A)  /* RX 26 Channel table ptr reg */
+#define	malrxctp27r	(MAL_DCR_BASE+0x5B)  /* RX 27 Channel table ptr reg */
+#define	malrxctp28r	(MAL_DCR_BASE+0x5C)  /* RX 28 Channel table ptr reg */
+#define	malrxctp29r	(MAL_DCR_BASE+0x5D)  /* RX 29 Channel table ptr reg */
+#define	malrxctp30r	(MAL_DCR_BASE+0x5E)  /* RX 30 Channel table ptr reg */
+#define	malrxctp31r	(MAL_DCR_BASE+0x5F)  /* RX 31 Channel table ptr reg */
+#define	malrcbs0	(MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg */
+#define	malrcbs1	(MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg */
+#define	malrcbs2	(MAL_DCR_BASE+0x62)  /* RX 2 Channel buffer size reg */
+#define	malrcbs3	(MAL_DCR_BASE+0x63)  /* RX 3 Channel buffer size reg */
+#define	malrcbs4	(MAL_DCR_BASE+0x64)  /* RX 4 Channel buffer size reg */
+#define	malrcbs5	(MAL_DCR_BASE+0x65)  /* RX 5 Channel buffer size reg */
+#define	malrcbs6	(MAL_DCR_BASE+0x66)  /* RX 6 Channel buffer size reg */
+#define	malrcbs7	(MAL_DCR_BASE+0x67)  /* RX 7 Channel buffer size reg */
+#define	malrcbs8	(MAL_DCR_BASE+0x68)  /* RX 8 Channel buffer size reg */
+#define	malrcbs9	(MAL_DCR_BASE+0x69)  /* RX 9 Channel buffer size reg */
+#define	malrcbs10	(MAL_DCR_BASE+0x6A)  /* RX 10 Channel buffer size reg */
+#define	malrcbs11	(MAL_DCR_BASE+0x6B)  /* RX 11 Channel buffer size reg */
+#define	malrcbs12	(MAL_DCR_BASE+0x6C)  /* RX 12 Channel buffer size reg */
+#define	malrcbs13	(MAL_DCR_BASE+0x6D)  /* RX 13 Channel buffer size reg */
+#define	malrcbs14	(MAL_DCR_BASE+0x6E)  /* RX 14 Channel buffer size reg */
+#define	malrcbs15	(MAL_DCR_BASE+0x6F)  /* RX 15 Channel buffer size reg */
+#define	malrcbs16	(MAL_DCR_BASE+0x70)  /* RX 16 Channel buffer size reg */
+#define	malrcbs17	(MAL_DCR_BASE+0x71)  /* RX 17 Channel buffer size reg */
+#define	malrcbs18	(MAL_DCR_BASE+0x72)  /* RX 18 Channel buffer size reg */
+#define	malrcbs19	(MAL_DCR_BASE+0x73)  /* RX 19 Channel buffer size reg */
+#define	malrcbs20	(MAL_DCR_BASE+0x74)  /* RX 20 Channel buffer size reg */
+#define	malrcbs21	(MAL_DCR_BASE+0x75)  /* RX 21 Channel buffer size reg */
+#define	malrcbs22	(MAL_DCR_BASE+0x76)  /* RX 22 Channel buffer size reg */
+#define	malrcbs23	(MAL_DCR_BASE+0x77)  /* RX 23 Channel buffer size reg */
+#define	malrcbs24	(MAL_DCR_BASE+0x78)  /* RX 24 Channel buffer size reg */
+#define	malrcbs25	(MAL_DCR_BASE+0x79)  /* RX 25 Channel buffer size reg */
+#define	malrcbs26	(MAL_DCR_BASE+0x7A)  /* RX 26 Channel buffer size reg */
+#define	malrcbs27	(MAL_DCR_BASE+0x7B)  /* RX 27 Channel buffer size reg */
+#define	malrcbs28	(MAL_DCR_BASE+0x7C)  /* RX 28 Channel buffer size reg */
+#define	malrcbs29	(MAL_DCR_BASE+0x7D)  /* RX 29 Channel buffer size reg */
+#define	malrcbs30	(MAL_DCR_BASE+0x7E)  /* RX 30 Channel buffer size reg */
+#define	malrcbs31	(MAL_DCR_BASE+0x7F)  /* RX 31 Channel buffer size reg */
+
+#else /* !defined(CONFIG_405EZ) */
+
 #define MAL_DCR_BASE 0x180
 #define malmcr  (MAL_DCR_BASE+0x00)  /* MAL Config reg                       */
 #define malesr  (MAL_DCR_BASE+0x01)  /* Error Status reg (Read/Clear)        */
@@ -596,6 +1075,7 @@
 #define malrxctp1r (MAL_DCR_BASE+0x41)  /* RX 1 Channel table pointer reg    */
 #define malrcbs0   (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg      */
 #define malrcbs1   (MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg      */
+#endif /* defined(CONFIG_405EZ) */
 
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
@@ -633,15 +1113,76 @@
 /******************************************************************************
  * On Chip Memory
  ******************************************************************************/
+#if defined(CONFIG_405EZ)
+#define OCM_DCR_BASE 0x020
+#define ocmplb3cr1      (OCM_DCR_BASE+0x00)  /* OCM PLB3 Bank 1 Config Reg    */
+#define ocmplb3cr2      (OCM_DCR_BASE+0x01)  /* OCM PLB3 Bank 2 Config Reg    */
+#define ocmplb3bear     (OCM_DCR_BASE+0x02)  /* OCM PLB3 Bus Error Add Reg    */
+#define ocmplb3besr0    (OCM_DCR_BASE+0x03)  /* OCM PLB3 Bus Error Stat Reg 0 */
+#define ocmplb3besr1    (OCM_DCR_BASE+0x04)  /* OCM PLB3 Bus Error Stat Reg 1 */
+#define ocmcid          (OCM_DCR_BASE+0x05)  /* OCM Core ID                   */
+#define ocmrevid        (OCM_DCR_BASE+0x06)  /* OCM Revision ID               */
+#define ocmplb3dpc      (OCM_DCR_BASE+0x07)  /* OCM PLB3 Data Parity Check    */
+#define ocmdscr1        (OCM_DCR_BASE+0x08)  /* OCM D-side Bank 1 Config Reg  */
+#define ocmdscr2        (OCM_DCR_BASE+0x09)  /* OCM D-side Bank 2 Config Reg  */
+#define ocmiscr1        (OCM_DCR_BASE+0x0A)  /* OCM I-side Bank 1 Config Reg  */
+#define ocmiscr2        (OCM_DCR_BASE+0x0B)  /* OCM I-side Bank 2 Config Reg  */
+#define ocmdsisdpc      (OCM_DCR_BASE+0x0C)  /* OCM D-side/I-side Data Par Chk*/
+#define ocmdsisbear     (OCM_DCR_BASE+0x0D)  /* OCM D-side/I-side Bus Err Addr*/
+#define ocmdsisbesr     (OCM_DCR_BASE+0x0E)  /* OCM D-side/I-side Bus Err Stat*/
+#else
 #define OCM_DCR_BASE 0x018
 #define ocmisarc   (OCM_DCR_BASE+0x00)  /* OCM I-side address compare reg    */
 #define ocmiscntl  (OCM_DCR_BASE+0x01)  /* OCM I-side control reg            */
 #define ocmdsarc   (OCM_DCR_BASE+0x02)  /* OCM D-side address compare reg    */
 #define ocmdscntl  (OCM_DCR_BASE+0x03)  /* OCM D-side control reg            */
+#endif /* CONFIG_405EZ */
 
 /******************************************************************************
  * GPIO macro register defines
  ******************************************************************************/
+#if defined(CONFIG_405EZ)
+/* Only the 405EZ has 2 GPIOs */
+#define GPIO_BASE  0xEF600700
+#define GPIO0_OR		(GPIO_BASE+0x0)
+#define GPIO0_TCR		(GPIO_BASE+0x4)
+#define GPIO0_OSRL		(GPIO_BASE+0x8)
+#define GPIO0_OSRH		(GPIO_BASE+0xC)
+#define GPIO0_TSRL		(GPIO_BASE+0x10)
+#define GPIO0_TSRH		(GPIO_BASE+0x14)
+#define GPIO0_ODR		(GPIO_BASE+0x18)
+#define GPIO0_IR		(GPIO_BASE+0x1C)
+#define GPIO0_RR1		(GPIO_BASE+0x20)
+#define GPIO0_RR2		(GPIO_BASE+0x24)
+#define GPIO0_RR3		(GPIO_BASE+0x28)
+#define GPIO0_ISR1L		(GPIO_BASE+0x30)
+#define GPIO0_ISR1H		(GPIO_BASE+0x34)
+#define GPIO0_ISR2L		(GPIO_BASE+0x38)
+#define GPIO0_ISR2H		(GPIO_BASE+0x3C)
+#define GPIO0_ISR3L		(GPIO_BASE+0x40)
+#define GPIO0_ISR3H		(GPIO_BASE+0x44)
+
+#define GPIO1_BASE  0xEF600800
+#define GPIO1_OR		(GPIO1_BASE+0x0)
+#define GPIO1_TCR		(GPIO1_BASE+0x4)
+#define GPIO1_OSRL		(GPIO1_BASE+0x8)
+#define GPIO1_OSRH		(GPIO1_BASE+0xC)
+#define GPIO1_TSRL		(GPIO1_BASE+0x10)
+#define GPIO1_TSRH		(GPIO1_BASE+0x14)
+#define GPIO1_ODR		(GPIO1_BASE+0x18)
+#define GPIO1_IR		(GPIO1_BASE+0x1C)
+#define GPIO1_RR1		(GPIO1_BASE+0x20)
+#define GPIO1_RR2		(GPIO1_BASE+0x24)
+#define GPIO1_RR3		(GPIO1_BASE+0x28)
+#define GPIO1_ISR1L		(GPIO1_BASE+0x30)
+#define GPIO1_ISR1H		(GPIO1_BASE+0x34)
+#define GPIO1_ISR2L		(GPIO1_BASE+0x38)
+#define GPIO1_ISR2H		(GPIO1_BASE+0x3C)
+#define GPIO1_ISR3L		(GPIO1_BASE+0x40)
+#define GPIO1_ISR3H		(GPIO1_BASE+0x44)
+
+#else	/* !405EZ */
+
 #define GPIO_BASE  0xEF600700
 #define GPIO0_OR               (GPIO_BASE+0x0)
 #define GPIO0_TCR              (GPIO_BASE+0x4)
@@ -658,6 +1199,7 @@
 #define GPIO0_ISR2H            (GPIO_BASE+0x38)
 #define GPIO0_ISR2L            (GPIO_BASE+0x3C)
 
+#endif /* CONFIG_405EZ */
 
 /*
  * Macro for accessing the indirect EBC register
diff --git a/include/ppc440.h b/include/ppc440.h
index e407320..9b15c2c 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -417,7 +417,9 @@
 #define SDR0_PEGPLLSET1		0x000003A0	/* PE Pll LC Tank Setting1 */
 #define SDR0_PEGPLLSET2		0x000003A1	/* PE Pll LC Tank Setting2 */
 #define SDR0_PEGPLLSTS		0x000003A2	/* PE Pll LC Tank Status */
+#endif /* CONFIG_440SPE */
 
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 /*----------------------------------------------------------------------------+
 | SDRAM Controller
 +----------------------------------------------------------------------------*/
@@ -453,9 +455,16 @@
 /*-----------------------------------------------------------------------------+
 |  Memory Bank 0-7 configuration
 +-----------------------------------------------------------------------------*/
-#define SDRAM_RXBAS_SDBA_MASK		0xFF800000	/* Base address	*/
+#if defined(CONFIG_440SPE)
+#define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/
 #define SDRAM_RXBAS_SDBA_ENCODE(n)	((((unsigned long)(n))&0xFFE00000)>>2)
 #define SDRAM_RXBAS_SDBA_DECODE(n)	((((unsigned long)(n))&0xFFE00000)<<2)
+#endif /* CONFIG_440SPE */
+#if defined(CONFIG_440SP)
+#define SDRAM_RXBAS_SDBA_MASK		0xFF800000	/* Base address	*/
+#define SDRAM_RXBAS_SDBA_ENCODE(n)	((((unsigned long)(n))&0xFF800000))
+#define SDRAM_RXBAS_SDBA_DECODE(n)	((((unsigned long)(n))&0xFF800000))
+#endif /* CONFIG_440SP */
 #define SDRAM_RXBAS_SDSZ_MASK		0x0000FFC0	/* Size		*/
 #define SDRAM_RXBAS_SDSZ_ENCODE(n)	((((unsigned long)(n))&0x3FF)<<6)
 #define SDRAM_RXBAS_SDSZ_DECODE(n)	((((unsigned long)(n))>>6)&0x3FF)
@@ -533,9 +542,12 @@
 #define SDRAM_MCSTAT_MIC_MASK		0x80000000	/* Memory init status mask	*/
 #define SDRAM_MCSTAT_MIC_NOTCOMP	0x00000000	/* Mem init not complete	*/
 #define SDRAM_MCSTAT_MIC_COMP		0x80000000	/* Mem init complete		*/
-#define SDRAM_MCSTAT_SRMS_MASK		0x80000000	/* Mem self refresh stat mask	*/
+#define SDRAM_MCSTAT_SRMS_MASK		0x40000000	/* Mem self refresh stat mask	*/
 #define SDRAM_MCSTAT_SRMS_NOT_SF	0x00000000	/* Mem not in self refresh	*/
-#define SDRAM_MCSTAT_SRMS_SF		0x80000000	/* Mem in self refresh		*/
+#define SDRAM_MCSTAT_SRMS_SF		0x40000000	/* Mem in self refresh		*/
+#define SDRAM_MCSTAT_IDLE_MASK		0x20000000	/* Mem self refresh stat mask	*/
+#define SDRAM_MCSTAT_IDLE_NOT		0x00000000	/* Mem contr not idle		*/
+#define SDRAM_MCSTAT_IDLE		0x20000000	/* Mem contr idle		*/
 
 /*-----------------------------------------------------------------------------+
 |  Memory Controller Options 1
@@ -730,6 +742,7 @@
 #define SDRAM_WRDTR_LLWP_1_CYC		0x00000000
 #define SDRAM_WRDTR_WTR_MASK		0x0E000000
 #define SDRAM_WRDTR_WTR_0_DEG		0x06000000
+#define SDRAM_WRDTR_WTR_90_DEG_ADV	0x04000000
 #define SDRAM_WRDTR_WTR_180_DEG_ADV	0x02000000
 #define SDRAM_WRDTR_WTR_270_DEG_ADV	0x00000000
 
@@ -847,6 +860,7 @@
 #define pbear		0x20	/* periph bus error addr reg		*/
 #define pbesr		0x21	/* periph bus error status reg		*/
 #define xbcfg		0x23	/* external bus configuration reg	*/
+#define EBC0_CFG	0x23	/* external bus configuration reg	*/
 #define xbcid		0x24	/* external bus core id reg		*/
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -887,12 +901,14 @@
 
 /* PLB4 Arbiter - PowerPC440EP Pass1 */
 #define PLB4_DCR_BASE           0x080
+#define plb4_acr                (PLB4_DCR_BASE+0x1)
 #define plb4_revid              (PLB4_DCR_BASE+0x2)
-#define plb4_acr                (PLB4_DCR_BASE+0x3)
 #define plb4_besr               (PLB4_DCR_BASE+0x4)
 #define plb4_bearl              (PLB4_DCR_BASE+0x6)
 #define plb4_bearh              (PLB4_DCR_BASE+0x7)
 
+#define PLB4_ACR_WRP		(0x80000000 >> 7)
+
 /* Nebula PLB4 Arbiter - PowerPC440EP */
 #define PLB_ARBITER_BASE   0x80
 
@@ -1350,26 +1366,26 @@
 
 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define UIC2_DCR_BASE 0xe0
-#define uic2sr	(UIC0_DCR_BASE+0x0)   /* UIC2 status-Read Clear		*/
-#define uic2srs	(UIC0_DCR_BASE+0x1)   /* UIC2 status-Read Set */
-#define uic2er	(UIC0_DCR_BASE+0x2)   /* UIC2 enable			*/
-#define uic2cr	(UIC0_DCR_BASE+0x3)   /* UIC2 critical			*/
-#define uic2pr	(UIC0_DCR_BASE+0x4)   /* UIC2 polarity			*/
-#define uic2tr	(UIC0_DCR_BASE+0x5)   /* UIC2 triggering		*/
-#define uic2msr (UIC0_DCR_BASE+0x6)   /* UIC2 masked status		*/
-#define uic2vr	(UIC0_DCR_BASE+0x7)   /* UIC2 vector			*/
-#define uic2vcr (UIC0_DCR_BASE+0x8)   /* UIC2 vector configuration	*/
+#define uic2sr	(UIC2_DCR_BASE+0x0)   /* UIC2 status-Read Clear		*/
+#define uic2srs	(UIC2_DCR_BASE+0x1)   /* UIC2 status-Read Set */
+#define uic2er	(UIC2_DCR_BASE+0x2)   /* UIC2 enable			*/
+#define uic2cr	(UIC2_DCR_BASE+0x3)   /* UIC2 critical			*/
+#define uic2pr	(UIC2_DCR_BASE+0x4)   /* UIC2 polarity			*/
+#define uic2tr	(UIC2_DCR_BASE+0x5)   /* UIC2 triggering		*/
+#define uic2msr (UIC2_DCR_BASE+0x6)   /* UIC2 masked status		*/
+#define uic2vr	(UIC2_DCR_BASE+0x7)   /* UIC2 vector			*/
+#define uic2vcr (UIC2_DCR_BASE+0x8)   /* UIC2 vector configuration	*/
 
 #define UIC3_DCR_BASE 0xf0
-#define uic3sr	(UIC1_DCR_BASE+0x0)   /* UIC3 status-Read Clear		*/
-#define uic3srs	(UIC0_DCR_BASE+0x1)   /* UIC3 status-Read Set */
-#define uic3er	(UIC1_DCR_BASE+0x2)   /* UIC3 enable			*/
-#define uic3cr	(UIC1_DCR_BASE+0x3)   /* UIC3 critical			*/
-#define uic3pr	(UIC1_DCR_BASE+0x4)   /* UIC3 polarity			*/
-#define uic3tr	(UIC1_DCR_BASE+0x5)   /* UIC3 triggering		*/
-#define uic3msr (UIC1_DCR_BASE+0x6)   /* UIC3 masked status		*/
-#define uic3vr	(UIC1_DCR_BASE+0x7)   /* UIC3 vector			*/
-#define uic3vcr (UIC1_DCR_BASE+0x8)   /* UIC3 vector configuration	*/
+#define uic3sr	(UIC3_DCR_BASE+0x0)   /* UIC3 status-Read Clear		*/
+#define uic3srs	(UIC3_DCR_BASE+0x1)   /* UIC3 status-Read Set */
+#define uic3er	(UIC3_DCR_BASE+0x2)   /* UIC3 enable			*/
+#define uic3cr	(UIC3_DCR_BASE+0x3)   /* UIC3 critical			*/
+#define uic3pr	(UIC3_DCR_BASE+0x4)   /* UIC3 polarity			*/
+#define uic3tr	(UIC3_DCR_BASE+0x5)   /* UIC3 triggering		*/
+#define uic3msr (UIC3_DCR_BASE+0x6)   /* UIC3 masked status		*/
+#define uic3vr	(UIC3_DCR_BASE+0x7)   /* UIC3 vector			*/
+#define uic3vcr (UIC3_DCR_BASE+0x8)   /* UIC3 vector configuration	*/
 #endif /* CONFIG_440SPE */
 
 #if defined(CONFIG_440GX)
@@ -2160,6 +2176,20 @@
 /*-----------------------------------------------------------------------------+
 |  SDR0 Bit Settings
 +-----------------------------------------------------------------------------*/
+#if defined(CONFIG_440SP)
+#define SDR0_SRST			0x0200
+
+#define SDR0_DDR0			0x00E1
+#define SDR0_DDR0_DPLLRST		0x80000000
+#define SDR0_DDR0_DDRM_MASK		0x60000000
+#define SDR0_DDR0_DDRM_DDR1		0x20000000
+#define SDR0_DDR0_DDRM_DDR2		0x40000000
+#define SDR0_DDR0_DDRM_ENCODE(n)	((((unsigned long)(n))&0x03)<<29)
+#define SDR0_DDR0_DDRM_DECODE(n)	((((unsigned long)(n))>>29)&0x03)
+#define SDR0_DDR0_TUNE_ENCODE(n)	((((unsigned long)(n))&0x2FF)<<0)
+#define SDR0_DDR0_TUNE_DECODE(n)	((((unsigned long)(n))>>0)&0x2FF)
+#endif
+
 #if defined(CONFIG_440SPE)
 #define SDR0_CP440			0x0180
 #define SDR0_CP440_ERPN_MASK		0x30000000
@@ -3183,7 +3213,8 @@
 #define GPIO0			0
 #define GPIO1			1
 
-#if defined(CONFIG_440GP)
+#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000700)
 
 #define GPIO0_OR               (GPIO0_BASE+0x0)
@@ -3268,6 +3299,8 @@
 #define GPIO_IN_SEL	    0x40000000	    /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
 					    /* For the other GPIO number, you must shift */
 
+#define GPIO_VAL(gpio)		(0x80000000 >> (gpio))
+
 #ifndef __ASSEMBLY__
 
 typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
@@ -3278,32 +3311,31 @@ typedef struct { unsigned long	add;	/* gpio core base address */
 	gpio_select_t  alt_nb; /* Selected Alternate */
 } gpio_param_s;
 
-
 #endif /* __ASSEMBLY__ */
 
 /*
  * Macros for accessing the indirect EBC registers
  */
-#define mtebc(reg, data)	mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
-#define mfebc(reg, data)	mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
+#define mtebc(reg, data)	do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } while (0)
+#define mfebc(reg, data)	do { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } while (0)
 
 /*
  * Macros for accessing the indirect SDRAM controller registers
  */
-#define mtsdram(reg, data)	mtdcr(memcfga,reg);mtdcr(memcfgd,data)
-#define mfsdram(reg, data)	mtdcr(memcfga,reg);data = mfdcr(memcfgd)
+#define mtsdram(reg, data)	do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
+#define mfsdram(reg, data)	do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
 
 /*
  * Macros for accessing the indirect clocking controller registers
  */
-#define mtclk(reg, data)	mtdcr(clkcfga,reg);mtdcr(clkcfgd,data)
-#define mfclk(reg, data)	mtdcr(clkcfga,reg);data = mfdcr(clkcfgd)
+#define mtclk(reg, data)	do { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } while (0)
+#define mfclk(reg, data)	do { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } while (0)
 
 /*
  * Macros for accessing the sdr controller registers
  */
-#define mtsdr(reg, data)	mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
-#define mfsdr(reg, data)	mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
+#define mtsdr(reg, data)	do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
+#define mfsdr(reg, data)	do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
 
 
 #ifndef __ASSEMBLY__
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 43c5ca4..3d8ca09 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -130,13 +130,13 @@ typedef struct emac_4xx_hw_st {
 
 
 #if defined(CONFIG_440GX)
-#define EMAC_NUM_DEV	    4
+#define EMAC_NUM_DEV		4
 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) &&	\
 	defined(CONFIG_NET_MULTI) &&			\
 	!defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
-#define EMAC_NUM_DEV	    2
+#define EMAC_NUM_DEV		2
 #else
-#define EMAC_NUM_DEV	    1
+#define EMAC_NUM_DEV		1
 #endif
 
 #ifdef CONFIG_IBM_EMAC4_V4	/* EMAC4 V4 changed bit setting */
@@ -153,16 +153,16 @@ typedef struct emac_4xx_hw_st {
 /*ZMII Bridge Register addresses */
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0D00)
+#define ZMII_BASE		(CFG_PERIPHERAL_BASE + 0x0D00)
 #else
-#define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0780)
+#define ZMII_BASE		(CFG_PERIPHERAL_BASE + 0x0780)
 #endif
-#define ZMII_FER			(ZMII_BASE)
-#define ZMII_SSR			(ZMII_BASE + 4)
-#define ZMII_SMIISR			(ZMII_BASE + 8)
+#define ZMII_FER		(ZMII_BASE)
+#define ZMII_SSR		(ZMII_BASE + 4)
+#define ZMII_SMIISR		(ZMII_BASE + 8)
 
-#define ZMII_RMII			0x22000000
-#define ZMII_MDI0			0x80000000
+#define ZMII_RMII		0x22000000
+#define ZMII_MDI0		0x80000000
 
 /* ZMII FER Register Bit Definitions */
 #define ZMII_FER_DIS		(0x0)
@@ -299,49 +299,41 @@ typedef struct emac_4xx_hw_st {
 #if defined(CONFIG_440)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0E00)
+#define EMAC_BASE		(CFG_PERIPHERAL_BASE + 0x0E00)
 #else
-#define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0800)
+#define EMAC_BASE		(CFG_PERIPHERAL_BASE + 0x0800)
 #endif
 #else
-#define EMAC_BASE 			0xEF600800
+#if defined(CONFIG_405EZ)
+#define EMAC_BASE 		0xEF600900
+#else
+#define EMAC_BASE 		0xEF600800
+#endif
 #endif
 
-#define EMAC_M0				    (EMAC_BASE)
-#define EMAC_M1				    (EMAC_BASE + 4)
-#define EMAC_TXM0				(EMAC_BASE + 8)
-#define EMAC_TXM1				(EMAC_BASE + 12)
-#define EMAC_RXM				(EMAC_BASE + 16)
-#define EMAC_ISR				(EMAC_BASE + 20)
-#define EMAC_IER				(EMAC_BASE + 24)
-#define EMAC_IAH				(EMAC_BASE + 28)
-#define EMAC_IAL				(EMAC_BASE + 32)
-#define EMAC_VLAN_TPID_REG		(EMAC_BASE + 36)
-#define EMAC_VLAN_TCI_REG		(EMAC_BASE + 40)
+#define EMAC_M0			(EMAC_BASE)
+#define EMAC_M1			(EMAC_BASE + 4)
+#define EMAC_TXM0		(EMAC_BASE + 8)
+#define EMAC_TXM1		(EMAC_BASE + 12)
+#define EMAC_RXM		(EMAC_BASE + 16)
+#define EMAC_ISR		(EMAC_BASE + 20)
+#define EMAC_IER		(EMAC_BASE + 24)
+#define EMAC_IAH		(EMAC_BASE + 28)
+#define EMAC_IAL		(EMAC_BASE + 32)
 #define EMAC_PAUSE_TIME_REG	(EMAC_BASE + 44)
-#define EMAC_IND_HASH_1			(EMAC_BASE + 48)
-#define EMAC_IND_HASH_2			(EMAC_BASE + 52)
-#define EMAC_IND_HASH_3			(EMAC_BASE + 56)
-#define EMAC_IND_HASH_4			(EMAC_BASE + 60)
-#define EMAC_GRP_HASH_1			(EMAC_BASE + 64)
-#define EMAC_GRP_HASH_2			(EMAC_BASE + 68)
-#define EMAC_GRP_HASH_3			(EMAC_BASE + 72)
-#define EMAC_GRP_HASH_4			(EMAC_BASE + 76)
-#define EMAC_LST_SRC_LOW		(EMAC_BASE + 80)
-#define EMAC_LST_SRC_HI			(EMAC_BASE + 84)
 #define EMAC_I_FRAME_GAP_REG	(EMAC_BASE + 88)
-#define EMAC_STACR			    (EMAC_BASE + 92)
-#define EMAC_TRTR				(EMAC_BASE + 96)
-#define EMAC_RX_HI_LO_WMARK		(EMAC_BASE + 100)
+#define EMAC_STACR		(EMAC_BASE + 92)
+#define EMAC_TRTR		(EMAC_BASE + 96)
+#define EMAC_RX_HI_LO_WMARK	(EMAC_BASE + 100)
 
 /* bit definitions */
 /* MODE REG 0 */
-#define EMAC_M0_RXI			    (0x80000000)
-#define EMAC_M0_TXI			    (0x40000000)
-#define EMAC_M0_SRST			(0x20000000)
-#define EMAC_M0_TXE			    (0x10000000)
-#define EMAC_M0_RXE			    (0x08000000)
-#define EMAC_M0_WKE			    (0x04000000)
+#define EMAC_M0_RXI		(0x80000000)
+#define EMAC_M0_TXI		(0x40000000)
+#define EMAC_M0_SRST		(0x20000000)
+#define EMAC_M0_TXE		(0x10000000)
+#define EMAC_M0_RXE		(0x08000000)
+#define EMAC_M0_WKE		(0x04000000)
 
 /* on 440GX EMAC_MR1 has a different layout! */
 #if defined(CONFIG_440GX) || \
@@ -351,23 +343,23 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M1_FDE		(0x80000000)
 #define EMAC_M1_ILE		(0x40000000)
 #define EMAC_M1_VLE		(0x20000000)
-#define EMAC_M1_EIFC			(0x10000000)
-#define EMAC_M1_APP			    (0x08000000)
-#define EMAC_M1_RSVD			(0x06000000)
-#define EMAC_M1_IST			    (0x01000000)
-#define EMAC_M1_MF_1000MBPS		(0x00800000)	/* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS		(0x00400000)
-#define EMAC_M1_RFS_16K			(0x00280000)	/* ~4k for 512 byte */
-#define EMAC_M1_RFS_8K			(0x00200000)	/* ~4k for 512 byte */
-#define EMAC_M1_RFS_4K			(0x00180000)	/* ~4k for 512 byte */
-#define EMAC_M1_RFS_2K			(0x00100000)
-#define EMAC_M1_RFS_1K			(0x00080000)
-#define EMAC_M1_TX_FIFO_16K		(0x00050000)	/* 0's for 512 byte */
-#define EMAC_M1_TX_FIFO_8K		(0x00040000)
-#define EMAC_M1_TX_FIFO_4K		(0x00030000)
+#define EMAC_M1_EIFC		(0x10000000)
+#define EMAC_M1_APP		(0x08000000)
+#define EMAC_M1_RSVD		(0x06000000)
+#define EMAC_M1_IST		(0x01000000)
+#define EMAC_M1_MF_1000MBPS	(0x00800000)	/* 0's for 10MBPS */
+#define EMAC_M1_MF_100MBPS	(0x00400000)
+#define EMAC_M1_RFS_16K		(0x00280000)	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_8K		(0x00200000)	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_4K		(0x00180000)	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_2K		(0x00100000)
+#define EMAC_M1_RFS_1K		(0x00080000)
+#define EMAC_M1_TX_FIFO_16K	(0x00050000)	/* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_8K	(0x00040000)
+#define EMAC_M1_TX_FIFO_4K	(0x00030000)
 #define EMAC_M1_TX_FIFO_2K	(0x00020000)
-#define EMAC_M1_TX_FIFO_1K		(0x00010000)
-#define EMAC_M1_TR_MULTI		(0x00008000)	/* 0'x for single packet */
+#define EMAC_M1_TX_FIFO_1K	(0x00010000)
+#define EMAC_M1_TR_MULTI	(0x00008000)	/* 0'x for single packet */
 #define EMAC_M1_MWSW		(0x00007000)
 #define EMAC_M1_JUMBO_ENABLE	(0x00000800)
 #define EMAC_M1_IPPA		(0x000007c0)
@@ -378,34 +370,34 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M1_RSVD1		(0x00000007)
 #else /* defined(CONFIG_440GX) */
 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
-#define EMAC_M1_FDE			0x80000000
-#define EMAC_M1_ILE			0x40000000
-#define EMAC_M1_VLE			0x20000000
-#define EMAC_M1_EIFC			0x10000000
-#define EMAC_M1_APP			0x08000000
-#define EMAC_M1_AEMI			0x02000000
-#define EMAC_M1_IST			0x01000000
-#define EMAC_M1_MF_1000MBPS		0x00800000	/* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS		0x00400000
-#define EMAC_M1_RFS_4K			0x00300000	/* ~4k for 512 byte */
-#define EMAC_M1_RFS_2K			0x00200000
-#define EMAC_M1_RFS_1K			0x00100000
-#define EMAC_M1_TX_FIFO_2K		0x00080000	/* 0's for 512 byte */
-#define EMAC_M1_TX_FIFO_1K		0x00040000
-#define EMAC_M1_TR0_DEPEND		0x00010000	/* 0'x for single packet */
-#define EMAC_M1_TR0_MULTI		0x00008000
-#define EMAC_M1_TR1_DEPEND		0x00004000
-#define EMAC_M1_TR1_MULTI		0x00002000
+#define EMAC_M1_FDE		0x80000000
+#define EMAC_M1_ILE		0x40000000
+#define EMAC_M1_VLE		0x20000000
+#define EMAC_M1_EIFC		0x10000000
+#define EMAC_M1_APP		0x08000000
+#define EMAC_M1_AEMI		0x02000000
+#define EMAC_M1_IST		0x01000000
+#define EMAC_M1_MF_1000MBPS	0x00800000	/* 0's for 10MBPS */
+#define EMAC_M1_MF_100MBPS	0x00400000
+#define EMAC_M1_RFS_4K		0x00300000	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_2K		0x00200000
+#define EMAC_M1_RFS_1K		0x00100000
+#define EMAC_M1_TX_FIFO_2K	0x00080000	/* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_1K	0x00040000
+#define EMAC_M1_TR0_DEPEND	0x00010000	/* 0'x for single packet */
+#define EMAC_M1_TR0_MULTI	0x00008000
+#define EMAC_M1_TR1_DEPEND	0x00004000
+#define EMAC_M1_TR1_MULTI	0x00002000
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define EMAC_M1_JUMBO_ENABLE		0x00001000
+#define EMAC_M1_JUMBO_ENABLE	0x00001000
 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
 #endif /* defined(CONFIG_440GX) */
 
 /* Transmit Mode Register 0 */
-#define EMAC_TXM0_GNP0			(0x80000000)
-#define EMAC_TXM0_GNP1			(0x40000000)
-#define EMAC_TXM0_GNPD			(0x20000000)
-#define EMAC_TXM0_FC			(0x10000000)
+#define EMAC_TXM0_GNP0		(0x80000000)
+#define EMAC_TXM0_GNP1		(0x40000000)
+#define EMAC_TXM0_GNPD		(0x20000000)
+#define EMAC_TXM0_FC		(0x10000000)
 
 /* Receive Mode Register */
 #define EMAC_RMR_SP		(0x80000000)
@@ -427,39 +419,38 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_ISR_PP		(0x01000000)
 #define EMAC_ISR_BP		(0x00800000)
 #define EMAC_ISR_RP		(0x00400000)
-#define EMAC_ISR_SE			(0x00200000)
-#define EMAC_ISR_SYE			(0x00100000)
-#define EMAC_ISR_BFCS			(0x00080000)
-#define EMAC_ISR_PTLE			(0x00040000)
-#define EMAC_ISR_ORE			(0x00020000)
-#define EMAC_ISR_IRE			(0x00010000)
-#define EMAC_ISR_DBDM			(0x00000200)
-#define EMAC_ISR_DB0			(0x00000100)
-#define EMAC_ISR_SE0			(0x00000080)
-#define EMAC_ISR_TE0			(0x00000040)
-#define EMAC_ISR_DB1			(0x00000020)
-#define EMAC_ISR_SE1			(0x00000010)
-#define EMAC_ISR_TE1			(0x00000008)
-#define EMAC_ISR_MOS			(0x00000002)
-#define EMAC_ISR_MOF			(0x00000001)
-
+#define EMAC_ISR_SE		(0x00200000)
+#define EMAC_ISR_SYE		(0x00100000)
+#define EMAC_ISR_BFCS		(0x00080000)
+#define EMAC_ISR_PTLE		(0x00040000)
+#define EMAC_ISR_ORE		(0x00020000)
+#define EMAC_ISR_IRE		(0x00010000)
+#define EMAC_ISR_DBDM		(0x00000200)
+#define EMAC_ISR_DB0		(0x00000100)
+#define EMAC_ISR_SE0		(0x00000080)
+#define EMAC_ISR_TE0		(0x00000040)
+#define EMAC_ISR_DB1		(0x00000020)
+#define EMAC_ISR_SE1		(0x00000010)
+#define EMAC_ISR_TE1		(0x00000008)
+#define EMAC_ISR_MOS		(0x00000002)
+#define EMAC_ISR_MOF		(0x00000001)
 
 /* STA CONTROL REG */
-#define EMAC_STACR_OC			(0x00008000)
-#define EMAC_STACR_PHYE			(0x00004000)
+#define EMAC_STACR_OC		(0x00008000)
+#define EMAC_STACR_PHYE		(0x00004000)
 
 #ifdef CONFIG_IBM_EMAC4_V4	/* EMAC4 V4 changed bit setting */
-#define EMAC_STACR_INDIRECT_MODE	(0x00002000)
-#define EMAC_STACR_WRITE		(0x00000800) /* $BUC */
-#define EMAC_STACR_READ			(0x00001000) /* $BUC */
-#define EMAC_STACR_OP_MASK		(0x00001800)
-#define EMAC_STACR_MDIO_ADDR		(0x00000000)
-#define EMAC_STACR_MDIO_WRITE		(0x00000800)
-#define EMAC_STACR_MDIO_READ		(0x00001800)
-#define EMAC_STACR_MDIO_READ_INC	(0x00001000)
+#define EMAC_STACR_INDIRECT_MODE (0x00002000)
+#define EMAC_STACR_WRITE	(0x00000800) /* $BUC */
+#define EMAC_STACR_READ		(0x00001000) /* $BUC */
+#define EMAC_STACR_OP_MASK	(0x00001800)
+#define EMAC_STACR_MDIO_ADDR	(0x00000000)
+#define EMAC_STACR_MDIO_WRITE	(0x00000800)
+#define EMAC_STACR_MDIO_READ	(0x00001800)
+#define EMAC_STACR_MDIO_READ_INC (0x00001000)
 #else
-#define EMAC_STACR_WRITE		(0x00002000)
-#define EMAC_STACR_READ			(0x00001000)
+#define EMAC_STACR_WRITE	(0x00002000)
+#define EMAC_STACR_READ		(0x00001000)
 #endif
 
 #define EMAC_STACR_CLK_83MHZ	(0x00000800)  /* 0's for 50Mhz */
@@ -467,9 +458,9 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_STACR_CLK_100MHZ	(0x00000C00)
 
 /* Transmit Request Threshold Register */
-#define EMAC_TRTR_256			(0x18000000)   /* 0's for 64 Bytes */
-#define EMAC_TRTR_192			(0x10000000)
-#define EMAC_TRTR_128			(0x01000000)
+#define EMAC_TRTR_256		(0x18000000)   /* 0's for 64 Bytes */
+#define EMAC_TRTR_192		(0x10000000)
+#define EMAC_TRTR_128		(0x01000000)
 
 /* the follwing defines are for the MadMAL status and control registers. */
 /* For bits 0..5 look at the mal.h file					 */
diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile
index de7114b..3197fe1 100644
--- a/lib_blackfin/Makefile
+++ b/lib_blackfin/Makefile
@@ -29,9 +29,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(ARCH).a
 
-SOBJS	=
+SOBJS	= memcpy.o memcmp.o memset.o memmove.o
 
-COBJS	= board.o bf533_linux.o bf533_string.o cache.o muldi3.o
+COBJS	= post.o tests.o board.o bf533_linux.o bf533_string.o cache.o muldi3.o
 
 SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/lib_blackfin/bf533_linux.c b/lib_blackfin/bf533_linux.c
index 88b4da2..1b0d90a 100644
--- a/lib_blackfin/bf533_linux.c
+++ b/lib_blackfin/bf533_linux.c
@@ -43,20 +43,21 @@
 #define SHOW_BOOT_PROGRESS(arg)
 #endif
 
-#define CMD_LINE_ADDR 0xFF900000  /* L1 scratchpad */
+#define CMD_LINE_ADDR 0xFF900000	/* L1 scratchpad */
 
 #ifdef SHARED_RESOURCES
-	extern void swap_to(int device_id);
+extern void swap_to(int device_id);
 #endif
 
+extern image_header_t header;
+extern void flush_instruction_cache(void);
+extern void flush_data_cache(void);
 static char *make_command_line(void);
 
-extern image_header_t header;
-extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
 void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
 		    ulong addr, ulong * len_ptr, int verify)
 {
-	int (*appl)(char *cmdline);
+	int (*appl) (char *cmdline);
 	char *cmdline;
 
 #ifdef SHARED_RESOURCES
@@ -66,26 +67,26 @@ void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
 	appl = (int (*)(char *))ntohl(header.ih_ep);
 	printf("Starting Kernel at = %x\n", appl);
 	cmdline = make_command_line();
-	if(icache_status()){
+	if (icache_status()) {
 		flush_instruction_cache();
 		icache_disable();
-		}
-	if(dcache_status()){
+	}
+	if (dcache_status()) {
 		flush_data_cache();
 		dcache_disable();
-		}
-	(*appl)(cmdline);
+	}
+	(*appl) (cmdline);
 }
 
 char *make_command_line(void)
 {
-    char *dest = (char *) CMD_LINE_ADDR;
-    char *bootargs;
+	char *dest = (char *)CMD_LINE_ADDR;
+	char *bootargs;
 
-    if ( (bootargs = getenv("bootargs")) == NULL )
-	return NULL;
+	if ((bootargs = getenv("bootargs")) == NULL)
+		return NULL;
 
-    strncpy(dest, bootargs, 0x1000);
-    dest[0xfff] = 0;
-    return dest;
+	strncpy(dest, bootargs, 0x1000);
+	dest[0xfff] = 0;
+	return dest;
 }
diff --git a/lib_blackfin/bf533_string.c b/lib_blackfin/bf533_string.c
index c8b1a3a..85b1150 100644
--- a/lib_blackfin/bf533_string.c
+++ b/lib_blackfin/bf533_string.c
@@ -28,9 +28,15 @@
 #include <common.h>
 #include <asm/setup.h>
 #include <asm/page.h>
-#include <asm/cpu/defBF533.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
 
-void *dma_memcpy(void *,const void *,size_t);
+extern void blackfin_icache_flush_range(const void *, const void *);
+extern void blackfin_dcache_flush_range(const void *, const void *);
+extern void *memcpy_ASM(void *dest, const void *src, size_t count);
+
+void *dma_memcpy(void *, const void *, size_t);
 
 char *strcpy(char *dest, const char *src)
 {
@@ -38,11 +44,11 @@ char *strcpy(char *dest, const char *src)
 	char temp = 0;
 
 	__asm__ __volatile__
-		("1:\t%2 = B [%1++] (Z);\n\t"
-		"B [%0++] = %2;\n\t"
-		"CC = %2;\n\t"
-		"if cc jump 1b (bp);\n":"=a"(dest), "=a"(src), "=d"(temp)
-		:"0"(dest), "1"(src), "2"(temp):"memory");
+	    ("1:\t%2 = B [%1++] (Z);\n\t"
+	     "B [%0++] = %2;\n\t"
+	     "CC = %2;\n\t"
+	     "if cc jump 1b (bp);\n":"=a"(dest), "=a"(src), "=d"(temp)
+	     :"0"(dest), "1"(src), "2"(temp):"memory");
 
 	return xdest;
 }
@@ -56,16 +62,16 @@ char *strncpy(char *dest, const char *src, size_t n)
 		return xdest;
 
 	__asm__ __volatile__
-		("1:\t%3 = B [%1++] (Z);\n\t"
-		"B [%0++] = %3;\n\t"
-		"CC = %3;\n\t"
-		"if ! cc jump 2f;\n\t"
-		"%2 += -1;\n\t"
-		"CC = %2 == 0;\n\t"
-		"if ! cc jump 1b (bp);\n"
-		"2:\n":"=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
-		:"0"(dest), "1"(src), "2"(n), "3"(temp)
-		:"memory");
+	    ("1:\t%3 = B [%1++] (Z);\n\t"
+	     "B [%0++] = %3;\n\t"
+	     "CC = %3;\n\t"
+	     "if ! cc jump 2f;\n\t"
+	     "%2 += -1;\n\t"
+	     "CC = %2 == 0;\n\t"
+	     "if ! cc jump 1b (bp);\n"
+	     "2:\n":"=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
+	     :"0"(dest), "1"(src), "2"(n), "3"(temp)
+	     :"memory");
 
 	return xdest;
 }
@@ -74,18 +80,16 @@ int strcmp(const char *cs, const char *ct)
 {
 	char __res1, __res2;
 
-	__asm__
-		("1:\t%2 = B[%0++] (Z);\n\t"	/* get *cs */
-		"%3 = B[%1++] (Z);\n\t"		/* get *ct */
-		"CC = %2 == %3;\n\t"		/* compare a byte */
-		"if ! cc jump 2f;\n\t"		/* not equal, break out */
-		"CC = %2;\n\t"			/* at end of cs? */
+	__asm__("1:\t%2 = B[%0++] (Z);\n\t"	/* get *cs */
+		"%3 = B[%1++] (Z);\n\t"	/* get *ct */
+		"CC = %2 == %3;\n\t"	/* compare a byte */
+		"if ! cc jump 2f;\n\t"	/* not equal, break out */
+		"CC = %2;\n\t"	/* at end of cs? */
 		"if cc jump 1b (bp);\n\t"	/* no, keep going */
-		"jump.s 3f;\n"			/* strings are equal */
-		"2:\t%2 = %2 - %3;\n"		/* *cs - *ct */
-		"3:\n":	"=a"(cs), "=a"(ct), "=d"(__res1),
-		"=d"(__res2)
-		: "0"(cs), "1"(ct));
+		"jump.s 3f;\n"	/* strings are equal */
+		"2:\t%2 = %2 - %3;\n"	/* *cs - *ct */
+      "3:\n":	"=a"(cs), "=a"(ct), "=d"(__res1), "=d"(__res2)
+      :	"0"(cs), "1"(ct));
 
 	return __res1;
 }
@@ -97,20 +101,19 @@ int strncmp(const char *cs, const char *ct, size_t count)
 	if (!count)
 		return 0;
 
-	__asm__
-		("1:\t%3 = B[%0++] (Z);\n\t"	/* get *cs */
-		"%4 = B[%1++] (Z);\n\t"		/* get *ct */
-		"CC = %3 == %4;\n\t"		/* compare a byte */
-		"if ! cc jump 3f;\n\t"		/* not equal, break out */
-		"CC = %3;\n\t"			/* at end of cs? */
-		"if ! cc jump 4f;\n\t"		/* yes, all done */
-		"%2 += -1;\n\t"			/* no, adjust count */
+	__asm__("1:\t%3 = B[%0++] (Z);\n\t"	/* get *cs */
+		"%4 = B[%1++] (Z);\n\t"	/* get *ct */
+		"CC = %3 == %4;\n\t"	/* compare a byte */
+		"if ! cc jump 3f;\n\t"	/* not equal, break out */
+		"CC = %3;\n\t"	/* at end of cs? */
+		"if ! cc jump 4f;\n\t"	/* yes, all done */
+		"%2 += -1;\n\t"	/* no, adjust count */
 		"CC = %2 == 0;\n\t" "if ! cc jump 1b;\n"	/* more to do, keep going */
-		"2:\t%3 = 0;\n\t"		/* strings are equal */
+		"2:\t%3 = 0;\n\t"	/* strings are equal */
 		"jump.s    4f;\n" "3:\t%3 = %3 - %4;\n"	/* *cs - *ct */
- 		"4:":	"=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1),
+      "4:":	"=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1),
 		"=d"(__res2)
-		: "0"(cs), "1"(ct), "2"(count));
+      :	"0"(cs), "1"(ct), "2"(count));
 
 	return __res1;
 }
@@ -124,62 +127,65 @@ int strncmp(const char *cs, const char *ct, size_t count)
  * You should not use this function to access IO space, use memcpy_toio()
  * or memcpy_fromio() instead.
  */
-void * memcpy(void * dest,const void *src,size_t count)
+void *memcpy(void *dest, const void *src, size_t count)
 {
-	char *tmp = (char *) dest, *s = (char *) src;
-
-/* Turn off the cache, if destination in the L1 memory */
-	if ( (tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)
-		|| (tmp >= (char *)DATA_BANKA_SRAM) && (tmp < DATA_BANKA_SRAM_END)
-	    || (tmp >= (char *)DATA_BANKB_SRAM) && (tmp < DATA_BANKB_SRAM_END) ){
-			if(icache_status()){
-					blackfin_icache_flush_range(src, src+count);
-					icache_disable();
-			}
-			if(dcache_status()){
-					blackfin_dcache_flush_range(src, src+count);
-					dcache_disable();
-			}
-			dma_memcpy(dest,src,count);
-	}else{
-		while(count--)
-			*tmp++ = *s++;
+	char *tmp = (char *)dest, *s = (char *)src;
+
+	/* L1_ISRAM can only be accessed via dma */
+	if ((tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)) {
+		/* L1 is the destination */
+		dma_memcpy(dest, src, count);
+
+		if (icache_status()) {
+			blackfin_icache_flush_range(src, src + count);
+		}
+	} else if ((s >= (char *)L1_ISRAM) && (s < (char *)L1_ISRAM_END)) {
+		/* L1 is the source */
+		dma_memcpy(dest, src, count);
+
+		if (icache_status()) {
+			blackfin_icache_flush_range(dest, dest + count);
+		}
+		if (dcache_status()) {
+			blackfin_dcache_flush_range(dest, dest + count);
+		}
+	} else {
+		memcpy_ASM(dest, src, count);
 	}
 	return dest;
 }
 
-void *dma_memcpy(void * dest,const void *src,size_t count)
+void *dma_memcpy(void *dest, const void *src, size_t count)
 {
-
-		*pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR;
-
-		/* Copy sram functions from sdram to sram */
-		/* Setup destination start address */
-		*pMDMA_D0_START_ADDR = (volatile void **)dest;
-		/* Setup destination xcount */
-		*pMDMA_D0_X_COUNT = count ;
-		/* Setup destination xmodify */
-		*pMDMA_D0_X_MODIFY = 1;
-
-		/* Setup Source start address */
-		*pMDMA_S0_START_ADDR = (volatile void **)src;
-		/* Setup Source xcount */
-		*pMDMA_S0_X_COUNT = count;
-		/* Setup Source xmodify */
-		*pMDMA_S0_X_MODIFY = 1;
-
-		/* Enable source DMA */
-		*pMDMA_S0_CONFIG = (DMAEN);
-		asm("ssync;");
-
-		*pMDMA_D0_CONFIG = ( WNR | DMAEN);
-
-		while(*pMDMA_D0_IRQ_STATUS & DMA_RUN){
-			*pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
-		}
+	*pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR;
+
+	/* Copy sram functions from sdram to sram */
+	/* Setup destination start address */
+	*pMDMA_D0_START_ADDR = (volatile void **)dest;
+	/* Setup destination xcount */
+	*pMDMA_D0_X_COUNT = count;
+	/* Setup destination xmodify */
+	*pMDMA_D0_X_MODIFY = 1;
+
+	/* Setup Source start address */
+	*pMDMA_S0_START_ADDR = (volatile void **)src;
+	/* Setup Source xcount */
+	*pMDMA_S0_X_COUNT = count;
+	/* Setup Source xmodify */
+	*pMDMA_S0_X_MODIFY = 1;
+
+	/* Enable source DMA */
+	*pMDMA_S0_CONFIG = (DMAEN);
+	sync();
+
+	*pMDMA_D0_CONFIG = (WNR | DMAEN);
+
+	while (*pMDMA_D0_IRQ_STATUS & DMA_RUN) {
 		*pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
+	}
+	*pMDMA_D0_IRQ_STATUS |= (DMA_DONE | DMA_ERR);
 
-		dest += count;
-		src  += count;
-		return dest;
+	dest += count;
+	src += count;
+	return dest;
 }
diff --git a/lib_blackfin/blackfin_board.h b/lib_blackfin/blackfin_board.h
index 31c16a2..e0b96da 100644
--- a/lib_blackfin/blackfin_board.h
+++ b/lib_blackfin/blackfin_board.h
@@ -28,6 +28,8 @@
 #ifndef __BLACKFIN_BOARD_H__
 #define __BLACKFIN_BOARD_H__
 
+#include <version.h>
+
 extern void timer_init(void);
 extern void init_IRQ(void);
 extern void rtc_init(void);
diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c
index d9dc2b6..1a0a282 100644
--- a/lib_blackfin/board.c
+++ b/lib_blackfin/board.c
@@ -32,21 +32,69 @@
 #include <version.h>
 #include <net.h>
 #include <environment.h>
+#include <i2c.h>
 #include "blackfin_board.h"
+#include <asm/cplb.h>
 #include "../drivers/smc91111.h"
 
-DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
+#include <post.h>
+int post_flag;
+#endif
 
+#ifndef CFG_NO_FLASH
 extern flash_info_t flash_info[];
+#endif
+
+static inline u_long get_vco(void)
+{
+	u_long msel;
+	u_long vco;
 
+	msel = (*pPLL_CTL >> 9) & 0x3F;
+	if (0 == msel)
+		msel = 64;
+
+	vco = CONFIG_CLKIN_HZ;
+	vco >>= (1 & *pPLL_CTL);	/* DF bit */
+	vco = msel * vco;
+	return vco;
+}
+
+/*Get the Core clock*/
+u_long get_cclk(void)
+{
+	u_long csel, ssel;
+	if (*pPLL_STAT & 0x1)
+		return CONFIG_CLKIN_HZ;
+
+	ssel = *pPLL_DIV;
+	csel = ((ssel >> 4) & 0x03);
+	ssel &= 0xf;
+	if (ssel && ssel < (1 << csel))	/* SCLK > CCLK */
+		return get_vco() / ssel;
+	return get_vco() >> csel;
+}
+
+/* Get the System clock */
+u_long get_sclk(void)
+{
+	u_long ssel;
+
+	if (*pPLL_STAT & 0x1)
+		return CONFIG_CLKIN_HZ;
+
+	ssel = (*pPLL_DIV & 0xf);
+
+	return get_vco() / ssel;
+}
 
 static void mem_malloc_init(void)
 {
 	mem_malloc_start = CFG_MALLOC_BASE;
 	mem_malloc_end = (CFG_MALLOC_BASE + CFG_MALLOC_LEN);
 	mem_malloc_brk = mem_malloc_start;
-	memset((void *) mem_malloc_start, 0,
-	mem_malloc_end - mem_malloc_start);
+	memset((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
 }
 
 void *sbrk(ptrdiff_t increment)
@@ -59,7 +107,7 @@ void *sbrk(ptrdiff_t increment)
 	}
 	mem_malloc_brk = new;
 
-	return ((void *) old);
+	return ((void *)old);
 }
 
 static int display_banner(void)
@@ -78,17 +126,20 @@ static void display_flash_config(ulong size)
 
 static int init_baudrate(void)
 {
-	uchar tmp[64];
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char tmp[64];
 	int i = getenv_r("baudrate", tmp, sizeof(tmp));
 	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
-		? (int) simple_strtoul(tmp, NULL, 10)
-		: CONFIG_BAUDRATE;
+	    ? (int)simple_strtoul(tmp, NULL, 10)
+	    : CONFIG_BAUDRATE;
 	return (0);
 }
 
 #ifdef DEBUG
 static void display_global_data(void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
 	bd_t *bd;
 	bd = gd->bd;
 	printf("--flags:%x\n", gd->flags);
@@ -103,12 +154,10 @@ static void display_global_data(void)
 	printf("---bi_baudrate:%x\n", bd->bi_baudrate);
 	printf("---bi_ip_addr:%x\n", bd->bi_ip_addr);
 	printf("---bi_enetaddr:%x %x %x %x %x %x\n",
-				bd->bi_enetaddr[0],
-				bd->bi_enetaddr[1],
-				bd->bi_enetaddr[2],
-				bd->bi_enetaddr[3],
-				bd->bi_enetaddr[4],
-				bd->bi_enetaddr[5]);
+	       bd->bi_enetaddr[0],
+	       bd->bi_enetaddr[1],
+	       bd->bi_enetaddr[2],
+	       bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
 	printf("---bi_arch_number:%x\n", bd->bi_arch_number);
 	printf("---bi_boot_params:%x\n", bd->bi_boot_params);
 	printf("---bi_memstart:%x\n", bd->bi_memstart);
@@ -120,6 +169,71 @@ static void display_global_data(void)
 }
 #endif
 
+/* we cover everything with 4 meg pages, and need an extra for L1 */
+unsigned int icplb_table[page_descriptor_table_size][2];
+unsigned int dcplb_table[page_descriptor_table_size][2];
+
+void init_cplbtables(void)
+{
+	int i, j;
+
+	j = 0;
+	icplb_table[j][0] = 0xFFA00000;
+	icplb_table[j][1] = L1_IMEMORY;
+	j++;
+
+	for (i = 0; i <= CONFIG_MEM_SIZE / 4; i++) {
+		icplb_table[j][0] = (i * 4 * 1024 * 1024);
+		if (i * 4 * 1024 * 1024 <= CFG_MONITOR_BASE
+		    && (i + 1) * 4 * 1024 * 1024 >= CFG_MONITOR_BASE) {
+			icplb_table[j][1] = SDRAM_IKERNEL;
+		} else {
+			icplb_table[j][1] = SDRAM_IGENERIC;
+		}
+		j++;
+	}
+#if defined(CONFIG_BF561)
+	/* Async Memory space */
+	for (i = 0; i < 3; i++) {
+		icplb_table[j++][0] = 0x20000000 + i * 4 * 1024 * 1024;
+		icplb_table[j++][1] = SDRAM_IGENERIC;
+	}
+#else
+	icplb_table[j][0] = 0x20000000;
+	icplb_table[j][1] = SDRAM_IGENERIC;
+#endif
+	j = 0;
+	dcplb_table[j][0] = 0xFF800000;
+	dcplb_table[j][1] = L1_DMEMORY;
+	j++;
+
+	for (i = 0; i < CONFIG_MEM_SIZE / 4; i++) {
+		dcplb_table[j][0] = (i * 4 * 1024 * 1024);
+		if (i * 4 * 1024 * 1024 <= CFG_MONITOR_BASE
+		    && (i + 1) * 4 * 1024 * 1024 >= CFG_MONITOR_BASE) {
+			dcplb_table[j][1] = SDRAM_DKERNEL;
+		} else {
+			dcplb_table[j][1] = SDRAM_DGENERIC;
+		}
+		j++;
+	}
+
+#if defined(CONFIG_BF561)
+	/* MAC space */
+	dcplb_table[j++][0] = CONFIG_ASYNC_EBIU_BASE;
+	dcplb_table[j++][1] = SDRAM_EBIU;
+
+	/* Flash space */
+	for (i = 0; i < 2; i++) {
+		dcplb_table[j++][0] = 0x20000000 + i * 4 * 1024 * 1024;
+		dcplb_table[j++][1] = SDRAM_EBIU;
+	}
+#else
+	dcplb_table[j][0] = 0x20000000;
+	dcplb_table[j][1] = SDRAM_EBIU;
+#endif
+}
+
 /*
  * All attempts to come up with a "common" initialization sequence
  * that works for all boards and architectures failed: some of the
@@ -135,20 +249,24 @@ static void display_global_data(void)
 
 void board_init_f(ulong bootflag)
 {
+	DECLARE_GLOBAL_DATA_PTR;
 	ulong addr;
 	bd_t *bd;
+	int i;
+
+	init_cplbtables();
 
 	gd = (gd_t *) (CFG_GBL_DATA_ADDR);
-	memset((void *) gd, 0, sizeof(gd_t));
+	memset((void *)gd, 0, sizeof(gd_t));
 
 	/* Board data initialization */
 	addr = (CFG_GBL_DATA_ADDR + sizeof(gd_t));
 
 	/* Align to 4 byte boundary */
 	addr &= ~(4 - 1);
-	bd = (bd_t*)addr;
+	bd = (bd_t *) addr;
 	gd->bd = bd;
-	memset((void *) bd, 0, sizeof(bd_t));
+	memset((void *)bd, 0, sizeof(bd_t));
 
 	/* Initialize */
 	init_IRQ();
@@ -156,21 +274,51 @@ void board_init_f(ulong bootflag)
 	init_baudrate();	/* initialze baudrate settings */
 	serial_init();		/* serial communications setup */
 	console_init_f();
+#ifdef CONFIG_ICACHE_ON
+	icache_enable();
+#endif
+#ifdef CONFIG_DCACHE_ON
+	dcache_enable();
+#endif
 	display_banner();	/* say that we are here */
+
+	for (i = 0; i < page_descriptor_table_size; i++) {
+		debug
+		    ("data (%02i)= 0x%08x : 0x%08x    intr = 0x%08x : 0x%08x\n",
+		     i, dcplb_table[i][0], dcplb_table[i][1], icplb_table[i][0],
+		     icplb_table[i][1]);
+	}
+
 	checkboard();
 #if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
 	rtc_init();
 #endif
 	timer_init();
-	printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n", \
-	CONFIG_VCO_HZ/1000000, CONFIG_CCLK_HZ/1000000, CONFIG_SCLK_HZ/1000000);
+	printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n",
+	       get_vco() / 1000000, get_cclk() / 1000000, get_sclk() / 1000000);
 	printf("SDRAM: ");
 	print_size(initdram(0), "\n");
+#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
+	post_init_f();
+	post_bootmode_init();
+	post_run(NULL, POST_ROM | post_bootmode_get(0));
+#endif
 	board_init_r((gd_t *) gd, 0x20000010);
 }
 
+#if defined(CONFIG_SOFT_I2C) || defined(CONFIG_HARD_I2C)
+static int init_func_i2c(void)
+{
+	puts("I2C:   ");
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	puts("ready\n");
+	return (0);
+}
+#endif
+
 void board_init_r(gd_t * id, ulong dest_addr)
 {
+	DECLARE_GLOBAL_DATA_PTR;
 	ulong size;
 	extern void malloc_bin_reloc(void);
 	char *s, *e;
@@ -180,12 +328,18 @@ void board_init_r(gd_t * id, ulong dest_addr)
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 	bd = gd->bd;
 
-#if	CONFIG_STAMP
+#if    defined(CONFIG_BF537) && defined(CONFIG_POST)
+	post_output_backlog();
+	post_reloc();
+#endif
+
+#if	(CONFIG_STAMP || CONFIG_BF537 || CONFIG_EZKIT561) && !defined(CFG_NO_FLASH)
 	/* There are some other pointer constants we must deal with */
 	/* configure available FLASH banks */
 	size = flash_init();
 	display_flash_config(size);
-	flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + 0x1ffff, &flash_info[0]);
+	flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,
+		      CFG_FLASH_BASE + 0x1ffff, &flash_info[0]);
 	bd->bi_flashstart = CFG_FLASH_BASE;
 	bd->bi_flashsize = size;
 	bd->bi_flashoffset = 0;
@@ -198,6 +352,13 @@ void board_init_r(gd_t * id, ulong dest_addr)
 	mem_malloc_init();
 	malloc_bin_reloc();
 
+#ifdef CONFIG_SPI
+# if ! defined(CFG_ENV_IS_IN_EEPROM)
+	spi_init_f();
+# endif
+	spi_init_r();
+#endif
+
 	/* relocate environment function pointers etc. */
 	env_relocate();
 
@@ -228,18 +389,30 @@ void board_init_r(gd_t * id, ulong dest_addr)
 		copy_filename(BootFile, s, sizeof(BootFile));
 	}
 #endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
 #if defined(CONFIG_MISC_INIT_R)
 	/* miscellaneous platform dependent initialisations */
 	misc_init_r();
 #endif
 
+#if ((BFIN_CPU == ADSP_BF537) || (BFIN_CPU == ADSP_BF536))
+	printf("Net:    ");
+	eth_initialize(bd);
+#endif
+
 #ifdef CONFIG_DRIVER_SMC91111
 #ifdef SHARED_RESOURCES
 	/* Switch to Ethernet */
 	swap_to(ETHERNET);
 #endif
-	if  ( (SMC_inw(BANK_SELECT) & UPPER_BYTE_MASK) != SMC_IDENT ) {
-		printf("ERROR: Can't find SMC91111 at address %x\n", SMC_BASE_ADDRESS);
+	if ((SMC_inw(BANK_SELECT) & UPPER_BYTE_MASK) != SMC_IDENT) {
+		printf("ERROR: Can't find SMC91111 at address %x\n",
+		       SMC_BASE_ADDRESS);
 	} else {
 		printf("Net:   SMC91111 at 0x%08X\n", SMC_BASE_ADDRESS);
 	}
@@ -248,12 +421,17 @@ void board_init_r(gd_t * id, ulong dest_addr)
 	swap_to(FLASH);
 #endif
 #endif
-#ifdef CONFIG_SOFT_I2C
+#if defined(CONFIG_SOFT_I2C) || defined(CONFIG_HARD_I2C)
 	init_func_i2c();
 #endif
 
 #ifdef DEBUG
-	display_global_data(void);
+	display_global_data();
+#endif
+
+#if defined(CONFIG_BF537) && defined(CONFIG_POST)
+	if (post_flag)
+		post_run(NULL, POST_RAM | post_bootmode_get(0));
 #endif
 
 	/* main_loop() can return to retry autoboot, if so just run it again. */
@@ -262,18 +440,8 @@ void board_init_r(gd_t * id, ulong dest_addr)
 	}
 }
 
-#ifdef CONFIG_SOFT_I2C
-static int init_func_i2c (void)
-{
-	puts ("I2C:   ");
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
-	puts ("ready\n");
-	return (0);
-}
-#endif
-
 void hang(void)
 {
 	puts("### ERROR ### Please RESET the board ###\n");
-	for (;;);
+	for (;;) ;
 }
diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c
index 847278d..a15914b 100644
--- a/lib_blackfin/cache.c
+++ b/lib_blackfin/cache.c
@@ -26,15 +26,26 @@
  */
 
 /* for now: just dummy functions to satisfy the linker */
-extern void blackfin_icache_range (unsigned long *, unsigned long *);
-extern void blackfin_dcache_range (unsigned long *, unsigned long *);
-void flush_cache (unsigned long dummy1, unsigned long dummy2)
+#include <config.h>
+#include <common.h>
+#include <asm/blackfin.h>
+
+extern void blackfin_icache_flush_range(unsigned long, unsigned long);
+extern void blackfin_dcache_flush_range(unsigned long, unsigned long);
+
+void flush_cache(unsigned long dummy1, unsigned long dummy2)
 {
-	if (icache_status ()) {
-		blackfin_icache_flush_range (dummy1, dummy1 + dummy2);
-	}
-	if (dcache_status ()) {
-		blackfin_dcache_flush_range (dummy1, dummy1 + dummy2);
-	}
+	if ((dummy1 >= L1_ISRAM) && (dummy1 < L1_ISRAM_END))
+		return;
+	if ((dummy1 >= DATA_BANKA_SRAM) && (dummy1 < DATA_BANKA_SRAM_END))
+		return;
+	if ((dummy1 >= DATA_BANKB_SRAM) && (dummy1 < DATA_BANKB_SRAM_END))
+		return;
+
+	if (icache_status())
+		blackfin_icache_flush_range(dummy1, dummy1 + dummy2);
+	if (dcache_status())
+		blackfin_dcache_flush_range(dummy1, dummy1 + dummy2);
+
 	return;
 }
diff --git a/lib_blackfin/memcmp.S b/lib_blackfin/memcmp.S
new file mode 100644
index 0000000..fcea5b3
--- /dev/null
+++ b/lib_blackfin/memcmp.S
@@ -0,0 +1,109 @@
+/*
+ * File:         arch/blackfin/lib/memcmp.S
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:          $Id: memcmp.S 2386 2006-11-01 04:57:26Z magicyang $
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+.align 2
+
+/*
+ * C Library function MEMCMP
+ * R0 = First Address
+ * R1 = Second Address
+ * R2 = count
+ * Favours word aligned data.
+ */
+
+.globl _memcmp;
+_memcmp:
+	I1 = P3;
+	P0 = R0;			/* P0 = s1 address */
+	P3 = R1;			/* P3 = s2 Address  */
+	P2 = R2 ;			/* P2 = count */
+	CC = R2 <= 7(IU);
+	IF CC JUMP  .Ltoo_small;
+	I0 = R1;			/* s2 */
+	R1 = R1 | R0;		/* OR addresses together */
+	R1 <<= 30;		/* check bottom two bits */
+	CC =  AZ;			/* AZ set if zero. */
+	IF !CC JUMP  .Lbytes ;	/* Jump if addrs not aligned. */
+
+	P1 = P2 >> 2;		/* count = n/4 */
+	R3 =  3;
+	R2 = R2 & R3;		/* remainder */
+	P2 = R2;			/* set remainder */
+
+	LSETUP (.Lquad_loop_s , .Lquad_loop_e) LC0=P1;
+.Lquad_loop_s:
+	NOP;
+	R0 = [P0++];
+	R1 = [I0++];
+	CC = R0 == R1;
+	IF !CC JUMP .Lquad_different;
+.Lquad_loop_e:
+	NOP;
+
+	P3 = I0;			/* s2 */
+.Ltoo_small:
+	CC = P2 == 0;		/* Check zero count*/
+	IF CC JUMP .Lfinished;	/* very unlikely*/
+
+.Lbytes:
+	LSETUP (.Lbyte_loop_s , .Lbyte_loop_e) LC0=P2;
+.Lbyte_loop_s:
+	R1 = B[P3++](Z);	/* *s2 */
+	R0 = B[P0++](Z);	/* *s1 */
+	CC = R0 == R1;
+	IF !CC JUMP .Ldifferent;
+.Lbyte_loop_e:
+	NOP;
+
+.Ldifferent:
+	R0 = R0 - R1;
+	P3 = I1;
+	RTS;
+
+.Lquad_different:
+/* We've read two quads which don't match.
+ * Can't just compare them, because we're
+ * a little-endian machine, so the MSBs of
+ * the regs occur at later addresses in the
+ * string.
+ * Arrange to re-read those two quads again,
+ * byte-by-byte.
+ */
+	P0 += -4;		/* back up to the start of the */
+	P3 = I0;		/* quads, and increase the*/
+	P2 += 4;		/* remainder count*/
+	P3 += -4;
+	JUMP .Lbytes;
+
+.Lfinished:
+	R0 = 0;
+	P3 = I1;
+	RTS;
diff --git a/lib_blackfin/memcpy.S b/lib_blackfin/memcpy.S
new file mode 100644
index 0000000..a73ff90
--- /dev/null
+++ b/lib_blackfin/memcpy.S
@@ -0,0 +1,127 @@
+/*
+ * File:         arch/blackfin/lib/memcpy.S
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  internal version of memcpy(), issued by the compiler
+ *               to copy blocks of data around.
+ *               This is really memmove() - it has to be able to deal with
+ *               possible overlaps, because that ambiguity is when the compiler
+ *               gives up and calls a function. We have our own, internal version
+ *               so that we get something we trust, even if the user has redefined
+ *               the normal symbol.
+ * Rev:          $Id: memcpy.S 2775 2007-02-21 13:58:44Z hennerich $
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+.align 2
+
+.globl _memcpy_ASM;
+_memcpy_ASM:
+	CC = R2 <=  0;	/* length not positive?*/
+	IF CC JUMP  .L_P1L2147483647;	/* Nothing to do */
+
+	P0 = R0 ;	/* dst*/
+	P1 = R1 ;	/* src*/
+	P2 = R2 ;	/* length */
+
+	/* check for overlapping data */
+	CC = R1 < R0;	/* src < dst */
+	IF !CC JUMP .Lno_overlap;
+	R3 = R1 + R2;
+	CC = R0 < R3;	/* and dst < src+len */
+	IF CC JUMP .Lhas_overlap;
+
+.Lno_overlap:
+	/* Check for aligned data.*/
+
+	R3 = R1 | R0;
+	R0 = 0x3;
+	R3 = R3 & R0;
+	CC = R3;	/* low bits set on either address? */
+	IF CC JUMP .Lnot_aligned;
+
+	/* Both addresses are word-aligned, so we can copy
+	at least part of the data using word copies.*/
+	P2 = P2 >> 2;
+	CC = P2 <= 2;
+	IF !CC JUMP .Lmore_than_seven;
+	/* less than eight bytes... */
+	P2 = R2;
+	LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
+	R0 = R1;	/* setup src address for return */
+.Lthree_start:
+	R3 = B[P1++] (X);
+.Lthree_end:
+	B[P0++] = R3;
+
+	RTS;
+
+.Lmore_than_seven:
+	/* There's at least eight bytes to copy. */
+	P2 += -1;	/* because we unroll one iteration */
+	LSETUP(.Lword_loop, .Lword_loop) LC0=P2;
+	R0 = R1;
+	I1 = P1;
+	R3 = [I1++];
+.Lword_loop:
+	MNOP || [P0++] = R3 || R3 = [I1++];
+
+	[P0++] = R3;
+	/* Any remaining bytes to copy? */
+	R3 = 0x3;
+	R3 = R2 & R3;
+	CC = R3 == 0;
+	P1 = I1;	/* in case there's something left, */
+	IF !CC JUMP .Lbytes_left;
+	RTS;
+.Lbytes_left:	P2 = R3;
+.Lnot_aligned:
+	/* From here, we're copying byte-by-byte. */
+	LSETUP (.Lbyte_start , .Lbyte_end) LC0=P2;
+	R0 = R1;	/* Save src address for return */
+.Lbyte_start:
+	R1 = B[P1++] (X);
+.Lbyte_end:
+	B[P0++] = R1;
+
+.L_P1L2147483647:
+	RTS;
+
+.Lhas_overlap:
+/* Need to reverse the copying, because the
+ * dst would clobber the src.
+ * Don't bother to work out alignment for
+ * the reverse case.
+ */
+	R0 = R1;	/* save src for later. */
+	P0 = P0 + P2;
+	P0 += -1;
+	P1 = P1 + P2;
+	P1 += -1;
+	LSETUP(.Lover_start, .Lover_end) LC0=P2;
+.Lover_start:
+	R1 = B[P1--] (X);
+.Lover_end:
+	B[P0--] = R1;
+
+	RTS;
diff --git a/lib_blackfin/memmove.S b/lib_blackfin/memmove.S
new file mode 100644
index 0000000..79558f9
--- /dev/null
+++ b/lib_blackfin/memmove.S
@@ -0,0 +1,102 @@
+/*
+ * File:         arch/blackfin/lib/memmove.S
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:          $Id: memmove.S 2205 2006-09-23 07:53:49Z vapier $
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+.align 2
+
+/*
+ * C Library function MEMMOVE
+ * R0 = To Address (leave unchanged to form result)
+ * R1 = From Address
+ * R2 = count
+ * Data may overlap
+ */
+
+.globl _memmove;
+_memmove:
+	I1 = P3;
+	P0 = R0;                  /* P0 = To address */
+	P3 = R1;                  /* P3 = From Address */
+	P2 = R2 ;                 /* P2 = count */
+	CC = P2 == 0;             /* Check zero count*/
+	IF CC JUMP .Lfinished;    /* very unlikely */
+
+	CC = R1 < R0 (IU);        /* From < To */
+	IF !CC JUMP .Lno_overlap;
+	R3 = R1 + R2;
+	CC = R0 <= R3 (IU);       /* (From+len) >= To */
+	IF CC JUMP .Loverlap;
+.Lno_overlap:
+	R3 = 11;
+	CC = R2 <= R3;
+	IF CC JUMP  .Lbytes;
+	R3 = R1 | R0;             /* OR addresses together */
+	R3 <<= 30;                /* check bottom two bits */
+	CC =  AZ;                 /* AZ set if zero.*/
+	IF !CC JUMP  .Lbytes ;    /* Jump if addrs not aligned.*/
+
+	I0 = P3;
+	P1 = P2 >> 2;             /* count = n/4 */
+	P1 += -1;
+	R3 =  3;
+	R2 = R2 & R3;             /* remainder */
+	P2 = R2;                  /* set remainder */
+	R1 = [I0++];
+
+	LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
+.Lquad_loop: MNOP || [P0++] = R1 || R1 = [I0++];
+	[P0++] = R1;
+
+	CC = P2 == 0;             /* any remaining bytes? */
+	P3 = I0;                  /* Ammend P3 to updated ptr. */
+	IF !CC JUMP .Lbytes;
+	P3 = I1;
+	RTS;
+
+.Lbytes:     LSETUP (.Lbyte2_s , .Lbyte2_e) LC0=P2;
+.Lbyte2_s:   R1 = B[P3++](Z);
+.Lbyte2_e:   B[P0++] = R1;
+
+.Lfinished:  P3 = I1;
+	RTS;
+
+.Loverlap:
+	P2 += -1;
+	P0 = P0 + P2;
+	P3 = P3 + P2;
+	R1 = B[P3--] (Z);
+	CC = P2 == 0;
+	IF CC JUMP .Lno_loop;
+	LSETUP (.Lol_s, .Lol_e) LC0 = P2;
+.Lol_s:    B[P0--] = R1;
+.Lol_e:    R1 = B[P3--] (Z);
+.Lno_loop: B[P0] = R1;
+	P3 = I1;
+	RTS;
diff --git a/lib_blackfin/memset.S b/lib_blackfin/memset.S
new file mode 100644
index 0000000..7e6ee19
--- /dev/null
+++ b/lib_blackfin/memset.S
@@ -0,0 +1,103 @@
+/*
+ * File:         arch/blackfin/lib/memset.S
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:          $Id: memset.S 2769 2007-02-19 16:45:53Z hennerich $
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+
+.align 2
+
+/*
+ * C Library function MEMSET
+ * R0 = address (leave unchanged to form result)
+ * R1 = filler byte
+ * R2 = count
+ * Favours word aligned data.
+ */
+
+.globl _memset;
+_memset:
+	P0 = R0 ;              /* P0 = address */
+	P2 = R2 ;              /* P2 = count   */
+	R3 = R0 + R2;          /* end          */
+	CC = R2 <= 7(IU);
+	IF CC JUMP  .Ltoo_small;
+	R1 = R1.B (Z);         /* R1 = fill char */
+	R2 =  3;
+	R2 = R0 & R2;          /* addr bottom two bits */
+	CC =  R2 == 0;             /* AZ set if zero.	*/
+	IF !CC JUMP  .Lforce_align ;  /* Jump if addr not aligned. */
+
+.Laligned:
+	P1 = P2 >> 2;          /* count = n/4        */
+	R2 = R1 <<  8;         /* create quad filler */
+	R2.L = R2.L + R1.L(NS);
+	R2.H = R2.L + R1.H(NS);
+	P2 = R3;
+
+	LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
+.Lquad_loop:
+	[P0++] = R2;
+
+	CC = P0 == P2;
+	IF !CC JUMP .Lbytes_left;
+	RTS;
+
+.Lbytes_left:
+	R2 = R3;                /* end point */
+	R3 = P0;                /* current position */
+	R2 = R2 - R3;           /* bytes left */
+	P2 = R2;
+
+.Ltoo_small:
+	CC = P2 == 0;           /* Check zero count */
+	IF CC JUMP .Lfinished;    /* Unusual */
+
+.Lbytes:
+	LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
+.Lbyte_loop:
+	B[P0++] = R1;
+
+.Lfinished:
+	RTS;
+
+.Lforce_align:
+	CC = BITTST (R0, 0);  /* odd byte */
+	R0 = 4;
+	R0 = R0 - R2;
+	P1 = R0;
+	R0 = P0;		    /* Recover return address */
+	IF !CC JUMP .Lskip1;
+	B[P0++] = R1;
+.Lskip1:
+	CC = R2 <= 2;          /* 2 bytes */
+	P2 -= P1;              /* reduce count */
+	IF !CC JUMP .Laligned;
+	B[P0++] = R1;
+	B[P0++] = R1;
+	JUMP .Laligned;
diff --git a/lib_blackfin/muldi3.c b/lib_blackfin/muldi3.c
index 1fc34e3..da55711 100644
--- a/lib_blackfin/muldi3.c
+++ b/lib_blackfin/muldi3.c
@@ -64,29 +64,29 @@ do {									\
 	__w.ll; })
 #endif
 
-typedef unsigned int USItype    __attribute__ ((mode (SI)));
-typedef int SItype     __attribute__ ((mode (SI)));
-typedef int DItype     __attribute__ ((mode (DI)));
-typedef	int word_type __attribute__ ((mode (__word__)));
+typedef unsigned int USItype __attribute__ ((mode(SI)));
+typedef int SItype __attribute__ ((mode(SI)));
+typedef int DItype __attribute__ ((mode(DI)));
+typedef int word_type __attribute__ ((mode(__word__)));
 
-struct DIstruct {SItype low, high;};
-typedef union
-{
+struct DIstruct {
+	SItype low, high;
+};
+typedef union {
 	struct DIstruct s;
 	DItype ll;
 } DIunion;
 
-DItype __muldi3 (DItype u, DItype v)
+DItype __muldi3(DItype u, DItype v)
 {
 	DIunion w;
 	DIunion uu, vv;
 
-	uu.ll = u,
-	vv.ll = v;
+	uu.ll = u, vv.ll = v;
 	/*  panic("kernel panic for __muldi3"); */
-	w.ll = __umulsidi3 (uu.s.low, vv.s.low);
+	w.ll = __umulsidi3(uu.s.low, vv.s.low);
 	w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
-	+ (USItype) uu.s.high * (USItype) vv.s.low);
+		     + (USItype) uu.s.high * (USItype) vv.s.low);
 
 	return w.ll;
 }
diff --git a/lib_blackfin/post.c b/lib_blackfin/post.c
new file mode 100644
index 0000000..0e76026
--- /dev/null
+++ b/lib_blackfin/post.c
@@ -0,0 +1,435 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <console.h>
+#include <watchdog.h>
+#include <post.h>
+
+#ifdef CONFIG_LOGBUFFER
+#include <logbuff.h>
+#endif
+
+#ifdef CONFIG_POST
+
+#define POST_MAX_NUMBER		32
+
+#define BOOTMODE_MAGIC	0xDEAD0000
+
+int post_init_f(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int res = 0;
+	unsigned int i;
+
+	for (i = 0; i < post_list_size; i++) {
+		struct post_test *test = post_list + i;
+
+		if (test->init_f && test->init_f()) {
+			res = -1;
+		}
+	}
+
+	gd->post_init_f_time = post_time_ms(0);
+	if (!gd->post_init_f_time) {
+		printf
+		    ("post/post.c: post_time_ms seems not to be implemented\n");
+	}
+
+	return res;
+}
+
+void post_bootmode_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int bootmode = post_bootmode_get(0);
+	int newword;
+
+	if (post_hotkeys_pressed() && !(bootmode & POST_POWERTEST)) {
+		newword = BOOTMODE_MAGIC | POST_SLOWTEST;
+	} else if (bootmode == 0) {
+		newword = BOOTMODE_MAGIC | POST_POWERON;
+	} else if (bootmode == POST_POWERON || bootmode == POST_SLOWTEST) {
+		newword = BOOTMODE_MAGIC | POST_NORMAL;
+	} else {
+		/* Use old value */
+		newword = post_word_load() & ~POST_COLDBOOT;
+	}
+
+	if (bootmode == 0) {
+		/* We are booting after power-on */
+		newword |= POST_COLDBOOT;
+	}
+
+	post_word_store(newword);
+
+	/* Reset activity record */
+	gd->post_log_word = 0;
+}
+
+int post_bootmode_get(unsigned int *last_test)
+{
+	unsigned long word = post_word_load();
+	int bootmode;
+
+	if ((word & 0xFFFF0000) != BOOTMODE_MAGIC) {
+		return 0;
+	}
+
+	bootmode = word & 0x7F;
+
+	if (last_test && (bootmode & POST_POWERTEST)) {
+		*last_test = (word >> 8) & 0xFF;
+	}
+
+	return bootmode;
+}
+
+/* POST tests run before relocation only mark status bits .... */
+static void post_log_mark_start(unsigned long testid)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gd->post_log_word |= (testid) << 16;
+}
+
+static void post_log_mark_succ(unsigned long testid)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gd->post_log_word |= testid;
+}
+
+/* ... and the messages are output once we are relocated */
+void post_output_backlog(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int j;
+
+	for (j = 0; j < post_list_size; j++) {
+		if (gd->post_log_word & (post_list[j].testid << 16)) {
+			post_log("POST %s ", post_list[j].cmd);
+			if (gd->post_log_word & post_list[j].testid)
+				post_log("PASSED\n");
+			else {
+				post_log("FAILED\n");
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+				show_boot_progress(-31);
+#endif
+			}
+		}
+	}
+}
+
+static void post_bootmode_test_on(unsigned int last_test)
+{
+	unsigned long word = post_word_load();
+
+	word |= POST_POWERTEST;
+
+	word |= (last_test & 0xFF) << 8;
+
+	post_word_store(word);
+}
+
+static void post_bootmode_test_off(void)
+{
+	unsigned long word = post_word_load();
+
+	word &= ~POST_POWERTEST;
+
+	post_word_store(word);
+}
+
+static void post_get_flags(int *test_flags)
+{
+	int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST };
+	char *var[] = { "post_poweron", "post_normal", "post_slowtest" };
+	int varnum = sizeof(var) / sizeof(var[0]);
+	char list[128];		/* long enough for POST list */
+	char *name;
+	char *s;
+	int last;
+	int i, j;
+
+	for (j = 0; j < post_list_size; j++) {
+		test_flags[j] = post_list[j].flags;
+	}
+
+	for (i = 0; i < varnum; i++) {
+		if (getenv_r(var[i], list, sizeof(list)) <= 0)
+			continue;
+
+		for (j = 0; j < post_list_size; j++) {
+			test_flags[j] &= ~flag[i];
+		}
+
+		last = 0;
+		name = list;
+		while (!last) {
+			while (*name && *name == ' ')
+				name++;
+			if (*name == 0)
+				break;
+			s = name + 1;
+			while (*s && *s != ' ')
+				s++;
+			if (*s == 0)
+				last = 1;
+			else
+				*s = 0;
+
+			for (j = 0; j < post_list_size; j++) {
+				if (strcmp(post_list[j].cmd, name) == 0) {
+					test_flags[j] |= flag[i];
+					break;
+				}
+			}
+
+			if (j == post_list_size) {
+				printf("No such test: %s\n", name);
+			}
+
+			name = s + 1;
+		}
+	}
+
+	for (j = 0; j < post_list_size; j++) {
+		if (test_flags[j] & POST_POWERON) {
+			test_flags[j] |= POST_SLOWTEST;
+		}
+	}
+}
+
+static int post_run_single(struct post_test *test,
+			   int test_flags, int flags, unsigned int i)
+{
+	if ((flags & test_flags & POST_ALWAYS) &&
+	    (flags & test_flags & POST_MEM)) {
+		WATCHDOG_RESET();
+
+		if (!(flags & POST_REBOOT)) {
+			if ((test_flags & POST_REBOOT)
+			    && !(flags & POST_MANUAL)) {
+				post_bootmode_test_on(i);
+			}
+
+			if (test_flags & POST_PREREL)
+				post_log_mark_start(test->testid);
+			else
+				post_log("POST %s ", test->cmd);
+		}
+
+		if (test_flags & POST_PREREL) {
+			if ((*test->test) (flags) == 0)
+				post_log_mark_succ(test->testid);
+		} else {
+			if ((*test->test) (flags) != 0) {
+				post_log("FAILED\n");
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+				show_boot_progress(-32);
+#endif
+			} else
+				post_log("PASSED\n");
+		}
+
+		if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) {
+			post_bootmode_test_off();
+		}
+
+		return 0;
+	} else {
+		return -1;
+	}
+}
+
+int post_run(char *name, int flags)
+{
+	unsigned int i;
+	int test_flags[POST_MAX_NUMBER];
+
+	post_get_flags(test_flags);
+
+	if (name == NULL) {
+		unsigned int last;
+
+		if (post_bootmode_get(&last) & POST_POWERTEST) {
+			if (last < post_list_size &&
+			    (flags & test_flags[last] & POST_ALWAYS) &&
+			    (flags & test_flags[last] & POST_MEM)) {
+
+				post_run_single(post_list + last,
+						test_flags[last],
+						flags | POST_REBOOT, last);
+
+				for (i = last + 1; i < post_list_size; i++) {
+					post_run_single(post_list + i,
+							test_flags[i],
+							flags, i);
+				}
+			}
+		} else {
+			for (i = 0; i < post_list_size; i++) {
+				post_run_single(post_list + i,
+						test_flags[i], flags, i);
+			}
+		}
+
+		return 0;
+	} else {
+		for (i = 0; i < post_list_size; i++) {
+			if (strcmp(post_list[i].cmd, name) == 0)
+				break;
+		}
+
+		if (i < post_list_size) {
+			return post_run_single(post_list + i,
+					       test_flags[i], flags, i);
+		} else {
+			return -1;
+		}
+	}
+}
+
+static int post_info_single(struct post_test *test, int full)
+{
+	if (test->flags & POST_MANUAL) {
+		if (full)
+			printf("%s - %s\n"
+			       "  %s\n", test->cmd, test->name, test->desc);
+		else
+			printf("  %-15s - %s\n", test->cmd, test->name);
+
+		return 0;
+	} else {
+		return -1;
+	}
+}
+
+int post_info(char *name)
+{
+	unsigned int i;
+
+	if (name == NULL) {
+		for (i = 0; i < post_list_size; i++) {
+			post_info_single(post_list + i, 0);
+		}
+
+		return 0;
+	} else {
+		for (i = 0; i < post_list_size; i++) {
+			if (strcmp(post_list[i].cmd, name) == 0)
+				break;
+		}
+
+		if (i < post_list_size) {
+			return post_info_single(post_list + i, 1);
+		} else {
+			return -1;
+		}
+	}
+}
+
+int post_log(char *format, ...)
+{
+	va_list args;
+	uint i;
+	char printbuffer[CFG_PBSIZE];
+
+	va_start(args, format);
+
+	/* For this to work, printbuffer must be larger than
+	 * anything we ever want to print.
+	 */
+	i = vsprintf(printbuffer, format, args);
+	va_end(args);
+
+#ifdef CONFIG_LOGBUFFER
+	/* Send to the logbuffer */
+	logbuff_log(printbuffer);
+#else
+	/* Send to the stdout file */
+	puts(printbuffer);
+#endif
+
+	return 0;
+}
+
+void post_reloc(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned int i;
+
+	/*
+	 * We have to relocate the test table manually
+	 */
+	for (i = 0; i < post_list_size; i++) {
+		ulong addr;
+		struct post_test *test = post_list + i;
+
+		if (test->name) {
+			addr = (ulong) (test->name) + gd->reloc_off;
+			test->name = (char *)addr;
+		}
+
+		if (test->cmd) {
+			addr = (ulong) (test->cmd) + gd->reloc_off;
+			test->cmd = (char *)addr;
+		}
+
+		if (test->desc) {
+			addr = (ulong) (test->desc) + gd->reloc_off;
+			test->desc = (char *)addr;
+		}
+
+		if (test->test) {
+			addr = (ulong) (test->test) + gd->reloc_off;
+			test->test = (int (*)(int flags))addr;
+		}
+
+		if (test->init_f) {
+			addr = (ulong) (test->init_f) + gd->reloc_off;
+			test->init_f = (int (*)(void))addr;
+		}
+
+		if (test->reloc) {
+			addr = (ulong) (test->reloc) + gd->reloc_off;
+			test->reloc = (void (*)(void))addr;
+
+			test->reloc();
+		}
+	}
+}
+
+/*
+ * Some tests (e.g. SYSMON) need the time when post_init_f started,
+ * but we cannot use get_timer() at this point.
+ *
+ * On PowerPC we implement it using the timebase register.
+ */
+unsigned long post_time_ms(unsigned long base)
+{
+	return (unsigned long)get_ticks() / (get_tbclk() / CFG_HZ) - base;
+}
+
+#endif				/* CONFIG_POST */
diff --git a/lib_blackfin/tests.c b/lib_blackfin/tests.c
new file mode 100644
index 0000000..051649d
--- /dev/null
+++ b/lib_blackfin/tests.c
@@ -0,0 +1,253 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Be sure to mark tests to be run before relocation as such with the
+ * CFG_POST_PREREL flag so that logging is done correctly if the
+ * logbuffer support is enabled.
+ */
+
+#include <common.h>
+#include <config.h>
+#ifdef CONFIG_POST
+
+#include <post.h>
+#define CFG_POST_FLASH  0x00004000
+#define CFG_POST_LED    0x00008000
+#define CFG_POST_BUTTON 0x00010000
+
+extern int cache_post_test(int flags);
+extern int watchdog_post_test(int flags);
+extern int i2c_post_test(int flags);
+extern int rtc_post_test(int flags);
+extern int memory_post_test(int flags);
+extern int cpu_post_test(int flags);
+extern int uart_post_test(int flags);
+extern int ether_post_test(int flags);
+extern int spi_post_test(int flags);
+extern int usb_post_test(int flags);
+extern int spr_post_test(int flags);
+extern int sysmon_post_test(int flags);
+extern int dsp_post_test(int flags);
+extern int codec_post_test(int flags);
+
+extern int sysmon_init_f(void);
+
+extern void sysmon_reloc(void);
+
+extern int flash_post_test(int flags);
+extern int led_post_test(int flags);
+extern int button_post_test(int flags);
+
+struct post_test post_list[] = {
+#if CONFIG_POST & CFG_POST_CACHE
+	{
+	 "Cache test",
+	 "cache",
+	 "This test verifies the CPU cache operation.",
+	 POST_RAM | POST_ALWAYS,
+	 &cache_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_CACHE},
+#endif
+#if CONFIG_POST & CFG_POST_WATCHDOG
+	{
+	 "Watchdog timer test",
+	 "watchdog",
+	 "This test checks the watchdog timer.",
+	 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
+	 &watchdog_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_WATCHDOG},
+#endif
+#if CONFIG_POST & CFG_POST_I2C
+	{
+	 "I2C test",
+	 "i2c",
+	 "This test verifies the I2C operation.",
+	 POST_RAM | POST_ALWAYS,
+	 &i2c_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_I2C},
+#endif
+#if CONFIG_POST & CFG_POST_RTC
+	{
+	 "RTC test",
+	 "rtc",
+	 "This test verifies the RTC operation.",
+	 POST_RAM | POST_SLOWTEST | POST_MANUAL,
+	 &rtc_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_RTC},
+#endif
+#if CONFIG_POST & CFG_POST_MEMORY
+	{
+	 "Memory test",
+	 "memory",
+	 "This test checks RAM.",
+	 POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
+	 &memory_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_MEMORY},
+#endif
+#if CONFIG_POST & CFG_POST_CPU
+	{
+	 "CPU test",
+	 "cpu",
+	 "This test verifies the arithmetic logic unit of" " CPU.",
+	 POST_RAM | POST_ALWAYS,
+	 &cpu_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_CPU},
+#endif
+#if CONFIG_POST & CFG_POST_UART
+	{
+	 "UART test",
+	 "uart",
+	 "This test verifies the UART operation.",
+	 POST_RAM | POST_SLOWTEST | POST_MANUAL,
+	 &uart_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_UART},
+#endif
+#if CONFIG_POST & CFG_POST_ETHER
+	{
+	 "ETHERNET test",
+	 "ethernet",
+	 "This test verifies the ETHERNET operation.",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &ether_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_ETHER},
+#endif
+#if CONFIG_POST & CFG_POST_SPI
+	{
+	 "SPI test",
+	 "spi",
+	 "This test verifies the SPI operation.",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &spi_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_SPI},
+#endif
+#if CONFIG_POST & CFG_POST_USB
+	{
+	 "USB test",
+	 "usb",
+	 "This test verifies the USB operation.",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &usb_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_USB},
+#endif
+#if CONFIG_POST & CFG_POST_SPR
+	{
+	 "SPR test",
+	 "spr",
+	 "This test checks SPR contents.",
+	 POST_ROM | POST_ALWAYS | POST_PREREL,
+	 &spr_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_SPR},
+#endif
+#if CONFIG_POST & CFG_POST_SYSMON
+	{
+	 "SYSMON test",
+	 "sysmon",
+	 "This test monitors system hardware.",
+	 POST_RAM | POST_ALWAYS,
+	 &sysmon_post_test,
+	 &sysmon_init_f,
+	 &sysmon_reloc,
+	 CFG_POST_SYSMON},
+#endif
+#if CONFIG_POST & CFG_POST_DSP
+	{
+	 "DSP test",
+	 "dsp",
+	 "This test checks any connected DSP(s).",
+	 POST_RAM | POST_MANUAL,
+	 &dsp_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_DSP},
+#endif
+#if CONFIG_POST & CFG_POST_CODEC
+	{
+	 "CODEC test",
+	 "codec",
+	 "This test checks any connected codec(s).",
+	 POST_RAM | POST_MANUAL,
+	 &codec_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_CODEC},
+#endif
+#if CONFIG_POST & CFG_POST_FLASH
+	{
+	 "FLASH test",
+	 "flash",
+	 "This test checks flash.",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &flash_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_FLASH},
+#endif
+#if CONFIG_POST & CFG_POST_LED
+	{
+	 "LED test",
+	 "LED",
+	 "This test checks LED ",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &led_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_LED},
+#endif
+#if CONFIG_POST & CFG_POST_BUTTON
+	{
+	 "Button test",
+	 "button",
+	 "This test checks Button ",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &button_post_test,
+	 NULL,
+	 NULL,
+	 CFG_POST_BUTTON},
+#endif
+
+};
+
+unsigned int post_list_size = sizeof(post_list) / sizeof(struct post_test);
+
+#endif				/* CONFIG_POST */
diff --git a/lib_generic/display_options.c b/lib_generic/display_options.c
index 512e898..5ddd94f 100644
--- a/lib_generic/display_options.c
+++ b/lib_generic/display_options.c
@@ -21,7 +21,10 @@
  * MA 02111-1307 USA
  */
 
+#include <config.h>
 #include <common.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
 
 int display_options (void)
 {
@@ -65,3 +68,70 @@ void print_size (ulong size, const char *s)
 	}
 	printf (" %cB%s", c, s);
 }
+
+/*
+ * Print data buffer in hex and ascii form to the terminal.
+ *
+ * data reads are buffered so that each memory address is only read once.
+ * Useful when displaying the contents of volatile registers.
+ *
+ * parameters:
+ *    addr: Starting address to display at start of line
+ *    data: pointer to data buffer
+ *    width: data value width.  May be 1, 2, or 4.
+ *    count: number of values to display
+ *    linelen: Number of values to print per line; specify 0 for default length
+ */
+#define MAX_LINE_LENGTH_BYTES (64)
+#define DEFAULT_LINE_LENGTH_BYTES (16)
+int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen)
+{
+	uint8_t linebuf[MAX_LINE_LENGTH_BYTES];
+	uint32_t *uip = (void*)linebuf;
+	uint16_t *usp = (void*)linebuf;
+	uint8_t *ucp = (void*)linebuf;
+	int i;
+
+	if (linelen*width > MAX_LINE_LENGTH_BYTES)
+		linelen = MAX_LINE_LENGTH_BYTES / width;
+	if (linelen < 1)
+		linelen = DEFAULT_LINE_LENGTH_BYTES / width;
+
+	while (count) {
+		printf("%08lx:", addr);
+
+		/* check for overflow condition */
+		if (count < linelen)
+			linelen = count;
+
+		/* Copy from memory into linebuf and print hex values */
+		for (i = 0; i < linelen; i++) {
+			if (width == 4) {
+				uip[i] = *(volatile uint32_t *)data;
+				printf(" %08x", uip[i]);
+			} else if (width == 2) {
+				usp[i] = *(volatile uint16_t *)data;
+				printf(" %04x", usp[i]);
+			} else {
+				ucp[i] = *(volatile uint8_t *)data;
+				printf(" %02x", ucp[i]);
+			}
+			data += width;
+		}
+
+		/* Print data in ASCII characters */
+		puts("    ");
+		for (i = 0; i < linelen * width; i++)
+			putc(isprint(ucp[i]) && (ucp[i] < 0x80) ? ucp[i] : '.');
+		putc ('\n');
+
+		/* update references */
+		addr += linelen * width;
+		count -= linelen;
+
+		if (ctrlc())
+			return -1;
+	}
+
+	return 0;
+}
diff --git a/lib_m68k/time.c b/lib_m68k/time.c
index d45e470..12e38f0 100644
--- a/lib_m68k/time.c
+++ b/lib_m68k/time.c
@@ -153,7 +153,11 @@ void udelay(unsigned long usec)
 		timerp[MCFTIMER_PMR] = 0;
 		/* set period to 1 us */
 		timerp[MCFTIMER_PCSR] =
+#ifdef CONFIG_M5271
+			(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
+#else /* !CONFIG_M5271 */
 			(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
+#endif /* CONFIG_M5271 */
 
 		timerp[MCFTIMER_PMR] = tmp;
 		while (timerp[MCFTIMER_PCNTR] > 0);
@@ -171,7 +175,11 @@ void timer_init (void)
 	timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
 	timerp[MCFTIMER_PMR] = lastinc = 0;
 	timerp[MCFTIMER_PCSR] =
+#ifdef CONFIG_M5271
+		(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
+#else /* !CONFIG_M5271 */
 		(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
+#endif /* CONFIG_M5271 */
 }
 
 void set_timer (ulong t)
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 844bbc9..24e8e97 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -72,6 +72,14 @@
 #include <keyboard.h>
 #endif
 
+#ifdef CFG_UPDATE_FLASH_SIZE
+extern int update_flash_size (int flash_size);
+#endif
+
+#if defined(CONFIG_SOLIDCARD3)
+extern void sc3_read_eeprom(void);
+#endif
+
 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
 void doc_init (void);
 #endif
@@ -89,6 +97,9 @@ static char *failed = "*** failed ***\n";
 extern flash_info_t flash_info[];
 #endif
 
+#if defined(CONFIG_START_IDE)
+extern int board_start_ide(void);
+#endif
 #include <environment.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -511,7 +522,7 @@ void board_init_f (ulong bootflag)
 	bd->bi_mbar_base = CFG_MBAR;	/* base of internal registers */
 #endif
 #if defined(CONFIG_MPC83XX)
-	bd->bi_immrbar = CFG_IMMRBAR;
+	bd->bi_immrbar = CFG_IMMR;
 #endif
 #if defined(CONFIG_MPC8220)
 	bd->bi_mbar_base = CFG_MBAR;	/* base of internal registers */
@@ -521,17 +532,17 @@ void board_init_f (ulong bootflag)
 	bd->bi_pevfreq   = gd->pev_clk;
 	bd->bi_flbfreq   = gd->flb_clk;
 
-    /* store bootparam to sram (backward compatible), here? */
-    {
-	u32 *sram = (u32 *)CFG_SRAM_BASE;
-	*sram++ = gd->ram_size;
-	*sram++ = gd->bus_clk;
-	*sram++ = gd->inp_clk;
-	*sram++ = gd->cpu_clk;
-	*sram++ = gd->vco_clk;
-	*sram++ = gd->flb_clk;
-	*sram++ = 0xb8c3ba11;  /* boot signature */
-    }
+	/* store bootparam to sram (backward compatible), here? */
+	{
+		u32 *sram = (u32 *)CFG_SRAM_BASE;
+		*sram++ = gd->ram_size;
+		*sram++ = gd->bus_clk;
+		*sram++ = gd->inp_clk;
+		*sram++ = gd->cpu_clk;
+		*sram++ = gd->vco_clk;
+		*sram++ = gd->flb_clk;
+		*sram++ = 0xb8c3ba11;  /* boot signature */
+	}
 #endif
 
 	bd->bi_bootflags = bootflag;	/* boot / reboot flag (for LynxOS)    */
@@ -730,6 +741,13 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	bd->bi_flashstart = CFG_FLASH_BASE;	/* update start of FLASH memory    */
 	bd->bi_flashsize = flash_size;	/* size of FLASH memory (final value) */
+
+#if defined(CFG_UPDATE_FLASH_SIZE)
+	/* Make a update of the Memctrl. */
+	update_flash_size (flash_size);
+#endif
+
+
 # if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
 	/* flash mapped at end of memory map */
 	bd->bi_flashoffset = TEXT_BASE + flash_size;
@@ -804,6 +822,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #endif	/* CONFIG_405GP, CONFIG_405EP */
 #endif	/* CFG_EXTBDINFO */
 
+#if defined(CONFIG_SOLIDCARD3)
+	sc3_read_eeprom();
+#endif
 	s = getenv ("ethaddr");
 #if defined (CONFIG_MBX) || \
     defined (CONFIG_RPXCLASSIC) || \
@@ -876,6 +897,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #endif
 
 #if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
+    defined(CONFIG_TQM8272) || \
     defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
 	load_sernum_ethaddr ();
 #endif
@@ -909,6 +931,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
     defined(CONFIG_KUP4X)	|| \
     defined(CONFIG_LWMON)	|| \
     defined(CONFIG_PCU_E)	|| \
+    defined(CONFIG_SOLIDCARD3)	|| \
     defined(CONFIG_W7O)		|| \
     defined(CONFIG_MISC_INIT_R)
 	/* miscellaneous platform dependent initialisations */
@@ -1018,7 +1041,12 @@ void board_init_r (gd_t *id, ulong dest_addr)
 # else
 	puts ("IDE:   ");
 #endif
+#if defined(CONFIG_START_IDE)
+	if (board_start_ide())
+		ide_init ();
+#else
 	ide_init ();
+#endif
 #endif /* CFG_CMD_IDE */
 
 #ifdef CONFIG_LAST_STAGE_INIT
diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile
index a71f583..510999d 100644
--- a/nand_spl/board/amcc/sequoia/Makefile
+++ b/nand_spl/board/amcc/sequoia/Makefile
@@ -30,7 +30,7 @@ AFLAGS	+= -DCONFIG_NAND_SPL
 CFLAGS	+= -DCONFIG_NAND_SPL
 
 SOBJS	= start.o init.o resetvec.o
-COBJS	= nand_boot.o ndfc.o sdram.o
+COBJS	= nand_boot.o ndfc.o sdram.o speed.o
 
 SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -69,6 +69,10 @@ $(obj)start.S:
 	@rm -f $(obj)start.S
 	ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
 
+$(obj)speed.c:
+	@rm -f $(obj)speed.c
+	ln -s $(SRCTREE)/cpu/ppc4xx/speed.c $(obj)speed.c
+
 # from board directory
 $(obj)init.S:
 	@rm -f $(obj)init.S
@@ -76,7 +80,9 @@ $(obj)init.S:
 
 $(obj)sdram.c:
 	@rm -f $(obj)sdram.c
+	@rm -f $(obj)sdram.h
 	ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c
+	ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h
 
 # from nand_spl directory
 $(obj)nand_boot.c:
diff --git a/net/eth.c b/net/eth.c
index e8ac251..cca9392 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -54,6 +54,7 @@ extern int scc_initialize(bd_t*);
 extern int skge_initialize(bd_t*);
 extern int tsec_initialize(bd_t*, int, char *);
 extern int npe_initialize(bd_t *);
+extern int uec_initialize(int);
 
 static struct eth_device *eth_devices, *eth_current;
 
@@ -142,13 +143,10 @@ int eth_initialize(bd_t *bis)
 	miiphy_init();
 #endif
 
-#ifdef CONFIG_DB64360
+#if defined(CONFIG_DB64360) || defined(CONFIG_CPCI750)
 	mv6436x_eth_initialize(bis);
 #endif
-#ifdef CONFIG_CPCI750
-	mv6436x_eth_initialize(bis);
-#endif
-#ifdef CONFIG_DB64460
+#if defined(CONFIG_DB64460) || defined(CONFIG_P3Mx)
 	mv6446x_eth_initialize(bis);
 #endif
 #if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) && !defined(CONFIG_AP1000)
@@ -196,6 +194,12 @@ int eth_initialize(bd_t *bis)
 	tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
 #    endif
 #endif
+#if defined(CONFIG_UEC_ETH1)
+	uec_initialize(0);
+#endif
+#if defined(CONFIG_UEC_ETH2)
+	uec_initialize(1);
+#endif
 #if defined(CONFIG_MPC86XX_TSEC1)
        tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME);
 #endif
diff --git a/post/Makefile b/post/Makefile
index 228bafc..f32af95 100644
--- a/post/Makefile
+++ b/post/Makefile
@@ -22,14 +22,10 @@
 #
 
 
-SUBDIRS = cpu
+SUBDIRS = drivers cpu lib_$(ARCH) board/$(BOARDDIR)
 
 LIB	= libpost.a
 
-AOBJS	= cache_8xx.o
-COBJS	= cache.o codec.o cpu.o dsp.o ether.o
-COBJS  += i2c.o memory.o post.o rtc.o
-COBJS  += spr.o sysmon.o tests.o uart.o
-COBJS  += usb.o watchdog.o
+COBJS	= post.o tests.o
 
 include $(TOPDIR)/post/rules.mk
diff --git a/post/board/lwmon/Makefile b/post/board/lwmon/Makefile
new file mode 100644
index 0000000..899b0dc
--- /dev/null
+++ b/post/board/lwmon/Makefile
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+LIB	= libpostlwmon.a
+
+COBJS	= sysmon.o
+
+include $(TOPDIR)/post/rules.mk
diff --git a/post/sysmon.c b/post/board/lwmon/sysmon.c
index f61d598..f61d598 100644
--- a/post/sysmon.c
+++ b/post/board/lwmon/sysmon.c
diff --git a/post/board/netta/Makefile b/post/board/netta/Makefile
new file mode 100644
index 0000000..60c7790
--- /dev/null
+++ b/post/board/netta/Makefile
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+LIB	= libpostnetta.a
+
+COBJS	= codec.o dsp.o
+
+include $(TOPDIR)/post/rules.mk
diff --git a/post/codec.c b/post/board/netta/codec.c
index e881752..e881752 100644
--- a/post/codec.c
+++ b/post/board/netta/codec.c
diff --git a/post/dsp.c b/post/board/netta/dsp.c
index 63531a2..63531a2 100644
--- a/post/dsp.c
+++ b/post/board/netta/dsp.c
diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile
new file mode 100644
index 0000000..9dd3f0f
--- /dev/null
+++ b/post/cpu/mpc8xx/Makefile
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+LIB	= libpostmpc8xx.a
+
+AOBJS	= cache_8xx.o
+COBJS	= ether.o spr.o uart.o usb.o watchdog.o
+
+include $(TOPDIR)/post/rules.mk
diff --git a/post/cache_8xx.S b/post/cpu/mpc8xx/cache_8xx.S
index 2d41b55..2d41b55 100644
--- a/post/cache_8xx.S
+++ b/post/cpu/mpc8xx/cache_8xx.S
diff --git a/post/ether.c b/post/cpu/mpc8xx/ether.c
index 8c87b59..8c87b59 100644
--- a/post/ether.c
+++ b/post/cpu/mpc8xx/ether.c
diff --git a/post/spr.c b/post/cpu/mpc8xx/spr.c
index 330b977..330b977 100644
--- a/post/spr.c
+++ b/post/cpu/mpc8xx/spr.c
diff --git a/post/uart.c b/post/cpu/mpc8xx/uart.c
index fd97e38..fd97e38 100644
--- a/post/uart.c
+++ b/post/cpu/mpc8xx/uart.c
diff --git a/post/usb.c b/post/cpu/mpc8xx/usb.c
index 0c74cfa..0c74cfa 100644
--- a/post/usb.c
+++ b/post/cpu/mpc8xx/usb.c
diff --git a/post/watchdog.c b/post/cpu/mpc8xx/watchdog.c
index 48c4282..48c4282 100644
--- a/post/watchdog.c
+++ b/post/cpu/mpc8xx/watchdog.c
diff --git a/post/drivers/Makefile b/post/drivers/Makefile
new file mode 100644
index 0000000..068fa98
--- /dev/null
+++ b/post/drivers/Makefile
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+SUBDIRS =
+
+LIB	= libpostdrivers.a
+
+COBJS	= cache.o i2c.o memory.o rtc.o
+
+include $(TOPDIR)/post/rules.mk
diff --git a/post/cache.c b/post/drivers/cache.c
index 501465c..501465c 100644
--- a/post/cache.c
+++ b/post/drivers/cache.c
diff --git a/post/i2c.c b/post/drivers/i2c.c
index 1b2e644..1b2e644 100644
--- a/post/i2c.c
+++ b/post/drivers/i2c.c
diff --git a/post/memory.c b/post/drivers/memory.c
index a2c088b..a2c088b 100644
--- a/post/memory.c
+++ b/post/drivers/memory.c
diff --git a/post/rtc.c b/post/drivers/rtc.c
index 7d4f9b8..7d4f9b8 100644
--- a/post/rtc.c
+++ b/post/drivers/rtc.c
diff --git a/post/cpu/Makefile b/post/lib_ppc/Makefile
index 645e838..14354a0 100644
--- a/post/cpu/Makefile
+++ b/post/lib_ppc/Makefile
@@ -21,12 +21,11 @@
 # MA 02111-1307 USA
 #
 
-SUBDIRS =
 
-LIB	= libcpu.a
+LIB	= libpostppc.a
 
 AOBJS	= asm.o
-COBJS	= cmp.o cmpi.o two.o twox.o three.o threex.o
+COBJS	= cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o
 COBJS   += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o
 COBJS	+= store.o load.o cr.o b.o multi.o string.o complex.o
 
diff --git a/post/cpu/andi.c b/post/lib_ppc/andi.c
index 7ddf2ab..7ddf2ab 100644
--- a/post/cpu/andi.c
+++ b/post/lib_ppc/andi.c
diff --git a/post/cpu/asm.S b/post/lib_ppc/asm.S
index a0815a4..a0815a4 100644
--- a/post/cpu/asm.S
+++ b/post/lib_ppc/asm.S
diff --git a/post/cpu/b.c b/post/lib_ppc/b.c
index b4b17c8..b4b17c8 100644
--- a/post/cpu/b.c
+++ b/post/lib_ppc/b.c
diff --git a/post/cpu/cmp.c b/post/lib_ppc/cmp.c
index 789a24c..789a24c 100644
--- a/post/cpu/cmp.c
+++ b/post/lib_ppc/cmp.c
diff --git a/post/cpu/cmpi.c b/post/lib_ppc/cmpi.c
index e0c2aaf..e0c2aaf 100644
--- a/post/cpu/cmpi.c
+++ b/post/lib_ppc/cmpi.c
diff --git a/post/cpu/complex.c b/post/lib_ppc/complex.c
index 033584b..033584b 100644
--- a/post/cpu/complex.c
+++ b/post/lib_ppc/complex.c
diff --git a/post/cpu.c b/post/lib_ppc/cpu.c
index 1f2ded2..1f2ded2 100644
--- a/post/cpu.c
+++ b/post/lib_ppc/cpu.c
diff --git a/post/cpu/cpu_asm.h b/post/lib_ppc/cpu_asm.h
index 1cbaf41..1cbaf41 100644
--- a/post/cpu/cpu_asm.h
+++ b/post/lib_ppc/cpu_asm.h
diff --git a/post/cpu/cr.c b/post/lib_ppc/cr.c
index da6ef37..da6ef37 100644
--- a/post/cpu/cr.c
+++ b/post/lib_ppc/cr.c
diff --git a/post/cpu/load.c b/post/lib_ppc/load.c
index 393c568..393c568 100644
--- a/post/cpu/load.c
+++ b/post/lib_ppc/load.c
diff --git a/post/cpu/multi.c b/post/lib_ppc/multi.c
index 8724384..8724384 100644
--- a/post/cpu/multi.c
+++ b/post/lib_ppc/multi.c
diff --git a/post/cpu/rlwimi.c b/post/lib_ppc/rlwimi.c
index f65f79a..f65f79a 100644
--- a/post/cpu/rlwimi.c
+++ b/post/lib_ppc/rlwimi.c
diff --git a/post/cpu/rlwinm.c b/post/lib_ppc/rlwinm.c
index e240c41..e240c41 100644
--- a/post/cpu/rlwinm.c
+++ b/post/lib_ppc/rlwinm.c
diff --git a/post/cpu/rlwnm.c b/post/lib_ppc/rlwnm.c
index 523cf4d..523cf4d 100644
--- a/post/cpu/rlwnm.c
+++ b/post/lib_ppc/rlwnm.c
diff --git a/post/cpu/srawi.c b/post/lib_ppc/srawi.c
index 91c82c9..91c82c9 100644
--- a/post/cpu/srawi.c
+++ b/post/lib_ppc/srawi.c
diff --git a/post/cpu/store.c b/post/lib_ppc/store.c
index f495bf2..f495bf2 100644
--- a/post/cpu/store.c
+++ b/post/lib_ppc/store.c
diff --git a/post/cpu/string.c b/post/lib_ppc/string.c
index bd83bd1..bd83bd1 100644
--- a/post/cpu/string.c
+++ b/post/lib_ppc/string.c
diff --git a/post/cpu/three.c b/post/lib_ppc/three.c
index c2d7476..c2d7476 100644
--- a/post/cpu/three.c
+++ b/post/lib_ppc/three.c
diff --git a/post/cpu/threei.c b/post/lib_ppc/threei.c
index 79f0178..79f0178 100644
--- a/post/cpu/threei.c
+++ b/post/lib_ppc/threei.c
diff --git a/post/cpu/threex.c b/post/lib_ppc/threex.c
index 2c72063..2c72063 100644
--- a/post/cpu/threex.c
+++ b/post/lib_ppc/threex.c
diff --git a/post/cpu/two.c b/post/lib_ppc/two.c
index cfbac5e..cfbac5e 100644
--- a/post/cpu/two.c
+++ b/post/lib_ppc/two.c
diff --git a/post/cpu/twox.c b/post/lib_ppc/twox.c
index 48d9954..48d9954 100644
--- a/post/cpu/twox.c
+++ b/post/lib_ppc/twox.c
diff --git a/post/post.c b/post/post.c
index e1066da..ac41990 100644
--- a/post/post.c
+++ b/post/post.c
@@ -430,6 +430,7 @@ unsigned long post_time_ms (unsigned long base)
 #ifdef CONFIG_PPC
 	return (unsigned long)get_ticks () / (get_tbclk () / CFG_HZ) - base;
 #else
+#warning "Not implemented yet"
 	return 0; /* Not implemented yet */
 #endif
 }
diff --git a/rtc/Makefile b/rtc/Makefile
index cf2b24e..96c68c0 100644
--- a/rtc/Makefile
+++ b/rtc/Makefile
@@ -28,8 +28,8 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)librtc.a
 
 COBJS	= date.o   \
-	  bf533_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
-	  ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o \
+	  bf5xx_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
+	  ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o ds3231.o \
 	  m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
 	  mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o
 
diff --git a/rtc/bf533_rtc.c b/rtc/bf5xx_rtc.c
index 948be64..85bbb56 100644
--- a/rtc/bf533_rtc.c
+++ b/rtc/bf5xx_rtc.c
@@ -49,36 +49,36 @@
 #include <command.h>
 #include <rtc.h>
 
-#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+#if defined(CONFIG_RTC_BFIN) && (CONFIG_COMMANDS & CFG_CMD_DATE)
 
 #include <asm/blackfin.h>
-#include <asm/cpu/bf533_rtc.h>
+#include <asm/arch/bf5xx_rtc.h>
 
-void rtc_reset (void)
+void rtc_reset(void)
 {
 	return;			/* nothing to do */
 }
 
 /* Wait for pending writes to complete */
-void wait_for_complete (void)
+void wait_for_complete(void)
 {
-	while (!(*(volatile unsigned short *) RTC_ISTAT & 0x8000)) {
-		printf ("");
+	while (!(*(volatile unsigned short *)RTC_ISTAT & 0x8000)) {
+		printf("");
 	}
-	*(volatile unsigned short *) RTC_ISTAT = 0x8000;
+	*(volatile unsigned short *)RTC_ISTAT = 0x8000;
 }
 
 /* Enable the RTC prescaler enable register */
-void rtc_init ()
+void rtc_init()
 {
-	*(volatile unsigned short *) RTC_PREN = 0x1;
-	wait_for_complete ();
+	*(volatile unsigned short *)RTC_PREN = 0x1;
+	wait_for_complete();
 }
 
 /* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
  * based on this value.
  */
-void rtc_set (struct rtc_time *tmp)
+void rtc_set(struct rtc_time *tmp)
 {
 	unsigned long n_days_1970 = 0;
 	unsigned long n_secs_rem = 0;
@@ -88,46 +88,46 @@ void rtc_set (struct rtc_time *tmp)
 	unsigned long time_in_secs;
 
 	if (tmp == NULL) {
-		printf ("Error setting the date/time \n");
+		printf("Error setting the date/time \n");
 		return;
 	}
 
 	time_in_secs =
-		mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
-			tmp->tm_min, tmp->tm_sec);
+	    mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
+		   tmp->tm_min, tmp->tm_sec);
 
 	/* Compute no. of days since 1970 */
-	n_days_1970 = (unsigned long) (time_in_secs / (NUM_SECS_IN_DAY));
+	n_days_1970 = (unsigned long)(time_in_secs / (NUM_SECS_IN_DAY));
 
 	/* From the remining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
-	n_secs_rem = (unsigned long) (time_in_secs % (NUM_SECS_IN_DAY));
+	n_secs_rem = (unsigned long)(time_in_secs % (NUM_SECS_IN_DAY));
 	n_hrs = n_secs_rem / (NUM_SECS_IN_HOUR);
 	n_secs_rem = n_secs_rem % (NUM_SECS_IN_HOUR);
 	n_mins = n_secs_rem / (NUM_SECS_IN_MIN);
 	n_secs = n_secs_rem % (NUM_SECS_IN_MIN);
 
 	/* Store the new time in the RTC_STAT register */
-	*(volatile unsigned long *) RTC_STAT =
-		((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) |
-		 (n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF));
+	*(volatile unsigned long *)RTC_STAT =
+	    ((n_days_1970 << DAY_BITS_OFF) | (n_hrs << HOUR_BITS_OFF) |
+	     (n_mins << MIN_BITS_OFF) | (n_secs << SEC_BITS_OFF));
 
-	wait_for_complete ();
+	wait_for_complete();
 }
 
 /* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
-void rtc_get (struct rtc_time *tmp)
+void rtc_get(struct rtc_time *tmp)
 {
 	unsigned long cur_rtc_stat = 0;
 	unsigned long time_in_sec;
 	unsigned long tm_sec = 0, tm_min = 0, tm_hour = 0, tm_day = 0;
 
 	if (tmp == NULL) {
-		printf ("Error getting the date/time \n");
+		printf("Error getting the date/time \n");
 		return;
 	}
 
 	/* Read the RTC_STAT register */
-	cur_rtc_stat = *(volatile unsigned long *) RTC_STAT;
+	cur_rtc_stat = *(volatile unsigned long *)RTC_STAT;
 
 	/* Get the secs (0-59), mins (0-59), hrs (0-23) and the days since Jan 1970 */
 	tm_sec = (cur_rtc_stat >> SEC_BITS_OFF) & 0x3f;
@@ -137,9 +137,7 @@ void rtc_get (struct rtc_time *tmp)
 
 	/* Calculate the total number of seconds since Jan 1970 */
 	time_in_sec = (tm_sec) +
-		MIN_TO_SECS (tm_min) +
-		HRS_TO_SECS (tm_hour) +
-		DAYS_TO_SECS (tm_day);
-	to_tm (time_in_sec, tmp);
+	    MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hour) + DAYS_TO_SECS(tm_day);
+	to_tm(time_in_sec, tmp);
 }
-#endif /* CONFIG_RTC_BF533 && CFG_CMD_DATE */
+#endif				/* CONFIG_RTC_BFIN && CFG_CMD_DATE */
diff --git a/rtc/ds3231.c b/rtc/ds3231.c
new file mode 100644
index 0000000..50aeeb5
--- /dev/null
+++ b/rtc/ds3231.c
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, mk@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
+ * Extremly Accurate DS3231 Real Time Clock (RTC).
+ *
+ * copied from ds1337.c
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+#include <i2c.h>
+
+#if defined(CONFIG_RTC_DS3231) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_RTC
+
+#ifdef DEBUG_RTC
+#define DEBUGR(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGR(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+/*
+ * RTC register addresses
+ */
+#define RTC_SEC_REG_ADDR	0x0
+#define RTC_MIN_REG_ADDR	0x1
+#define RTC_HR_REG_ADDR		0x2
+#define RTC_DAY_REG_ADDR	0x3
+#define RTC_DATE_REG_ADDR	0x4
+#define RTC_MON_REG_ADDR	0x5
+#define RTC_YR_REG_ADDR		0x6
+#define RTC_CTL_REG_ADDR	0x0e
+#define RTC_STAT_REG_ADDR	0x0f
+
+
+/*
+ * RTC control register bits
+ */
+#define RTC_CTL_BIT_A1IE	0x1	/* Alarm 1 interrupt enable     */
+#define RTC_CTL_BIT_A2IE	0x2	/* Alarm 2 interrupt enable     */
+#define RTC_CTL_BIT_INTCN	0x4	/* Interrupt control            */
+#define RTC_CTL_BIT_RS1		0x8	/* Rate select 1                */
+#define RTC_CTL_BIT_RS2		0x10	/* Rate select 2                */
+#define RTC_CTL_BIT_DOSC	0x80	/* Disable Oscillator           */
+
+/*
+ * RTC status register bits
+ */
+#define RTC_STAT_BIT_A1F	0x1	/* Alarm 1 flag                 */
+#define RTC_STAT_BIT_A2F	0x2	/* Alarm 2 flag                 */
+#define RTC_STAT_BIT_OSF	0x80	/* Oscillator stop flag         */
+
+
+static uchar rtc_read (uchar reg);
+static void rtc_write (uchar reg, uchar val);
+static uchar bin2bcd (unsigned int n);
+static unsigned bcd2bin (uchar c);
+
+
+/*
+ * Get the current time from the RTC
+ */
+void rtc_get (struct rtc_time *tmp)
+{
+	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
+
+	control = rtc_read (RTC_CTL_REG_ADDR);
+	status = rtc_read (RTC_STAT_REG_ADDR);
+	sec = rtc_read (RTC_SEC_REG_ADDR);
+	min = rtc_read (RTC_MIN_REG_ADDR);
+	hour = rtc_read (RTC_HR_REG_ADDR);
+	wday = rtc_read (RTC_DAY_REG_ADDR);
+	mday = rtc_read (RTC_DATE_REG_ADDR);
+	mon_cent = rtc_read (RTC_MON_REG_ADDR);
+	year = rtc_read (RTC_YR_REG_ADDR);
+
+	DEBUGR ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
+		"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
+		year, mon_cent, mday, wday, hour, min, sec, control, status);
+
+	if (status & RTC_STAT_BIT_OSF) {
+		printf ("### Warning: RTC oscillator has stopped\n");
+		/* clear the OSF flag */
+		rtc_write (RTC_STAT_REG_ADDR,
+			   rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
+	}
+
+	tmp->tm_sec  = bcd2bin (sec & 0x7F);
+	tmp->tm_min  = bcd2bin (min & 0x7F);
+	tmp->tm_hour = bcd2bin (hour & 0x3F);
+	tmp->tm_mday = bcd2bin (mday & 0x3F);
+	tmp->tm_mon  = bcd2bin (mon_cent & 0x1F);
+	tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
+	tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
+	tmp->tm_yday = 0;
+	tmp->tm_isdst= 0;
+
+	DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+}
+
+
+/*
+ * Set the RTC
+ */
+void rtc_set (struct rtc_time *tmp)
+{
+	uchar century;
+
+	DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+	rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
+
+	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
+	rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
+
+	rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
+	rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
+	rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
+	rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
+	rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
+}
+
+
+/*
+ * Reset the RTC.  We also enable the oscillator output on the
+ * SQW/INTB* pin and program it for 32,768 Hz output. Note that
+ * according to the datasheet, turning on the square wave output
+ * increases the current drain on the backup battery from about
+ * 600 nA to 2uA.
+ */
+void rtc_reset (void)
+{
+	rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2);
+}
+
+
+/*
+ * Helper functions
+ */
+
+static
+uchar rtc_read (uchar reg)
+{
+	return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg));
+}
+
+
+static void rtc_write (uchar reg, uchar val)
+{
+	i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val);
+}
+
+static unsigned bcd2bin (uchar n)
+{
+	return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+static unsigned char bin2bcd (unsigned int n)
+{
+	return (((n / 10) << 4) | (n % 10));
+}
+
+#endif /* (CONFIG_RTC_DS3231) && (CONFIG_COMMANDS & CFG_CMD_DATE) */