diff options
Diffstat (limited to 'arch/arm/cpu')
36 files changed, 873 insertions, 981 deletions
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 5d3b4c2..a067b8a 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -165,13 +165,7 @@ next: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -188,14 +182,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -245,7 +235,15 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop - b clear_bss + bx lr + +#endif + +relocate_done: + + bx lr + +#ifndef CONFIG_SPL_BUILD _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -253,54 +251,13 @@ _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start -#endif -clear_bss: -#ifdef CONFIG_SPL_BUILD - /* No relocation for SPL */ - ldr r0, =__bss_start - ldr r1, =__bss_end__ -#else - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 #endif - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr r0, _nand_boot_ofs - mov pc, r0 + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: -_nand_boot_ofs: - .word nand_boot -#else -jump_2_ram: - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start -#endif + bx lr /* ************************************************************************* diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 667a0e0..40df4b1 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -224,12 +224,7 @@ skip_tcmdisable: */ bl lowlevel_init /* go setup pll,mux,memory */ -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -246,14 +241,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -343,49 +334,9 @@ mmu_enable: skip_hw_init: #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -#ifndef CONFIG_NAND_SPL - bl coloured_LED_init - bl red_led_on -#endif -#endif +relocate_done: -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr pc, _nand_boot - -_nand_boot: .word nand_boot -#else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start -#endif + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -399,6 +350,11 @@ _mmu_table_base: .word mmu_table #endif + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + #ifndef CONFIG_NAND_SPL /* * we assume that cache operation is done before. (eg. cleanup_before_linux()) diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index c2a7763..771d386 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -147,12 +147,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -169,14 +164,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -228,43 +219,10 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - - bl coloured_LED_init - bl red_led_on -#endif +relocate_done: -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start - _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: @@ -272,6 +230,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 14c9156..511d21d 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -182,12 +182,7 @@ copyex: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -204,14 +199,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -263,51 +254,10 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - - bl coloured_LED_init - bl red_led_on -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr r0, _nand_boot_ofs - mov pc, r0 +relocate_done: -_nand_boot_ofs: - .word nand_boot -#else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start -#endif - _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: @@ -315,6 +265,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 3a483f6..e8d6d71 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -34,10 +34,6 @@ #include <config.h> #include <version.h> -#if defined(CONFIG_OMAP1510) -#include <./configs/omap1510.h> -#endif - /* ************************************************************************* * @@ -176,12 +172,7 @@ poll1: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -198,14 +189,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -257,51 +244,10 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - - bl coloured_LED_init - bl red_led_on -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr r0, _nand_boot_ofs - mov pc, r0 +relocate_done: -_nand_boot_ofs: - .word nand_boot -#else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start -#endif - _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: @@ -309,6 +255,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c b/arch/arm/cpu/arm926ejs/davinci/reset.c index 968fb03..80f1ce9 100644 --- a/arch/arm/cpu/arm926ejs/davinci/reset.c +++ b/arch/arm/cpu/arm926ejs/davinci/reset.c @@ -16,7 +16,7 @@ void reset_cpu(unsigned long a) { struct davinci_timer *const wdttimer = - (struct davinci_timer *)DAVINCI_TIMER1_BASE; + (struct davinci_timer *)DAVINCI_WDOG_BASE; writel(0x08, &wdttimer->tgcr); writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr); writel(0, &wdttimer->tim12); diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c index 03eb2de..0ba6f09 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c @@ -31,7 +31,7 @@ static u32 kirkwood_variant(void) #define MPP_CTRL(i) (KW_MPP_BASE + (i* 4)) #define MPP_NR_REGS (1 + MPP_MAX/8) -void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save) +void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save) { u32 mpp_ctrl[MPP_NR_REGS]; unsigned int variant_mask; diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index bfea6ab..4ff19c3 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -333,6 +333,8 @@ uint32_t mxc_get_clock(enum mxc_clock clk) return mx28_get_sspclk(MXC_SSPCLK2); case MXC_SSP3_CLK: return mx28_get_sspclk(MXC_SSPCLK3); + case MXC_XTAL_CLK: + return XTAL_FREQ_KHZ * 1000; } return 0; diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 8ea7c36..1b8502e 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -50,7 +50,7 @@ void early_delay(int delay) } #define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) -const iomux_cfg_t iomux_boot[] = { +static const iomux_cfg_t iomux_boot[] = { MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD, MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD, MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD, @@ -59,7 +59,7 @@ const iomux_cfg_t iomux_boot[] = { MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD, }; -uint8_t mxs_get_bootmode_index(void) +static uint8_t mxs_get_bootmode_index(void) { uint8_t bootmode = 0; int i; diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index e693145..401c513 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -30,7 +30,11 @@ #include "mxs_init.h" -static uint32_t mx28_dram_vals[] = { +static uint32_t dram_vals[] = { +/* + * i.MX28 DDR2 at 200MHz + */ +#if defined(CONFIG_MX28) 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -79,6 +83,9 @@ static uint32_t mx28_dram_vals[] = { 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001 +#else +#error Unsupported memory initialization +#endif }; void __mxs_adjust_memory_params(uint32_t *dram_vals) @@ -87,17 +94,17 @@ void __mxs_adjust_memory_params(uint32_t *dram_vals) void mxs_adjust_memory_params(uint32_t *dram_vals) __attribute__((weak, alias("__mxs_adjust_memory_params"))); -void init_mx28_200mhz_ddr2(void) +static void initialize_dram_values(void) { int i; - mxs_adjust_memory_params(mx28_dram_vals); + mxs_adjust_memory_params(dram_vals); - for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++) - writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i)); + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) + writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); } -void mxs_mem_init_clock(void) +static void mxs_mem_init_clock(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; @@ -128,7 +135,7 @@ void mxs_mem_init_clock(void) early_delay(10000); } -void mxs_mem_setup_cpu_and_hbus(void) +static void mxs_mem_setup_cpu_and_hbus(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; @@ -160,7 +167,7 @@ void mxs_mem_setup_cpu_and_hbus(void) early_delay(15000); } -void mxs_mem_setup_vdda(void) +static void mxs_mem_setup_vdda(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -171,17 +178,6 @@ void mxs_mem_setup_vdda(void) &power_regs->hw_power_vddactrl); } -void mxs_mem_setup_vddd(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - - writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) | - (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) | - POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW, - &power_regs->hw_power_vdddctrl); -} - uint32_t mxs_mem_get_size(void) { uint32_t sz, da; @@ -229,7 +225,7 @@ void mxs_mem_init(void) /* Clear START bit from DRAM_CTL16 */ clrbits_le32(MXS_DRAM_BASE + 0x40, 1); - init_mx28_200mhz_ddr2(); + initialize_dram_values(); /* Clear SREFRESH bit from DRAM_CTL17 */ clrbits_le32(MXS_DRAM_BASE + 0x44, 1); @@ -241,8 +237,6 @@ void mxs_mem_init(void) while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) ; - mxs_mem_setup_vddd(); - early_delay(10000); mxs_mem_setup_cpu_and_hbus(); diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 4b917bd..be44c22 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -30,7 +30,7 @@ #include "mxs_init.h" -void mxs_power_clock2xtal(void) +static void mxs_power_clock2xtal(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; @@ -40,7 +40,7 @@ void mxs_power_clock2xtal(void) &clkctrl_regs->hw_clkctrl_clkseq_set); } -void mxs_power_clock2pll(void) +static void mxs_power_clock2pll(void) { struct mxs_clkctrl_regs *clkctrl_regs = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; @@ -52,7 +52,7 @@ void mxs_power_clock2pll(void) CLKCTRL_CLKSEQ_BYPASS_CPU); } -void mxs_power_clear_auto_restart(void) +static void mxs_power_clear_auto_restart(void) { struct mxs_rtc_regs *rtc_regs = (struct mxs_rtc_regs *)MXS_RTC_BASE; @@ -85,7 +85,7 @@ void mxs_power_clear_auto_restart(void) ; } -void mxs_power_set_linreg(void) +static void mxs_power_set_linreg(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -104,7 +104,7 @@ void mxs_power_set_linreg(void) POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); } -int mxs_get_batt_volt(void) +static int mxs_get_batt_volt(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -115,12 +115,12 @@ int mxs_get_batt_volt(void) return volt; } -int mxs_is_batt_ready(void) +static int mxs_is_batt_ready(void) { return (mxs_get_batt_volt() >= 3600); } -int mxs_is_batt_good(void) +static int mxs_is_batt_good(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -160,7 +160,7 @@ int mxs_is_batt_good(void) return 0; } -void mxs_power_setup_5v_detect(void) +static void mxs_power_setup_5v_detect(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -172,7 +172,7 @@ void mxs_power_setup_5v_detect(void) POWER_5VCTRL_PWRUP_VBUS_CMPS); } -void mxs_src_power_init(void) +static void mxs_src_power_init(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -203,7 +203,7 @@ void mxs_src_power_init(void) clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); } -void mxs_power_init_4p2_params(void) +static void mxs_power_init_4p2_params(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -227,7 +227,7 @@ void mxs_power_init_4p2_params(void) 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } -void mxs_enable_4p2_dcdc_input(int xfer) +static void mxs_enable_4p2_dcdc_input(int xfer) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -323,7 +323,7 @@ void mxs_enable_4p2_dcdc_input(int xfer) POWER_CTRL_ENIRQ_VDD5V_DROOP); } -void mxs_power_init_4p2_regulator(void) +static void mxs_power_init_4p2_regulator(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -407,7 +407,7 @@ void mxs_power_init_4p2_regulator(void) writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); } -void mxs_power_init_dcdc_4p2_source(void) +static void mxs_power_init_dcdc_4p2_source(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -429,7 +429,7 @@ void mxs_power_init_dcdc_4p2_source(void) } } -void mxs_power_enable_4p2(void) +static void mxs_power_enable_4p2(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -488,7 +488,7 @@ void mxs_power_enable_4p2(void) &power_regs->hw_power_charge_clr); } -void mxs_boot_valid_5v(void) +static void mxs_boot_valid_5v(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -511,7 +511,7 @@ void mxs_boot_valid_5v(void) mxs_power_enable_4p2(); } -void mxs_powerdown(void) +static void mxs_powerdown(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -520,7 +520,7 @@ void mxs_powerdown(void) &power_regs->hw_power_reset); } -void mxs_batt_boot(void) +static void mxs_batt_boot(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -564,7 +564,7 @@ void mxs_batt_boot(void) 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } -void mxs_handle_5v_conflict(void) +static void mxs_handle_5v_conflict(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -600,7 +600,7 @@ void mxs_handle_5v_conflict(void) } } -void mxs_5v_boot(void) +static void mxs_5v_boot(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -623,7 +623,7 @@ void mxs_5v_boot(void) mxs_handle_5v_conflict(); } -void mxs_init_batt_bo(void) +static void mxs_init_batt_bo(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -637,7 +637,7 @@ void mxs_init_batt_bo(void) writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); } -void mxs_switch_vddd_to_dcdc_source(void) +static void mxs_switch_vddd_to_dcdc_source(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -651,7 +651,7 @@ void mxs_switch_vddd_to_dcdc_source(void) POWER_VDDDCTRL_DISABLE_STEPPING); } -void mxs_power_configure_power_source(void) +static void mxs_power_configure_power_source(void) { int batt_ready, batt_good; struct mxs_power_regs *power_regs = @@ -689,7 +689,7 @@ void mxs_power_configure_power_source(void) mxs_switch_vddd_to_dcdc_source(); } -void mxs_enable_output_rail_protection(void) +static void mxs_enable_output_rail_protection(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -707,7 +707,7 @@ void mxs_enable_output_rail_protection(void) POWER_VDDIOCTRL_PWDN_BRNOUT); } -int mxs_get_vddio_power_source_off(void) +static int mxs_get_vddio_power_source_off(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -735,7 +735,7 @@ int mxs_get_vddio_power_source_off(void) } -int mxs_get_vddd_power_source_off(void) +static int mxs_get_vddd_power_source_off(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; @@ -766,201 +766,115 @@ int mxs_get_vddd_power_source_off(void) return 0; } -void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout) +struct mxs_vddx_cfg { + uint32_t *reg; + uint8_t step_mV; + uint16_t lowest_mV; + int (*powered_by_linreg)(void); + uint32_t trg_mask; + uint32_t bo_irq; + uint32_t bo_enirq; + uint32_t bo_offset_mask; + uint32_t bo_offset_offset; +}; + +static const struct mxs_vddx_cfg mxs_vddio_cfg = { + .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> + hw_power_vddioctrl), + .step_mV = 50, + .lowest_mV = 2800, + .powered_by_linreg = mxs_get_vddio_power_source_off, + .trg_mask = POWER_VDDIOCTRL_TRG_MASK, + .bo_irq = POWER_CTRL_VDDIO_BO_IRQ, + .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO, + .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK, + .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET, +}; + +static const struct mxs_vddx_cfg mxs_vddd_cfg = { + .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> + hw_power_vdddctrl), + .step_mV = 25, + .lowest_mV = 800, + .powered_by_linreg = mxs_get_vddd_power_source_off, + .trg_mask = POWER_VDDDCTRL_TRG_MASK, + .bo_irq = POWER_CTRL_VDDD_BO_IRQ, + .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO, + .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK, + .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET, +}; + +static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, + uint32_t new_target, uint32_t new_brownout) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t cur_target, diff, bo_int = 0; uint32_t powered_by_linreg = 0; + int adjust_up, tmp; - new_brownout = (new_target - new_brownout + 25) / 50; + new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV); - cur_target = readl(&power_regs->hw_power_vddioctrl); - cur_target &= POWER_VDDIOCTRL_TRG_MASK; - cur_target *= 50; /* 50 mV step*/ - cur_target += 2800; /* 2800 mV lowest */ + cur_target = readl(cfg->reg); + cur_target &= cfg->trg_mask; + cur_target *= cfg->step_mV; + cur_target += cfg->lowest_mV; - powered_by_linreg = mxs_get_vddio_power_source_off(); - if (new_target > cur_target) { + adjust_up = new_target > cur_target; + powered_by_linreg = cfg->powered_by_linreg(); + if (adjust_up) { if (powered_by_linreg) { - bo_int = readl(&power_regs->hw_power_vddioctrl); - clrbits_le32(&power_regs->hw_power_vddioctrl, - POWER_CTRL_ENIRQ_VDDIO_BO); + bo_int = readl(cfg->reg); + clrbits_le32(cfg->reg, cfg->bo_enirq); } + setbits_le32(cfg->reg, cfg->bo_offset_mask); + } - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_BO_OFFSET_MASK); - do { - if (new_target - cur_target > 100) + do { + if (abs(new_target - cur_target) > 100) { + if (adjust_up) diff = cur_target + 100; else - diff = new_target; - - diff -= 2800; - diff /= 50; - - clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_TRG_MASK, diff); - - if (powered_by_linreg || - (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) - early_delay(500); - else { - while (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DC_OK)) - ; - - } - - cur_target = readl(&power_regs->hw_power_vddioctrl); - cur_target &= POWER_VDDIOCTRL_TRG_MASK; - cur_target *= 50; /* 50 mV step*/ - cur_target += 2800; /* 2800 mV lowest */ - } while (new_target > cur_target); - - if (powered_by_linreg) { - writel(POWER_CTRL_VDDIO_BO_IRQ, - &power_regs->hw_power_ctrl_clr); - if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO) - setbits_le32(&power_regs->hw_power_vddioctrl, - POWER_CTRL_ENIRQ_VDDIO_BO); - } - } else { - do { - if (cur_target - new_target > 100) diff = cur_target - 100; - else - diff = new_target; - - diff -= 2800; - diff /= 50; - - clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_TRG_MASK, diff); - - if (powered_by_linreg || - (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) - early_delay(500); - else { - while (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DC_OK)) - ; - - } - - cur_target = readl(&power_regs->hw_power_vddioctrl); - cur_target &= POWER_VDDIOCTRL_TRG_MASK; - cur_target *= 50; /* 50 mV step*/ - cur_target += 2800; /* 2800 mV lowest */ - } while (new_target < cur_target); - } - - clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDIOCTRL_BO_OFFSET_MASK, - new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET); -} - -void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - uint32_t cur_target, diff, bo_int = 0; - uint32_t powered_by_linreg = 0; - - new_brownout = (new_target - new_brownout + 12) / 25; - - cur_target = readl(&power_regs->hw_power_vdddctrl); - cur_target &= POWER_VDDDCTRL_TRG_MASK; - cur_target *= 25; /* 25 mV step*/ - cur_target += 800; /* 800 mV lowest */ - - powered_by_linreg = mxs_get_vddd_power_source_off(); - if (new_target > cur_target) { - if (powered_by_linreg) { - bo_int = readl(&power_regs->hw_power_vdddctrl); - clrbits_le32(&power_regs->hw_power_vdddctrl, - POWER_CTRL_ENIRQ_VDDD_BO); + } else { + diff = new_target; } - setbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_BO_OFFSET_MASK); - - do { - if (new_target - cur_target > 100) - diff = cur_target + 100; - else - diff = new_target; - - diff -= 800; - diff /= 25; - - clrsetbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_TRG_MASK, diff); + diff -= cfg->lowest_mV; + diff /= cfg->step_mV; - if (powered_by_linreg || - (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) - early_delay(500); - else { - while (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DC_OK)) - ; + clrsetbits_le32(cfg->reg, cfg->trg_mask, diff); + if (powered_by_linreg || + (readl(&power_regs->hw_power_sts) & + POWER_STS_VDD5V_GT_VDDIO)) + early_delay(500); + else { + for (;;) { + tmp = readl(&power_regs->hw_power_sts); + if (tmp & POWER_STS_DC_OK) + break; } - - cur_target = readl(&power_regs->hw_power_vdddctrl); - cur_target &= POWER_VDDDCTRL_TRG_MASK; - cur_target *= 25; /* 25 mV step*/ - cur_target += 800; /* 800 mV lowest */ - } while (new_target > cur_target); - - if (powered_by_linreg) { - writel(POWER_CTRL_VDDD_BO_IRQ, - &power_regs->hw_power_ctrl_clr); - if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO) - setbits_le32(&power_regs->hw_power_vdddctrl, - POWER_CTRL_ENIRQ_VDDD_BO); } - } else { - do { - if (cur_target - new_target > 100) - diff = cur_target - 100; - else - diff = new_target; - diff -= 800; - diff /= 25; + cur_target = readl(cfg->reg); + cur_target &= cfg->trg_mask; + cur_target *= cfg->step_mV; + cur_target += cfg->lowest_mV; + } while (new_target > cur_target); - clrsetbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_TRG_MASK, diff); - - if (powered_by_linreg || - (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) - early_delay(500); - else { - while (!(readl(&power_regs->hw_power_sts) & - POWER_STS_DC_OK)) - ; - - } - - cur_target = readl(&power_regs->hw_power_vdddctrl); - cur_target &= POWER_VDDDCTRL_TRG_MASK; - cur_target *= 25; /* 25 mV step*/ - cur_target += 800; /* 800 mV lowest */ - } while (new_target < cur_target); + if (adjust_up && powered_by_linreg) { + writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr); + if (bo_int & cfg->bo_enirq) + setbits_le32(cfg->reg, cfg->bo_enirq); } - clrsetbits_le32(&power_regs->hw_power_vdddctrl, - POWER_VDDDCTRL_BO_OFFSET_MASK, - new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); + clrsetbits_le32(cfg->reg, cfg->bo_offset_mask, + new_brownout << cfg->bo_offset_offset); } -void mxs_setup_batt_detect(void) +static void mxs_setup_batt_detect(void) { mxs_lradc_init(); mxs_lradc_enable_batt_measurement(); @@ -982,9 +896,8 @@ void mxs_power_init(void) mxs_power_configure_power_source(); mxs_enable_output_rail_protection(); - mxs_power_set_vddio(3300, 3150); - - mxs_power_set_vddd(1350, 1200); + mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150); + mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000); writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 2188f7e..66a8b65 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -36,12 +36,6 @@ #include <common.h> #include <version.h> -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#elif defined(CONFIG_OMAP730) -#include <./configs/omap730.h> -#endif - /* ************************************************************************* * @@ -198,20 +192,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: -#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) -#else -#ifdef CONFIG_SPL_BUILD - ldr sp, =(CONFIG_SPL_STACK) -#else - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) -#endif -#endif - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -229,15 +210,11 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start sub r9, r6, r0 /* r9 <- relocation offset */ cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + moveq r9, #0 /* no relocation. offset(r9) = 0 */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -289,56 +266,9 @@ fixnext: blo fixloop #endif -clear_bss: -#ifdef CONFIG_SPL_BUILD - /* No relocation for SPL */ - ldr r0, =__bss_start - ldr r1, =__bss_end__ -#else - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 -#endif - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - -#ifndef CONFIG_SPL_BUILD - bl coloured_LED_init - bl red_led_on -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr r0, _nand_boot_ofs - mov pc, r0 +relocate_done: -_nand_boot_ofs: - .word nand_boot -#else - ldr r0, _board_init_r_ofs - ldr r1, _TEXT_BASE - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start -#endif + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -346,8 +276,14 @@ _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start + #endif + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + bx lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 30e2183..a7a98a4 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -147,12 +147,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -169,14 +164,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -228,46 +219,10 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -#endif - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr pc, _nand_boot +relocate_done: -_nand_boot: .word nand_boot -#else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start -#endif - _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: @@ -275,6 +230,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index a133d19..c189849 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -143,12 +143,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -165,14 +160,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -224,50 +215,9 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - - bl coloured_LED_init - bl red_led_on -#endif +relocate_done: -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_NAND_SPL - ldr r0, _nand_boot_ofs - mov pc, r0 - -_nand_boot_ofs: - .word nand_boot -#else - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start -#endif + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -276,6 +226,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 74875b3..70c443e 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -18,10 +18,12 @@ LIB = $(obj)lib$(SOC).o COBJS += clock.o COBJS += sys_info.o +COBJS += mem.o COBJS += ddr.o COBJS += emif4.o COBJS += board.o COBJS += mux.o +COBJS-$(CONFIG_NAND_OMAP_GPMC) += elm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index e4c123c..ab31326 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -25,6 +25,7 @@ #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> +#include <asm/arch/mem.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> @@ -33,6 +34,11 @@ #include <i2c.h> #include <miiphy.h> #include <cpsw.h> +#include <asm/errno.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/musb.h> +#include <asm/omap_musb.h> DECLARE_GLOBAL_DATA_PTR; @@ -63,3 +69,83 @@ void setup_clocks_for_console(void) /* Not yet implemented */ return; } + +/* AM33XX has two MUSB controllers which can be host or gadget */ +#if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \ + (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* USB 2.0 PHY Control */ +#define CM_PHY_PWRDN (1 << 0) +#define CM_PHY_OTG_PWRDN (1 << 1) +#define OTGVDET_EN (1 << 19) +#define OTGSESSENDEN (1 << 20) + +static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) +{ + if (on) { + clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, + OTGVDET_EN | OTGSESSENDEN); + } else { + clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); + } +} + +static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, +}; + +#ifdef CONFIG_AM335X_USB0 +static void am33xx_otg0_set_phy_power(u8 on) +{ + am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); +} + +struct omap_musb_board_data otg0_board_data = { + .set_phy_power = am33xx_otg0_set_phy_power, +}; + +static struct musb_hdrc_platform_data otg0_plat = { + .mode = CONFIG_AM335X_USB0_MODE, + .config = &musb_config, + .power = 50, + .platform_ops = &musb_dsps_ops, + .board_data = &otg0_board_data, +}; +#endif + +#ifdef CONFIG_AM335X_USB1 +static void am33xx_otg1_set_phy_power(u8 on) +{ + am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); +} + +struct omap_musb_board_data otg1_board_data = { + .set_phy_power = am33xx_otg1_set_phy_power, +}; + +static struct musb_hdrc_platform_data otg1_plat = { + .mode = CONFIG_AM335X_USB1_MODE, + .config = &musb_config, + .power = 50, + .platform_ops = &musb_dsps_ops, + .board_data = &otg1_board_data, +}; +#endif +#endif + +int arch_misc_init(void) +{ +#ifdef CONFIG_AM335X_USB0 + musb_register(&otg0_plat, &otg0_board_data, + (void *)AM335X_USB0_OTG_BASE); +#endif +#ifdef CONFIG_AM335X_USB1 + musb_register(&otg1_plat, &otg1_board_data, + (void *)AM335X_USB1_OTG_BASE); +#endif + return 0; +} diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index bc2abb6..d7d98d1 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -40,6 +40,7 @@ #define CLK_MODE_MASK 0xfffffff8 #define CLK_DIV_SEL 0xFFFFFFE0 #define CPGMAC0_IDLE 0x30000 +#define DPLL_CLKDCOLDO_GATE_CTRL 0x300 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; @@ -150,6 +151,16 @@ static void enable_per_clocks(void) ; #endif /* CONFIG_SERIAL6 */ + /* GPMC */ + writel(PRCM_MOD_EN, &cmper->gpmcclkctrl); + while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN) + ; + + /* ELM */ + writel(PRCM_MOD_EN, &cmper->elmclkctrl); + while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN) + ; + /* MMC0*/ writel(PRCM_MOD_EN, &cmper->mmc0clkctrl); while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN) @@ -194,6 +205,11 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl); while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN) ; + + /* MUSB */ + writel(PRCM_MOD_EN, &cmper->usb0clkctrl); + while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN) + ; } static void mpu_pll_config(void) @@ -290,6 +306,8 @@ static void per_pll_config(void) while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK) ; + + writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper); } void ddr_pll_config(unsigned int ddrpll_m) diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c new file mode 100644 index 0000000..9eed23d --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/elm.c @@ -0,0 +1,212 @@ +/* + * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com> + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * BCH Error Location Module (ELM) support. + * + * NOTE: + * 1. Supports only continuous mode. Dont see need for page mode in uboot + * 2. Supports only syndrome polynomial 0. i.e. poly local variable is + * always set to ELM_DEFAULT_POLY. Dont see need for other polynomial + * sets in uboot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/cpu.h> +#include <asm/arch/omap_gpmc.h> +#include <asm/arch/elm.h> + +#define ELM_DEFAULT_POLY (0) + +struct elm *elm_cfg; + +/** + * elm_load_syndromes - Load BCH syndromes based on nibble selection + * @syndrome: BCH syndrome + * @nibbles: + * @poly: Syndrome Polynomial set to use + * + * Load BCH syndromes based on nibble selection + */ +static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) +{ + u32 *ptr; + u32 val; + + /* reg 0 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0]; + val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) | + (syndrome[3] << 24); + writel(val, ptr); + /* reg 1 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1]; + val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) | + (syndrome[7] << 24); + writel(val, ptr); + + /* BCH 8-bit with 26 nibbles (4*8=32) */ + if (nibbles > 13) { + /* reg 2 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2]; + val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) | + (syndrome[11] << 24); + writel(val, ptr); + /* reg 3 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3]; + val = syndrome[12] | (syndrome[13] << 8) | + (syndrome[14] << 16) | (syndrome[15] << 24); + writel(val, ptr); + } + + /* BCH 16-bit with 52 nibbles (7*8=56) */ + if (nibbles > 26) { + /* reg 4 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4]; + val = syndrome[16] | (syndrome[17] << 8) | + (syndrome[18] << 16) | (syndrome[19] << 24); + writel(val, ptr); + + /* reg 5 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5]; + val = syndrome[20] | (syndrome[21] << 8) | + (syndrome[22] << 16) | (syndrome[23] << 24); + writel(val, ptr); + + /* reg 6 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]; + val = syndrome[24] | (syndrome[25] << 8) | + (syndrome[26] << 16) | (syndrome[27] << 24); + writel(val, ptr); + } +} + +/** + * elm_check_errors - Check for BCH errors and return error locations + * @syndrome: BCH syndrome + * @nibbles: + * @error_count: Returns number of errrors in the syndrome + * @error_locations: Returns error locations (in decimal) in this array + * + * Check the provided syndrome for BCH errors and return error count + * and locations in the array passed. Returns -1 if error is not correctable, + * else returns 0 + */ +int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, + u32 *error_locations) +{ + u8 poly = ELM_DEFAULT_POLY; + s8 i; + u32 location_status; + + elm_load_syndromes(syndrome, nibbles, poly); + + /* start processing */ + writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]) + | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID), + &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]); + + /* wait for processing to complete */ + while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1) + ; + /* clear status */ + writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)), + &elm_cfg->irqstatus); + + /* check if correctable */ + location_status = readl(&elm_cfg->error_location[poly].location_status); + if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) + return -1; + + /* get error count */ + *error_count = readl(&elm_cfg->error_location[poly].location_status) & + ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK; + + for (i = 0; i < *error_count; i++) { + error_locations[i] = + readl(&elm_cfg->error_location[poly].error_location_x[i]); + } + + return 0; +} + + +/** + * elm_config - Configure ELM module + * @level: 4 / 8 / 16 bit BCH + * + * Configure ELM module based on BCH level. + * Set mode as continuous mode. + * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used. + * Also, the mode is set only for syndrome 0 + */ +int elm_config(enum bch_level level) +{ + u32 val; + u8 poly = ELM_DEFAULT_POLY; + u32 buffer_size = 0x7FF; + + /* config size and level */ + val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK; + val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) & + ELM_LOCATION_CONFIG_ECC_SIZE_MASK); + writel(val, &elm_cfg->location_config); + + /* config continous mode */ + /* enable interrupt generation for syndrome polynomial set */ + writel((readl(&elm_cfg->irqenable) | (0x1 << poly)), + &elm_cfg->irqenable); + /* set continuous mode for the syndrome polynomial set */ + writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)), + &elm_cfg->page_ctrl); + + return 0; +} + +/** + * elm_reset - Do a soft reset of ELM + * + * Perform a soft reset of ELM and return after reset is done. + */ +void elm_reset(void) +{ + /* initiate reset */ + writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET), + &elm_cfg->sysconfig); + + /* wait for reset complete and normal operation */ + while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) != + ELM_SYSSTATUS_RESETDONE) + ; +} + +/** + * elm_init - Initialize ELM module + * + * Initialize ELM support. Currently it does only base address init + * and ELM reset. + */ +void elm_init(void) +{ + elm_cfg = (struct elm *)ELM_BASE; + elm_reset(); +} diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c new file mode 100644 index 0000000..b8f54ab --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Author : + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Manikandan Pillai <mani.pillai@ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <command.h> + +struct gpmc *gpmc_cfg; + +#if defined(CONFIG_CMD_NAND) +static const u32 gpmc_m_nand[GPMC_MAX_REG] = { + M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, 0 +}; +#endif + + +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size) +{ + writel(0, &cs->config7); + sdelay(1000); + /* Delay for settling */ + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); + /* Enable the config */ + writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), &cs->config7); + sdelay(2000); +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ + /* putting a blanket check on GPMC based on ZeBu for now */ + gpmc_cfg = (struct gpmc *)GPMC_BASE; + +#ifdef CONFIG_CMD_NAND + const u32 *gpmc_config = NULL; + u32 base = 0; + u32 size = 0; +#endif + /* global settings */ + writel(0x00000008, &gpmc_cfg->sysconfig); + writel(0x00000100, &gpmc_cfg->irqstatus); + writel(0x00000200, &gpmc_cfg->irqenable); + writel(0x00000012, &gpmc_cfg->config); + /* + * Disable the GPMC0 config set by ROM code + */ + writel(0, &gpmc_cfg->cs[0].config7); + sdelay(1000); + +#ifdef CONFIG_CMD_NAND + gpmc_config = gpmc_m_nand; + + base = PISMO1_NAND_BASE; + size = PISMO1_NAND_SIZE; + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); +#endif +} diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index fe61f88..7459979 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -921,6 +921,21 @@ static int exynos5_set_spi_clk(enum periph_id periph_id, return 0; } +static unsigned long exynos4_get_i2c_clk(void) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long sclk, aclk_100; + unsigned int ratio; + + sclk = get_pll_clk(APLL); + + ratio = (readl(&clk->div_top)) >> 4; + ratio &= 0xf; + aclk_100 = sclk / (ratio + 1); + return aclk_100; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -941,6 +956,8 @@ unsigned long get_i2c_clk(void) { if (cpu_is_exynos5()) { return exynos5_get_i2c_clk(); + } else if (cpu_is_exynos4()) { + return exynos4_get_i2c_clk(); } else { debug("I2C clock is not set for this CPU\n"); return 0; diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index f02f441..20a4b84 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -329,54 +329,60 @@ static int exynos5_pinmux_config(int peripheral, int flags) return 0; } -static int exynos4_mmc_config(int peripheral, int flags) +static void exynos4_i2c_config(int peripheral, int flags) { - struct exynos4_gpio_part2 *gpio2 = - (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - struct s5p_gpio_bank *bank, *bank_ext; - int i; + struct exynos4_gpio_part1 *gpio1 = + (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1(); switch (peripheral) { - case PERIPH_ID_SDMMC0: - bank = &gpio2->k0; - bank_ext = &gpio2->k1; + case PERIPH_ID_I2C0: + s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2)); break; - case PERIPH_ID_SDMMC2: - bank = &gpio2->k2; - bank_ext = &gpio2->k3; + case PERIPH_ID_I2C1: + s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2)); + break; + case PERIPH_ID_I2C2: + s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C3: + s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C4: + s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C5: + s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3)); + break; + case PERIPH_ID_I2C6: + s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4)); + break; + case PERIPH_ID_I2C7: + s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3)); break; - default: - return -1; - } - for (i = 0; i < 7; i++) { - if (i == 2) - continue; - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); - } - if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = 3; i < 7; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); - s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); - } } - - return 0; } static int exynos4_pinmux_config(int peripheral, int flags) { switch (peripheral) { - case PERIPH_ID_SDMMC0: - case PERIPH_ID_SDMMC2: - return exynos4_mmc_config(peripheral, flags); - case PERIPH_ID_SDMMC1: - case PERIPH_ID_SDMMC3: - case PERIPH_ID_SDMMC4: - printf("SDMMC device %d not implemented\n", peripheral); - return -1; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + exynos4_i2c_config(peripheral, flags); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 1f2fa02..0efc80d 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -25,9 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)libomap-common.o -SOBJS := reset.o - -COBJS := timer.o +COBJS := reset.o +COBJS += timer.o COBJS += utils.o ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 0f19141..2b584e0 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -21,6 +21,7 @@ #include <asm/omap_common.h> #include <asm/arch/omap.h> #include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> /* * This is used to verify if the configuration header diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 30dcf1b..88253cf 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -33,6 +33,8 @@ #include <asm/utils.h> #include <linux/compiler.h> +static int emif1_enabled = -1, emif2_enabled = -1; + void set_lpmode_selfrefresh(u32 base) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -1109,6 +1111,7 @@ void emif_post_init_config(u32 base) void dmm_init(u32 base) { const struct dmm_lisa_map_regs *lisa_map_regs; + u32 i, section, valid; #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS emif_get_dmm_regs(&lisa_map_regs); @@ -1216,6 +1219,29 @@ void dmm_init(u32 base) writel(lisa_map_regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); } + + /* + * EMIF should be configured only when + * memory is mapped on it. Using emif1_enabled + * and emif2_enabled variables for this. + */ + emif1_enabled = 0; + emif2_enabled = 0; + for (i = 0; i < 4; i++) { + section = __raw_readl(DMM_BASE + i*4); + valid = (section & EMIF_SDRC_MAP_MASK) >> + (EMIF_SDRC_MAP_SHIFT); + if (valid == 3) { + emif1_enabled = 1; + emif2_enabled = 1; + break; + } else if (valid == 1) { + emif1_enabled = 1; + } else if (valid == 2) { + emif2_enabled = 1; + } + } + } /* @@ -1255,15 +1281,20 @@ void sdram_init(void) writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); } - do_sdram_init(EMIF1_BASE); - do_sdram_init(EMIF2_BASE); - if (!in_sdram) dmm_init(DMM_BASE); + if (emif1_enabled) + do_sdram_init(EMIF1_BASE); + + if (emif2_enabled) + do_sdram_init(EMIF2_BASE); + if (!(in_sdram || warm_reset())) { - emif_post_init_config(EMIF1_BASE); - emif_post_init_config(EMIF2_BASE); + if (emif1_enabled) + emif_post_init_config(EMIF1_BASE); + if (emif2_enabled) + emif_post_init_config(EMIF2_BASE); } /* for the shadow registers to take effect */ diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index ac597be..de167ee 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -38,6 +38,7 @@ endif COBJS-$(CONFIG_DRIVER_TI_EMAC) += emac.o COBJS-$(CONFIG_EMIF4) += emif4.o COBJS-$(CONFIG_SDRC) += sdrc.o +COBJS-$(CONFIG_USB_MUSB_AM35X) += am35x_musb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap3/am35x_musb.c b/arch/arm/cpu/armv7/omap3/am35x_musb.c new file mode 100644 index 0000000..7183c4f --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/am35x_musb.c @@ -0,0 +1,75 @@ +/* + * This file configures the internal USB PHY in AM35X. + * + * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com> + * + * Based on omap_phy_internal.c code from Linux by + * Hema HK <hemahk@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/am35x_def.h> + +void am35x_musb_reset(void) +{ + /* Reset the musb interface */ + clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, + 0, USBOTGSS_SW_RST); + clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, + USBOTGSS_SW_RST, 0); +} + +void am35x_musb_phy_power(u8 on) +{ + unsigned long start = get_timer(0); + + if (on) { + /* + * Start the on-chip PHY and its PLL. + */ + clrsetbits_le32(&am35x_scm_general_regs->devconf2, + CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN, + CONF2_PHY_PLLON); + + debug("Waiting for PHY clock good...\n"); + while (!(readl(&am35x_scm_general_regs->devconf2) + & CONF2_PHYCLKGD)) { + + if (get_timer(start) > CONFIG_SYS_HZ / 10) { + printf("musb PHY clock good timed out\n"); + break; + } + } + } else { + /* + * Power down the on-chip PHY. + */ + clrsetbits_le32(&am35x_scm_general_regs->devconf2, + CONF2_PHY_PLLON, + CONF2_PHYPWRDN | CONF2_OTGPWRDN); + } +} + +void am35x_musb_clear_irq(void) +{ + clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr, + 0, USBOTGSS_INT_CLR); + readl(&am35x_scm_general_regs->lvl_intr_clr); +} + diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index f3cd81a..89c587e 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -478,7 +478,7 @@ void omap3_outer_cache_disable(void) */ omap3_update_aux_cr(0, 0x2); } -#endif +#endif /* !CONFIG_SYS_L2CACHE_OFF */ #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) @@ -486,4 +486,4 @@ void enable_caches(void) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } -#endif +#endif /* !CONFIG_SYS_DCACHE_OFF */ diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index 2fe5ac7..d04a5a1 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -42,14 +42,7 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG5, M_NAND_GPMC_CONFIG6, 0 }; - -#if defined(CONFIG_ENV_IS_IN_NAND) -#define GPMC_CS 0 -#else -#define GPMC_CS 1 -#endif - -#endif +#endif /* CONFIG_CMD_NAND */ #if defined(CONFIG_CMD_ONENAND) static const u32 gpmc_onenand[GPMC_MAX_REG] = { @@ -60,14 +53,7 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG5, ONENAND_GPMC_CONFIG6, 0 }; - -#if defined(CONFIG_ENV_IS_IN_ONENAND) -#define GPMC_CS 0 -#else -#define GPMC_CS 1 -#endif - -#endif +#endif /* CONFIG_CMD_ONENAND */ /******************************************************** * mem_ok() - test used to see if timings are correct diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index f6d9b97..e32bf11 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -113,18 +113,18 @@ u32 get_sdr_cs_offset(u32 cs) * - Test CS to make sure it's OK for use */ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, - u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr) + struct board_sdrc_timings *timings) { /* Setup timings we got from the board. */ - writel(mcfg, &sdrc_base->cs[cs].mcfg); - writel(ctrla, &sdrc_actim_base->ctrla); - writel(ctrlb, &sdrc_actim_base->ctrlb); - writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); + writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); + writel(timings->ctrla, &sdrc_actim_base->ctrla); + writel(timings->ctrlb, &sdrc_actim_base->ctrlb); + writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); writel(CMD_NOP, &sdrc_base->cs[cs].manual); writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(mr, &sdrc_base->cs[cs].mr); + writel(timings->mr, &sdrc_base->cs[cs].mr); /* * Test ram in this bank @@ -143,7 +143,7 @@ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, void do_sdrc_init(u32 cs, u32 early) { struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; - u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr; + struct board_sdrc_timings timings; sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; @@ -158,7 +158,7 @@ void do_sdrc_init(u32 cs, u32 early) * setup CS1. */ #ifdef CONFIG_SPL_BUILD - get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr); + get_board_mem_timings(&timings); #endif if (early) { /* reset sdrc controller */ @@ -177,11 +177,9 @@ void do_sdrc_init(u32 cs, u32 early) writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); #ifdef CONFIG_SPL_BUILD - write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, - rfr_ctrl, mr); + write_sdrc_timings(CS0, sdrc_actim_base0, &timings); make_cs1_contiguous(); - write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb, - rfr_ctrl, mr); + write_sdrc_timings(CS1, sdrc_actim_base1, &timings); #endif } @@ -193,14 +191,12 @@ void do_sdrc_init(u32 cs, u32 early) * so we may be asked now to setup CS1. */ if (cs == CS1) { - mcfg = readl(&sdrc_base->cs[CS0].mcfg), - rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); - ctrla = readl(&sdrc_actim_base0->ctrla), - ctrlb = readl(&sdrc_actim_base0->ctrlb); - mr = readl(&sdrc_base->cs[CS0].mr); - write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb, - rfr_ctrl, mr); - + timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), + timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); + timings.ctrla = readl(&sdrc_actim_base0->ctrla); + timings.ctrlb = readl(&sdrc_actim_base0->ctrlb); + timings.mr = readl(&sdrc_base->cs[CS0].mr); + write_sdrc_timings(cs, sdrc_actim_base1, &timings); } } diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 5bd0a88..12c5803 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -44,7 +44,7 @@ */ #define printf(fmt, args...) #define puts(s) -#endif +#endif /* !CONFIG_SPL_BUILD */ struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 2c34e48..f4123aa 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -116,7 +116,7 @@ void do_io_settings(void) if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2)) writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2); } -#endif +#endif /* CONFIG_SPL_BUILD */ /* dummy fuction for omap4 */ void config_data_eye_leveling_samples(u32 emif_base) @@ -182,4 +182,4 @@ void v7_outer_cache_disable(void) { set_pl310_ctrl_reg(0); } -#endif +#endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7df97c5..dcc1f83 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -155,12 +155,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -177,14 +172,10 @@ ENTRY(relocate_code) mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -233,34 +224,22 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop - b clear_bss + +relocate_done: + + bx lr + _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start +ENDPROC(relocate_code) -clear_bss: - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: +#endif -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -jump_2_ram: +ENTRY(c_runtime_cpu_setup) /* * If I-cache is enabled invalidate it */ @@ -279,20 +258,9 @@ jump_2_ram: mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif /* !Tegra20 */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start -ENDPROC(relocate_code) -#endif + bx lr + +ENDPROC(c_runtime_cpu_setup) /************************************************************************* * diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index c12f1a7..efb5a40 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -245,12 +245,7 @@ reset: orr r0,r0,#0x13 msr cpsr,r0 -/* Set initial stackpointer in SDRAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -267,14 +262,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -326,42 +317,9 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - - bl coloured_LED_init - bl red_led_on -#endif +relocate_done: -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -370,6 +328,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + bx lr + /****************************************************************************/ /* */ /* Interrupt handling */ diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 536cf5c..72af869 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -164,12 +164,7 @@ reset: bl lock_cache_for_stack #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0, =0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ #ifndef CONFIG_SPL_BUILD @@ -186,10 +181,6 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - /* Disable the Dcache RAM lock for stack now */ #ifdef CONFIG_CPU_PXA25X bl cpu_init_crit @@ -198,7 +189,7 @@ stack_setup: adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -250,48 +241,9 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -#endif /* #ifndef CONFIG_SPL_BUILD */ +relocate_done: -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -#ifdef CONFIG_ONENAND_SPL - ldr r0, _onenand_boot_ofs - mov pc, r0 - -_onenand_boot_ofs: - .word onenand_boot -#else -jump_2_ram: - ldr r0, _board_init_r_ofs - ldr r1, _TEXT_BASE - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start -#endif + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -299,7 +251,14 @@ _rel_dyn_end_ofs: .word __rel_dyn_end - _start _dynsym_start_ofs: .word __dynsym_start - _start + #endif + + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + bx lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 323b923..4528c91 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -128,12 +128,7 @@ reset: bl lowlevel_init #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -150,14 +145,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -209,42 +200,9 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: - - bl coloured_LED_init - bl red_led_on -#endif +relocate_done: -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ - mov pc, lr - -_board_init_r_ofs: - .word board_init_r - _start + bx lr _rel_dyn_start_ofs: .word __rel_dyn_start - _start @@ -253,6 +211,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + bx lr + /* ************************************************************************* * diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 1ea92d1..3144299 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -132,12 +132,7 @@ reset: bl cpu_init_crit #endif -/* Set stackpointer in internal RAM to call board_init_f */ -call_board_init_f: - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - ldr r0,=0x00000000 - bl board_init_f + bl _main /*------------------------------------------------------------------------------*/ @@ -154,14 +149,10 @@ relocate_code: mov r5, r1 /* save addr of gd */ mov r6, r2 /* save addr of destination */ - /* Set up the stack */ -stack_setup: - mov sp, r4 - adr r0, _start cmp r0, r6 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ - beq clear_bss /* skip relocation */ + beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs add r2, r0, r3 /* r2 <- source end address */ @@ -213,40 +204,10 @@ fixnext: blo fixloop #endif -clear_bss: -#ifndef CONFIG_SPL_BUILD - ldr r0, _bss_start_ofs - ldr r1, _bss_end_ofs - mov r4, r6 /* reloc addr */ - add r0, r0, r4 - add r1, r1, r4 - mov r2, #0x00000000 /* clear */ - -clbss_l:cmp r0, r1 /* clear loop... */ - bhs clbss_e /* if reached end of bss, exit */ - str r2, [r0] - add r0, r0, #4 - b clbss_l -clbss_e: -#endif +relocate_done: -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ - ldr r0, _board_init_r_ofs - adr r1, _start - add lr, r0, r1 - add lr, lr, r9 - /* setup parameters for board_init_r */ - mov r0, r5 /* gd_t */ - mov r1, r6 /* dest_addr */ - /* jump to it ... */ mov pc, lr -_board_init_r_ofs: - .word board_init_r - _start - _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: @@ -254,6 +215,11 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start + .globl c_runtime_cpu_setup +c_runtime_cpu_setup: + + mov pc, lr + /* ************************************************************************* * |